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1 | 81fdc5f8 | ths | /*
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2 | 81fdc5f8 | ths | * CRIS virtual CPU header
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3 | 81fdc5f8 | ths | *
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4 | 81fdc5f8 | ths | * Copyright (c) 2007 AXIS Communications AB
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5 | 81fdc5f8 | ths | * Written by Edgar E. Iglesias
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6 | 81fdc5f8 | ths | *
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7 | 81fdc5f8 | ths | * This library is free software; you can redistribute it and/or
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8 | 81fdc5f8 | ths | * modify it under the terms of the GNU Lesser General Public
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9 | 81fdc5f8 | ths | * License as published by the Free Software Foundation; either
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10 | 81fdc5f8 | ths | * version 2 of the License, or (at your option) any later version.
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11 | 81fdc5f8 | ths | *
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12 | 81fdc5f8 | ths | * This library is distributed in the hope that it will be useful,
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13 | 81fdc5f8 | ths | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 | 81fdc5f8 | ths | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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15 | 81fdc5f8 | ths | * General Public License for more details.
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16 | 81fdc5f8 | ths | *
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17 | 81fdc5f8 | ths | * You should have received a copy of the GNU Lesser General Public
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18 | 81fdc5f8 | ths | * License along with this library; if not, write to the Free Software
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19 | 81fdc5f8 | ths | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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20 | 81fdc5f8 | ths | */
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21 | 81fdc5f8 | ths | #ifndef CPU_CRIS_H
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22 | 81fdc5f8 | ths | #define CPU_CRIS_H
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23 | 81fdc5f8 | ths | |
24 | 81fdc5f8 | ths | #define TARGET_LONG_BITS 32 |
25 | 81fdc5f8 | ths | |
26 | 81fdc5f8 | ths | #include "cpu-defs.h" |
27 | 81fdc5f8 | ths | |
28 | 81fdc5f8 | ths | #include "softfloat.h" |
29 | 81fdc5f8 | ths | |
30 | 81fdc5f8 | ths | #define TARGET_HAS_ICE 1 |
31 | 81fdc5f8 | ths | |
32 | 81fdc5f8 | ths | #define ELF_MACHINE EM_CRIS
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33 | 81fdc5f8 | ths | |
34 | 81fdc5f8 | ths | #define EXCP_MMU_EXEC 0 |
35 | 81fdc5f8 | ths | #define EXCP_MMU_READ 1 |
36 | 81fdc5f8 | ths | #define EXCP_MMU_WRITE 2 |
37 | 81fdc5f8 | ths | #define EXCP_MMU_FLUSH 3 |
38 | 81fdc5f8 | ths | #define EXCP_MMU_MISS 4 |
39 | 81fdc5f8 | ths | #define EXCP_BREAK 16 /* trap. */ |
40 | 81fdc5f8 | ths | |
41 | 81fdc5f8 | ths | /* CPU flags. */
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42 | 81fdc5f8 | ths | #define S_FLAG 0x200 |
43 | 81fdc5f8 | ths | #define R_FLAG 0x100 |
44 | 81fdc5f8 | ths | #define P_FLAG 0x80 |
45 | 81fdc5f8 | ths | #define U_FLAG 0x40 |
46 | 81fdc5f8 | ths | #define P_FLAG 0x80 |
47 | 81fdc5f8 | ths | #define U_FLAG 0x40 |
48 | 81fdc5f8 | ths | #define I_FLAG 0x20 |
49 | 81fdc5f8 | ths | #define X_FLAG 0x10 |
50 | 81fdc5f8 | ths | #define N_FLAG 0x08 |
51 | 81fdc5f8 | ths | #define Z_FLAG 0x04 |
52 | 81fdc5f8 | ths | #define V_FLAG 0x02 |
53 | 81fdc5f8 | ths | #define C_FLAG 0x01 |
54 | 81fdc5f8 | ths | #define ALU_FLAGS 0x1F |
55 | 81fdc5f8 | ths | |
56 | 81fdc5f8 | ths | /* Condition codes. */
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57 | 81fdc5f8 | ths | #define CC_CC 0 |
58 | 81fdc5f8 | ths | #define CC_CS 1 |
59 | 81fdc5f8 | ths | #define CC_NE 2 |
60 | 81fdc5f8 | ths | #define CC_EQ 3 |
61 | 81fdc5f8 | ths | #define CC_VC 4 |
62 | 81fdc5f8 | ths | #define CC_VS 5 |
63 | 81fdc5f8 | ths | #define CC_PL 6 |
64 | 81fdc5f8 | ths | #define CC_MI 7 |
65 | 81fdc5f8 | ths | #define CC_LS 8 |
66 | 81fdc5f8 | ths | #define CC_HI 9 |
67 | 81fdc5f8 | ths | #define CC_GE 10 |
68 | 81fdc5f8 | ths | #define CC_LT 11 |
69 | 81fdc5f8 | ths | #define CC_GT 12 |
70 | 81fdc5f8 | ths | #define CC_LE 13 |
71 | 81fdc5f8 | ths | #define CC_A 14 |
72 | 81fdc5f8 | ths | #define CC_P 15 |
73 | 81fdc5f8 | ths | |
74 | 81fdc5f8 | ths | /* Internal flags for the implementation. */
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75 | 81fdc5f8 | ths | #define F_DELAYSLOT 1 |
76 | 81fdc5f8 | ths | |
77 | 81fdc5f8 | ths | typedef struct CPUCRISState { |
78 | 81fdc5f8 | ths | uint32_t debug1; |
79 | 81fdc5f8 | ths | uint32_t debug2; |
80 | 81fdc5f8 | ths | uint32_t debug3; |
81 | 81fdc5f8 | ths | |
82 | 81fdc5f8 | ths | /*
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83 | 81fdc5f8 | ths | * We just store the stores to the tlbset here for later evaluation
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84 | 81fdc5f8 | ths | * when the hw needs access to them.
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85 | 81fdc5f8 | ths | *
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86 | 81fdc5f8 | ths | * One for I and another for D.
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87 | 81fdc5f8 | ths | */
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88 | 81fdc5f8 | ths | struct
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89 | 81fdc5f8 | ths | { |
90 | 81fdc5f8 | ths | uint32_t hi; |
91 | 81fdc5f8 | ths | uint32_t lo; |
92 | 81fdc5f8 | ths | } tlbsets[2][4][16]; |
93 | 81fdc5f8 | ths | |
94 | 81fdc5f8 | ths | uint32_t sregs[256][16]; /* grrr why so many?? */ |
95 | 81fdc5f8 | ths | uint32_t regs[16];
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96 | 81fdc5f8 | ths | uint32_t pregs[16];
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97 | 81fdc5f8 | ths | uint32_t pc; |
98 | 81fdc5f8 | ths | uint32_t sr; |
99 | 81fdc5f8 | ths | uint32_t flag_mask; /* Per insn mask of affected flags. */
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100 | 81fdc5f8 | ths | |
101 | 81fdc5f8 | ths | /* SSP and USP. */
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102 | 81fdc5f8 | ths | int current_sp;
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103 | 81fdc5f8 | ths | uint32_t sp[2];
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104 | 81fdc5f8 | ths | |
105 | 81fdc5f8 | ths | /* These are setup up by the guest code just before transfering the
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106 | 81fdc5f8 | ths | control back to the host. */
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107 | 81fdc5f8 | ths | int jmp;
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108 | 81fdc5f8 | ths | uint32_t btarget; |
109 | 81fdc5f8 | ths | int btaken;
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110 | 81fdc5f8 | ths | |
111 | 81fdc5f8 | ths | /* for traps. */
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112 | 81fdc5f8 | ths | int trapnr;
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113 | 81fdc5f8 | ths | |
114 | 81fdc5f8 | ths | /* Condition flag tracking. */
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115 | 81fdc5f8 | ths | uint32_t cc_op; |
116 | 81fdc5f8 | ths | uint32_t cc_mask; |
117 | 81fdc5f8 | ths | uint32_t cc_dest; |
118 | 81fdc5f8 | ths | uint32_t cc_src; |
119 | 81fdc5f8 | ths | uint32_t cc_result; |
120 | 81fdc5f8 | ths | |
121 | 81fdc5f8 | ths | /* size of the operation, 1 = byte, 2 = word, 4 = dword. */
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122 | 81fdc5f8 | ths | int cc_size;
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123 | 81fdc5f8 | ths | |
124 | 81fdc5f8 | ths | /* extended arithmetics. */
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125 | 81fdc5f8 | ths | int cc_x_live;
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126 | 81fdc5f8 | ths | int cc_x;
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127 | 81fdc5f8 | ths | |
128 | 81fdc5f8 | ths | int features;
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129 | 81fdc5f8 | ths | |
130 | 81fdc5f8 | ths | uint64_t pending_interrupts; |
131 | 81fdc5f8 | ths | int interrupt_request;
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132 | 81fdc5f8 | ths | int exception_index;
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133 | 81fdc5f8 | ths | int user_mode_only;
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134 | 81fdc5f8 | ths | int halted;
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135 | 81fdc5f8 | ths | |
136 | 81fdc5f8 | ths | struct
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137 | 81fdc5f8 | ths | { |
138 | 81fdc5f8 | ths | int exec_insns;
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139 | 81fdc5f8 | ths | int exec_loads;
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140 | 81fdc5f8 | ths | int exec_stores;
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141 | 81fdc5f8 | ths | } stats; |
142 | 81fdc5f8 | ths | |
143 | 81fdc5f8 | ths | |
144 | 81fdc5f8 | ths | jmp_buf jmp_env; |
145 | 81fdc5f8 | ths | CPU_COMMON |
146 | 81fdc5f8 | ths | } CPUCRISState; |
147 | 81fdc5f8 | ths | |
148 | 81fdc5f8 | ths | CPUCRISState *cpu_cris_init(void);
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149 | 81fdc5f8 | ths | int cpu_cris_exec(CPUCRISState *s);
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150 | 81fdc5f8 | ths | void cpu_cris_close(CPUCRISState *s);
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151 | 81fdc5f8 | ths | void do_interrupt(CPUCRISState *env);
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152 | 81fdc5f8 | ths | /* you can call this signal handler from your SIGBUS and SIGSEGV
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153 | 81fdc5f8 | ths | signal handlers to inform the virtual CPU of exceptions. non zero
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154 | 81fdc5f8 | ths | is returned if the signal was handled by the virtual CPU. */
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155 | 81fdc5f8 | ths | int cpu_cris_signal_handler(int host_signum, void *pinfo, |
156 | 81fdc5f8 | ths | void *puc);
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157 | 81fdc5f8 | ths | void cpu_cris_flush_flags(CPUCRISState *, int); |
158 | 81fdc5f8 | ths | |
159 | 81fdc5f8 | ths | |
160 | 81fdc5f8 | ths | void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec, |
161 | 81fdc5f8 | ths | int is_asi);
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162 | 81fdc5f8 | ths | |
163 | 81fdc5f8 | ths | enum {
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164 | 81fdc5f8 | ths | CC_OP_DYNAMIC, /* Use env->cc_op */
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165 | 81fdc5f8 | ths | CC_OP_FLAGS, |
166 | 81fdc5f8 | ths | CC_OP_LOGIC, |
167 | 81fdc5f8 | ths | CC_OP_CMP, |
168 | 81fdc5f8 | ths | CC_OP_MOVE, |
169 | 81fdc5f8 | ths | CC_OP_MOVE_PD, |
170 | 81fdc5f8 | ths | CC_OP_MOVE_SD, |
171 | 81fdc5f8 | ths | CC_OP_ADD, |
172 | 81fdc5f8 | ths | CC_OP_ADDC, |
173 | 81fdc5f8 | ths | CC_OP_MCP, |
174 | 81fdc5f8 | ths | CC_OP_ADDU, |
175 | 81fdc5f8 | ths | CC_OP_SUB, |
176 | 81fdc5f8 | ths | CC_OP_SUBU, |
177 | 81fdc5f8 | ths | CC_OP_NEG, |
178 | 81fdc5f8 | ths | CC_OP_BTST, |
179 | 81fdc5f8 | ths | CC_OP_MULS, |
180 | 81fdc5f8 | ths | CC_OP_MULU, |
181 | 81fdc5f8 | ths | CC_OP_DSTEP, |
182 | 81fdc5f8 | ths | CC_OP_BOUND, |
183 | 81fdc5f8 | ths | |
184 | 81fdc5f8 | ths | CC_OP_OR, |
185 | 81fdc5f8 | ths | CC_OP_AND, |
186 | 81fdc5f8 | ths | CC_OP_XOR, |
187 | 81fdc5f8 | ths | CC_OP_LSL, |
188 | 81fdc5f8 | ths | CC_OP_LSR, |
189 | 81fdc5f8 | ths | CC_OP_ASR, |
190 | 81fdc5f8 | ths | CC_OP_LZ |
191 | 81fdc5f8 | ths | }; |
192 | 81fdc5f8 | ths | |
193 | 81fdc5f8 | ths | #define CCF_C 0x01 |
194 | 81fdc5f8 | ths | #define CCF_V 0x02 |
195 | 81fdc5f8 | ths | #define CCF_Z 0x04 |
196 | 81fdc5f8 | ths | #define CCF_N 0x08 |
197 | 81fdc5f8 | ths | #define CCF_X 0x10 |
198 | 81fdc5f8 | ths | |
199 | 81fdc5f8 | ths | #define CRIS_SSP 0 |
200 | 81fdc5f8 | ths | #define CRIS_USP 1 |
201 | 81fdc5f8 | ths | |
202 | 81fdc5f8 | ths | typedef struct cris_def_t cris_def_t; |
203 | 81fdc5f8 | ths | |
204 | 81fdc5f8 | ths | int cpu_cris_set_model(CPUCRISState *env, const char * name); |
205 | 81fdc5f8 | ths | |
206 | 81fdc5f8 | ths | void cris_set_irq_level(CPUCRISState *env, int level, uint8_t vector); |
207 | 81fdc5f8 | ths | void cris_set_macsr(CPUCRISState *env, uint32_t val);
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208 | 81fdc5f8 | ths | void cris_switch_sp(CPUCRISState *env);
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209 | 81fdc5f8 | ths | |
210 | 81fdc5f8 | ths | void do_cris_semihosting(CPUCRISState *env, int nr); |
211 | 81fdc5f8 | ths | |
212 | 81fdc5f8 | ths | enum cris_features {
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213 | 81fdc5f8 | ths | CRIS_FEATURE_CF_ISA_MUL, |
214 | 81fdc5f8 | ths | }; |
215 | 81fdc5f8 | ths | |
216 | 81fdc5f8 | ths | static inline int cris_feature(CPUCRISState *env, int feature) |
217 | 81fdc5f8 | ths | { |
218 | 81fdc5f8 | ths | return (env->features & (1u << feature)) != 0; |
219 | 81fdc5f8 | ths | } |
220 | 81fdc5f8 | ths | |
221 | 81fdc5f8 | ths | void register_cris_insns (CPUCRISState *env);
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222 | 81fdc5f8 | ths | |
223 | 81fdc5f8 | ths | /* CRIS uses 8k pages. */
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224 | 81fdc5f8 | ths | #define TARGET_PAGE_BITS 13 |
225 | 81fdc5f8 | ths | |
226 | 81fdc5f8 | ths | #define CPUState CPUCRISState
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227 | 81fdc5f8 | ths | #define cpu_init cpu_cris_init
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228 | 81fdc5f8 | ths | #define cpu_exec cpu_cris_exec
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229 | 81fdc5f8 | ths | #define cpu_gen_code cpu_cris_gen_code
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230 | 81fdc5f8 | ths | #define cpu_signal_handler cpu_cris_signal_handler
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231 | 81fdc5f8 | ths | |
232 | 81fdc5f8 | ths | #include "cpu-all.h" |
233 | 81fdc5f8 | ths | |
234 | 81fdc5f8 | ths | /* Register aliases. */
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235 | 81fdc5f8 | ths | #define REG_SP 14 |
236 | 81fdc5f8 | ths | #define REG_ACR 15 |
237 | 81fdc5f8 | ths | #define REG_MOF 7 |
238 | 81fdc5f8 | ths | |
239 | 81fdc5f8 | ths | /* Support regs. */
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240 | 81fdc5f8 | ths | #define SR_PID 2 |
241 | 81fdc5f8 | ths | #define SR_SRS 3 |
242 | 81fdc5f8 | ths | #define SR_EBP 9 |
243 | 81fdc5f8 | ths | #define SR_ERP 10 |
244 | 81fdc5f8 | ths | #define SR_CCS 13 |
245 | 81fdc5f8 | ths | |
246 | 81fdc5f8 | ths | /* Support func regs. */
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247 | 81fdc5f8 | ths | #define SFR_RW_GC_CFG 0][0 |
248 | 81fdc5f8 | ths | #define SFR_RW_MM_CFG 1][0 |
249 | 81fdc5f8 | ths | #define SFR_RW_MM_KBASE_LO 1][1 |
250 | 81fdc5f8 | ths | #define SFR_RW_MM_KBASE_HI 1][2 |
251 | 81fdc5f8 | ths | #define SFR_R_MM_CAUSE 1][3 |
252 | 81fdc5f8 | ths | #define SFR_RW_MM_TLB_SEL 1][4 |
253 | 81fdc5f8 | ths | #define SFR_RW_MM_TLB_LO 1][5 |
254 | 81fdc5f8 | ths | #define SFR_RW_MM_TLB_HI 1][6 |
255 | 81fdc5f8 | ths | |
256 | 81fdc5f8 | ths | #endif |