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/*
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 * QEMU System Emulator header
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 * 
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 * Copyright (c) 2003 Fabrice Bellard
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 * 
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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#ifndef VL_H
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#define VL_H
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/* we put basic includes here to avoid repeating them in device drivers */
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#include <stdlib.h>
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#include <stdio.h>
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#include <stdarg.h>
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#include <string.h>
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#include <inttypes.h>
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#include <limits.h>
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#include <time.h>
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#include <ctype.h>
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#include <errno.h>
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#include <unistd.h>
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#include <fcntl.h>
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#include <sys/stat.h>
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#include "audio/audio.h"
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#ifndef O_LARGEFILE
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#define O_LARGEFILE 0
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#endif
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#ifndef O_BINARY
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#define O_BINARY 0
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#endif
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#ifdef _WIN32
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#define lseek _lseeki64
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#define ENOTSUP 4096
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/* XXX: find 64 bit version */
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#define ftruncate chsize
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static inline char *realpath(const char *path, char *resolved_path)
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{
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    _fullpath(resolved_path, path, _MAX_PATH);
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    return resolved_path;
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}
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#endif
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#ifdef QEMU_TOOL
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/* we use QEMU_TOOL in the command line tools which do not depend on
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   the target CPU type */
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#include "config-host.h"
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#include <setjmp.h>
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#include "osdep.h"
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#include "bswap.h"
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#else
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#include "cpu.h"
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#include "gdbstub.h"
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#endif /* !defined(QEMU_TOOL) */
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#ifndef glue
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#define xglue(x, y) x ## y
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#define glue(x, y) xglue(x, y)
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#define stringify(s)        tostring(s)
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#define tostring(s)        #s
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#endif
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/* vl.c */
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uint64_t muldiv64(uint64_t a, uint32_t b, uint32_t c);
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void hw_error(const char *fmt, ...);
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int get_image_size(const char *filename);
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int load_image(const char *filename, uint8_t *addr);
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extern const char *bios_dir;
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void pstrcpy(char *buf, int buf_size, const char *str);
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char *pstrcat(char *buf, int buf_size, const char *s);
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int strstart(const char *str, const char *val, const char **ptr);
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extern int vm_running;
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typedef struct vm_change_state_entry VMChangeStateEntry;
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typedef void VMChangeStateHandler(void *opaque, int running);
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typedef void VMStopHandler(void *opaque, int reason);
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VMChangeStateEntry *qemu_add_vm_change_state_handler(VMChangeStateHandler *cb,
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                                                     void *opaque);
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void qemu_del_vm_change_state_handler(VMChangeStateEntry *e);
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int qemu_add_vm_stop_handler(VMStopHandler *cb, void *opaque);
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void qemu_del_vm_stop_handler(VMStopHandler *cb, void *opaque);
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void vm_start(void);
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void vm_stop(int reason);
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typedef void QEMUResetHandler(void *opaque);
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void qemu_register_reset(QEMUResetHandler *func, void *opaque);
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void qemu_system_reset_request(void);
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void qemu_system_shutdown_request(void);
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void qemu_system_powerdown_request(void);
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#if !defined(TARGET_SPARC)
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// Please implement a power failure function to signal the OS
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#define qemu_system_powerdown() do{}while(0)
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#else
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void qemu_system_powerdown(void);
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#endif
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void main_loop_wait(int timeout);
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extern int ram_size;
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extern int bios_size;
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extern int rtc_utc;
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extern int cirrus_vga_enabled;
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extern int graphic_width;
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extern int graphic_height;
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extern int graphic_depth;
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extern const char *keyboard_layout;
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extern int kqemu_allowed;
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extern int win2k_install_hack;
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extern int usb_enabled;
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extern int smp_cpus;
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/* XXX: make it dynamic */
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#if defined (TARGET_PPC)
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#define BIOS_SIZE ((512 + 32) * 1024)
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#elif defined(TARGET_MIPS)
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#define BIOS_SIZE (128 * 1024)
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#else
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#define BIOS_SIZE ((256 + 64) * 1024)
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#endif
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/* keyboard/mouse support */
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#define MOUSE_EVENT_LBUTTON 0x01
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#define MOUSE_EVENT_RBUTTON 0x02
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#define MOUSE_EVENT_MBUTTON 0x04
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typedef void QEMUPutKBDEvent(void *opaque, int keycode);
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typedef void QEMUPutMouseEvent(void *opaque, int dx, int dy, int dz, int buttons_state);
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void qemu_add_kbd_event_handler(QEMUPutKBDEvent *func, void *opaque);
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void qemu_add_mouse_event_handler(QEMUPutMouseEvent *func, void *opaque);
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void kbd_put_keycode(int keycode);
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void kbd_mouse_event(int dx, int dy, int dz, int buttons_state);
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/* keysym is a unicode code except for special keys (see QEMU_KEY_xxx
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   constants) */
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#define QEMU_KEY_ESC1(c) ((c) | 0xe100)
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#define QEMU_KEY_BACKSPACE  0x007f
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#define QEMU_KEY_UP         QEMU_KEY_ESC1('A')
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#define QEMU_KEY_DOWN       QEMU_KEY_ESC1('B')
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#define QEMU_KEY_RIGHT      QEMU_KEY_ESC1('C')
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#define QEMU_KEY_LEFT       QEMU_KEY_ESC1('D')
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#define QEMU_KEY_HOME       QEMU_KEY_ESC1(1)
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#define QEMU_KEY_END        QEMU_KEY_ESC1(4)
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#define QEMU_KEY_PAGEUP     QEMU_KEY_ESC1(5)
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#define QEMU_KEY_PAGEDOWN   QEMU_KEY_ESC1(6)
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#define QEMU_KEY_DELETE     QEMU_KEY_ESC1(3)
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#define QEMU_KEY_CTRL_UP         0xe400
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#define QEMU_KEY_CTRL_DOWN       0xe401
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#define QEMU_KEY_CTRL_LEFT       0xe402
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#define QEMU_KEY_CTRL_RIGHT      0xe403
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#define QEMU_KEY_CTRL_HOME       0xe404
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#define QEMU_KEY_CTRL_END        0xe405
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#define QEMU_KEY_CTRL_PAGEUP     0xe406
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#define QEMU_KEY_CTRL_PAGEDOWN   0xe407
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void kbd_put_keysym(int keysym);
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/* async I/O support */
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typedef void IOReadHandler(void *opaque, const uint8_t *buf, int size);
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typedef int IOCanRWHandler(void *opaque);
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typedef void IOHandler(void *opaque);
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int qemu_set_fd_handler2(int fd, 
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                         IOCanRWHandler *fd_read_poll, 
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                         IOHandler *fd_read, 
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                         IOHandler *fd_write, 
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                         void *opaque);
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int qemu_set_fd_handler(int fd,
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                        IOHandler *fd_read, 
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                        IOHandler *fd_write,
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                        void *opaque);
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/* character device */
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#define CHR_EVENT_BREAK 0 /* serial break char */
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#define CHR_EVENT_FOCUS 1 /* focus to this terminal (modal input needed) */
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#define CHR_IOCTL_SERIAL_SET_PARAMS   1
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typedef struct {
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    int speed;
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    int parity;
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    int data_bits;
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    int stop_bits;
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} QEMUSerialSetParams;
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#define CHR_IOCTL_SERIAL_SET_BREAK    2
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#define CHR_IOCTL_PP_READ_DATA        3
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#define CHR_IOCTL_PP_WRITE_DATA       4
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#define CHR_IOCTL_PP_READ_CONTROL     5
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#define CHR_IOCTL_PP_WRITE_CONTROL    6
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#define CHR_IOCTL_PP_READ_STATUS      7
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typedef void IOEventHandler(void *opaque, int event);
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typedef struct CharDriverState {
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    int (*chr_write)(struct CharDriverState *s, const uint8_t *buf, int len);
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    void (*chr_add_read_handler)(struct CharDriverState *s, 
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                                 IOCanRWHandler *fd_can_read, 
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                                 IOReadHandler *fd_read, void *opaque);
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    int (*chr_ioctl)(struct CharDriverState *s, int cmd, void *arg);
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    IOEventHandler *chr_event;
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    void (*chr_send_event)(struct CharDriverState *chr, int event);
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    void *opaque;
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} CharDriverState;
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void qemu_chr_printf(CharDriverState *s, const char *fmt, ...);
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int qemu_chr_write(CharDriverState *s, const uint8_t *buf, int len);
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void qemu_chr_send_event(CharDriverState *s, int event);
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void qemu_chr_add_read_handler(CharDriverState *s, 
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                               IOCanRWHandler *fd_can_read, 
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                               IOReadHandler *fd_read, void *opaque);
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void qemu_chr_add_event_handler(CharDriverState *s, IOEventHandler *chr_event);
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int qemu_chr_ioctl(CharDriverState *s, int cmd, void *arg);
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/* consoles */
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typedef struct DisplayState DisplayState;
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typedef struct TextConsole TextConsole;
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typedef void (*vga_hw_update_ptr)(void *);
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typedef void (*vga_hw_invalidate_ptr)(void *);
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typedef void (*vga_hw_screen_dump_ptr)(void *, const char *);
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TextConsole *graphic_console_init(DisplayState *ds, vga_hw_update_ptr update,
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                                  vga_hw_invalidate_ptr invalidate,
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                                  vga_hw_screen_dump_ptr screen_dump,
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                                  void *opaque);
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void vga_hw_update(void);
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void vga_hw_invalidate(void);
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void vga_hw_screen_dump(const char *filename);
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int is_graphic_console(void);
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CharDriverState *text_console_init(DisplayState *ds);
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void console_select(unsigned int index);
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/* serial ports */
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#define MAX_SERIAL_PORTS 4
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extern CharDriverState *serial_hds[MAX_SERIAL_PORTS];
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/* parallel ports */
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#define MAX_PARALLEL_PORTS 3
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extern CharDriverState *parallel_hds[MAX_PARALLEL_PORTS];
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/* VLANs support */
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typedef struct VLANClientState VLANClientState;
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struct VLANClientState {
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    IOReadHandler *fd_read;
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    /* Packets may still be sent if this returns zero.  It's used to
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       rate-limit the slirp code.  */
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    IOCanRWHandler *fd_can_read;
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    void *opaque;
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    struct VLANClientState *next;
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    struct VLANState *vlan;
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    char info_str[256];
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};
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typedef struct VLANState {
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    int id;
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    VLANClientState *first_client;
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    struct VLANState *next;
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} VLANState;
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VLANState *qemu_find_vlan(int id);
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VLANClientState *qemu_new_vlan_client(VLANState *vlan,
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                                      IOReadHandler *fd_read,
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                                      IOCanRWHandler *fd_can_read,
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                                      void *opaque);
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int qemu_can_send_packet(VLANClientState *vc);
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void qemu_send_packet(VLANClientState *vc, const uint8_t *buf, int size);
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void qemu_handler_true(void *opaque);
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void do_info_network(void);
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/* TAP win32 */
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int tap_win32_init(VLANState *vlan, const char *ifname);
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void tap_win32_poll(void);
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/* NIC info */
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#define MAX_NICS 8
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typedef struct NICInfo {
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    uint8_t macaddr[6];
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    const char *model;
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    VLANState *vlan;
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} NICInfo;
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extern int nb_nics;
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extern NICInfo nd_table[MAX_NICS];
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/* timers */
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typedef struct QEMUClock QEMUClock;
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typedef struct QEMUTimer QEMUTimer;
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typedef void QEMUTimerCB(void *opaque);
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/* The real time clock should be used only for stuff which does not
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   change the virtual machine state, as it is run even if the virtual
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   machine is stopped. The real time clock has a frequency of 1000
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   Hz. */
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extern QEMUClock *rt_clock;
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/* The virtual clock is only run during the emulation. It is stopped
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   when the virtual machine is stopped. Virtual timers use a high
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   precision clock, usually cpu cycles (use ticks_per_sec). */
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extern QEMUClock *vm_clock;
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int64_t qemu_get_clock(QEMUClock *clock);
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QEMUTimer *qemu_new_timer(QEMUClock *clock, QEMUTimerCB *cb, void *opaque);
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void qemu_free_timer(QEMUTimer *ts);
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void qemu_del_timer(QEMUTimer *ts);
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void qemu_mod_timer(QEMUTimer *ts, int64_t expire_time);
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int qemu_timer_pending(QEMUTimer *ts);
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extern int64_t ticks_per_sec;
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extern int pit_min_timer_count;
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void cpu_enable_ticks(void);
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void cpu_disable_ticks(void);
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/* VM Load/Save */
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typedef FILE QEMUFile;
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void qemu_put_buffer(QEMUFile *f, const uint8_t *buf, int size);
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void qemu_put_byte(QEMUFile *f, int v);
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void qemu_put_be16(QEMUFile *f, unsigned int v);
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void qemu_put_be32(QEMUFile *f, unsigned int v);
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void qemu_put_be64(QEMUFile *f, uint64_t v);
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int qemu_get_buffer(QEMUFile *f, uint8_t *buf, int size);
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int qemu_get_byte(QEMUFile *f);
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unsigned int qemu_get_be16(QEMUFile *f);
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unsigned int qemu_get_be32(QEMUFile *f);
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uint64_t qemu_get_be64(QEMUFile *f);
379 8a7ddc38 bellard
380 8a7ddc38 bellard
static inline void qemu_put_be64s(QEMUFile *f, const uint64_t *pv)
381 8a7ddc38 bellard
{
382 8a7ddc38 bellard
    qemu_put_be64(f, *pv);
383 8a7ddc38 bellard
}
384 8a7ddc38 bellard
385 8a7ddc38 bellard
static inline void qemu_put_be32s(QEMUFile *f, const uint32_t *pv)
386 8a7ddc38 bellard
{
387 8a7ddc38 bellard
    qemu_put_be32(f, *pv);
388 8a7ddc38 bellard
}
389 8a7ddc38 bellard
390 8a7ddc38 bellard
static inline void qemu_put_be16s(QEMUFile *f, const uint16_t *pv)
391 8a7ddc38 bellard
{
392 8a7ddc38 bellard
    qemu_put_be16(f, *pv);
393 8a7ddc38 bellard
}
394 8a7ddc38 bellard
395 8a7ddc38 bellard
static inline void qemu_put_8s(QEMUFile *f, const uint8_t *pv)
396 8a7ddc38 bellard
{
397 8a7ddc38 bellard
    qemu_put_byte(f, *pv);
398 8a7ddc38 bellard
}
399 8a7ddc38 bellard
400 8a7ddc38 bellard
static inline void qemu_get_be64s(QEMUFile *f, uint64_t *pv)
401 8a7ddc38 bellard
{
402 8a7ddc38 bellard
    *pv = qemu_get_be64(f);
403 8a7ddc38 bellard
}
404 8a7ddc38 bellard
405 8a7ddc38 bellard
static inline void qemu_get_be32s(QEMUFile *f, uint32_t *pv)
406 8a7ddc38 bellard
{
407 8a7ddc38 bellard
    *pv = qemu_get_be32(f);
408 8a7ddc38 bellard
}
409 8a7ddc38 bellard
410 8a7ddc38 bellard
static inline void qemu_get_be16s(QEMUFile *f, uint16_t *pv)
411 8a7ddc38 bellard
{
412 8a7ddc38 bellard
    *pv = qemu_get_be16(f);
413 8a7ddc38 bellard
}
414 8a7ddc38 bellard
415 8a7ddc38 bellard
static inline void qemu_get_8s(QEMUFile *f, uint8_t *pv)
416 8a7ddc38 bellard
{
417 8a7ddc38 bellard
    *pv = qemu_get_byte(f);
418 8a7ddc38 bellard
}
419 8a7ddc38 bellard
420 c27004ec bellard
#if TARGET_LONG_BITS == 64
421 c27004ec bellard
#define qemu_put_betl qemu_put_be64
422 c27004ec bellard
#define qemu_get_betl qemu_get_be64
423 c27004ec bellard
#define qemu_put_betls qemu_put_be64s
424 c27004ec bellard
#define qemu_get_betls qemu_get_be64s
425 c27004ec bellard
#else
426 c27004ec bellard
#define qemu_put_betl qemu_put_be32
427 c27004ec bellard
#define qemu_get_betl qemu_get_be32
428 c27004ec bellard
#define qemu_put_betls qemu_put_be32s
429 c27004ec bellard
#define qemu_get_betls qemu_get_be32s
430 c27004ec bellard
#endif
431 c27004ec bellard
432 8a7ddc38 bellard
int64_t qemu_ftell(QEMUFile *f);
433 8a7ddc38 bellard
int64_t qemu_fseek(QEMUFile *f, int64_t pos, int whence);
434 8a7ddc38 bellard
435 8a7ddc38 bellard
typedef void SaveStateHandler(QEMUFile *f, void *opaque);
436 8a7ddc38 bellard
typedef int LoadStateHandler(QEMUFile *f, void *opaque, int version_id);
437 8a7ddc38 bellard
438 8a7ddc38 bellard
int qemu_loadvm(const char *filename);
439 8a7ddc38 bellard
int qemu_savevm(const char *filename);
440 8a7ddc38 bellard
int register_savevm(const char *idstr, 
441 8a7ddc38 bellard
                    int instance_id, 
442 8a7ddc38 bellard
                    int version_id,
443 8a7ddc38 bellard
                    SaveStateHandler *save_state,
444 8a7ddc38 bellard
                    LoadStateHandler *load_state,
445 8a7ddc38 bellard
                    void *opaque);
446 8a7ddc38 bellard
void qemu_get_timer(QEMUFile *f, QEMUTimer *ts);
447 8a7ddc38 bellard
void qemu_put_timer(QEMUFile *f, QEMUTimer *ts);
448 c4b1fcc0 bellard
449 6a00d601 bellard
void cpu_save(QEMUFile *f, void *opaque);
450 6a00d601 bellard
int cpu_load(QEMUFile *f, void *opaque, int version_id);
451 6a00d601 bellard
452 fc01f7e7 bellard
/* block.c */
453 fc01f7e7 bellard
typedef struct BlockDriverState BlockDriverState;
454 ea2384d3 bellard
typedef struct BlockDriver BlockDriver;
455 ea2384d3 bellard
456 ea2384d3 bellard
extern BlockDriver bdrv_raw;
457 ea2384d3 bellard
extern BlockDriver bdrv_cow;
458 ea2384d3 bellard
extern BlockDriver bdrv_qcow;
459 ea2384d3 bellard
extern BlockDriver bdrv_vmdk;
460 3c56521b bellard
extern BlockDriver bdrv_cloop;
461 585d0ed9 bellard
extern BlockDriver bdrv_dmg;
462 a8753c34 bellard
extern BlockDriver bdrv_bochs;
463 6a0f9e82 bellard
extern BlockDriver bdrv_vpc;
464 de167e41 bellard
extern BlockDriver bdrv_vvfat;
465 ea2384d3 bellard
466 ea2384d3 bellard
void bdrv_init(void);
467 ea2384d3 bellard
BlockDriver *bdrv_find_format(const char *format_name);
468 ea2384d3 bellard
int bdrv_create(BlockDriver *drv, 
469 ea2384d3 bellard
                const char *filename, int64_t size_in_sectors,
470 ea2384d3 bellard
                const char *backing_file, int flags);
471 c4b1fcc0 bellard
BlockDriverState *bdrv_new(const char *device_name);
472 c4b1fcc0 bellard
void bdrv_delete(BlockDriverState *bs);
473 c4b1fcc0 bellard
int bdrv_open(BlockDriverState *bs, const char *filename, int snapshot);
474 ea2384d3 bellard
int bdrv_open2(BlockDriverState *bs, const char *filename, int snapshot,
475 ea2384d3 bellard
               BlockDriver *drv);
476 fc01f7e7 bellard
void bdrv_close(BlockDriverState *bs);
477 fc01f7e7 bellard
int bdrv_read(BlockDriverState *bs, int64_t sector_num, 
478 fc01f7e7 bellard
              uint8_t *buf, int nb_sectors);
479 fc01f7e7 bellard
int bdrv_write(BlockDriverState *bs, int64_t sector_num, 
480 fc01f7e7 bellard
               const uint8_t *buf, int nb_sectors);
481 fc01f7e7 bellard
void bdrv_get_geometry(BlockDriverState *bs, int64_t *nb_sectors_ptr);
482 33e3963e bellard
int bdrv_commit(BlockDriverState *bs);
483 77fef8c1 bellard
void bdrv_set_boot_sector(BlockDriverState *bs, const uint8_t *data, int size);
484 33e3963e bellard
485 c4b1fcc0 bellard
#define BDRV_TYPE_HD     0
486 c4b1fcc0 bellard
#define BDRV_TYPE_CDROM  1
487 c4b1fcc0 bellard
#define BDRV_TYPE_FLOPPY 2
488 46d4767d bellard
#define BIOS_ATA_TRANSLATION_AUTO 0
489 46d4767d bellard
#define BIOS_ATA_TRANSLATION_NONE 1
490 46d4767d bellard
#define BIOS_ATA_TRANSLATION_LBA  2
491 c4b1fcc0 bellard
492 c4b1fcc0 bellard
void bdrv_set_geometry_hint(BlockDriverState *bs, 
493 c4b1fcc0 bellard
                            int cyls, int heads, int secs);
494 c4b1fcc0 bellard
void bdrv_set_type_hint(BlockDriverState *bs, int type);
495 46d4767d bellard
void bdrv_set_translation_hint(BlockDriverState *bs, int translation);
496 c4b1fcc0 bellard
void bdrv_get_geometry_hint(BlockDriverState *bs, 
497 c4b1fcc0 bellard
                            int *pcyls, int *pheads, int *psecs);
498 c4b1fcc0 bellard
int bdrv_get_type_hint(BlockDriverState *bs);
499 46d4767d bellard
int bdrv_get_translation_hint(BlockDriverState *bs);
500 c4b1fcc0 bellard
int bdrv_is_removable(BlockDriverState *bs);
501 c4b1fcc0 bellard
int bdrv_is_read_only(BlockDriverState *bs);
502 c4b1fcc0 bellard
int bdrv_is_inserted(BlockDriverState *bs);
503 c4b1fcc0 bellard
int bdrv_is_locked(BlockDriverState *bs);
504 c4b1fcc0 bellard
void bdrv_set_locked(BlockDriverState *bs, int locked);
505 c4b1fcc0 bellard
void bdrv_set_change_cb(BlockDriverState *bs, 
506 c4b1fcc0 bellard
                        void (*change_cb)(void *opaque), void *opaque);
507 ea2384d3 bellard
void bdrv_get_format(BlockDriverState *bs, char *buf, int buf_size);
508 c4b1fcc0 bellard
void bdrv_info(void);
509 c4b1fcc0 bellard
BlockDriverState *bdrv_find(const char *name);
510 82c643ff bellard
void bdrv_iterate(void (*it)(void *opaque, const char *name), void *opaque);
511 ea2384d3 bellard
int bdrv_is_encrypted(BlockDriverState *bs);
512 ea2384d3 bellard
int bdrv_set_key(BlockDriverState *bs, const char *key);
513 ea2384d3 bellard
void bdrv_iterate_format(void (*it)(void *opaque, const char *name), 
514 ea2384d3 bellard
                         void *opaque);
515 ea2384d3 bellard
const char *bdrv_get_device_name(BlockDriverState *bs);
516 c4b1fcc0 bellard
517 ea2384d3 bellard
int qcow_get_cluster_size(BlockDriverState *bs);
518 ea2384d3 bellard
int qcow_compress_cluster(BlockDriverState *bs, int64_t sector_num,
519 ea2384d3 bellard
                          const uint8_t *buf);
520 ea2384d3 bellard
521 ea2384d3 bellard
#ifndef QEMU_TOOL
522 54fa5af5 bellard
523 54fa5af5 bellard
typedef void QEMUMachineInitFunc(int ram_size, int vga_ram_size, 
524 54fa5af5 bellard
                                 int boot_device,
525 54fa5af5 bellard
             DisplayState *ds, const char **fd_filename, int snapshot,
526 54fa5af5 bellard
             const char *kernel_filename, const char *kernel_cmdline,
527 54fa5af5 bellard
             const char *initrd_filename);
528 54fa5af5 bellard
529 54fa5af5 bellard
typedef struct QEMUMachine {
530 54fa5af5 bellard
    const char *name;
531 54fa5af5 bellard
    const char *desc;
532 54fa5af5 bellard
    QEMUMachineInitFunc *init;
533 54fa5af5 bellard
    struct QEMUMachine *next;
534 54fa5af5 bellard
} QEMUMachine;
535 54fa5af5 bellard
536 54fa5af5 bellard
int qemu_register_machine(QEMUMachine *m);
537 54fa5af5 bellard
538 54fa5af5 bellard
typedef void SetIRQFunc(void *opaque, int irq_num, int level);
539 3de388f6 bellard
typedef void IRQRequestFunc(void *opaque, int level);
540 54fa5af5 bellard
541 26aa7d72 bellard
/* ISA bus */
542 26aa7d72 bellard
543 26aa7d72 bellard
extern target_phys_addr_t isa_mem_base;
544 26aa7d72 bellard
545 26aa7d72 bellard
typedef void (IOPortWriteFunc)(void *opaque, uint32_t address, uint32_t data);
546 26aa7d72 bellard
typedef uint32_t (IOPortReadFunc)(void *opaque, uint32_t address);
547 26aa7d72 bellard
548 26aa7d72 bellard
int register_ioport_read(int start, int length, int size, 
549 26aa7d72 bellard
                         IOPortReadFunc *func, void *opaque);
550 26aa7d72 bellard
int register_ioport_write(int start, int length, int size, 
551 26aa7d72 bellard
                          IOPortWriteFunc *func, void *opaque);
552 69b91039 bellard
void isa_unassign_ioport(int start, int length);
553 69b91039 bellard
554 69b91039 bellard
/* PCI bus */
555 69b91039 bellard
556 69b91039 bellard
extern target_phys_addr_t pci_mem_base;
557 69b91039 bellard
558 46e50e9d bellard
typedef struct PCIBus PCIBus;
559 69b91039 bellard
typedef struct PCIDevice PCIDevice;
560 69b91039 bellard
561 69b91039 bellard
typedef void PCIConfigWriteFunc(PCIDevice *pci_dev, 
562 69b91039 bellard
                                uint32_t address, uint32_t data, int len);
563 69b91039 bellard
typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev, 
564 69b91039 bellard
                                   uint32_t address, int len);
565 69b91039 bellard
typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num, 
566 69b91039 bellard
                                uint32_t addr, uint32_t size, int type);
567 69b91039 bellard
568 69b91039 bellard
#define PCI_ADDRESS_SPACE_MEM                0x00
569 69b91039 bellard
#define PCI_ADDRESS_SPACE_IO                0x01
570 69b91039 bellard
#define PCI_ADDRESS_SPACE_MEM_PREFETCH        0x08
571 69b91039 bellard
572 69b91039 bellard
typedef struct PCIIORegion {
573 5768f5ac bellard
    uint32_t addr; /* current PCI mapping address. -1 means not mapped */
574 69b91039 bellard
    uint32_t size;
575 69b91039 bellard
    uint8_t type;
576 69b91039 bellard
    PCIMapIORegionFunc *map_func;
577 69b91039 bellard
} PCIIORegion;
578 69b91039 bellard
579 8a8696a3 bellard
#define PCI_ROM_SLOT 6
580 8a8696a3 bellard
#define PCI_NUM_REGIONS 7
581 69b91039 bellard
struct PCIDevice {
582 69b91039 bellard
    /* PCI config space */
583 69b91039 bellard
    uint8_t config[256];
584 69b91039 bellard
585 69b91039 bellard
    /* the following fields are read only */
586 46e50e9d bellard
    PCIBus *bus;
587 69b91039 bellard
    int devfn;
588 69b91039 bellard
    char name[64];
589 8a8696a3 bellard
    PCIIORegion io_regions[PCI_NUM_REGIONS];
590 69b91039 bellard
    
591 69b91039 bellard
    /* do not access the following fields */
592 69b91039 bellard
    PCIConfigReadFunc *config_read;
593 69b91039 bellard
    PCIConfigWriteFunc *config_write;
594 5768f5ac bellard
    int irq_index;
595 69b91039 bellard
};
596 69b91039 bellard
597 46e50e9d bellard
PCIDevice *pci_register_device(PCIBus *bus, const char *name,
598 46e50e9d bellard
                               int instance_size, int devfn,
599 69b91039 bellard
                               PCIConfigReadFunc *config_read, 
600 69b91039 bellard
                               PCIConfigWriteFunc *config_write);
601 69b91039 bellard
602 69b91039 bellard
void pci_register_io_region(PCIDevice *pci_dev, int region_num, 
603 69b91039 bellard
                            uint32_t size, int type, 
604 69b91039 bellard
                            PCIMapIORegionFunc *map_func);
605 69b91039 bellard
606 5768f5ac bellard
void pci_set_irq(PCIDevice *pci_dev, int irq_num, int level);
607 5768f5ac bellard
608 5768f5ac bellard
uint32_t pci_default_read_config(PCIDevice *d, 
609 5768f5ac bellard
                                 uint32_t address, int len);
610 5768f5ac bellard
void pci_default_write_config(PCIDevice *d, 
611 5768f5ac bellard
                              uint32_t address, uint32_t val, int len);
612 30ca2aab bellard
void generic_pci_save(QEMUFile* f, void *opaque);
613 30ca2aab bellard
int generic_pci_load(QEMUFile* f, void *opaque, int version_id);
614 5768f5ac bellard
615 9995c51f bellard
extern struct PIIX3State *piix3_state;
616 9995c51f bellard
617 46e50e9d bellard
PCIBus *i440fx_init(void);
618 46e50e9d bellard
void piix3_init(PCIBus *bus);
619 69b91039 bellard
void pci_bios_init(void);
620 5768f5ac bellard
void pci_info(void);
621 26aa7d72 bellard
622 77d4bc34 bellard
/* temporary: will be moved in platform specific file */
623 54fa5af5 bellard
void pci_set_pic(PCIBus *bus, SetIRQFunc *set_irq, void *irq_opaque);
624 46e50e9d bellard
PCIBus *pci_prep_init(void);
625 54fa5af5 bellard
PCIBus *pci_grackle_init(uint32_t base);
626 46e50e9d bellard
PCIBus *pci_pmac_init(void);
627 83469015 bellard
PCIBus *pci_apb_init(target_ulong special_base, target_ulong mem_base);
628 77d4bc34 bellard
629 a41b2ff2 pbrook
void pci_nic_init(PCIBus *bus, NICInfo *nd);
630 a41b2ff2 pbrook
631 28b9b5af bellard
/* openpic.c */
632 28b9b5af bellard
typedef struct openpic_t openpic_t;
633 54fa5af5 bellard
void openpic_set_irq(void *opaque, int n_IRQ, int level);
634 7668a27f bellard
openpic_t *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus,
635 7668a27f bellard
                         CPUState **envp);
636 28b9b5af bellard
637 54fa5af5 bellard
/* heathrow_pic.c */
638 54fa5af5 bellard
typedef struct HeathrowPICS HeathrowPICS;
639 54fa5af5 bellard
void heathrow_pic_set_irq(void *opaque, int num, int level);
640 54fa5af5 bellard
HeathrowPICS *heathrow_pic_init(int *pmem_index);
641 54fa5af5 bellard
642 6a36d84e bellard
#ifdef HAS_AUDIO
643 6a36d84e bellard
struct soundhw {
644 6a36d84e bellard
    const char *name;
645 6a36d84e bellard
    const char *descr;
646 6a36d84e bellard
    int enabled;
647 6a36d84e bellard
    int isa;
648 6a36d84e bellard
    union {
649 6a36d84e bellard
        int (*init_isa) (AudioState *s);
650 6a36d84e bellard
        int (*init_pci) (PCIBus *bus, AudioState *s);
651 6a36d84e bellard
    } init;
652 6a36d84e bellard
};
653 6a36d84e bellard
654 6a36d84e bellard
extern struct soundhw soundhw[];
655 6a36d84e bellard
#endif
656 6a36d84e bellard
657 313aa567 bellard
/* vga.c */
658 313aa567 bellard
659 4fa0f5d2 bellard
#define VGA_RAM_SIZE (4096 * 1024)
660 313aa567 bellard
661 82c643ff bellard
struct DisplayState {
662 313aa567 bellard
    uint8_t *data;
663 313aa567 bellard
    int linesize;
664 313aa567 bellard
    int depth;
665 82c643ff bellard
    int width;
666 82c643ff bellard
    int height;
667 313aa567 bellard
    void (*dpy_update)(struct DisplayState *s, int x, int y, int w, int h);
668 313aa567 bellard
    void (*dpy_resize)(struct DisplayState *s, int w, int h);
669 313aa567 bellard
    void (*dpy_refresh)(struct DisplayState *s);
670 82c643ff bellard
};
671 313aa567 bellard
672 313aa567 bellard
static inline void dpy_update(DisplayState *s, int x, int y, int w, int h)
673 313aa567 bellard
{
674 313aa567 bellard
    s->dpy_update(s, x, y, w, h);
675 313aa567 bellard
}
676 313aa567 bellard
677 313aa567 bellard
static inline void dpy_resize(DisplayState *s, int w, int h)
678 313aa567 bellard
{
679 313aa567 bellard
    s->dpy_resize(s, w, h);
680 313aa567 bellard
}
681 313aa567 bellard
682 46e50e9d bellard
int vga_initialize(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base, 
683 d5295253 bellard
                   unsigned long vga_ram_offset, int vga_ram_size,
684 d5295253 bellard
                   unsigned long vga_bios_offset, int vga_bios_size);
685 313aa567 bellard
686 d6bfa22f bellard
/* cirrus_vga.c */
687 46e50e9d bellard
void pci_cirrus_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base, 
688 d6bfa22f bellard
                         unsigned long vga_ram_offset, int vga_ram_size);
689 d6bfa22f bellard
void isa_cirrus_vga_init(DisplayState *ds, uint8_t *vga_ram_base, 
690 d6bfa22f bellard
                         unsigned long vga_ram_offset, int vga_ram_size);
691 d6bfa22f bellard
692 313aa567 bellard
/* sdl.c */
693 d63d307f bellard
void sdl_display_init(DisplayState *ds, int full_screen);
694 313aa567 bellard
695 da4dbf74 bellard
/* cocoa.m */
696 da4dbf74 bellard
void cocoa_display_init(DisplayState *ds, int full_screen);
697 da4dbf74 bellard
698 5391d806 bellard
/* ide.c */
699 5391d806 bellard
#define MAX_DISKS 4
700 5391d806 bellard
701 5391d806 bellard
extern BlockDriverState *bs_table[MAX_DISKS];
702 5391d806 bellard
703 69b91039 bellard
void isa_ide_init(int iobase, int iobase2, int irq,
704 69b91039 bellard
                  BlockDriverState *hd0, BlockDriverState *hd1);
705 54fa5af5 bellard
void pci_cmd646_ide_init(PCIBus *bus, BlockDriverState **hd_table,
706 54fa5af5 bellard
                         int secondary_ide_enabled);
707 46e50e9d bellard
void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table);
708 28b9b5af bellard
int pmac_ide_init (BlockDriverState **hd_table,
709 54fa5af5 bellard
                   SetIRQFunc *set_irq, void *irq_opaque, int irq);
710 5391d806 bellard
711 1d14ffa9 bellard
/* es1370.c */
712 c0fe3827 bellard
int es1370_init (PCIBus *bus, AudioState *s);
713 1d14ffa9 bellard
714 fb065187 bellard
/* sb16.c */
715 c0fe3827 bellard
int SB16_init (AudioState *s);
716 fb065187 bellard
717 fb065187 bellard
/* adlib.c */
718 c0fe3827 bellard
int Adlib_init (AudioState *s);
719 fb065187 bellard
720 fb065187 bellard
/* gus.c */
721 c0fe3827 bellard
int GUS_init (AudioState *s);
722 27503323 bellard
723 27503323 bellard
/* dma.c */
724 85571bc7 bellard
typedef int (*DMA_transfer_handler) (void *opaque, int nchan, int pos, int size);
725 27503323 bellard
int DMA_get_channel_mode (int nchan);
726 85571bc7 bellard
int DMA_read_memory (int nchan, void *buf, int pos, int size);
727 85571bc7 bellard
int DMA_write_memory (int nchan, void *buf, int pos, int size);
728 27503323 bellard
void DMA_hold_DREQ (int nchan);
729 27503323 bellard
void DMA_release_DREQ (int nchan);
730 16f62432 bellard
void DMA_schedule(int nchan);
731 27503323 bellard
void DMA_run (void);
732 28b9b5af bellard
void DMA_init (int high_page_enable);
733 27503323 bellard
void DMA_register_channel (int nchan,
734 85571bc7 bellard
                           DMA_transfer_handler transfer_handler,
735 85571bc7 bellard
                           void *opaque);
736 7138fcfb bellard
/* fdc.c */
737 7138fcfb bellard
#define MAX_FD 2
738 7138fcfb bellard
extern BlockDriverState *fd_table[MAX_FD];
739 7138fcfb bellard
740 baca51fa bellard
typedef struct fdctrl_t fdctrl_t;
741 baca51fa bellard
742 baca51fa bellard
fdctrl_t *fdctrl_init (int irq_lvl, int dma_chann, int mem_mapped, 
743 baca51fa bellard
                       uint32_t io_base,
744 baca51fa bellard
                       BlockDriverState **fds);
745 baca51fa bellard
int fdctrl_get_drive_type(fdctrl_t *fdctrl, int drive_num);
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747 80cabfad bellard
/* ne2000.c */
748 80cabfad bellard
749 7c9d8e07 bellard
void isa_ne2000_init(int base, int irq, NICInfo *nd);
750 7c9d8e07 bellard
void pci_ne2000_init(PCIBus *bus, NICInfo *nd);
751 80cabfad bellard
752 a41b2ff2 pbrook
/* rtl8139.c */
753 a41b2ff2 pbrook
754 a41b2ff2 pbrook
void pci_rtl8139_init(PCIBus *bus, NICInfo *nd);
755 a41b2ff2 pbrook
756 80cabfad bellard
/* pckbd.c */
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758 80cabfad bellard
void kbd_init(void);
759 80cabfad bellard
760 80cabfad bellard
/* mc146818rtc.c */
761 80cabfad bellard
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typedef struct RTCState RTCState;
763 80cabfad bellard
764 8a7ddc38 bellard
RTCState *rtc_init(int base, int irq);
765 8a7ddc38 bellard
void rtc_set_memory(RTCState *s, int addr, int val);
766 8a7ddc38 bellard
void rtc_set_date(RTCState *s, const struct tm *tm);
767 80cabfad bellard
768 80cabfad bellard
/* serial.c */
769 80cabfad bellard
770 c4b1fcc0 bellard
typedef struct SerialState SerialState;
771 e5d13e2f bellard
SerialState *serial_init(SetIRQFunc *set_irq, void *opaque,
772 e5d13e2f bellard
                         int base, int irq, CharDriverState *chr);
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SerialState *serial_mm_init (SetIRQFunc *set_irq, void *opaque,
774 e5d13e2f bellard
                             target_ulong base, int it_shift,
775 e5d13e2f bellard
                             int irq, CharDriverState *chr);
776 80cabfad bellard
777 6508fe59 bellard
/* parallel.c */
778 6508fe59 bellard
779 6508fe59 bellard
typedef struct ParallelState ParallelState;
780 6508fe59 bellard
ParallelState *parallel_init(int base, int irq, CharDriverState *chr);
781 6508fe59 bellard
782 80cabfad bellard
/* i8259.c */
783 80cabfad bellard
784 3de388f6 bellard
typedef struct PicState2 PicState2;
785 3de388f6 bellard
extern PicState2 *isa_pic;
786 80cabfad bellard
void pic_set_irq(int irq, int level);
787 54fa5af5 bellard
void pic_set_irq_new(void *opaque, int irq, int level);
788 3de388f6 bellard
PicState2 *pic_init(IRQRequestFunc *irq_request, void *irq_request_opaque);
789 d592d303 bellard
void pic_set_alt_irq_func(PicState2 *s, SetIRQFunc *alt_irq_func,
790 d592d303 bellard
                          void *alt_irq_opaque);
791 3de388f6 bellard
int pic_read_irq(PicState2 *s);
792 3de388f6 bellard
void pic_update_irq(PicState2 *s);
793 3de388f6 bellard
uint32_t pic_intack_read(PicState2 *s);
794 c20709aa bellard
void pic_info(void);
795 4a0fb71e bellard
void irq_info(void);
796 80cabfad bellard
797 c27004ec bellard
/* APIC */
798 d592d303 bellard
typedef struct IOAPICState IOAPICState;
799 d592d303 bellard
800 c27004ec bellard
int apic_init(CPUState *env);
801 c27004ec bellard
int apic_get_interrupt(CPUState *env);
802 d592d303 bellard
IOAPICState *ioapic_init(void);
803 d592d303 bellard
void ioapic_set_irq(void *opaque, int vector, int level);
804 c27004ec bellard
805 80cabfad bellard
/* i8254.c */
806 80cabfad bellard
807 80cabfad bellard
#define PIT_FREQ 1193182
808 80cabfad bellard
809 ec844b96 bellard
typedef struct PITState PITState;
810 ec844b96 bellard
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PITState *pit_init(int base, int irq);
812 ec844b96 bellard
void pit_set_gate(PITState *pit, int channel, int val);
813 ec844b96 bellard
int pit_get_gate(PITState *pit, int channel);
814 ec844b96 bellard
int pit_get_out(PITState *pit, int channel, int64_t current_time);
815 80cabfad bellard
816 80cabfad bellard
/* pc.c */
817 54fa5af5 bellard
extern QEMUMachine pc_machine;
818 3dbbdc25 bellard
extern QEMUMachine isapc_machine;
819 80cabfad bellard
820 6a00d601 bellard
void ioport_set_a20(int enable);
821 6a00d601 bellard
int ioport_get_a20(void);
822 6a00d601 bellard
823 26aa7d72 bellard
/* ppc.c */
824 54fa5af5 bellard
extern QEMUMachine prep_machine;
825 54fa5af5 bellard
extern QEMUMachine core99_machine;
826 54fa5af5 bellard
extern QEMUMachine heathrow_machine;
827 54fa5af5 bellard
828 6af0bf9c bellard
/* mips_r4k.c */
829 6af0bf9c bellard
extern QEMUMachine mips_machine;
830 6af0bf9c bellard
831 8cc43fef bellard
#ifdef TARGET_PPC
832 8cc43fef bellard
ppc_tb_t *cpu_ppc_tb_init (CPUState *env, uint32_t freq);
833 8cc43fef bellard
#endif
834 64201201 bellard
void PREP_debug_write (void *opaque, uint32_t addr, uint32_t val);
835 77d4bc34 bellard
836 77d4bc34 bellard
extern CPUWriteMemoryFunc *PPC_io_write[];
837 77d4bc34 bellard
extern CPUReadMemoryFunc *PPC_io_read[];
838 54fa5af5 bellard
void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val);
839 26aa7d72 bellard
840 e95c8d51 bellard
/* sun4m.c */
841 54fa5af5 bellard
extern QEMUMachine sun4m_machine;
842 e80cfcfc bellard
uint32_t iommu_translate(uint32_t addr);
843 ba3c64fb bellard
void pic_set_irq_cpu(int irq, int level, unsigned int cpu);
844 e95c8d51 bellard
845 e95c8d51 bellard
/* iommu.c */
846 e80cfcfc bellard
void *iommu_init(uint32_t addr);
847 e80cfcfc bellard
uint32_t iommu_translate_local(void *opaque, uint32_t addr);
848 e95c8d51 bellard
849 e95c8d51 bellard
/* lance.c */
850 7c9d8e07 bellard
void lance_init(NICInfo *nd, int irq, uint32_t leaddr, uint32_t ledaddr);
851 e95c8d51 bellard
852 e95c8d51 bellard
/* tcx.c */
853 95219897 pbrook
void tcx_init(DisplayState *ds, uint32_t addr, uint8_t *vram_base,
854 6f7e9aec bellard
               unsigned long vram_offset, int vram_size, int width, int height);
855 e80cfcfc bellard
856 e80cfcfc bellard
/* slavio_intctl.c */
857 e80cfcfc bellard
void *slavio_intctl_init();
858 ba3c64fb bellard
void slavio_intctl_set_cpu(void *opaque, unsigned int cpu, CPUState *env);
859 e80cfcfc bellard
void slavio_pic_info(void *opaque);
860 e80cfcfc bellard
void slavio_irq_info(void *opaque);
861 e80cfcfc bellard
void slavio_pic_set_irq(void *opaque, int irq, int level);
862 ba3c64fb bellard
void slavio_pic_set_irq_cpu(void *opaque, int irq, int level, unsigned int cpu);
863 e95c8d51 bellard
864 e95c8d51 bellard
/* magic-load.c */
865 e80cfcfc bellard
int load_elf(const char *filename, uint8_t *addr);
866 e80cfcfc bellard
int load_aout(const char *filename, uint8_t *addr);
867 e80cfcfc bellard
868 e80cfcfc bellard
/* slavio_timer.c */
869 ba3c64fb bellard
void slavio_timer_init(uint32_t addr, int irq, int mode, unsigned int cpu);
870 8d5f07fa bellard
871 e80cfcfc bellard
/* slavio_serial.c */
872 e80cfcfc bellard
SerialState *slavio_serial_init(int base, int irq, CharDriverState *chr1, CharDriverState *chr2);
873 e80cfcfc bellard
void slavio_serial_ms_kbd_init(int base, int irq);
874 e95c8d51 bellard
875 3475187d bellard
/* slavio_misc.c */
876 3475187d bellard
void *slavio_misc_init(uint32_t base, int irq);
877 3475187d bellard
void slavio_set_power_fail(void *opaque, int power_failing);
878 3475187d bellard
879 6f7e9aec bellard
/* esp.c */
880 6f7e9aec bellard
void esp_init(BlockDriverState **bd, int irq, uint32_t espaddr, uint32_t espdaddr);
881 6f7e9aec bellard
882 3475187d bellard
/* sun4u.c */
883 3475187d bellard
extern QEMUMachine sun4u_machine;
884 3475187d bellard
885 64201201 bellard
/* NVRAM helpers */
886 64201201 bellard
#include "hw/m48t59.h"
887 64201201 bellard
888 64201201 bellard
void NVRAM_set_byte (m48t59_t *nvram, uint32_t addr, uint8_t value);
889 64201201 bellard
uint8_t NVRAM_get_byte (m48t59_t *nvram, uint32_t addr);
890 64201201 bellard
void NVRAM_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value);
891 64201201 bellard
uint16_t NVRAM_get_word (m48t59_t *nvram, uint32_t addr);
892 64201201 bellard
void NVRAM_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value);
893 64201201 bellard
uint32_t NVRAM_get_lword (m48t59_t *nvram, uint32_t addr);
894 64201201 bellard
void NVRAM_set_string (m48t59_t *nvram, uint32_t addr,
895 64201201 bellard
                       const unsigned char *str, uint32_t max);
896 64201201 bellard
int NVRAM_get_string (m48t59_t *nvram, uint8_t *dst, uint16_t addr, int max);
897 64201201 bellard
void NVRAM_set_crc (m48t59_t *nvram, uint32_t addr,
898 64201201 bellard
                    uint32_t start, uint32_t count);
899 64201201 bellard
int PPC_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
900 64201201 bellard
                          const unsigned char *arch,
901 64201201 bellard
                          uint32_t RAM_size, int boot_device,
902 64201201 bellard
                          uint32_t kernel_image, uint32_t kernel_size,
903 28b9b5af bellard
                          const char *cmdline,
904 64201201 bellard
                          uint32_t initrd_image, uint32_t initrd_size,
905 28b9b5af bellard
                          uint32_t NVRAM_image,
906 28b9b5af bellard
                          int width, int height, int depth);
907 64201201 bellard
908 63066f4f bellard
/* adb.c */
909 63066f4f bellard
910 63066f4f bellard
#define MAX_ADB_DEVICES 16
911 63066f4f bellard
912 e2733d20 bellard
#define ADB_MAX_OUT_LEN 16
913 63066f4f bellard
914 e2733d20 bellard
typedef struct ADBDevice ADBDevice;
915 63066f4f bellard
916 e2733d20 bellard
/* buf = NULL means polling */
917 e2733d20 bellard
typedef int ADBDeviceRequest(ADBDevice *d, uint8_t *buf_out,
918 e2733d20 bellard
                              const uint8_t *buf, int len);
919 12c28fed bellard
typedef int ADBDeviceReset(ADBDevice *d);
920 12c28fed bellard
921 63066f4f bellard
struct ADBDevice {
922 63066f4f bellard
    struct ADBBusState *bus;
923 63066f4f bellard
    int devaddr;
924 63066f4f bellard
    int handler;
925 e2733d20 bellard
    ADBDeviceRequest *devreq;
926 12c28fed bellard
    ADBDeviceReset *devreset;
927 63066f4f bellard
    void *opaque;
928 63066f4f bellard
};
929 63066f4f bellard
930 63066f4f bellard
typedef struct ADBBusState {
931 63066f4f bellard
    ADBDevice devices[MAX_ADB_DEVICES];
932 63066f4f bellard
    int nb_devices;
933 e2733d20 bellard
    int poll_index;
934 63066f4f bellard
} ADBBusState;
935 63066f4f bellard
936 e2733d20 bellard
int adb_request(ADBBusState *s, uint8_t *buf_out,
937 e2733d20 bellard
                const uint8_t *buf, int len);
938 e2733d20 bellard
int adb_poll(ADBBusState *s, uint8_t *buf_out);
939 63066f4f bellard
940 63066f4f bellard
ADBDevice *adb_register_device(ADBBusState *s, int devaddr, 
941 e2733d20 bellard
                               ADBDeviceRequest *devreq, 
942 12c28fed bellard
                               ADBDeviceReset *devreset, 
943 63066f4f bellard
                               void *opaque);
944 63066f4f bellard
void adb_kbd_init(ADBBusState *bus);
945 63066f4f bellard
void adb_mouse_init(ADBBusState *bus);
946 63066f4f bellard
947 63066f4f bellard
/* cuda.c */
948 63066f4f bellard
949 63066f4f bellard
extern ADBBusState adb_bus;
950 54fa5af5 bellard
int cuda_init(SetIRQFunc *set_irq, void *irq_opaque, int irq);
951 63066f4f bellard
952 bb36d470 bellard
#include "hw/usb.h"
953 bb36d470 bellard
954 a594cfbf bellard
/* usb ports of the VM */
955 a594cfbf bellard
956 a594cfbf bellard
#define MAX_VM_USB_PORTS 8
957 a594cfbf bellard
958 a594cfbf bellard
extern USBPort *vm_usb_ports[MAX_VM_USB_PORTS];
959 a594cfbf bellard
extern USBDevice *vm_usb_hub;
960 a594cfbf bellard
961 a594cfbf bellard
void do_usb_add(const char *devname);
962 a594cfbf bellard
void do_usb_del(const char *devname);
963 a594cfbf bellard
void usb_info(void);
964 a594cfbf bellard
965 b5ff1b31 bellard
/* integratorcp.c */
966 40f137e1 pbrook
extern QEMUMachine integratorcp926_machine;
967 40f137e1 pbrook
extern QEMUMachine integratorcp1026_machine;
968 b5ff1b31 bellard
969 daa57963 bellard
/* ps2.c */
970 daa57963 bellard
void *ps2_kbd_init(void (*update_irq)(void *, int), void *update_arg);
971 daa57963 bellard
void *ps2_mouse_init(void (*update_irq)(void *, int), void *update_arg);
972 daa57963 bellard
void ps2_write_mouse(void *, int val);
973 daa57963 bellard
void ps2_write_keyboard(void *, int val);
974 daa57963 bellard
uint32_t ps2_read_data(void *);
975 daa57963 bellard
void ps2_queue(void *, int b);
976 f94f5d71 pbrook
void ps2_keyboard_set_translation(void *opaque, int mode);
977 daa57963 bellard
978 80337b66 bellard
/* smc91c111.c */
979 80337b66 bellard
void smc91c111_init(NICInfo *, uint32_t, void *, int);
980 80337b66 bellard
981 bdd5003a pbrook
/* pl110.c */
982 95219897 pbrook
void *pl110_init(DisplayState *ds, uint32_t base, void *pic, int irq, int);
983 bdd5003a pbrook
984 ea2384d3 bellard
#endif /* defined(QEMU_TOOL) */
985 ea2384d3 bellard
986 c4b1fcc0 bellard
/* monitor.c */
987 82c643ff bellard
void monitor_init(CharDriverState *hd, int show_banner);
988 ea2384d3 bellard
void term_puts(const char *str);
989 ea2384d3 bellard
void term_vprintf(const char *fmt, va_list ap);
990 40c3bac3 bellard
void term_printf(const char *fmt, ...) __attribute__ ((__format__ (__printf__, 1, 2)));
991 c4b1fcc0 bellard
void term_flush(void);
992 c4b1fcc0 bellard
void term_print_help(void);
993 ea2384d3 bellard
void monitor_readline(const char *prompt, int is_password,
994 ea2384d3 bellard
                      char *buf, int buf_size);
995 ea2384d3 bellard
996 ea2384d3 bellard
/* readline.c */
997 ea2384d3 bellard
typedef void ReadLineFunc(void *opaque, const char *str);
998 ea2384d3 bellard
999 ea2384d3 bellard
extern int completion_index;
1000 ea2384d3 bellard
void add_completion(const char *str);
1001 ea2384d3 bellard
void readline_handle_byte(int ch);
1002 ea2384d3 bellard
void readline_find_completion(const char *cmdline);
1003 ea2384d3 bellard
const char *readline_get_history(unsigned int index);
1004 ea2384d3 bellard
void readline_start(const char *prompt, int is_password,
1005 ea2384d3 bellard
                    ReadLineFunc *readline_func, void *opaque);
1006 c4b1fcc0 bellard
1007 5e6ad6f9 bellard
void kqemu_record_dump(void);
1008 5e6ad6f9 bellard
1009 fc01f7e7 bellard
#endif /* VL_H */