Revision 9543b0cd
b/hw/arm-misc.h | ||
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50 | 50 |
* perform any necessary CPU reset handling and set the PC for thei |
51 | 51 |
* secondary CPUs to point at this boot blob. |
52 | 52 |
*/ |
53 |
void (*write_secondary_boot)(CPUARMState *env,
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void (*write_secondary_boot)(ARMCPU *cpu,
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54 | 54 |
const struct arm_boot_info *info); |
55 | 55 |
void (*secondary_cpu_reset_hook)(CPUARMState *env, |
56 | 56 |
const struct arm_boot_info *info); |
b/hw/arm_boot.c | ||
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59 | 59 |
0 /* bootreg: Boot register address is held here */ |
60 | 60 |
}; |
61 | 61 |
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62 |
static void default_write_secondary(CPUARMState *env,
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static void default_write_secondary(ARMCPU *cpu,
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63 | 63 |
const struct arm_boot_info *info) |
64 | 64 |
{ |
65 | 65 |
int n; |
... | ... | |
303 | 303 |
|
304 | 304 |
void arm_load_kernel(CPUARMState *env, struct arm_boot_info *info) |
305 | 305 |
{ |
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ARMCPU *cpu; |
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ARMCPU *cpu = arm_env_get_cpu(env);
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307 | 307 |
int kernel_size; |
308 | 308 |
int initrd_size; |
309 | 309 |
int n; |
... | ... | |
402 | 402 |
rom_add_blob_fixed("bootloader", bootloader, sizeof(bootloader), |
403 | 403 |
info->loader_start); |
404 | 404 |
if (info->nb_cpus > 1) { |
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info->write_secondary_boot(env, info);
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info->write_secondary_boot(cpu, info);
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406 | 406 |
} |
407 | 407 |
} |
408 | 408 |
info->is_linux = is_linux; |
b/hw/exynos4210.c | ||
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65 | 65 |
static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43, |
66 | 66 |
0x09, 0x00, 0x00, 0x00 }; |
67 | 67 |
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void exynos4210_write_secondary(CPUARMState *env,
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void exynos4210_write_secondary(ARMCPU *cpu,
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69 | 69 |
const struct arm_boot_info *info) |
70 | 70 |
{ |
71 | 71 |
int n; |
b/hw/exynos4210.h | ||
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97 | 97 |
MemoryRegion bootreg_mem; |
98 | 98 |
} Exynos4210State; |
99 | 99 |
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100 |
void exynos4210_write_secondary(CPUARMState *env,
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void exynos4210_write_secondary(ARMCPU *cpu,
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101 | 101 |
const struct arm_boot_info *info); |
102 | 102 |
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103 | 103 |
Exynos4210State *exynos4210_init(MemoryRegion *system_mem, |
b/hw/highbank.c | ||
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36 | 36 |
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37 | 37 |
/* Board init. */ |
38 | 38 |
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static void hb_write_secondary(CPUARMState *env, const struct arm_boot_info *info)
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static void hb_write_secondary(ARMCPU *cpu, const struct arm_boot_info *info)
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40 | 40 |
{ |
41 | 41 |
int n; |
42 | 42 |
uint32_t smpboot[] = { |
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