Revision 9543b0cd

b/hw/arm-misc.h
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     * perform any necessary CPU reset handling and set the PC for thei
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     * secondary CPUs to point at this boot blob.
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     */
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    void (*write_secondary_boot)(CPUARMState *env,
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    void (*write_secondary_boot)(ARMCPU *cpu,
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                                 const struct arm_boot_info *info);
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    void (*secondary_cpu_reset_hook)(CPUARMState *env,
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                                     const struct arm_boot_info *info);
b/hw/arm_boot.c
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  0           /* bootreg: Boot register address is held here */
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};
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static void default_write_secondary(CPUARMState *env,
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static void default_write_secondary(ARMCPU *cpu,
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                                    const struct arm_boot_info *info)
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{
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    int n;
......
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void arm_load_kernel(CPUARMState *env, struct arm_boot_info *info)
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{
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    ARMCPU *cpu;
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    ARMCPU *cpu = arm_env_get_cpu(env);
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    int kernel_size;
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    int initrd_size;
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    int n;
......
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        rom_add_blob_fixed("bootloader", bootloader, sizeof(bootloader),
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                           info->loader_start);
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        if (info->nb_cpus > 1) {
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            info->write_secondary_boot(env, info);
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            info->write_secondary_boot(cpu, info);
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        }
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    }
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    info->is_linux = is_linux;
b/hw/exynos4210.c
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static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43,
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                                    0x09, 0x00, 0x00, 0x00 };
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void exynos4210_write_secondary(CPUARMState *env,
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void exynos4210_write_secondary(ARMCPU *cpu,
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        const struct arm_boot_info *info)
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{
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    int n;
b/hw/exynos4210.h
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    MemoryRegion bootreg_mem;
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} Exynos4210State;
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void exynos4210_write_secondary(CPUARMState *env,
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void exynos4210_write_secondary(ARMCPU *cpu,
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        const struct arm_boot_info *info);
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Exynos4210State *exynos4210_init(MemoryRegion *system_mem,
b/hw/highbank.c
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/* Board init.  */
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static void hb_write_secondary(CPUARMState *env, const struct arm_boot_info *info)
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static void hb_write_secondary(ARMCPU *cpu, const struct arm_boot_info *info)
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{
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    int n;
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    uint32_t smpboot[] = {

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