Revision 956a3e6b hw/pc.c

b/hw/pc.c
365 365
    rtc_set_memory(s, 0x39, val);
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}
367 367

  
368
void ioport_set_a20(int enable)
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static void handle_a20_line_change(void *opaque, int irq, int level)
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{
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    /* XXX: send to all CPUs ? */
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    cpu_x86_set_a20(first_cpu, enable);
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}
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int ioport_get_a20(void)
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{
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    return ((first_cpu->a20_mask >> 20) & 1);
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}
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static void ioport92_write(void *opaque, uint32_t addr, uint32_t val)
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{
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    ioport_set_a20((val >> 1) & 1);
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    /* XXX: bit 0 is fast reset */
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}
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    CPUState *cpu = opaque;
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static uint32_t ioport92_read(void *opaque, uint32_t addr)
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{
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    return ioport_get_a20() << 1;
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    /* XXX: send to all CPUs ? */
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    cpu_x86_set_a20(cpu, level);
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}
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/***********************************************************/
......
935 921
    int i;
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    DriveInfo *fd[MAX_FD];
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    PITState *pit;
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    qemu_irq *a20_line;
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    ISADevice *i8042;
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939 927
    register_ioport_write(0x80, 1, 1, ioport80_write, NULL);
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......
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    qemu_register_boot_set(pc_boot_set, *rtc_state);
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947
    register_ioport_read(0x92, 1, 1, ioport92_read, NULL);
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    register_ioport_write(0x92, 1, 1, ioport92_write, NULL);
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    pit = pit_init(0x40, isa_reserve_irq(0));
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    pcspk_init(pit);
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    if (!no_hpet) {
......
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        }
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    }
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    isa_create_simple("i8042");
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    a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 1);
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    i8042 = isa_create_simple("i8042");
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    i8042_setup_a20_line(i8042, a20_line);
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    vmmouse_init(i8042);
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    DMA_init(0);
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    for(i = 0; i < MAX_FD; i++) {

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