root / hw / pl061.c @ 9596ebb7
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1 | 9ee6e8bb | pbrook | /*
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2 | 9ee6e8bb | pbrook | * Arm PrimeCell PL061 General Purpose IO with additional
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3 | 9ee6e8bb | pbrook | * Luminary Micro Stellaris bits.
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4 | 9ee6e8bb | pbrook | *
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5 | 9ee6e8bb | pbrook | * Copyright (c) 2007 CodeSourcery.
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6 | 9ee6e8bb | pbrook | * Written by Paul Brook
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7 | 9ee6e8bb | pbrook | *
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8 | 9ee6e8bb | pbrook | * This code is licenced under the GPL.
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9 | 9ee6e8bb | pbrook | */
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10 | 9ee6e8bb | pbrook | |
11 | 87ecb68b | pbrook | #include "hw.h" |
12 | 87ecb68b | pbrook | #include "primecell.h" |
13 | 9ee6e8bb | pbrook | |
14 | 9ee6e8bb | pbrook | //#define DEBUG_PL061 1
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15 | 9ee6e8bb | pbrook | |
16 | 9ee6e8bb | pbrook | #ifdef DEBUG_PL061
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17 | 9ee6e8bb | pbrook | #define DPRINTF(fmt, args...) \
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18 | 9ee6e8bb | pbrook | do { printf("pl061: " fmt , ##args); } while (0) |
19 | 9ee6e8bb | pbrook | #define BADF(fmt, args...) \
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20 | 9ee6e8bb | pbrook | do { fprintf(stderr, "pl061: error: " fmt , ##args); exit(1);} while (0) |
21 | 9ee6e8bb | pbrook | #else
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22 | 9ee6e8bb | pbrook | #define DPRINTF(fmt, args...) do {} while(0) |
23 | 9ee6e8bb | pbrook | #define BADF(fmt, args...) \
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24 | 9ee6e8bb | pbrook | do { fprintf(stderr, "pl061: error: " fmt , ##args);} while (0) |
25 | 9ee6e8bb | pbrook | #endif
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26 | 9ee6e8bb | pbrook | |
27 | 9ee6e8bb | pbrook | static const uint8_t pl061_id[12] = |
28 | 9ee6e8bb | pbrook | { 0x00, 0x00, 0x00, 0x00, 0x61, 0x00, 0x18, 0x01, 0x0d, 0xf0, 0x05, 0xb1 }; |
29 | 9ee6e8bb | pbrook | |
30 | 9ee6e8bb | pbrook | typedef struct { |
31 | 9ee6e8bb | pbrook | uint32_t base; |
32 | 9ee6e8bb | pbrook | int locked;
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33 | 9ee6e8bb | pbrook | uint8_t data; |
34 | 9ee6e8bb | pbrook | uint8_t old_data; |
35 | 9ee6e8bb | pbrook | uint8_t dir; |
36 | 9ee6e8bb | pbrook | uint8_t isense; |
37 | 9ee6e8bb | pbrook | uint8_t ibe; |
38 | 9ee6e8bb | pbrook | uint8_t iev; |
39 | 9ee6e8bb | pbrook | uint8_t im; |
40 | 9ee6e8bb | pbrook | uint8_t istate; |
41 | 9ee6e8bb | pbrook | uint8_t afsel; |
42 | 9ee6e8bb | pbrook | uint8_t dr2r; |
43 | 9ee6e8bb | pbrook | uint8_t dr4r; |
44 | 9ee6e8bb | pbrook | uint8_t dr8r; |
45 | 9ee6e8bb | pbrook | uint8_t odr; |
46 | 9ee6e8bb | pbrook | uint8_t pur; |
47 | 9ee6e8bb | pbrook | uint8_t pdr; |
48 | 9ee6e8bb | pbrook | uint8_t slr; |
49 | 9ee6e8bb | pbrook | uint8_t den; |
50 | 9ee6e8bb | pbrook | uint8_t cr; |
51 | 9ee6e8bb | pbrook | qemu_irq irq; |
52 | 9ee6e8bb | pbrook | qemu_irq out[8];
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53 | 9ee6e8bb | pbrook | } pl061_state; |
54 | 9ee6e8bb | pbrook | |
55 | 9ee6e8bb | pbrook | static void pl061_update(pl061_state *s) |
56 | 9ee6e8bb | pbrook | { |
57 | 9ee6e8bb | pbrook | uint8_t changed; |
58 | 9ee6e8bb | pbrook | uint8_t mask; |
59 | 9ee6e8bb | pbrook | int i;
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60 | 9ee6e8bb | pbrook | |
61 | 9ee6e8bb | pbrook | changed = s->old_data ^ s->data; |
62 | 9ee6e8bb | pbrook | if (!changed)
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63 | 9ee6e8bb | pbrook | return;
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64 | 9ee6e8bb | pbrook | |
65 | 9ee6e8bb | pbrook | s->old_data = s->data; |
66 | 9ee6e8bb | pbrook | for (i = 0; i < 8; i++) { |
67 | 9ee6e8bb | pbrook | mask = 1 << i;
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68 | 9ee6e8bb | pbrook | if ((changed & mask & s->dir) && s->out) {
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69 | 9ee6e8bb | pbrook | DPRINTF("Set output %d = %d\n", i, (s->data & mask) != 0); |
70 | 9ee6e8bb | pbrook | qemu_set_irq(s->out[i], (s->data & mask) != 0);
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71 | 9ee6e8bb | pbrook | } |
72 | 9ee6e8bb | pbrook | } |
73 | 9ee6e8bb | pbrook | |
74 | 9ee6e8bb | pbrook | /* FIXME: Implement input interrupts. */
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75 | 9ee6e8bb | pbrook | } |
76 | 9ee6e8bb | pbrook | |
77 | 9ee6e8bb | pbrook | static uint32_t pl061_read(void *opaque, target_phys_addr_t offset) |
78 | 9ee6e8bb | pbrook | { |
79 | 9ee6e8bb | pbrook | pl061_state *s = (pl061_state *)opaque; |
80 | 9ee6e8bb | pbrook | |
81 | 9ee6e8bb | pbrook | offset -= s->base; |
82 | 9ee6e8bb | pbrook | if (offset >= 0xfd0 && offset < 0x1000) { |
83 | 9ee6e8bb | pbrook | return pl061_id[(offset - 0xfd0) >> 2]; |
84 | 9ee6e8bb | pbrook | } |
85 | 9ee6e8bb | pbrook | if (offset < 0x400) { |
86 | 9ee6e8bb | pbrook | return s->data & (offset >> 2); |
87 | 9ee6e8bb | pbrook | } |
88 | 9ee6e8bb | pbrook | switch (offset) {
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89 | 9ee6e8bb | pbrook | case 0x400: /* Direction */ |
90 | 9ee6e8bb | pbrook | return s->dir;
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91 | 9ee6e8bb | pbrook | case 0x404: /* Interrupt sense */ |
92 | 9ee6e8bb | pbrook | return s->isense;
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93 | 9ee6e8bb | pbrook | case 0x408: /* Interrupt both edges */ |
94 | 9ee6e8bb | pbrook | return s->ibe;
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95 | 9ee6e8bb | pbrook | case 0x40c: /* Interupt event */ |
96 | 9ee6e8bb | pbrook | return s->iev;
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97 | 9ee6e8bb | pbrook | case 0x410: /* Interrupt mask */ |
98 | 9ee6e8bb | pbrook | return s->im;
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99 | 9ee6e8bb | pbrook | case 0x414: /* Raw interrupt status */ |
100 | 9ee6e8bb | pbrook | return s->istate;
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101 | 9ee6e8bb | pbrook | case 0x418: /* Masked interrupt status */ |
102 | 9ee6e8bb | pbrook | return s->istate | s->im;
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103 | 9ee6e8bb | pbrook | case 0x420: /* Alternate function select */ |
104 | 9ee6e8bb | pbrook | return s->afsel;
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105 | 9ee6e8bb | pbrook | case 0x500: /* 2mA drive */ |
106 | 9ee6e8bb | pbrook | return s->dr2r;
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107 | 9ee6e8bb | pbrook | case 0x504: /* 4mA drive */ |
108 | 9ee6e8bb | pbrook | return s->dr4r;
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109 | 9ee6e8bb | pbrook | case 0x508: /* 8mA drive */ |
110 | 9ee6e8bb | pbrook | return s->dr8r;
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111 | 9ee6e8bb | pbrook | case 0x50c: /* Open drain */ |
112 | 9ee6e8bb | pbrook | return s->odr;
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113 | 9ee6e8bb | pbrook | case 0x510: /* Pull-up */ |
114 | 9ee6e8bb | pbrook | return s->pur;
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115 | 9ee6e8bb | pbrook | case 0x514: /* Pull-down */ |
116 | 9ee6e8bb | pbrook | return s->pdr;
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117 | 9ee6e8bb | pbrook | case 0x518: /* Slew rate control */ |
118 | 9ee6e8bb | pbrook | return s->slr;
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119 | 9ee6e8bb | pbrook | case 0x51c: /* Digital enable */ |
120 | 9ee6e8bb | pbrook | return s->den;
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121 | 9ee6e8bb | pbrook | case 0x520: /* Lock */ |
122 | 9ee6e8bb | pbrook | return s->locked;
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123 | 9ee6e8bb | pbrook | case 0x524: /* Commit */ |
124 | 9ee6e8bb | pbrook | return s->cr;
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125 | 9ee6e8bb | pbrook | default:
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126 | 9ee6e8bb | pbrook | cpu_abort (cpu_single_env, "pl061_read: Bad offset %x\n",
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127 | 9ee6e8bb | pbrook | (int)offset);
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128 | 9ee6e8bb | pbrook | return 0; |
129 | 9ee6e8bb | pbrook | } |
130 | 9ee6e8bb | pbrook | } |
131 | 9ee6e8bb | pbrook | |
132 | 9ee6e8bb | pbrook | static void pl061_write(void *opaque, target_phys_addr_t offset, |
133 | 9ee6e8bb | pbrook | uint32_t value) |
134 | 9ee6e8bb | pbrook | { |
135 | 9ee6e8bb | pbrook | pl061_state *s = (pl061_state *)opaque; |
136 | 9ee6e8bb | pbrook | uint8_t mask; |
137 | 9ee6e8bb | pbrook | |
138 | 9ee6e8bb | pbrook | offset -= s->base; |
139 | 9ee6e8bb | pbrook | if (offset < 0x400) { |
140 | 9ee6e8bb | pbrook | mask = (offset >> 2) & s->dir;
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141 | 9ee6e8bb | pbrook | s->data = (s->data & ~mask) | (value & mask); |
142 | 9ee6e8bb | pbrook | pl061_update(s); |
143 | 9ee6e8bb | pbrook | return;
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144 | 9ee6e8bb | pbrook | } |
145 | 9ee6e8bb | pbrook | switch (offset) {
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146 | 9ee6e8bb | pbrook | case 0x400: /* Direction */ |
147 | 9ee6e8bb | pbrook | s->dir = value; |
148 | 9ee6e8bb | pbrook | break;
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149 | 9ee6e8bb | pbrook | case 0x404: /* Interrupt sense */ |
150 | 9ee6e8bb | pbrook | s->isense = value; |
151 | 9ee6e8bb | pbrook | break;
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152 | 9ee6e8bb | pbrook | case 0x408: /* Interrupt both edges */ |
153 | 9ee6e8bb | pbrook | s->ibe = value; |
154 | 9ee6e8bb | pbrook | break;
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155 | 9ee6e8bb | pbrook | case 0x40c: /* Interupt event */ |
156 | 9ee6e8bb | pbrook | s->iev = value; |
157 | 9ee6e8bb | pbrook | break;
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158 | 9ee6e8bb | pbrook | case 0x410: /* Interrupt mask */ |
159 | 9ee6e8bb | pbrook | s->im = value; |
160 | 9ee6e8bb | pbrook | break;
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161 | 9ee6e8bb | pbrook | case 0x41c: /* Interrupt clear */ |
162 | 9ee6e8bb | pbrook | s->istate &= ~value; |
163 | 9ee6e8bb | pbrook | break;
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164 | 9ee6e8bb | pbrook | case 0x420: /* Alternate function select */ |
165 | 9ee6e8bb | pbrook | mask = s->cr; |
166 | 9ee6e8bb | pbrook | s->afsel = (s->afsel & ~mask) | (value & mask); |
167 | 9ee6e8bb | pbrook | break;
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168 | 9ee6e8bb | pbrook | case 0x500: /* 2mA drive */ |
169 | 9ee6e8bb | pbrook | s->dr2r = value; |
170 | 9ee6e8bb | pbrook | break;
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171 | 9ee6e8bb | pbrook | case 0x504: /* 4mA drive */ |
172 | 9ee6e8bb | pbrook | s->dr4r = value; |
173 | 9ee6e8bb | pbrook | break;
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174 | 9ee6e8bb | pbrook | case 0x508: /* 8mA drive */ |
175 | 9ee6e8bb | pbrook | s->dr8r = value; |
176 | 9ee6e8bb | pbrook | break;
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177 | 9ee6e8bb | pbrook | case 0x50c: /* Open drain */ |
178 | 9ee6e8bb | pbrook | s->odr = value; |
179 | 9ee6e8bb | pbrook | break;
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180 | 9ee6e8bb | pbrook | case 0x510: /* Pull-up */ |
181 | 9ee6e8bb | pbrook | s->pur = value; |
182 | 9ee6e8bb | pbrook | break;
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183 | 9ee6e8bb | pbrook | case 0x514: /* Pull-down */ |
184 | 9ee6e8bb | pbrook | s->pdr = value; |
185 | 9ee6e8bb | pbrook | break;
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186 | 9ee6e8bb | pbrook | case 0x518: /* Slew rate control */ |
187 | 9ee6e8bb | pbrook | s->slr = value; |
188 | 9ee6e8bb | pbrook | break;
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189 | 9ee6e8bb | pbrook | case 0x51c: /* Digital enable */ |
190 | 9ee6e8bb | pbrook | s->den = value; |
191 | 9ee6e8bb | pbrook | break;
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192 | 9ee6e8bb | pbrook | case 0x520: /* Lock */ |
193 | 9ee6e8bb | pbrook | s->locked = (value != 0xacce551);
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194 | 9ee6e8bb | pbrook | break;
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195 | 9ee6e8bb | pbrook | case 0x524: /* Commit */ |
196 | 9ee6e8bb | pbrook | if (!s->locked)
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197 | 9ee6e8bb | pbrook | s->cr = value; |
198 | 9ee6e8bb | pbrook | break;
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199 | 9ee6e8bb | pbrook | default:
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200 | 9ee6e8bb | pbrook | cpu_abort (cpu_single_env, "pl061_write: Bad offset %x\n",
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201 | 9ee6e8bb | pbrook | (int)offset);
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202 | 9ee6e8bb | pbrook | } |
203 | 9ee6e8bb | pbrook | pl061_update(s); |
204 | 9ee6e8bb | pbrook | } |
205 | 9ee6e8bb | pbrook | |
206 | 9ee6e8bb | pbrook | static void pl061_reset(pl061_state *s) |
207 | 9ee6e8bb | pbrook | { |
208 | 9ee6e8bb | pbrook | s->locked = 1;
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209 | 9ee6e8bb | pbrook | s->cr = 0xff;
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210 | 9ee6e8bb | pbrook | } |
211 | 9ee6e8bb | pbrook | |
212 | 9596ebb7 | pbrook | static void pl061_set_irq(void * opaque, int irq, int level) |
213 | 9ee6e8bb | pbrook | { |
214 | 9ee6e8bb | pbrook | pl061_state *s = (pl061_state *)opaque; |
215 | 9ee6e8bb | pbrook | uint8_t mask; |
216 | 9ee6e8bb | pbrook | |
217 | 9ee6e8bb | pbrook | mask = 1 << irq;
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218 | 9ee6e8bb | pbrook | if ((s->dir & mask) == 0) { |
219 | 9ee6e8bb | pbrook | s->data &= ~mask; |
220 | 9ee6e8bb | pbrook | if (level)
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221 | 9ee6e8bb | pbrook | s->data |= mask; |
222 | 9ee6e8bb | pbrook | pl061_update(s); |
223 | 9ee6e8bb | pbrook | } |
224 | 9ee6e8bb | pbrook | } |
225 | 9ee6e8bb | pbrook | |
226 | 9ee6e8bb | pbrook | static CPUReadMemoryFunc *pl061_readfn[] = {
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227 | 9ee6e8bb | pbrook | pl061_read, |
228 | 9ee6e8bb | pbrook | pl061_read, |
229 | 9ee6e8bb | pbrook | pl061_read |
230 | 9ee6e8bb | pbrook | }; |
231 | 9ee6e8bb | pbrook | |
232 | 9ee6e8bb | pbrook | static CPUWriteMemoryFunc *pl061_writefn[] = {
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233 | 9ee6e8bb | pbrook | pl061_write, |
234 | 9ee6e8bb | pbrook | pl061_write, |
235 | 9ee6e8bb | pbrook | pl061_write |
236 | 9ee6e8bb | pbrook | }; |
237 | 9ee6e8bb | pbrook | |
238 | 9ee6e8bb | pbrook | /* Returns an array of inputs. */
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239 | 9ee6e8bb | pbrook | qemu_irq *pl061_init(uint32_t base, qemu_irq irq, qemu_irq **out) |
240 | 9ee6e8bb | pbrook | { |
241 | 9ee6e8bb | pbrook | int iomemtype;
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242 | 9ee6e8bb | pbrook | pl061_state *s; |
243 | 9ee6e8bb | pbrook | |
244 | 9ee6e8bb | pbrook | s = (pl061_state *)qemu_mallocz(sizeof(pl061_state));
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245 | 9ee6e8bb | pbrook | iomemtype = cpu_register_io_memory(0, pl061_readfn,
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246 | 9ee6e8bb | pbrook | pl061_writefn, s); |
247 | 9ee6e8bb | pbrook | cpu_register_physical_memory(base, 0x00001000, iomemtype);
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248 | 9ee6e8bb | pbrook | s->base = base; |
249 | 9ee6e8bb | pbrook | s->irq = irq; |
250 | 9ee6e8bb | pbrook | pl061_reset(s); |
251 | 9ee6e8bb | pbrook | if (out)
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252 | 9ee6e8bb | pbrook | *out = s->out; |
253 | 9ee6e8bb | pbrook | |
254 | 9ee6e8bb | pbrook | /* ??? Save/restore. */
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255 | 9ee6e8bb | pbrook | return qemu_allocate_irqs(pl061_set_irq, s, 8); |
256 | 9ee6e8bb | pbrook | } |