Archipelago » qemu

    return r;

}

{

    switch (fmt) {

    case AUD_FMT_U8:

    return "S16";

}

{

    if (!strcasecmp (s, "u8")) {

        *defaultp = 0;

    return 0;

}

{

    assert(index >=0);

    assert(count > 0);

    return 0;

}

{

    return array_remove_slice(array, index, 1);

}

/* return the index for a given member */

{

    size_t offset = (char*)pointer - array->pointer;

    assert(offset >= 0);

}

{

    if (!bdrv->bdrv_aio_read) {

        /* add AIO emulation layer */

    int count, wptr, rptr;

} QEMUFIFO;

{

    int l, len;

    return len1;

}

{

    int l, len;

int do_swap;

{

    va_list ap;

    va_start(ap, fmt);

    exit(1);

}

{

    char *data;

    return -1;

}

{

    struct elfhdr ehdr;

    struct elf_phdr *phdr = NULL, *ph;

 */

#include "hw.h"

#include "sysemu.h"

#define LOCK_VALUE 0xa05f

 */

#include "hw.h"

#include "qemu-timer.h"

/* Common timer implementation.  */

    }

}

{

    arm_timer_state *s = (arm_timer_state *)opaque;

}

{

    GT64120State *s = opaque;

int64_t irq_time[16];

#endif

{

    PicState2 *s = opaque;

#include "block.h"

#include "qemu-timer.h"

#include "sysemu.h"

/* debug IDE devices */

//#define DEBUG_IDE

#define REG_IBM_CENTURY_BYTE        0x32

#define REG_IBM_PS2_CENTURY_BYTE    0x37

{

    time_t ti;

    struct tm *tm;

}

/* Memory mapped interface */

{

    RTCState *s = opaque;

    return cmos_ioport_read(s, (addr - s->base) >> s->it_shift) & 0xFF;

}

{

    RTCState *s = opaque;

    cmos_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFF);

}

{

    RTCState *s = opaque;

    uint32_t val;

    return val;

}

{

    RTCState *s = opaque;

#ifdef TARGET_WORDS_BIGENDIAN

    cmos_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFFFF);

}

{

    RTCState *s = opaque;

    uint32_t val;

    return val;

}

{

    RTCState *s = opaque;

#ifdef TARGET_WORDS_BIGENDIAN

    }

}

{

    mcf_fec_state *s = (mcf_fec_state *)opaque;

    switch (addr & 0x3ff) {

   malta_fpga_writel

};

{

    MaltaFPGAState *s = opaque;

    malta_fpga_update_display(s);

}

{

    MaltaFPGAState *s;

    CharDriverState *uart_chr;

 */

#include "hw.h"

#include "pci.h"

#include "net.h"

/* debug NE2000 card */

m48t59_t *m48t59_init (qemu_irq IRQ, target_phys_addr_t mem_base,

                       uint32_t io_base, uint16_t size,

                       int type);

#endif /* !NVRAM_H */

    omap_badwidth_write16,

};

{

    s->inputs = 0;

    s->outputs = 0;

    omap_badwidth_write16,

};

{

    s->inputs = 0;

    s->outputs = ~0;

    omap_badwidth_write16,

};

{

    s->control = 0;

    s->setup[0] = 0;

}

/* Pseudonoise Pulse-Width Light Modulator */

{

    int output = (s->pwl.clk && s->pwl.enable) ? s->pwl.level : 0;

    omap_badwidth_write8,

};

{

    s->pwl.output = 0;

    s->pwl.level = 0;

    omap_badwidth_write8,

};

{

    s->pwt.frc = 0;

    s->pwt.vrc = 0;

    qemu_mod_timer(s->clk, s->tick);

}

{

    s->interrupts = 0;

    s->comp_reg = 0;

    return s;

}

{

    struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;

    omap_mcbsp_rx_start(s);

}

{

    struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;

#  error TARGET_PHYS_ADDR_BITS undefined

# endif

uint32_t omap_badwidth_read16(void *opaque, target_phys_addr_t addr);

void omap_badwidth_write16(void *opaque, target_phys_addr_t addr,

                uint32_t value);

    [32]	= draw_line16_32,

};

{

    struct omap_lcd_panel_s *omap_lcd = (struct omap_lcd_panel_s *) opaque;

    draw_line_func *draw_line;

    return 0;

}

    struct omap_lcd_panel_s *omap_lcd = opaque;

    omap_update_display(opaque);

    if (omap_lcd && omap_lcd->state->data)

                omap_lcd->state->linesize);

}

    struct omap_lcd_panel_s *omap_lcd = opaque;

    omap_lcd->invalidate = 1;

}

    if (!s->enable) {

        s->dma->current_frame = -1;

        s->sync_error = 0;

}

/* Memory mapped interface */

{

    ParallelState *s = opaque;

    return parallel_ioport_read_sw(s, (addr - s->base) >> s->it_shift) & 0xFF;

}

{

    ParallelState *s = opaque;

    parallel_ioport_write_sw(s, (addr - s->base) >> s->it_shift, value & 0xFF);

}

{

    ParallelState *s = opaque;

    return parallel_ioport_read_sw(s, (addr - s->base) >> s->it_shift) & 0xFFFF;

}

{

    ParallelState *s = opaque;

    parallel_ioport_write_sw(s, (addr - s->base) >> s->it_shift, value & 0xFFFF);

}

{

    ParallelState *s = opaque;

    return parallel_ioport_read_sw(s, (addr - s->base) >> s->it_shift);

}

{

    ParallelState *s = opaque;

/***********************************************************/

/* Bochs BIOS debug ports */

{

    static const char shutdown_str[8] = "Shutdown";

    static int shutdown_index = 0;

    }

}

{

    register_ioport_write(0x400, 1, 2, bochs_bios_write, NULL);

    register_ioport_write(0x401, 1, 2, bochs_bios_write, NULL);

    bdrv_set_boot_sector(bs_table[0], bootsect, sizeof(bootsect));

}

{

    int fd, size;

    int setup_sects;

    return bus;

}

{

    PCIBus *bus;

    bus = qemu_mallocz(sizeof(PCIBus));

    *(uint32_t *)(pci_dev->config + addr) = cpu_to_le32(type);

}

{

    return addr + pci_mem_base;

}

    PCIBus *bus;

} PCIBridge;

                             uint32_t address, uint32_t val, int len)

{

    PCIBridge *s = (PCIBridge *)d;

    return ps2_read_data(s->kbd);

}

{

    KBDState *s = opaque;

}

/* Memory mapped interface */

{

    KBDState *s = opaque;

    }

}

{

    KBDState *s = opaque;

    return pci_device_load(d, f);

}

{

    PCIDevice *d;

    uint8_t *pci_conf;

  s->cr = 0xff;

}

{

    pl061_state *s = (pl061_state *)opaque;

    uint8_t mask;

   pl190_write

};

{

  int i;

    /* TODO */

}

{

    struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque;

#include "hw.h"

#include "pcmcia.h"

struct pxa2xx_pcmcia_s {

    struct pcmcia_socket_s slot;

 */

#include "hw.h"

#define GIC_NIRQ 96

#define NCPU 1

} RTL8139State;

{

    DEBUG_PRINT(("RTL8139: eeprom command 0x%02x\n", command));

    }

}

{

    int bit = eeprom->eedi?1:0;

    }

}

{

    EEprom9346 *eeprom = &s->eeprom;

    if (!eeprom->eecs)

    return eeprom->eedo;

}

{

    EEprom9346 *eeprom = &s->eeprom;

    uint8_t old_eecs = eeprom->eecs;

    return ret;

}

{

    if (s->Cfg9346 & Cfg9346_Unlock)

    {

    return sd_crc7(buffer, 5) != req->crc;	/* TODO */

}

{

    uint32_t mask = CARD_STATUS_B ^ ILLEGAL_COMMAND;

    uint32_t status;

    response[3] = (status >> 0) & 0xff;

}

{

    response[0] = (sd->ocr >> 24) & 0xff;

    response[1] = (sd->ocr >> 16) & 0xff;

    response[3] = (sd->ocr >> 0) & 0xff;

}

{

    uint16_t arg;

    uint16_t status;

        sh_serial_receive_break(s);

}

{

    sh_serial_state *s = opaque;

    return sh_serial_ioport_read(s, addr - s->base);

}

{

    sh_serial_state *s = opaque;

    sh_serial_ioport_write(s, addr - s->base, value);

#endif

}

{

    sh_timer_state *s = (sh_timer_state *)opaque;

    }

}

{

    SMBusDevice *dev = (SMBusDevice *)s;

    switch (event) {

   ssys_write

};

{

    ssys_state *s = (ssys_state *)opaque;

#include "qemu-timer.h"

#include "usb.h"

#include "pci.h"

//#define DEBUG_OHCI

/* Dump packet contents.  */

    {  192, 88200,  128, 88200 },	/* SR: 11111 */

};

{

    int i;

    audsettings_t in_fmt;

        AUD_set_active_out(*s->out[0], 1);

}

{

#define R_ONLY	0x0000ffff

#define L_ONLY	0xffff0000

    return &s->i2c;

}

{

    struct wm8750_s *s = (struct wm8750_s *) i2c;

    wm8750_reset(&s->i2c);

static char separator_char;

static char scale_char;

int

print_insn_i386 (pc, info)

     bfd_vma pc;

 */

#include "qemu-common.h"

#include "disas.h"

#include "uboot_image.h"

/* return the size or -1 if error */

}

/* get the current CPU defined by the user */

{

    CPUState *env;

    return -1;

}

{

    if (!mon_cpu) {

        mon_set_cpu(0);

#include <sys/mman.h>

#include <fcntl.h>

{

    static int phys_ram_fd = -1;

    static int phys_ram_size = 0;

    return ptr;

}

{

    /* may be useful some day, but currently we do not need to free */

}

};

CharDriverState *qemu_chr_open(const char *filename);

void qemu_chr_printf(CharDriverState *s, const char *fmt, ...);

int qemu_chr_write(CharDriverState *s, const uint8_t *buf, int len);

void qemu_chr_send_event(CharDriverState *s, int event);

 * needed. It should only be called, if this is not an interrupt.

 * Returns the new exception number.

 */

{

    char first_contributory = env->old_exception == 0 ||

                              (env->old_exception >= 10 &&

    helper_fstt(ST0, A0);

}

{

    env->fpus |= mask;

    if (env->fpus & (~env->fpuc & FPUC_EM))

};

#include "dyngen.h"

#include "op.h"

    return p->class_name;

}

{

    const char *class_str, *speed_str;

target_phys_addr_t isa_mem_base = 0;

PicState2 *isa_pic;

{

#ifdef DEBUG_UNUSED_IOPORT

    fprintf(stderr, "unused inb: port=0x%04x\n", address);

    return 0xff;

}

{

#ifdef DEBUG_UNUSED_IOPORT

    fprintf(stderr, "unused outb: port=0x%04x data=0x%02x\n", address, data);

}

/* default is to make two byte accesses */

{

    uint32_t data;

    data = ioport_read_table[0][address](ioport_opaque[address], address);

    return data;

}

{

    ioport_write_table[0][address](ioport_opaque[address], address, data & 0xff);

    address = (address + 1) & (MAX_IOPORTS - 1);

    ioport_write_table[0][address](ioport_opaque[address], address, (data >> 8) & 0xff);

}

{

#ifdef DEBUG_UNUSED_IOPORT

    fprintf(stderr, "unused inl: port=0x%04x\n", address);

    return 0xffffffff;

}

{

#ifdef DEBUG_UNUSED_IOPORT

    fprintf(stderr, "unused outl: port=0x%04x data=0x%02x\n", address, data);

#endif

}

{

    int i;

static QEMUTimer *active_timers[2];

{

    QEMUClock *clock;

    clock = qemu_mallocz(sizeof(QEMUClock));

    alarm_timer = t;

}

{

    alarm_timer->stop(alarm_timer);

    alarm_timer = NULL;

    d->mux_cnt++;

}

{

    CharDriverState *chr;

    MuxDriver *d;

/***********************************************************/

/* network device redirectors */

{

    int len, i, j, c;

}

/* automatic user mode samba server configuration */

{

    char smb_conf[1024];

    char smb_cmdline[1024];

    return NULL;

}

{

    QEMUFile *f;

#define QEMU_VM_FILE_MAGIC   0x5145564d

#define QEMU_VM_FILE_VERSION 0x00000002

{

    SaveStateEntry *se;

    int len, ret;

        /* record size: filled later */

        len_pos = qemu_ftell(f);

        qemu_put_be32(f, 0);

        se->save_state(f, se->opaque);

        /* fill record size */

    return NULL;

}

{

    SaveStateEntry *se;

    int len, ret, instance_id, record_len, version_id;

    return 0;

}

{

    QEMUMachine *m;

/***********************************************************/

/* main execution loop */

{

    DisplayState *ds = opaque;

    ds->dpy_refresh(ds);

static CPUState *cur_cpu;

{

    int ret, timeout;

#ifdef CONFIG_PROFILER

}

/* XXX: currently we cannot use simultaneously different CPUs */

{

#if defined(TARGET_I386)

    qemu_register_machine(&pc_machine);

}

#if CONFIG_VNC_TLS

    struct VncState *vs = (struct VncState *)transport;

    int ret;

}

    struct VncState *vs = (struct VncState *)transport;

    int ret;

 * THE SOFTWARE.

 */

#include "qemu-common.h"

static const uint8_t x_keycode_to_pc_keycode[115] = {

   0xc7,      /*  97  Home   */