root / tcg / tcg-op.h @ 95d65800
History | View | Annotate | Download (78.1 kB)
1 |
/*
|
---|---|
2 |
* Tiny Code Generator for QEMU
|
3 |
*
|
4 |
* Copyright (c) 2008 Fabrice Bellard
|
5 |
*
|
6 |
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
7 |
* of this software and associated documentation files (the "Software"), to deal
|
8 |
* in the Software without restriction, including without limitation the rights
|
9 |
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
10 |
* copies of the Software, and to permit persons to whom the Software is
|
11 |
* furnished to do so, subject to the following conditions:
|
12 |
*
|
13 |
* The above copyright notice and this permission notice shall be included in
|
14 |
* all copies or substantial portions of the Software.
|
15 |
*
|
16 |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
17 |
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
18 |
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
19 |
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
20 |
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
21 |
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
22 |
* THE SOFTWARE.
|
23 |
*/
|
24 |
#include "tcg.h" |
25 |
|
26 |
int gen_new_label(void); |
27 |
|
28 |
static inline void tcg_gen_op1_i32(TCGOpcode opc, TCGv_i32 arg1) |
29 |
{ |
30 |
*gen_opc_ptr++ = opc; |
31 |
*gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
32 |
} |
33 |
|
34 |
static inline void tcg_gen_op1_i64(TCGOpcode opc, TCGv_i64 arg1) |
35 |
{ |
36 |
*gen_opc_ptr++ = opc; |
37 |
*gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
38 |
} |
39 |
|
40 |
static inline void tcg_gen_op1i(TCGOpcode opc, TCGArg arg1) |
41 |
{ |
42 |
*gen_opc_ptr++ = opc; |
43 |
*gen_opparam_ptr++ = arg1; |
44 |
} |
45 |
|
46 |
static inline void tcg_gen_op2_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2) |
47 |
{ |
48 |
*gen_opc_ptr++ = opc; |
49 |
*gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
50 |
*gen_opparam_ptr++ = GET_TCGV_I32(arg2); |
51 |
} |
52 |
|
53 |
static inline void tcg_gen_op2_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2) |
54 |
{ |
55 |
*gen_opc_ptr++ = opc; |
56 |
*gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
57 |
*gen_opparam_ptr++ = GET_TCGV_I64(arg2); |
58 |
} |
59 |
|
60 |
static inline void tcg_gen_op2i_i32(TCGOpcode opc, TCGv_i32 arg1, TCGArg arg2) |
61 |
{ |
62 |
*gen_opc_ptr++ = opc; |
63 |
*gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
64 |
*gen_opparam_ptr++ = arg2; |
65 |
} |
66 |
|
67 |
static inline void tcg_gen_op2i_i64(TCGOpcode opc, TCGv_i64 arg1, TCGArg arg2) |
68 |
{ |
69 |
*gen_opc_ptr++ = opc; |
70 |
*gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
71 |
*gen_opparam_ptr++ = arg2; |
72 |
} |
73 |
|
74 |
static inline void tcg_gen_op2ii(TCGOpcode opc, TCGArg arg1, TCGArg arg2) |
75 |
{ |
76 |
*gen_opc_ptr++ = opc; |
77 |
*gen_opparam_ptr++ = arg1; |
78 |
*gen_opparam_ptr++ = arg2; |
79 |
} |
80 |
|
81 |
static inline void tcg_gen_op3_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2, |
82 |
TCGv_i32 arg3) |
83 |
{ |
84 |
*gen_opc_ptr++ = opc; |
85 |
*gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
86 |
*gen_opparam_ptr++ = GET_TCGV_I32(arg2); |
87 |
*gen_opparam_ptr++ = GET_TCGV_I32(arg3); |
88 |
} |
89 |
|
90 |
static inline void tcg_gen_op3_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2, |
91 |
TCGv_i64 arg3) |
92 |
{ |
93 |
*gen_opc_ptr++ = opc; |
94 |
*gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
95 |
*gen_opparam_ptr++ = GET_TCGV_I64(arg2); |
96 |
*gen_opparam_ptr++ = GET_TCGV_I64(arg3); |
97 |
} |
98 |
|
99 |
static inline void tcg_gen_op3i_i32(TCGOpcode opc, TCGv_i32 arg1, |
100 |
TCGv_i32 arg2, TCGArg arg3) |
101 |
{ |
102 |
*gen_opc_ptr++ = opc; |
103 |
*gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
104 |
*gen_opparam_ptr++ = GET_TCGV_I32(arg2); |
105 |
*gen_opparam_ptr++ = arg3; |
106 |
} |
107 |
|
108 |
static inline void tcg_gen_op3i_i64(TCGOpcode opc, TCGv_i64 arg1, |
109 |
TCGv_i64 arg2, TCGArg arg3) |
110 |
{ |
111 |
*gen_opc_ptr++ = opc; |
112 |
*gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
113 |
*gen_opparam_ptr++ = GET_TCGV_I64(arg2); |
114 |
*gen_opparam_ptr++ = arg3; |
115 |
} |
116 |
|
117 |
static inline void tcg_gen_ldst_op_i32(TCGOpcode opc, TCGv_i32 val, |
118 |
TCGv_ptr base, TCGArg offset) |
119 |
{ |
120 |
*gen_opc_ptr++ = opc; |
121 |
*gen_opparam_ptr++ = GET_TCGV_I32(val); |
122 |
*gen_opparam_ptr++ = GET_TCGV_PTR(base); |
123 |
*gen_opparam_ptr++ = offset; |
124 |
} |
125 |
|
126 |
static inline void tcg_gen_ldst_op_i64(TCGOpcode opc, TCGv_i64 val, |
127 |
TCGv_ptr base, TCGArg offset) |
128 |
{ |
129 |
*gen_opc_ptr++ = opc; |
130 |
*gen_opparam_ptr++ = GET_TCGV_I64(val); |
131 |
*gen_opparam_ptr++ = GET_TCGV_PTR(base); |
132 |
*gen_opparam_ptr++ = offset; |
133 |
} |
134 |
|
135 |
static inline void tcg_gen_qemu_ldst_op_i64_i32(TCGOpcode opc, TCGv_i64 val, |
136 |
TCGv_i32 addr, TCGArg mem_index) |
137 |
{ |
138 |
*gen_opc_ptr++ = opc; |
139 |
*gen_opparam_ptr++ = GET_TCGV_I64(val); |
140 |
*gen_opparam_ptr++ = GET_TCGV_I32(addr); |
141 |
*gen_opparam_ptr++ = mem_index; |
142 |
} |
143 |
|
144 |
static inline void tcg_gen_qemu_ldst_op_i64_i64(TCGOpcode opc, TCGv_i64 val, |
145 |
TCGv_i64 addr, TCGArg mem_index) |
146 |
{ |
147 |
*gen_opc_ptr++ = opc; |
148 |
*gen_opparam_ptr++ = GET_TCGV_I64(val); |
149 |
*gen_opparam_ptr++ = GET_TCGV_I64(addr); |
150 |
*gen_opparam_ptr++ = mem_index; |
151 |
} |
152 |
|
153 |
static inline void tcg_gen_op4_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2, |
154 |
TCGv_i32 arg3, TCGv_i32 arg4) |
155 |
{ |
156 |
*gen_opc_ptr++ = opc; |
157 |
*gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
158 |
*gen_opparam_ptr++ = GET_TCGV_I32(arg2); |
159 |
*gen_opparam_ptr++ = GET_TCGV_I32(arg3); |
160 |
*gen_opparam_ptr++ = GET_TCGV_I32(arg4); |
161 |
} |
162 |
|
163 |
static inline void tcg_gen_op4_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2, |
164 |
TCGv_i64 arg3, TCGv_i64 arg4) |
165 |
{ |
166 |
*gen_opc_ptr++ = opc; |
167 |
*gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
168 |
*gen_opparam_ptr++ = GET_TCGV_I64(arg2); |
169 |
*gen_opparam_ptr++ = GET_TCGV_I64(arg3); |
170 |
*gen_opparam_ptr++ = GET_TCGV_I64(arg4); |
171 |
} |
172 |
|
173 |
static inline void tcg_gen_op4i_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2, |
174 |
TCGv_i32 arg3, TCGArg arg4) |
175 |
{ |
176 |
*gen_opc_ptr++ = opc; |
177 |
*gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
178 |
*gen_opparam_ptr++ = GET_TCGV_I32(arg2); |
179 |
*gen_opparam_ptr++ = GET_TCGV_I32(arg3); |
180 |
*gen_opparam_ptr++ = arg4; |
181 |
} |
182 |
|
183 |
static inline void tcg_gen_op4i_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2, |
184 |
TCGv_i64 arg3, TCGArg arg4) |
185 |
{ |
186 |
*gen_opc_ptr++ = opc; |
187 |
*gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
188 |
*gen_opparam_ptr++ = GET_TCGV_I64(arg2); |
189 |
*gen_opparam_ptr++ = GET_TCGV_I64(arg3); |
190 |
*gen_opparam_ptr++ = arg4; |
191 |
} |
192 |
|
193 |
static inline void tcg_gen_op4ii_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2, |
194 |
TCGArg arg3, TCGArg arg4) |
195 |
{ |
196 |
*gen_opc_ptr++ = opc; |
197 |
*gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
198 |
*gen_opparam_ptr++ = GET_TCGV_I32(arg2); |
199 |
*gen_opparam_ptr++ = arg3; |
200 |
*gen_opparam_ptr++ = arg4; |
201 |
} |
202 |
|
203 |
static inline void tcg_gen_op4ii_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2, |
204 |
TCGArg arg3, TCGArg arg4) |
205 |
{ |
206 |
*gen_opc_ptr++ = opc; |
207 |
*gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
208 |
*gen_opparam_ptr++ = GET_TCGV_I64(arg2); |
209 |
*gen_opparam_ptr++ = arg3; |
210 |
*gen_opparam_ptr++ = arg4; |
211 |
} |
212 |
|
213 |
static inline void tcg_gen_op5_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2, |
214 |
TCGv_i32 arg3, TCGv_i32 arg4, TCGv_i32 arg5) |
215 |
{ |
216 |
*gen_opc_ptr++ = opc; |
217 |
*gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
218 |
*gen_opparam_ptr++ = GET_TCGV_I32(arg2); |
219 |
*gen_opparam_ptr++ = GET_TCGV_I32(arg3); |
220 |
*gen_opparam_ptr++ = GET_TCGV_I32(arg4); |
221 |
*gen_opparam_ptr++ = GET_TCGV_I32(arg5); |
222 |
} |
223 |
|
224 |
static inline void tcg_gen_op5_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2, |
225 |
TCGv_i64 arg3, TCGv_i64 arg4, TCGv_i64 arg5) |
226 |
{ |
227 |
*gen_opc_ptr++ = opc; |
228 |
*gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
229 |
*gen_opparam_ptr++ = GET_TCGV_I64(arg2); |
230 |
*gen_opparam_ptr++ = GET_TCGV_I64(arg3); |
231 |
*gen_opparam_ptr++ = GET_TCGV_I64(arg4); |
232 |
*gen_opparam_ptr++ = GET_TCGV_I64(arg5); |
233 |
} |
234 |
|
235 |
static inline void tcg_gen_op5i_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2, |
236 |
TCGv_i32 arg3, TCGv_i32 arg4, TCGArg arg5) |
237 |
{ |
238 |
*gen_opc_ptr++ = opc; |
239 |
*gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
240 |
*gen_opparam_ptr++ = GET_TCGV_I32(arg2); |
241 |
*gen_opparam_ptr++ = GET_TCGV_I32(arg3); |
242 |
*gen_opparam_ptr++ = GET_TCGV_I32(arg4); |
243 |
*gen_opparam_ptr++ = arg5; |
244 |
} |
245 |
|
246 |
static inline void tcg_gen_op5i_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2, |
247 |
TCGv_i64 arg3, TCGv_i64 arg4, TCGArg arg5) |
248 |
{ |
249 |
*gen_opc_ptr++ = opc; |
250 |
*gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
251 |
*gen_opparam_ptr++ = GET_TCGV_I64(arg2); |
252 |
*gen_opparam_ptr++ = GET_TCGV_I64(arg3); |
253 |
*gen_opparam_ptr++ = GET_TCGV_I64(arg4); |
254 |
*gen_opparam_ptr++ = arg5; |
255 |
} |
256 |
|
257 |
static inline void tcg_gen_op5ii_i32(TCGOpcode opc, TCGv_i32 arg1, |
258 |
TCGv_i32 arg2, TCGv_i32 arg3, |
259 |
TCGArg arg4, TCGArg arg5) |
260 |
{ |
261 |
*gen_opc_ptr++ = opc; |
262 |
*gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
263 |
*gen_opparam_ptr++ = GET_TCGV_I32(arg2); |
264 |
*gen_opparam_ptr++ = GET_TCGV_I32(arg3); |
265 |
*gen_opparam_ptr++ = arg4; |
266 |
*gen_opparam_ptr++ = arg5; |
267 |
} |
268 |
|
269 |
static inline void tcg_gen_op5ii_i64(TCGOpcode opc, TCGv_i64 arg1, |
270 |
TCGv_i64 arg2, TCGv_i64 arg3, |
271 |
TCGArg arg4, TCGArg arg5) |
272 |
{ |
273 |
*gen_opc_ptr++ = opc; |
274 |
*gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
275 |
*gen_opparam_ptr++ = GET_TCGV_I64(arg2); |
276 |
*gen_opparam_ptr++ = GET_TCGV_I64(arg3); |
277 |
*gen_opparam_ptr++ = arg4; |
278 |
*gen_opparam_ptr++ = arg5; |
279 |
} |
280 |
|
281 |
static inline void tcg_gen_op6_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2, |
282 |
TCGv_i32 arg3, TCGv_i32 arg4, TCGv_i32 arg5, |
283 |
TCGv_i32 arg6) |
284 |
{ |
285 |
*gen_opc_ptr++ = opc; |
286 |
*gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
287 |
*gen_opparam_ptr++ = GET_TCGV_I32(arg2); |
288 |
*gen_opparam_ptr++ = GET_TCGV_I32(arg3); |
289 |
*gen_opparam_ptr++ = GET_TCGV_I32(arg4); |
290 |
*gen_opparam_ptr++ = GET_TCGV_I32(arg5); |
291 |
*gen_opparam_ptr++ = GET_TCGV_I32(arg6); |
292 |
} |
293 |
|
294 |
static inline void tcg_gen_op6_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2, |
295 |
TCGv_i64 arg3, TCGv_i64 arg4, TCGv_i64 arg5, |
296 |
TCGv_i64 arg6) |
297 |
{ |
298 |
*gen_opc_ptr++ = opc; |
299 |
*gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
300 |
*gen_opparam_ptr++ = GET_TCGV_I64(arg2); |
301 |
*gen_opparam_ptr++ = GET_TCGV_I64(arg3); |
302 |
*gen_opparam_ptr++ = GET_TCGV_I64(arg4); |
303 |
*gen_opparam_ptr++ = GET_TCGV_I64(arg5); |
304 |
*gen_opparam_ptr++ = GET_TCGV_I64(arg6); |
305 |
} |
306 |
|
307 |
static inline void tcg_gen_op6i_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2, |
308 |
TCGv_i32 arg3, TCGv_i32 arg4, |
309 |
TCGv_i32 arg5, TCGArg arg6) |
310 |
{ |
311 |
*gen_opc_ptr++ = opc; |
312 |
*gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
313 |
*gen_opparam_ptr++ = GET_TCGV_I32(arg2); |
314 |
*gen_opparam_ptr++ = GET_TCGV_I32(arg3); |
315 |
*gen_opparam_ptr++ = GET_TCGV_I32(arg4); |
316 |
*gen_opparam_ptr++ = GET_TCGV_I32(arg5); |
317 |
*gen_opparam_ptr++ = arg6; |
318 |
} |
319 |
|
320 |
static inline void tcg_gen_op6i_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2, |
321 |
TCGv_i64 arg3, TCGv_i64 arg4, |
322 |
TCGv_i64 arg5, TCGArg arg6) |
323 |
{ |
324 |
*gen_opc_ptr++ = opc; |
325 |
*gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
326 |
*gen_opparam_ptr++ = GET_TCGV_I64(arg2); |
327 |
*gen_opparam_ptr++ = GET_TCGV_I64(arg3); |
328 |
*gen_opparam_ptr++ = GET_TCGV_I64(arg4); |
329 |
*gen_opparam_ptr++ = GET_TCGV_I64(arg5); |
330 |
*gen_opparam_ptr++ = arg6; |
331 |
} |
332 |
|
333 |
static inline void tcg_gen_op6ii_i32(TCGOpcode opc, TCGv_i32 arg1, |
334 |
TCGv_i32 arg2, TCGv_i32 arg3, |
335 |
TCGv_i32 arg4, TCGArg arg5, TCGArg arg6) |
336 |
{ |
337 |
*gen_opc_ptr++ = opc; |
338 |
*gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
339 |
*gen_opparam_ptr++ = GET_TCGV_I32(arg2); |
340 |
*gen_opparam_ptr++ = GET_TCGV_I32(arg3); |
341 |
*gen_opparam_ptr++ = GET_TCGV_I32(arg4); |
342 |
*gen_opparam_ptr++ = arg5; |
343 |
*gen_opparam_ptr++ = arg6; |
344 |
} |
345 |
|
346 |
static inline void tcg_gen_op6ii_i64(TCGOpcode opc, TCGv_i64 arg1, |
347 |
TCGv_i64 arg2, TCGv_i64 arg3, |
348 |
TCGv_i64 arg4, TCGArg arg5, TCGArg arg6) |
349 |
{ |
350 |
*gen_opc_ptr++ = opc; |
351 |
*gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
352 |
*gen_opparam_ptr++ = GET_TCGV_I64(arg2); |
353 |
*gen_opparam_ptr++ = GET_TCGV_I64(arg3); |
354 |
*gen_opparam_ptr++ = GET_TCGV_I64(arg4); |
355 |
*gen_opparam_ptr++ = arg5; |
356 |
*gen_opparam_ptr++ = arg6; |
357 |
} |
358 |
|
359 |
static inline void gen_set_label(int n) |
360 |
{ |
361 |
tcg_gen_op1i(INDEX_op_set_label, n); |
362 |
} |
363 |
|
364 |
static inline void tcg_gen_br(int label) |
365 |
{ |
366 |
tcg_gen_op1i(INDEX_op_br, label); |
367 |
} |
368 |
|
369 |
static inline void tcg_gen_mov_i32(TCGv_i32 ret, TCGv_i32 arg) |
370 |
{ |
371 |
if (!TCGV_EQUAL_I32(ret, arg))
|
372 |
tcg_gen_op2_i32(INDEX_op_mov_i32, ret, arg); |
373 |
} |
374 |
|
375 |
static inline void tcg_gen_movi_i32(TCGv_i32 ret, int32_t arg) |
376 |
{ |
377 |
tcg_gen_op2i_i32(INDEX_op_movi_i32, ret, arg); |
378 |
} |
379 |
|
380 |
/* A version of dh_sizemask from def-helper.h that doesn't rely on
|
381 |
preprocessor magic. */
|
382 |
static inline int tcg_gen_sizemask(int n, int is_64bit, int is_signed) |
383 |
{ |
384 |
return (is_64bit << n*2) | (is_signed << (n*2 + 1)); |
385 |
} |
386 |
|
387 |
/* helper calls */
|
388 |
static inline void tcg_gen_helperN(void *func, int flags, int sizemask, |
389 |
TCGArg ret, int nargs, TCGArg *args)
|
390 |
{ |
391 |
TCGv_ptr fn; |
392 |
fn = tcg_const_ptr(func); |
393 |
tcg_gen_callN(&tcg_ctx, fn, flags, sizemask, ret, |
394 |
nargs, args); |
395 |
tcg_temp_free_ptr(fn); |
396 |
} |
397 |
|
398 |
/* Note: Both tcg_gen_helper32() and tcg_gen_helper64() are currently
|
399 |
reserved for helpers in tcg-runtime.c. These helpers are all const
|
400 |
and pure, hence the call to tcg_gen_callN() with TCG_CALL_CONST |
|
401 |
TCG_CALL_PURE. This may need to be adjusted if these functions
|
402 |
start to be used with other helpers. */
|
403 |
static inline void tcg_gen_helper32(void *func, int sizemask, TCGv_i32 ret, |
404 |
TCGv_i32 a, TCGv_i32 b) |
405 |
{ |
406 |
TCGv_ptr fn; |
407 |
TCGArg args[2];
|
408 |
fn = tcg_const_ptr(func); |
409 |
args[0] = GET_TCGV_I32(a);
|
410 |
args[1] = GET_TCGV_I32(b);
|
411 |
tcg_gen_callN(&tcg_ctx, fn, TCG_CALL_CONST | TCG_CALL_PURE, sizemask, |
412 |
GET_TCGV_I32(ret), 2, args);
|
413 |
tcg_temp_free_ptr(fn); |
414 |
} |
415 |
|
416 |
static inline void tcg_gen_helper64(void *func, int sizemask, TCGv_i64 ret, |
417 |
TCGv_i64 a, TCGv_i64 b) |
418 |
{ |
419 |
TCGv_ptr fn; |
420 |
TCGArg args[2];
|
421 |
fn = tcg_const_ptr(func); |
422 |
args[0] = GET_TCGV_I64(a);
|
423 |
args[1] = GET_TCGV_I64(b);
|
424 |
tcg_gen_callN(&tcg_ctx, fn, TCG_CALL_CONST | TCG_CALL_PURE, sizemask, |
425 |
GET_TCGV_I64(ret), 2, args);
|
426 |
tcg_temp_free_ptr(fn); |
427 |
} |
428 |
|
429 |
/* 32 bit ops */
|
430 |
|
431 |
static inline void tcg_gen_ld8u_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset) |
432 |
{ |
433 |
tcg_gen_ldst_op_i32(INDEX_op_ld8u_i32, ret, arg2, offset); |
434 |
} |
435 |
|
436 |
static inline void tcg_gen_ld8s_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset) |
437 |
{ |
438 |
tcg_gen_ldst_op_i32(INDEX_op_ld8s_i32, ret, arg2, offset); |
439 |
} |
440 |
|
441 |
static inline void tcg_gen_ld16u_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset) |
442 |
{ |
443 |
tcg_gen_ldst_op_i32(INDEX_op_ld16u_i32, ret, arg2, offset); |
444 |
} |
445 |
|
446 |
static inline void tcg_gen_ld16s_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset) |
447 |
{ |
448 |
tcg_gen_ldst_op_i32(INDEX_op_ld16s_i32, ret, arg2, offset); |
449 |
} |
450 |
|
451 |
static inline void tcg_gen_ld_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset) |
452 |
{ |
453 |
tcg_gen_ldst_op_i32(INDEX_op_ld_i32, ret, arg2, offset); |
454 |
} |
455 |
|
456 |
static inline void tcg_gen_st8_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset) |
457 |
{ |
458 |
tcg_gen_ldst_op_i32(INDEX_op_st8_i32, arg1, arg2, offset); |
459 |
} |
460 |
|
461 |
static inline void tcg_gen_st16_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset) |
462 |
{ |
463 |
tcg_gen_ldst_op_i32(INDEX_op_st16_i32, arg1, arg2, offset); |
464 |
} |
465 |
|
466 |
static inline void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset) |
467 |
{ |
468 |
tcg_gen_ldst_op_i32(INDEX_op_st_i32, arg1, arg2, offset); |
469 |
} |
470 |
|
471 |
static inline void tcg_gen_add_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
472 |
{ |
473 |
tcg_gen_op3_i32(INDEX_op_add_i32, ret, arg1, arg2); |
474 |
} |
475 |
|
476 |
static inline void tcg_gen_addi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
477 |
{ |
478 |
/* some cases can be optimized here */
|
479 |
if (arg2 == 0) { |
480 |
tcg_gen_mov_i32(ret, arg1); |
481 |
} else {
|
482 |
TCGv_i32 t0 = tcg_const_i32(arg2); |
483 |
tcg_gen_add_i32(ret, arg1, t0); |
484 |
tcg_temp_free_i32(t0); |
485 |
} |
486 |
} |
487 |
|
488 |
static inline void tcg_gen_sub_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
489 |
{ |
490 |
tcg_gen_op3_i32(INDEX_op_sub_i32, ret, arg1, arg2); |
491 |
} |
492 |
|
493 |
static inline void tcg_gen_subfi_i32(TCGv_i32 ret, int32_t arg1, TCGv_i32 arg2) |
494 |
{ |
495 |
TCGv_i32 t0 = tcg_const_i32(arg1); |
496 |
tcg_gen_sub_i32(ret, t0, arg2); |
497 |
tcg_temp_free_i32(t0); |
498 |
} |
499 |
|
500 |
static inline void tcg_gen_subi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
501 |
{ |
502 |
/* some cases can be optimized here */
|
503 |
if (arg2 == 0) { |
504 |
tcg_gen_mov_i32(ret, arg1); |
505 |
} else {
|
506 |
TCGv_i32 t0 = tcg_const_i32(arg2); |
507 |
tcg_gen_sub_i32(ret, arg1, t0); |
508 |
tcg_temp_free_i32(t0); |
509 |
} |
510 |
} |
511 |
|
512 |
static inline void tcg_gen_and_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
513 |
{ |
514 |
if (TCGV_EQUAL_I32(arg1, arg2)) {
|
515 |
tcg_gen_mov_i32(ret, arg1); |
516 |
} else {
|
517 |
tcg_gen_op3_i32(INDEX_op_and_i32, ret, arg1, arg2); |
518 |
} |
519 |
} |
520 |
|
521 |
static inline void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
522 |
{ |
523 |
/* some cases can be optimized here */
|
524 |
if (arg2 == 0) { |
525 |
tcg_gen_movi_i32(ret, 0);
|
526 |
} else if (arg2 == 0xffffffff) { |
527 |
tcg_gen_mov_i32(ret, arg1); |
528 |
} else {
|
529 |
TCGv_i32 t0 = tcg_const_i32(arg2); |
530 |
tcg_gen_and_i32(ret, arg1, t0); |
531 |
tcg_temp_free_i32(t0); |
532 |
} |
533 |
} |
534 |
|
535 |
static inline void tcg_gen_or_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
536 |
{ |
537 |
if (TCGV_EQUAL_I32(arg1, arg2)) {
|
538 |
tcg_gen_mov_i32(ret, arg1); |
539 |
} else {
|
540 |
tcg_gen_op3_i32(INDEX_op_or_i32, ret, arg1, arg2); |
541 |
} |
542 |
} |
543 |
|
544 |
static inline void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
545 |
{ |
546 |
/* some cases can be optimized here */
|
547 |
if (arg2 == 0xffffffff) { |
548 |
tcg_gen_movi_i32(ret, 0xffffffff);
|
549 |
} else if (arg2 == 0) { |
550 |
tcg_gen_mov_i32(ret, arg1); |
551 |
} else {
|
552 |
TCGv_i32 t0 = tcg_const_i32(arg2); |
553 |
tcg_gen_or_i32(ret, arg1, t0); |
554 |
tcg_temp_free_i32(t0); |
555 |
} |
556 |
} |
557 |
|
558 |
static inline void tcg_gen_xor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
559 |
{ |
560 |
if (TCGV_EQUAL_I32(arg1, arg2)) {
|
561 |
tcg_gen_movi_i32(ret, 0);
|
562 |
} else {
|
563 |
tcg_gen_op3_i32(INDEX_op_xor_i32, ret, arg1, arg2); |
564 |
} |
565 |
} |
566 |
|
567 |
static inline void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
568 |
{ |
569 |
/* some cases can be optimized here */
|
570 |
if (arg2 == 0) { |
571 |
tcg_gen_mov_i32(ret, arg1); |
572 |
} else {
|
573 |
TCGv_i32 t0 = tcg_const_i32(arg2); |
574 |
tcg_gen_xor_i32(ret, arg1, t0); |
575 |
tcg_temp_free_i32(t0); |
576 |
} |
577 |
} |
578 |
|
579 |
static inline void tcg_gen_shl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
580 |
{ |
581 |
tcg_gen_op3_i32(INDEX_op_shl_i32, ret, arg1, arg2); |
582 |
} |
583 |
|
584 |
static inline void tcg_gen_shli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
585 |
{ |
586 |
if (arg2 == 0) { |
587 |
tcg_gen_mov_i32(ret, arg1); |
588 |
} else {
|
589 |
TCGv_i32 t0 = tcg_const_i32(arg2); |
590 |
tcg_gen_shl_i32(ret, arg1, t0); |
591 |
tcg_temp_free_i32(t0); |
592 |
} |
593 |
} |
594 |
|
595 |
static inline void tcg_gen_shr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
596 |
{ |
597 |
tcg_gen_op3_i32(INDEX_op_shr_i32, ret, arg1, arg2); |
598 |
} |
599 |
|
600 |
static inline void tcg_gen_shri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
601 |
{ |
602 |
if (arg2 == 0) { |
603 |
tcg_gen_mov_i32(ret, arg1); |
604 |
} else {
|
605 |
TCGv_i32 t0 = tcg_const_i32(arg2); |
606 |
tcg_gen_shr_i32(ret, arg1, t0); |
607 |
tcg_temp_free_i32(t0); |
608 |
} |
609 |
} |
610 |
|
611 |
static inline void tcg_gen_sar_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
612 |
{ |
613 |
tcg_gen_op3_i32(INDEX_op_sar_i32, ret, arg1, arg2); |
614 |
} |
615 |
|
616 |
static inline void tcg_gen_sari_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
617 |
{ |
618 |
if (arg2 == 0) { |
619 |
tcg_gen_mov_i32(ret, arg1); |
620 |
} else {
|
621 |
TCGv_i32 t0 = tcg_const_i32(arg2); |
622 |
tcg_gen_sar_i32(ret, arg1, t0); |
623 |
tcg_temp_free_i32(t0); |
624 |
} |
625 |
} |
626 |
|
627 |
static inline void tcg_gen_brcond_i32(TCGCond cond, TCGv_i32 arg1, |
628 |
TCGv_i32 arg2, int label_index)
|
629 |
{ |
630 |
tcg_gen_op4ii_i32(INDEX_op_brcond_i32, arg1, arg2, cond, label_index); |
631 |
} |
632 |
|
633 |
static inline void tcg_gen_brcondi_i32(TCGCond cond, TCGv_i32 arg1, |
634 |
int32_t arg2, int label_index)
|
635 |
{ |
636 |
TCGv_i32 t0 = tcg_const_i32(arg2); |
637 |
tcg_gen_brcond_i32(cond, arg1, t0, label_index); |
638 |
tcg_temp_free_i32(t0); |
639 |
} |
640 |
|
641 |
static inline void tcg_gen_setcond_i32(TCGCond cond, TCGv_i32 ret, |
642 |
TCGv_i32 arg1, TCGv_i32 arg2) |
643 |
{ |
644 |
tcg_gen_op4i_i32(INDEX_op_setcond_i32, ret, arg1, arg2, cond); |
645 |
} |
646 |
|
647 |
static inline void tcg_gen_setcondi_i32(TCGCond cond, TCGv_i32 ret, |
648 |
TCGv_i32 arg1, int32_t arg2) |
649 |
{ |
650 |
TCGv_i32 t0 = tcg_const_i32(arg2); |
651 |
tcg_gen_setcond_i32(cond, ret, arg1, t0); |
652 |
tcg_temp_free_i32(t0); |
653 |
} |
654 |
|
655 |
static inline void tcg_gen_mul_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
656 |
{ |
657 |
tcg_gen_op3_i32(INDEX_op_mul_i32, ret, arg1, arg2); |
658 |
} |
659 |
|
660 |
static inline void tcg_gen_muli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
661 |
{ |
662 |
TCGv_i32 t0 = tcg_const_i32(arg2); |
663 |
tcg_gen_mul_i32(ret, arg1, t0); |
664 |
tcg_temp_free_i32(t0); |
665 |
} |
666 |
|
667 |
static inline void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
668 |
{ |
669 |
if (TCG_TARGET_HAS_div_i32) {
|
670 |
tcg_gen_op3_i32(INDEX_op_div_i32, ret, arg1, arg2); |
671 |
} else if (TCG_TARGET_HAS_div2_i32) { |
672 |
TCGv_i32 t0 = tcg_temp_new_i32(); |
673 |
tcg_gen_sari_i32(t0, arg1, 31);
|
674 |
tcg_gen_op5_i32(INDEX_op_div2_i32, ret, t0, arg1, t0, arg2); |
675 |
tcg_temp_free_i32(t0); |
676 |
} else {
|
677 |
int sizemask = 0; |
678 |
/* Return value and both arguments are 32-bit and signed. */
|
679 |
sizemask |= tcg_gen_sizemask(0, 0, 1); |
680 |
sizemask |= tcg_gen_sizemask(1, 0, 1); |
681 |
sizemask |= tcg_gen_sizemask(2, 0, 1); |
682 |
tcg_gen_helper32(tcg_helper_div_i32, sizemask, ret, arg1, arg2); |
683 |
} |
684 |
} |
685 |
|
686 |
static inline void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
687 |
{ |
688 |
if (TCG_TARGET_HAS_div_i32) {
|
689 |
tcg_gen_op3_i32(INDEX_op_rem_i32, ret, arg1, arg2); |
690 |
} else if (TCG_TARGET_HAS_div2_i32) { |
691 |
TCGv_i32 t0 = tcg_temp_new_i32(); |
692 |
tcg_gen_sari_i32(t0, arg1, 31);
|
693 |
tcg_gen_op5_i32(INDEX_op_div2_i32, t0, ret, arg1, t0, arg2); |
694 |
tcg_temp_free_i32(t0); |
695 |
} else {
|
696 |
int sizemask = 0; |
697 |
/* Return value and both arguments are 32-bit and signed. */
|
698 |
sizemask |= tcg_gen_sizemask(0, 0, 1); |
699 |
sizemask |= tcg_gen_sizemask(1, 0, 1); |
700 |
sizemask |= tcg_gen_sizemask(2, 0, 1); |
701 |
tcg_gen_helper32(tcg_helper_rem_i32, sizemask, ret, arg1, arg2); |
702 |
} |
703 |
} |
704 |
|
705 |
static inline void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
706 |
{ |
707 |
if (TCG_TARGET_HAS_div_i32) {
|
708 |
tcg_gen_op3_i32(INDEX_op_divu_i32, ret, arg1, arg2); |
709 |
} else if (TCG_TARGET_HAS_div2_i32) { |
710 |
TCGv_i32 t0 = tcg_temp_new_i32(); |
711 |
tcg_gen_movi_i32(t0, 0);
|
712 |
tcg_gen_op5_i32(INDEX_op_divu2_i32, ret, t0, arg1, t0, arg2); |
713 |
tcg_temp_free_i32(t0); |
714 |
} else {
|
715 |
int sizemask = 0; |
716 |
/* Return value and both arguments are 32-bit and unsigned. */
|
717 |
sizemask |= tcg_gen_sizemask(0, 0, 0); |
718 |
sizemask |= tcg_gen_sizemask(1, 0, 0); |
719 |
sizemask |= tcg_gen_sizemask(2, 0, 0); |
720 |
tcg_gen_helper32(tcg_helper_divu_i32, sizemask, ret, arg1, arg2); |
721 |
} |
722 |
} |
723 |
|
724 |
static inline void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
725 |
{ |
726 |
if (TCG_TARGET_HAS_div_i32) {
|
727 |
tcg_gen_op3_i32(INDEX_op_remu_i32, ret, arg1, arg2); |
728 |
} else if (TCG_TARGET_HAS_div2_i32) { |
729 |
TCGv_i32 t0 = tcg_temp_new_i32(); |
730 |
tcg_gen_movi_i32(t0, 0);
|
731 |
tcg_gen_op5_i32(INDEX_op_divu2_i32, t0, ret, arg1, t0, arg2); |
732 |
tcg_temp_free_i32(t0); |
733 |
} else {
|
734 |
int sizemask = 0; |
735 |
/* Return value and both arguments are 32-bit and unsigned. */
|
736 |
sizemask |= tcg_gen_sizemask(0, 0, 0); |
737 |
sizemask |= tcg_gen_sizemask(1, 0, 0); |
738 |
sizemask |= tcg_gen_sizemask(2, 0, 0); |
739 |
tcg_gen_helper32(tcg_helper_remu_i32, sizemask, ret, arg1, arg2); |
740 |
} |
741 |
} |
742 |
|
743 |
#if TCG_TARGET_REG_BITS == 32 |
744 |
|
745 |
static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg) |
746 |
{ |
747 |
if (!TCGV_EQUAL_I64(ret, arg)) {
|
748 |
tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
749 |
tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg)); |
750 |
} |
751 |
} |
752 |
|
753 |
static inline void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg) |
754 |
{ |
755 |
tcg_gen_movi_i32(TCGV_LOW(ret), arg); |
756 |
tcg_gen_movi_i32(TCGV_HIGH(ret), arg >> 32);
|
757 |
} |
758 |
|
759 |
static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2, |
760 |
tcg_target_long offset) |
761 |
{ |
762 |
tcg_gen_ld8u_i32(TCGV_LOW(ret), arg2, offset); |
763 |
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
764 |
} |
765 |
|
766 |
static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2, |
767 |
tcg_target_long offset) |
768 |
{ |
769 |
tcg_gen_ld8s_i32(TCGV_LOW(ret), arg2, offset); |
770 |
tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_HIGH(ret), 31);
|
771 |
} |
772 |
|
773 |
static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2, |
774 |
tcg_target_long offset) |
775 |
{ |
776 |
tcg_gen_ld16u_i32(TCGV_LOW(ret), arg2, offset); |
777 |
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
778 |
} |
779 |
|
780 |
static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2, |
781 |
tcg_target_long offset) |
782 |
{ |
783 |
tcg_gen_ld16s_i32(TCGV_LOW(ret), arg2, offset); |
784 |
tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
|
785 |
} |
786 |
|
787 |
static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2, |
788 |
tcg_target_long offset) |
789 |
{ |
790 |
tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset); |
791 |
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
792 |
} |
793 |
|
794 |
static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2, |
795 |
tcg_target_long offset) |
796 |
{ |
797 |
tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset); |
798 |
tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
|
799 |
} |
800 |
|
801 |
static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2, |
802 |
tcg_target_long offset) |
803 |
{ |
804 |
/* since arg2 and ret have different types, they cannot be the
|
805 |
same temporary */
|
806 |
#ifdef TCG_TARGET_WORDS_BIGENDIAN
|
807 |
tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset); |
808 |
tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset + 4);
|
809 |
#else
|
810 |
tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset); |
811 |
tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset + 4);
|
812 |
#endif
|
813 |
} |
814 |
|
815 |
static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
816 |
tcg_target_long offset) |
817 |
{ |
818 |
tcg_gen_st8_i32(TCGV_LOW(arg1), arg2, offset); |
819 |
} |
820 |
|
821 |
static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
822 |
tcg_target_long offset) |
823 |
{ |
824 |
tcg_gen_st16_i32(TCGV_LOW(arg1), arg2, offset); |
825 |
} |
826 |
|
827 |
static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
828 |
tcg_target_long offset) |
829 |
{ |
830 |
tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset); |
831 |
} |
832 |
|
833 |
static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
834 |
tcg_target_long offset) |
835 |
{ |
836 |
#ifdef TCG_TARGET_WORDS_BIGENDIAN
|
837 |
tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset); |
838 |
tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset + 4);
|
839 |
#else
|
840 |
tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset); |
841 |
tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset + 4);
|
842 |
#endif
|
843 |
} |
844 |
|
845 |
static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
846 |
{ |
847 |
tcg_gen_op6_i32(INDEX_op_add2_i32, TCGV_LOW(ret), TCGV_HIGH(ret), |
848 |
TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2), |
849 |
TCGV_HIGH(arg2)); |
850 |
} |
851 |
|
852 |
static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
853 |
{ |
854 |
tcg_gen_op6_i32(INDEX_op_sub2_i32, TCGV_LOW(ret), TCGV_HIGH(ret), |
855 |
TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2), |
856 |
TCGV_HIGH(arg2)); |
857 |
} |
858 |
|
859 |
static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
860 |
{ |
861 |
tcg_gen_and_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); |
862 |
tcg_gen_and_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); |
863 |
} |
864 |
|
865 |
static inline void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
866 |
{ |
867 |
tcg_gen_andi_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2); |
868 |
tcg_gen_andi_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
|
869 |
} |
870 |
|
871 |
static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
872 |
{ |
873 |
tcg_gen_or_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); |
874 |
tcg_gen_or_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); |
875 |
} |
876 |
|
877 |
static inline void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
878 |
{ |
879 |
tcg_gen_ori_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2); |
880 |
tcg_gen_ori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
|
881 |
} |
882 |
|
883 |
static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
884 |
{ |
885 |
tcg_gen_xor_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); |
886 |
tcg_gen_xor_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); |
887 |
} |
888 |
|
889 |
static inline void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
890 |
{ |
891 |
tcg_gen_xori_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2); |
892 |
tcg_gen_xori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
|
893 |
} |
894 |
|
895 |
/* XXX: use generic code when basic block handling is OK or CPU
|
896 |
specific code (x86) */
|
897 |
static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
898 |
{ |
899 |
int sizemask = 0; |
900 |
/* Return value and both arguments are 64-bit and signed. */
|
901 |
sizemask |= tcg_gen_sizemask(0, 1, 1); |
902 |
sizemask |= tcg_gen_sizemask(1, 1, 1); |
903 |
sizemask |= tcg_gen_sizemask(2, 1, 1); |
904 |
|
905 |
tcg_gen_helper64(tcg_helper_shl_i64, sizemask, ret, arg1, arg2); |
906 |
} |
907 |
|
908 |
static inline void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
909 |
{ |
910 |
tcg_gen_shifti_i64(ret, arg1, arg2, 0, 0); |
911 |
} |
912 |
|
913 |
static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
914 |
{ |
915 |
int sizemask = 0; |
916 |
/* Return value and both arguments are 64-bit and signed. */
|
917 |
sizemask |= tcg_gen_sizemask(0, 1, 1); |
918 |
sizemask |= tcg_gen_sizemask(1, 1, 1); |
919 |
sizemask |= tcg_gen_sizemask(2, 1, 1); |
920 |
|
921 |
tcg_gen_helper64(tcg_helper_shr_i64, sizemask, ret, arg1, arg2); |
922 |
} |
923 |
|
924 |
static inline void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
925 |
{ |
926 |
tcg_gen_shifti_i64(ret, arg1, arg2, 1, 0); |
927 |
} |
928 |
|
929 |
static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
930 |
{ |
931 |
int sizemask = 0; |
932 |
/* Return value and both arguments are 64-bit and signed. */
|
933 |
sizemask |= tcg_gen_sizemask(0, 1, 1); |
934 |
sizemask |= tcg_gen_sizemask(1, 1, 1); |
935 |
sizemask |= tcg_gen_sizemask(2, 1, 1); |
936 |
|
937 |
tcg_gen_helper64(tcg_helper_sar_i64, sizemask, ret, arg1, arg2); |
938 |
} |
939 |
|
940 |
static inline void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
941 |
{ |
942 |
tcg_gen_shifti_i64(ret, arg1, arg2, 1, 1); |
943 |
} |
944 |
|
945 |
static inline void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1, |
946 |
TCGv_i64 arg2, int label_index)
|
947 |
{ |
948 |
tcg_gen_op6ii_i32(INDEX_op_brcond2_i32, |
949 |
TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2), |
950 |
TCGV_HIGH(arg2), cond, label_index); |
951 |
} |
952 |
|
953 |
static inline void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret, |
954 |
TCGv_i64 arg1, TCGv_i64 arg2) |
955 |
{ |
956 |
tcg_gen_op6i_i32(INDEX_op_setcond2_i32, TCGV_LOW(ret), |
957 |
TCGV_LOW(arg1), TCGV_HIGH(arg1), |
958 |
TCGV_LOW(arg2), TCGV_HIGH(arg2), cond); |
959 |
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
960 |
} |
961 |
|
962 |
static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
963 |
{ |
964 |
TCGv_i64 t0; |
965 |
TCGv_i32 t1; |
966 |
|
967 |
t0 = tcg_temp_new_i64(); |
968 |
t1 = tcg_temp_new_i32(); |
969 |
|
970 |
tcg_gen_op4_i32(INDEX_op_mulu2_i32, TCGV_LOW(t0), TCGV_HIGH(t0), |
971 |
TCGV_LOW(arg1), TCGV_LOW(arg2)); |
972 |
|
973 |
tcg_gen_mul_i32(t1, TCGV_LOW(arg1), TCGV_HIGH(arg2)); |
974 |
tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1); |
975 |
tcg_gen_mul_i32(t1, TCGV_HIGH(arg1), TCGV_LOW(arg2)); |
976 |
tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1); |
977 |
|
978 |
tcg_gen_mov_i64(ret, t0); |
979 |
tcg_temp_free_i64(t0); |
980 |
tcg_temp_free_i32(t1); |
981 |
} |
982 |
|
983 |
static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
984 |
{ |
985 |
int sizemask = 0; |
986 |
/* Return value and both arguments are 64-bit and signed. */
|
987 |
sizemask |= tcg_gen_sizemask(0, 1, 1); |
988 |
sizemask |= tcg_gen_sizemask(1, 1, 1); |
989 |
sizemask |= tcg_gen_sizemask(2, 1, 1); |
990 |
|
991 |
tcg_gen_helper64(tcg_helper_div_i64, sizemask, ret, arg1, arg2); |
992 |
} |
993 |
|
994 |
static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
995 |
{ |
996 |
int sizemask = 0; |
997 |
/* Return value and both arguments are 64-bit and signed. */
|
998 |
sizemask |= tcg_gen_sizemask(0, 1, 1); |
999 |
sizemask |= tcg_gen_sizemask(1, 1, 1); |
1000 |
sizemask |= tcg_gen_sizemask(2, 1, 1); |
1001 |
|
1002 |
tcg_gen_helper64(tcg_helper_rem_i64, sizemask, ret, arg1, arg2); |
1003 |
} |
1004 |
|
1005 |
static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1006 |
{ |
1007 |
int sizemask = 0; |
1008 |
/* Return value and both arguments are 64-bit and unsigned. */
|
1009 |
sizemask |= tcg_gen_sizemask(0, 1, 0); |
1010 |
sizemask |= tcg_gen_sizemask(1, 1, 0); |
1011 |
sizemask |= tcg_gen_sizemask(2, 1, 0); |
1012 |
|
1013 |
tcg_gen_helper64(tcg_helper_divu_i64, sizemask, ret, arg1, arg2); |
1014 |
} |
1015 |
|
1016 |
static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1017 |
{ |
1018 |
int sizemask = 0; |
1019 |
/* Return value and both arguments are 64-bit and unsigned. */
|
1020 |
sizemask |= tcg_gen_sizemask(0, 1, 0); |
1021 |
sizemask |= tcg_gen_sizemask(1, 1, 0); |
1022 |
sizemask |= tcg_gen_sizemask(2, 1, 0); |
1023 |
|
1024 |
tcg_gen_helper64(tcg_helper_remu_i64, sizemask, ret, arg1, arg2); |
1025 |
} |
1026 |
|
1027 |
#else
|
1028 |
|
1029 |
static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg) |
1030 |
{ |
1031 |
if (!TCGV_EQUAL_I64(ret, arg))
|
1032 |
tcg_gen_op2_i64(INDEX_op_mov_i64, ret, arg); |
1033 |
} |
1034 |
|
1035 |
static inline void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg) |
1036 |
{ |
1037 |
tcg_gen_op2i_i64(INDEX_op_movi_i64, ret, arg); |
1038 |
} |
1039 |
|
1040 |
static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2, |
1041 |
tcg_target_long offset) |
1042 |
{ |
1043 |
tcg_gen_ldst_op_i64(INDEX_op_ld8u_i64, ret, arg2, offset); |
1044 |
} |
1045 |
|
1046 |
static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2, |
1047 |
tcg_target_long offset) |
1048 |
{ |
1049 |
tcg_gen_ldst_op_i64(INDEX_op_ld8s_i64, ret, arg2, offset); |
1050 |
} |
1051 |
|
1052 |
static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2, |
1053 |
tcg_target_long offset) |
1054 |
{ |
1055 |
tcg_gen_ldst_op_i64(INDEX_op_ld16u_i64, ret, arg2, offset); |
1056 |
} |
1057 |
|
1058 |
static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2, |
1059 |
tcg_target_long offset) |
1060 |
{ |
1061 |
tcg_gen_ldst_op_i64(INDEX_op_ld16s_i64, ret, arg2, offset); |
1062 |
} |
1063 |
|
1064 |
static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2, |
1065 |
tcg_target_long offset) |
1066 |
{ |
1067 |
tcg_gen_ldst_op_i64(INDEX_op_ld32u_i64, ret, arg2, offset); |
1068 |
} |
1069 |
|
1070 |
static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2, |
1071 |
tcg_target_long offset) |
1072 |
{ |
1073 |
tcg_gen_ldst_op_i64(INDEX_op_ld32s_i64, ret, arg2, offset); |
1074 |
} |
1075 |
|
1076 |
static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset) |
1077 |
{ |
1078 |
tcg_gen_ldst_op_i64(INDEX_op_ld_i64, ret, arg2, offset); |
1079 |
} |
1080 |
|
1081 |
static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
1082 |
tcg_target_long offset) |
1083 |
{ |
1084 |
tcg_gen_ldst_op_i64(INDEX_op_st8_i64, arg1, arg2, offset); |
1085 |
} |
1086 |
|
1087 |
static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
1088 |
tcg_target_long offset) |
1089 |
{ |
1090 |
tcg_gen_ldst_op_i64(INDEX_op_st16_i64, arg1, arg2, offset); |
1091 |
} |
1092 |
|
1093 |
static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
1094 |
tcg_target_long offset) |
1095 |
{ |
1096 |
tcg_gen_ldst_op_i64(INDEX_op_st32_i64, arg1, arg2, offset); |
1097 |
} |
1098 |
|
1099 |
static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset) |
1100 |
{ |
1101 |
tcg_gen_ldst_op_i64(INDEX_op_st_i64, arg1, arg2, offset); |
1102 |
} |
1103 |
|
1104 |
static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1105 |
{ |
1106 |
tcg_gen_op3_i64(INDEX_op_add_i64, ret, arg1, arg2); |
1107 |
} |
1108 |
|
1109 |
static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1110 |
{ |
1111 |
tcg_gen_op3_i64(INDEX_op_sub_i64, ret, arg1, arg2); |
1112 |
} |
1113 |
|
1114 |
static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1115 |
{ |
1116 |
if (TCGV_EQUAL_I64(arg1, arg2)) {
|
1117 |
tcg_gen_mov_i64(ret, arg1); |
1118 |
} else {
|
1119 |
tcg_gen_op3_i64(INDEX_op_and_i64, ret, arg1, arg2); |
1120 |
} |
1121 |
} |
1122 |
|
1123 |
static inline void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
1124 |
{ |
1125 |
TCGv_i64 t0 = tcg_const_i64(arg2); |
1126 |
tcg_gen_and_i64(ret, arg1, t0); |
1127 |
tcg_temp_free_i64(t0); |
1128 |
} |
1129 |
|
1130 |
static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1131 |
{ |
1132 |
if (TCGV_EQUAL_I64(arg1, arg2)) {
|
1133 |
tcg_gen_mov_i64(ret, arg1); |
1134 |
} else {
|
1135 |
tcg_gen_op3_i64(INDEX_op_or_i64, ret, arg1, arg2); |
1136 |
} |
1137 |
} |
1138 |
|
1139 |
static inline void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
1140 |
{ |
1141 |
TCGv_i64 t0 = tcg_const_i64(arg2); |
1142 |
tcg_gen_or_i64(ret, arg1, t0); |
1143 |
tcg_temp_free_i64(t0); |
1144 |
} |
1145 |
|
1146 |
static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1147 |
{ |
1148 |
if (TCGV_EQUAL_I64(arg1, arg2)) {
|
1149 |
tcg_gen_movi_i64(ret, 0);
|
1150 |
} else {
|
1151 |
tcg_gen_op3_i64(INDEX_op_xor_i64, ret, arg1, arg2); |
1152 |
} |
1153 |
} |
1154 |
|
1155 |
static inline void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
1156 |
{ |
1157 |
TCGv_i64 t0 = tcg_const_i64(arg2); |
1158 |
tcg_gen_xor_i64(ret, arg1, t0); |
1159 |
tcg_temp_free_i64(t0); |
1160 |
} |
1161 |
|
1162 |
static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1163 |
{ |
1164 |
tcg_gen_op3_i64(INDEX_op_shl_i64, ret, arg1, arg2); |
1165 |
} |
1166 |
|
1167 |
static inline void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
1168 |
{ |
1169 |
if (arg2 == 0) { |
1170 |
tcg_gen_mov_i64(ret, arg1); |
1171 |
} else {
|
1172 |
TCGv_i64 t0 = tcg_const_i64(arg2); |
1173 |
tcg_gen_shl_i64(ret, arg1, t0); |
1174 |
tcg_temp_free_i64(t0); |
1175 |
} |
1176 |
} |
1177 |
|
1178 |
static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1179 |
{ |
1180 |
tcg_gen_op3_i64(INDEX_op_shr_i64, ret, arg1, arg2); |
1181 |
} |
1182 |
|
1183 |
static inline void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
1184 |
{ |
1185 |
if (arg2 == 0) { |
1186 |
tcg_gen_mov_i64(ret, arg1); |
1187 |
} else {
|
1188 |
TCGv_i64 t0 = tcg_const_i64(arg2); |
1189 |
tcg_gen_shr_i64(ret, arg1, t0); |
1190 |
tcg_temp_free_i64(t0); |
1191 |
} |
1192 |
} |
1193 |
|
1194 |
static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1195 |
{ |
1196 |
tcg_gen_op3_i64(INDEX_op_sar_i64, ret, arg1, arg2); |
1197 |
} |
1198 |
|
1199 |
static inline void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
1200 |
{ |
1201 |
if (arg2 == 0) { |
1202 |
tcg_gen_mov_i64(ret, arg1); |
1203 |
} else {
|
1204 |
TCGv_i64 t0 = tcg_const_i64(arg2); |
1205 |
tcg_gen_sar_i64(ret, arg1, t0); |
1206 |
tcg_temp_free_i64(t0); |
1207 |
} |
1208 |
} |
1209 |
|
1210 |
static inline void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1, |
1211 |
TCGv_i64 arg2, int label_index)
|
1212 |
{ |
1213 |
tcg_gen_op4ii_i64(INDEX_op_brcond_i64, arg1, arg2, cond, label_index); |
1214 |
} |
1215 |
|
1216 |
static inline void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret, |
1217 |
TCGv_i64 arg1, TCGv_i64 arg2) |
1218 |
{ |
1219 |
tcg_gen_op4i_i64(INDEX_op_setcond_i64, ret, arg1, arg2, cond); |
1220 |
} |
1221 |
|
1222 |
static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1223 |
{ |
1224 |
tcg_gen_op3_i64(INDEX_op_mul_i64, ret, arg1, arg2); |
1225 |
} |
1226 |
|
1227 |
static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1228 |
{ |
1229 |
if (TCG_TARGET_HAS_div_i64) {
|
1230 |
tcg_gen_op3_i64(INDEX_op_div_i64, ret, arg1, arg2); |
1231 |
} else if (TCG_TARGET_HAS_div2_i64) { |
1232 |
TCGv_i64 t0 = tcg_temp_new_i64(); |
1233 |
tcg_gen_sari_i64(t0, arg1, 63);
|
1234 |
tcg_gen_op5_i64(INDEX_op_div2_i64, ret, t0, arg1, t0, arg2); |
1235 |
tcg_temp_free_i64(t0); |
1236 |
} else {
|
1237 |
int sizemask = 0; |
1238 |
/* Return value and both arguments are 64-bit and signed. */
|
1239 |
sizemask |= tcg_gen_sizemask(0, 1, 1); |
1240 |
sizemask |= tcg_gen_sizemask(1, 1, 1); |
1241 |
sizemask |= tcg_gen_sizemask(2, 1, 1); |
1242 |
tcg_gen_helper64(tcg_helper_div_i64, sizemask, ret, arg1, arg2); |
1243 |
} |
1244 |
} |
1245 |
|
1246 |
static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1247 |
{ |
1248 |
if (TCG_TARGET_HAS_div_i64) {
|
1249 |
tcg_gen_op3_i64(INDEX_op_rem_i64, ret, arg1, arg2); |
1250 |
} else if (TCG_TARGET_HAS_div2_i64) { |
1251 |
TCGv_i64 t0 = tcg_temp_new_i64(); |
1252 |
tcg_gen_sari_i64(t0, arg1, 63);
|
1253 |
tcg_gen_op5_i64(INDEX_op_div2_i64, t0, ret, arg1, t0, arg2); |
1254 |
tcg_temp_free_i64(t0); |
1255 |
} else {
|
1256 |
int sizemask = 0; |
1257 |
/* Return value and both arguments are 64-bit and signed. */
|
1258 |
sizemask |= tcg_gen_sizemask(0, 1, 1); |
1259 |
sizemask |= tcg_gen_sizemask(1, 1, 1); |
1260 |
sizemask |= tcg_gen_sizemask(2, 1, 1); |
1261 |
tcg_gen_helper64(tcg_helper_rem_i64, sizemask, ret, arg1, arg2); |
1262 |
} |
1263 |
} |
1264 |
|
1265 |
static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1266 |
{ |
1267 |
if (TCG_TARGET_HAS_div_i64) {
|
1268 |
tcg_gen_op3_i64(INDEX_op_divu_i64, ret, arg1, arg2); |
1269 |
} else if (TCG_TARGET_HAS_div2_i64) { |
1270 |
TCGv_i64 t0 = tcg_temp_new_i64(); |
1271 |
tcg_gen_movi_i64(t0, 0);
|
1272 |
tcg_gen_op5_i64(INDEX_op_divu2_i64, ret, t0, arg1, t0, arg2); |
1273 |
tcg_temp_free_i64(t0); |
1274 |
} else {
|
1275 |
int sizemask = 0; |
1276 |
/* Return value and both arguments are 64-bit and unsigned. */
|
1277 |
sizemask |= tcg_gen_sizemask(0, 1, 0); |
1278 |
sizemask |= tcg_gen_sizemask(1, 1, 0); |
1279 |
sizemask |= tcg_gen_sizemask(2, 1, 0); |
1280 |
tcg_gen_helper64(tcg_helper_divu_i64, sizemask, ret, arg1, arg2); |
1281 |
} |
1282 |
} |
1283 |
|
1284 |
static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1285 |
{ |
1286 |
if (TCG_TARGET_HAS_div_i64) {
|
1287 |
tcg_gen_op3_i64(INDEX_op_remu_i64, ret, arg1, arg2); |
1288 |
} else if (TCG_TARGET_HAS_div2_i64) { |
1289 |
TCGv_i64 t0 = tcg_temp_new_i64(); |
1290 |
tcg_gen_movi_i64(t0, 0);
|
1291 |
tcg_gen_op5_i64(INDEX_op_divu2_i64, t0, ret, arg1, t0, arg2); |
1292 |
tcg_temp_free_i64(t0); |
1293 |
} else {
|
1294 |
int sizemask = 0; |
1295 |
/* Return value and both arguments are 64-bit and unsigned. */
|
1296 |
sizemask |= tcg_gen_sizemask(0, 1, 0); |
1297 |
sizemask |= tcg_gen_sizemask(1, 1, 0); |
1298 |
sizemask |= tcg_gen_sizemask(2, 1, 0); |
1299 |
tcg_gen_helper64(tcg_helper_remu_i64, sizemask, ret, arg1, arg2); |
1300 |
} |
1301 |
} |
1302 |
#endif /* TCG_TARGET_REG_BITS == 32 */ |
1303 |
|
1304 |
static inline void tcg_gen_addi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
1305 |
{ |
1306 |
/* some cases can be optimized here */
|
1307 |
if (arg2 == 0) { |
1308 |
tcg_gen_mov_i64(ret, arg1); |
1309 |
} else {
|
1310 |
TCGv_i64 t0 = tcg_const_i64(arg2); |
1311 |
tcg_gen_add_i64(ret, arg1, t0); |
1312 |
tcg_temp_free_i64(t0); |
1313 |
} |
1314 |
} |
1315 |
|
1316 |
static inline void tcg_gen_subfi_i64(TCGv_i64 ret, int64_t arg1, TCGv_i64 arg2) |
1317 |
{ |
1318 |
TCGv_i64 t0 = tcg_const_i64(arg1); |
1319 |
tcg_gen_sub_i64(ret, t0, arg2); |
1320 |
tcg_temp_free_i64(t0); |
1321 |
} |
1322 |
|
1323 |
static inline void tcg_gen_subi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
1324 |
{ |
1325 |
/* some cases can be optimized here */
|
1326 |
if (arg2 == 0) { |
1327 |
tcg_gen_mov_i64(ret, arg1); |
1328 |
} else {
|
1329 |
TCGv_i64 t0 = tcg_const_i64(arg2); |
1330 |
tcg_gen_sub_i64(ret, arg1, t0); |
1331 |
tcg_temp_free_i64(t0); |
1332 |
} |
1333 |
} |
1334 |
static inline void tcg_gen_brcondi_i64(TCGCond cond, TCGv_i64 arg1, |
1335 |
int64_t arg2, int label_index)
|
1336 |
{ |
1337 |
TCGv_i64 t0 = tcg_const_i64(arg2); |
1338 |
tcg_gen_brcond_i64(cond, arg1, t0, label_index); |
1339 |
tcg_temp_free_i64(t0); |
1340 |
} |
1341 |
|
1342 |
static inline void tcg_gen_setcondi_i64(TCGCond cond, TCGv_i64 ret, |
1343 |
TCGv_i64 arg1, int64_t arg2) |
1344 |
{ |
1345 |
TCGv_i64 t0 = tcg_const_i64(arg2); |
1346 |
tcg_gen_setcond_i64(cond, ret, arg1, t0); |
1347 |
tcg_temp_free_i64(t0); |
1348 |
} |
1349 |
|
1350 |
static inline void tcg_gen_muli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
1351 |
{ |
1352 |
TCGv_i64 t0 = tcg_const_i64(arg2); |
1353 |
tcg_gen_mul_i64(ret, arg1, t0); |
1354 |
tcg_temp_free_i64(t0); |
1355 |
} |
1356 |
|
1357 |
|
1358 |
/***************************************/
|
1359 |
/* optional operations */
|
1360 |
|
1361 |
static inline void tcg_gen_ext8s_i32(TCGv_i32 ret, TCGv_i32 arg) |
1362 |
{ |
1363 |
if (TCG_TARGET_HAS_ext8s_i32) {
|
1364 |
tcg_gen_op2_i32(INDEX_op_ext8s_i32, ret, arg); |
1365 |
} else {
|
1366 |
tcg_gen_shli_i32(ret, arg, 24);
|
1367 |
tcg_gen_sari_i32(ret, ret, 24);
|
1368 |
} |
1369 |
} |
1370 |
|
1371 |
static inline void tcg_gen_ext16s_i32(TCGv_i32 ret, TCGv_i32 arg) |
1372 |
{ |
1373 |
if (TCG_TARGET_HAS_ext16s_i32) {
|
1374 |
tcg_gen_op2_i32(INDEX_op_ext16s_i32, ret, arg); |
1375 |
} else {
|
1376 |
tcg_gen_shli_i32(ret, arg, 16);
|
1377 |
tcg_gen_sari_i32(ret, ret, 16);
|
1378 |
} |
1379 |
} |
1380 |
|
1381 |
static inline void tcg_gen_ext8u_i32(TCGv_i32 ret, TCGv_i32 arg) |
1382 |
{ |
1383 |
if (TCG_TARGET_HAS_ext8u_i32) {
|
1384 |
tcg_gen_op2_i32(INDEX_op_ext8u_i32, ret, arg); |
1385 |
} else {
|
1386 |
tcg_gen_andi_i32(ret, arg, 0xffu);
|
1387 |
} |
1388 |
} |
1389 |
|
1390 |
static inline void tcg_gen_ext16u_i32(TCGv_i32 ret, TCGv_i32 arg) |
1391 |
{ |
1392 |
if (TCG_TARGET_HAS_ext16u_i32) {
|
1393 |
tcg_gen_op2_i32(INDEX_op_ext16u_i32, ret, arg); |
1394 |
} else {
|
1395 |
tcg_gen_andi_i32(ret, arg, 0xffffu);
|
1396 |
} |
1397 |
} |
1398 |
|
1399 |
/* Note: we assume the two high bytes are set to zero */
|
1400 |
static inline void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg) |
1401 |
{ |
1402 |
if (TCG_TARGET_HAS_bswap16_i32) {
|
1403 |
tcg_gen_op2_i32(INDEX_op_bswap16_i32, ret, arg); |
1404 |
} else {
|
1405 |
TCGv_i32 t0 = tcg_temp_new_i32(); |
1406 |
|
1407 |
tcg_gen_ext8u_i32(t0, arg); |
1408 |
tcg_gen_shli_i32(t0, t0, 8);
|
1409 |
tcg_gen_shri_i32(ret, arg, 8);
|
1410 |
tcg_gen_or_i32(ret, ret, t0); |
1411 |
tcg_temp_free_i32(t0); |
1412 |
} |
1413 |
} |
1414 |
|
1415 |
static inline void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg) |
1416 |
{ |
1417 |
if (TCG_TARGET_HAS_bswap32_i32) {
|
1418 |
tcg_gen_op2_i32(INDEX_op_bswap32_i32, ret, arg); |
1419 |
} else {
|
1420 |
TCGv_i32 t0, t1; |
1421 |
t0 = tcg_temp_new_i32(); |
1422 |
t1 = tcg_temp_new_i32(); |
1423 |
|
1424 |
tcg_gen_shli_i32(t0, arg, 24);
|
1425 |
|
1426 |
tcg_gen_andi_i32(t1, arg, 0x0000ff00);
|
1427 |
tcg_gen_shli_i32(t1, t1, 8);
|
1428 |
tcg_gen_or_i32(t0, t0, t1); |
1429 |
|
1430 |
tcg_gen_shri_i32(t1, arg, 8);
|
1431 |
tcg_gen_andi_i32(t1, t1, 0x0000ff00);
|
1432 |
tcg_gen_or_i32(t0, t0, t1); |
1433 |
|
1434 |
tcg_gen_shri_i32(t1, arg, 24);
|
1435 |
tcg_gen_or_i32(ret, t0, t1); |
1436 |
tcg_temp_free_i32(t0); |
1437 |
tcg_temp_free_i32(t1); |
1438 |
} |
1439 |
} |
1440 |
|
1441 |
#if TCG_TARGET_REG_BITS == 32 |
1442 |
static inline void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg) |
1443 |
{ |
1444 |
tcg_gen_ext8s_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
1445 |
tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
|
1446 |
} |
1447 |
|
1448 |
static inline void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg) |
1449 |
{ |
1450 |
tcg_gen_ext16s_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
1451 |
tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
|
1452 |
} |
1453 |
|
1454 |
static inline void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg) |
1455 |
{ |
1456 |
tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
1457 |
tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
|
1458 |
} |
1459 |
|
1460 |
static inline void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg) |
1461 |
{ |
1462 |
tcg_gen_ext8u_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
1463 |
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
1464 |
} |
1465 |
|
1466 |
static inline void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg) |
1467 |
{ |
1468 |
tcg_gen_ext16u_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
1469 |
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
1470 |
} |
1471 |
|
1472 |
static inline void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg) |
1473 |
{ |
1474 |
tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
1475 |
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
1476 |
} |
1477 |
|
1478 |
static inline void tcg_gen_trunc_i64_i32(TCGv_i32 ret, TCGv_i64 arg) |
1479 |
{ |
1480 |
tcg_gen_mov_i32(ret, TCGV_LOW(arg)); |
1481 |
} |
1482 |
|
1483 |
static inline void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg) |
1484 |
{ |
1485 |
tcg_gen_mov_i32(TCGV_LOW(ret), arg); |
1486 |
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
1487 |
} |
1488 |
|
1489 |
static inline void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg) |
1490 |
{ |
1491 |
tcg_gen_mov_i32(TCGV_LOW(ret), arg); |
1492 |
tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
|
1493 |
} |
1494 |
|
1495 |
/* Note: we assume the six high bytes are set to zero */
|
1496 |
static inline void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg) |
1497 |
{ |
1498 |
tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg)); |
1499 |
tcg_gen_bswap16_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
1500 |
} |
1501 |
|
1502 |
/* Note: we assume the four high bytes are set to zero */
|
1503 |
static inline void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg) |
1504 |
{ |
1505 |
tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg)); |
1506 |
tcg_gen_bswap32_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
1507 |
} |
1508 |
|
1509 |
static inline void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg) |
1510 |
{ |
1511 |
TCGv_i32 t0, t1; |
1512 |
t0 = tcg_temp_new_i32(); |
1513 |
t1 = tcg_temp_new_i32(); |
1514 |
|
1515 |
tcg_gen_bswap32_i32(t0, TCGV_LOW(arg)); |
1516 |
tcg_gen_bswap32_i32(t1, TCGV_HIGH(arg)); |
1517 |
tcg_gen_mov_i32(TCGV_LOW(ret), t1); |
1518 |
tcg_gen_mov_i32(TCGV_HIGH(ret), t0); |
1519 |
tcg_temp_free_i32(t0); |
1520 |
tcg_temp_free_i32(t1); |
1521 |
} |
1522 |
#else
|
1523 |
|
1524 |
static inline void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg) |
1525 |
{ |
1526 |
if (TCG_TARGET_HAS_ext8s_i64) {
|
1527 |
tcg_gen_op2_i64(INDEX_op_ext8s_i64, ret, arg); |
1528 |
} else {
|
1529 |
tcg_gen_shli_i64(ret, arg, 56);
|
1530 |
tcg_gen_sari_i64(ret, ret, 56);
|
1531 |
} |
1532 |
} |
1533 |
|
1534 |
static inline void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg) |
1535 |
{ |
1536 |
if (TCG_TARGET_HAS_ext16s_i64) {
|
1537 |
tcg_gen_op2_i64(INDEX_op_ext16s_i64, ret, arg); |
1538 |
} else {
|
1539 |
tcg_gen_shli_i64(ret, arg, 48);
|
1540 |
tcg_gen_sari_i64(ret, ret, 48);
|
1541 |
} |
1542 |
} |
1543 |
|
1544 |
static inline void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg) |
1545 |
{ |
1546 |
if (TCG_TARGET_HAS_ext32s_i64) {
|
1547 |
tcg_gen_op2_i64(INDEX_op_ext32s_i64, ret, arg); |
1548 |
} else {
|
1549 |
tcg_gen_shli_i64(ret, arg, 32);
|
1550 |
tcg_gen_sari_i64(ret, ret, 32);
|
1551 |
} |
1552 |
} |
1553 |
|
1554 |
static inline void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg) |
1555 |
{ |
1556 |
if (TCG_TARGET_HAS_ext8u_i64) {
|
1557 |
tcg_gen_op2_i64(INDEX_op_ext8u_i64, ret, arg); |
1558 |
} else {
|
1559 |
tcg_gen_andi_i64(ret, arg, 0xffu);
|
1560 |
} |
1561 |
} |
1562 |
|
1563 |
static inline void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg) |
1564 |
{ |
1565 |
if (TCG_TARGET_HAS_ext16u_i64) {
|
1566 |
tcg_gen_op2_i64(INDEX_op_ext16u_i64, ret, arg); |
1567 |
} else {
|
1568 |
tcg_gen_andi_i64(ret, arg, 0xffffu);
|
1569 |
} |
1570 |
} |
1571 |
|
1572 |
static inline void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg) |
1573 |
{ |
1574 |
if (TCG_TARGET_HAS_ext32u_i64) {
|
1575 |
tcg_gen_op2_i64(INDEX_op_ext32u_i64, ret, arg); |
1576 |
} else {
|
1577 |
tcg_gen_andi_i64(ret, arg, 0xffffffffu);
|
1578 |
} |
1579 |
} |
1580 |
|
1581 |
/* Note: we assume the target supports move between 32 and 64 bit
|
1582 |
registers. This will probably break MIPS64 targets. */
|
1583 |
static inline void tcg_gen_trunc_i64_i32(TCGv_i32 ret, TCGv_i64 arg) |
1584 |
{ |
1585 |
tcg_gen_mov_i32(ret, MAKE_TCGV_I32(GET_TCGV_I64(arg))); |
1586 |
} |
1587 |
|
1588 |
/* Note: we assume the target supports move between 32 and 64 bit
|
1589 |
registers */
|
1590 |
static inline void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg) |
1591 |
{ |
1592 |
tcg_gen_ext32u_i64(ret, MAKE_TCGV_I64(GET_TCGV_I32(arg))); |
1593 |
} |
1594 |
|
1595 |
/* Note: we assume the target supports move between 32 and 64 bit
|
1596 |
registers */
|
1597 |
static inline void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg) |
1598 |
{ |
1599 |
tcg_gen_ext32s_i64(ret, MAKE_TCGV_I64(GET_TCGV_I32(arg))); |
1600 |
} |
1601 |
|
1602 |
/* Note: we assume the six high bytes are set to zero */
|
1603 |
static inline void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg) |
1604 |
{ |
1605 |
if (TCG_TARGET_HAS_bswap16_i64) {
|
1606 |
tcg_gen_op2_i64(INDEX_op_bswap16_i64, ret, arg); |
1607 |
} else {
|
1608 |
TCGv_i64 t0 = tcg_temp_new_i64(); |
1609 |
|
1610 |
tcg_gen_ext8u_i64(t0, arg); |
1611 |
tcg_gen_shli_i64(t0, t0, 8);
|
1612 |
tcg_gen_shri_i64(ret, arg, 8);
|
1613 |
tcg_gen_or_i64(ret, ret, t0); |
1614 |
tcg_temp_free_i64(t0); |
1615 |
} |
1616 |
} |
1617 |
|
1618 |
/* Note: we assume the four high bytes are set to zero */
|
1619 |
static inline void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg) |
1620 |
{ |
1621 |
if (TCG_TARGET_HAS_bswap32_i64) {
|
1622 |
tcg_gen_op2_i64(INDEX_op_bswap32_i64, ret, arg); |
1623 |
} else {
|
1624 |
TCGv_i64 t0, t1; |
1625 |
t0 = tcg_temp_new_i64(); |
1626 |
t1 = tcg_temp_new_i64(); |
1627 |
|
1628 |
tcg_gen_shli_i64(t0, arg, 24);
|
1629 |
tcg_gen_ext32u_i64(t0, t0); |
1630 |
|
1631 |
tcg_gen_andi_i64(t1, arg, 0x0000ff00);
|
1632 |
tcg_gen_shli_i64(t1, t1, 8);
|
1633 |
tcg_gen_or_i64(t0, t0, t1); |
1634 |
|
1635 |
tcg_gen_shri_i64(t1, arg, 8);
|
1636 |
tcg_gen_andi_i64(t1, t1, 0x0000ff00);
|
1637 |
tcg_gen_or_i64(t0, t0, t1); |
1638 |
|
1639 |
tcg_gen_shri_i64(t1, arg, 24);
|
1640 |
tcg_gen_or_i64(ret, t0, t1); |
1641 |
tcg_temp_free_i64(t0); |
1642 |
tcg_temp_free_i64(t1); |
1643 |
} |
1644 |
} |
1645 |
|
1646 |
static inline void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg) |
1647 |
{ |
1648 |
if (TCG_TARGET_HAS_bswap64_i64) {
|
1649 |
tcg_gen_op2_i64(INDEX_op_bswap64_i64, ret, arg); |
1650 |
} else {
|
1651 |
TCGv_i64 t0 = tcg_temp_new_i64(); |
1652 |
TCGv_i64 t1 = tcg_temp_new_i64(); |
1653 |
|
1654 |
tcg_gen_shli_i64(t0, arg, 56);
|
1655 |
|
1656 |
tcg_gen_andi_i64(t1, arg, 0x0000ff00);
|
1657 |
tcg_gen_shli_i64(t1, t1, 40);
|
1658 |
tcg_gen_or_i64(t0, t0, t1); |
1659 |
|
1660 |
tcg_gen_andi_i64(t1, arg, 0x00ff0000);
|
1661 |
tcg_gen_shli_i64(t1, t1, 24);
|
1662 |
tcg_gen_or_i64(t0, t0, t1); |
1663 |
|
1664 |
tcg_gen_andi_i64(t1, arg, 0xff000000);
|
1665 |
tcg_gen_shli_i64(t1, t1, 8);
|
1666 |
tcg_gen_or_i64(t0, t0, t1); |
1667 |
|
1668 |
tcg_gen_shri_i64(t1, arg, 8);
|
1669 |
tcg_gen_andi_i64(t1, t1, 0xff000000);
|
1670 |
tcg_gen_or_i64(t0, t0, t1); |
1671 |
|
1672 |
tcg_gen_shri_i64(t1, arg, 24);
|
1673 |
tcg_gen_andi_i64(t1, t1, 0x00ff0000);
|
1674 |
tcg_gen_or_i64(t0, t0, t1); |
1675 |
|
1676 |
tcg_gen_shri_i64(t1, arg, 40);
|
1677 |
tcg_gen_andi_i64(t1, t1, 0x0000ff00);
|
1678 |
tcg_gen_or_i64(t0, t0, t1); |
1679 |
|
1680 |
tcg_gen_shri_i64(t1, arg, 56);
|
1681 |
tcg_gen_or_i64(ret, t0, t1); |
1682 |
tcg_temp_free_i64(t0); |
1683 |
tcg_temp_free_i64(t1); |
1684 |
} |
1685 |
} |
1686 |
|
1687 |
#endif
|
1688 |
|
1689 |
static inline void tcg_gen_neg_i32(TCGv_i32 ret, TCGv_i32 arg) |
1690 |
{ |
1691 |
if (TCG_TARGET_HAS_neg_i32) {
|
1692 |
tcg_gen_op2_i32(INDEX_op_neg_i32, ret, arg); |
1693 |
} else {
|
1694 |
TCGv_i32 t0 = tcg_const_i32(0);
|
1695 |
tcg_gen_sub_i32(ret, t0, arg); |
1696 |
tcg_temp_free_i32(t0); |
1697 |
} |
1698 |
} |
1699 |
|
1700 |
static inline void tcg_gen_neg_i64(TCGv_i64 ret, TCGv_i64 arg) |
1701 |
{ |
1702 |
if (TCG_TARGET_HAS_neg_i64) {
|
1703 |
tcg_gen_op2_i64(INDEX_op_neg_i64, ret, arg); |
1704 |
} else {
|
1705 |
TCGv_i64 t0 = tcg_const_i64(0);
|
1706 |
tcg_gen_sub_i64(ret, t0, arg); |
1707 |
tcg_temp_free_i64(t0); |
1708 |
} |
1709 |
} |
1710 |
|
1711 |
static inline void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg) |
1712 |
{ |
1713 |
if (TCG_TARGET_HAS_not_i32) {
|
1714 |
tcg_gen_op2_i32(INDEX_op_not_i32, ret, arg); |
1715 |
} else {
|
1716 |
tcg_gen_xori_i32(ret, arg, -1);
|
1717 |
} |
1718 |
} |
1719 |
|
1720 |
static inline void tcg_gen_not_i64(TCGv_i64 ret, TCGv_i64 arg) |
1721 |
{ |
1722 |
#if TCG_TARGET_REG_BITS == 64 |
1723 |
if (TCG_TARGET_HAS_not_i64) {
|
1724 |
tcg_gen_op2_i64(INDEX_op_not_i64, ret, arg); |
1725 |
} else {
|
1726 |
tcg_gen_xori_i64(ret, arg, -1);
|
1727 |
} |
1728 |
#else
|
1729 |
tcg_gen_not_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
1730 |
tcg_gen_not_i32(TCGV_HIGH(ret), TCGV_HIGH(arg)); |
1731 |
#endif
|
1732 |
} |
1733 |
|
1734 |
static inline void tcg_gen_discard_i32(TCGv_i32 arg) |
1735 |
{ |
1736 |
tcg_gen_op1_i32(INDEX_op_discard, arg); |
1737 |
} |
1738 |
|
1739 |
static inline void tcg_gen_discard_i64(TCGv_i64 arg) |
1740 |
{ |
1741 |
#if TCG_TARGET_REG_BITS == 32 |
1742 |
tcg_gen_discard_i32(TCGV_LOW(arg)); |
1743 |
tcg_gen_discard_i32(TCGV_HIGH(arg)); |
1744 |
#else
|
1745 |
tcg_gen_op1_i64(INDEX_op_discard, arg); |
1746 |
#endif
|
1747 |
} |
1748 |
|
1749 |
static inline void tcg_gen_concat_i32_i64(TCGv_i64 dest, TCGv_i32 low, TCGv_i32 high) |
1750 |
{ |
1751 |
#if TCG_TARGET_REG_BITS == 32 |
1752 |
tcg_gen_mov_i32(TCGV_LOW(dest), low); |
1753 |
tcg_gen_mov_i32(TCGV_HIGH(dest), high); |
1754 |
#else
|
1755 |
TCGv_i64 tmp = tcg_temp_new_i64(); |
1756 |
/* This extension is only needed for type correctness.
|
1757 |
We may be able to do better given target specific information. */
|
1758 |
tcg_gen_extu_i32_i64(tmp, high); |
1759 |
tcg_gen_shli_i64(tmp, tmp, 32);
|
1760 |
tcg_gen_extu_i32_i64(dest, low); |
1761 |
tcg_gen_or_i64(dest, dest, tmp); |
1762 |
tcg_temp_free_i64(tmp); |
1763 |
#endif
|
1764 |
} |
1765 |
|
1766 |
static inline void tcg_gen_concat32_i64(TCGv_i64 dest, TCGv_i64 low, TCGv_i64 high) |
1767 |
{ |
1768 |
#if TCG_TARGET_REG_BITS == 32 |
1769 |
tcg_gen_concat_i32_i64(dest, TCGV_LOW(low), TCGV_LOW(high)); |
1770 |
#else
|
1771 |
TCGv_i64 tmp = tcg_temp_new_i64(); |
1772 |
tcg_gen_ext32u_i64(dest, low); |
1773 |
tcg_gen_shli_i64(tmp, high, 32);
|
1774 |
tcg_gen_or_i64(dest, dest, tmp); |
1775 |
tcg_temp_free_i64(tmp); |
1776 |
#endif
|
1777 |
} |
1778 |
|
1779 |
static inline void tcg_gen_andc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
1780 |
{ |
1781 |
if (TCG_TARGET_HAS_andc_i32) {
|
1782 |
tcg_gen_op3_i32(INDEX_op_andc_i32, ret, arg1, arg2); |
1783 |
} else {
|
1784 |
TCGv_i32 t0 = tcg_temp_new_i32(); |
1785 |
tcg_gen_not_i32(t0, arg2); |
1786 |
tcg_gen_and_i32(ret, arg1, t0); |
1787 |
tcg_temp_free_i32(t0); |
1788 |
} |
1789 |
} |
1790 |
|
1791 |
static inline void tcg_gen_andc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1792 |
{ |
1793 |
#if TCG_TARGET_REG_BITS == 64 |
1794 |
if (TCG_TARGET_HAS_andc_i64) {
|
1795 |
tcg_gen_op3_i64(INDEX_op_andc_i64, ret, arg1, arg2); |
1796 |
} else {
|
1797 |
TCGv_i64 t0 = tcg_temp_new_i64(); |
1798 |
tcg_gen_not_i64(t0, arg2); |
1799 |
tcg_gen_and_i64(ret, arg1, t0); |
1800 |
tcg_temp_free_i64(t0); |
1801 |
} |
1802 |
#else
|
1803 |
tcg_gen_andc_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); |
1804 |
tcg_gen_andc_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); |
1805 |
#endif
|
1806 |
} |
1807 |
|
1808 |
static inline void tcg_gen_eqv_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
1809 |
{ |
1810 |
if (TCG_TARGET_HAS_eqv_i32) {
|
1811 |
tcg_gen_op3_i32(INDEX_op_eqv_i32, ret, arg1, arg2); |
1812 |
} else {
|
1813 |
tcg_gen_xor_i32(ret, arg1, arg2); |
1814 |
tcg_gen_not_i32(ret, ret); |
1815 |
} |
1816 |
} |
1817 |
|
1818 |
static inline void tcg_gen_eqv_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1819 |
{ |
1820 |
#if TCG_TARGET_REG_BITS == 64 |
1821 |
if (TCG_TARGET_HAS_eqv_i64) {
|
1822 |
tcg_gen_op3_i64(INDEX_op_eqv_i64, ret, arg1, arg2); |
1823 |
} else {
|
1824 |
tcg_gen_xor_i64(ret, arg1, arg2); |
1825 |
tcg_gen_not_i64(ret, ret); |
1826 |
} |
1827 |
#else
|
1828 |
tcg_gen_eqv_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); |
1829 |
tcg_gen_eqv_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); |
1830 |
#endif
|
1831 |
} |
1832 |
|
1833 |
static inline void tcg_gen_nand_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
1834 |
{ |
1835 |
if (TCG_TARGET_HAS_nand_i32) {
|
1836 |
tcg_gen_op3_i32(INDEX_op_nand_i32, ret, arg1, arg2); |
1837 |
} else {
|
1838 |
tcg_gen_and_i32(ret, arg1, arg2); |
1839 |
tcg_gen_not_i32(ret, ret); |
1840 |
} |
1841 |
} |
1842 |
|
1843 |
static inline void tcg_gen_nand_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1844 |
{ |
1845 |
#if TCG_TARGET_REG_BITS == 64 |
1846 |
if (TCG_TARGET_HAS_nand_i64) {
|
1847 |
tcg_gen_op3_i64(INDEX_op_nand_i64, ret, arg1, arg2); |
1848 |
} else {
|
1849 |
tcg_gen_and_i64(ret, arg1, arg2); |
1850 |
tcg_gen_not_i64(ret, ret); |
1851 |
} |
1852 |
#else
|
1853 |
tcg_gen_nand_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); |
1854 |
tcg_gen_nand_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); |
1855 |
#endif
|
1856 |
} |
1857 |
|
1858 |
static inline void tcg_gen_nor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
1859 |
{ |
1860 |
if (TCG_TARGET_HAS_nor_i32) {
|
1861 |
tcg_gen_op3_i32(INDEX_op_nor_i32, ret, arg1, arg2); |
1862 |
} else {
|
1863 |
tcg_gen_or_i32(ret, arg1, arg2); |
1864 |
tcg_gen_not_i32(ret, ret); |
1865 |
} |
1866 |
} |
1867 |
|
1868 |
static inline void tcg_gen_nor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1869 |
{ |
1870 |
#if TCG_TARGET_REG_BITS == 64 |
1871 |
if (TCG_TARGET_HAS_nor_i64) {
|
1872 |
tcg_gen_op3_i64(INDEX_op_nor_i64, ret, arg1, arg2); |
1873 |
} else {
|
1874 |
tcg_gen_or_i64(ret, arg1, arg2); |
1875 |
tcg_gen_not_i64(ret, ret); |
1876 |
} |
1877 |
#else
|
1878 |
tcg_gen_nor_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); |
1879 |
tcg_gen_nor_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); |
1880 |
#endif
|
1881 |
} |
1882 |
|
1883 |
static inline void tcg_gen_orc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
1884 |
{ |
1885 |
if (TCG_TARGET_HAS_orc_i32) {
|
1886 |
tcg_gen_op3_i32(INDEX_op_orc_i32, ret, arg1, arg2); |
1887 |
} else {
|
1888 |
TCGv_i32 t0 = tcg_temp_new_i32(); |
1889 |
tcg_gen_not_i32(t0, arg2); |
1890 |
tcg_gen_or_i32(ret, arg1, t0); |
1891 |
tcg_temp_free_i32(t0); |
1892 |
} |
1893 |
} |
1894 |
|
1895 |
static inline void tcg_gen_orc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1896 |
{ |
1897 |
#if TCG_TARGET_REG_BITS == 64 |
1898 |
if (TCG_TARGET_HAS_orc_i64) {
|
1899 |
tcg_gen_op3_i64(INDEX_op_orc_i64, ret, arg1, arg2); |
1900 |
} else {
|
1901 |
TCGv_i64 t0 = tcg_temp_new_i64(); |
1902 |
tcg_gen_not_i64(t0, arg2); |
1903 |
tcg_gen_or_i64(ret, arg1, t0); |
1904 |
tcg_temp_free_i64(t0); |
1905 |
} |
1906 |
#else
|
1907 |
tcg_gen_orc_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); |
1908 |
tcg_gen_orc_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); |
1909 |
#endif
|
1910 |
} |
1911 |
|
1912 |
static inline void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
1913 |
{ |
1914 |
if (TCG_TARGET_HAS_rot_i32) {
|
1915 |
tcg_gen_op3_i32(INDEX_op_rotl_i32, ret, arg1, arg2); |
1916 |
} else {
|
1917 |
TCGv_i32 t0, t1; |
1918 |
|
1919 |
t0 = tcg_temp_new_i32(); |
1920 |
t1 = tcg_temp_new_i32(); |
1921 |
tcg_gen_shl_i32(t0, arg1, arg2); |
1922 |
tcg_gen_subfi_i32(t1, 32, arg2);
|
1923 |
tcg_gen_shr_i32(t1, arg1, t1); |
1924 |
tcg_gen_or_i32(ret, t0, t1); |
1925 |
tcg_temp_free_i32(t0); |
1926 |
tcg_temp_free_i32(t1); |
1927 |
} |
1928 |
} |
1929 |
|
1930 |
static inline void tcg_gen_rotl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1931 |
{ |
1932 |
if (TCG_TARGET_HAS_rot_i64) {
|
1933 |
tcg_gen_op3_i64(INDEX_op_rotl_i64, ret, arg1, arg2); |
1934 |
} else {
|
1935 |
TCGv_i64 t0, t1; |
1936 |
t0 = tcg_temp_new_i64(); |
1937 |
t1 = tcg_temp_new_i64(); |
1938 |
tcg_gen_shl_i64(t0, arg1, arg2); |
1939 |
tcg_gen_subfi_i64(t1, 64, arg2);
|
1940 |
tcg_gen_shr_i64(t1, arg1, t1); |
1941 |
tcg_gen_or_i64(ret, t0, t1); |
1942 |
tcg_temp_free_i64(t0); |
1943 |
tcg_temp_free_i64(t1); |
1944 |
} |
1945 |
} |
1946 |
|
1947 |
static inline void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
1948 |
{ |
1949 |
/* some cases can be optimized here */
|
1950 |
if (arg2 == 0) { |
1951 |
tcg_gen_mov_i32(ret, arg1); |
1952 |
} else if (TCG_TARGET_HAS_rot_i32) { |
1953 |
TCGv_i32 t0 = tcg_const_i32(arg2); |
1954 |
tcg_gen_rotl_i32(ret, arg1, t0); |
1955 |
tcg_temp_free_i32(t0); |
1956 |
} else {
|
1957 |
TCGv_i32 t0, t1; |
1958 |
t0 = tcg_temp_new_i32(); |
1959 |
t1 = tcg_temp_new_i32(); |
1960 |
tcg_gen_shli_i32(t0, arg1, arg2); |
1961 |
tcg_gen_shri_i32(t1, arg1, 32 - arg2);
|
1962 |
tcg_gen_or_i32(ret, t0, t1); |
1963 |
tcg_temp_free_i32(t0); |
1964 |
tcg_temp_free_i32(t1); |
1965 |
} |
1966 |
} |
1967 |
|
1968 |
static inline void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
1969 |
{ |
1970 |
/* some cases can be optimized here */
|
1971 |
if (arg2 == 0) { |
1972 |
tcg_gen_mov_i64(ret, arg1); |
1973 |
} else if (TCG_TARGET_HAS_rot_i64) { |
1974 |
TCGv_i64 t0 = tcg_const_i64(arg2); |
1975 |
tcg_gen_rotl_i64(ret, arg1, t0); |
1976 |
tcg_temp_free_i64(t0); |
1977 |
} else {
|
1978 |
TCGv_i64 t0, t1; |
1979 |
t0 = tcg_temp_new_i64(); |
1980 |
t1 = tcg_temp_new_i64(); |
1981 |
tcg_gen_shli_i64(t0, arg1, arg2); |
1982 |
tcg_gen_shri_i64(t1, arg1, 64 - arg2);
|
1983 |
tcg_gen_or_i64(ret, t0, t1); |
1984 |
tcg_temp_free_i64(t0); |
1985 |
tcg_temp_free_i64(t1); |
1986 |
} |
1987 |
} |
1988 |
|
1989 |
static inline void tcg_gen_rotr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
1990 |
{ |
1991 |
if (TCG_TARGET_HAS_rot_i32) {
|
1992 |
tcg_gen_op3_i32(INDEX_op_rotr_i32, ret, arg1, arg2); |
1993 |
} else {
|
1994 |
TCGv_i32 t0, t1; |
1995 |
|
1996 |
t0 = tcg_temp_new_i32(); |
1997 |
t1 = tcg_temp_new_i32(); |
1998 |
tcg_gen_shr_i32(t0, arg1, arg2); |
1999 |
tcg_gen_subfi_i32(t1, 32, arg2);
|
2000 |
tcg_gen_shl_i32(t1, arg1, t1); |
2001 |
tcg_gen_or_i32(ret, t0, t1); |
2002 |
tcg_temp_free_i32(t0); |
2003 |
tcg_temp_free_i32(t1); |
2004 |
} |
2005 |
} |
2006 |
|
2007 |
static inline void tcg_gen_rotr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
2008 |
{ |
2009 |
if (TCG_TARGET_HAS_rot_i64) {
|
2010 |
tcg_gen_op3_i64(INDEX_op_rotr_i64, ret, arg1, arg2); |
2011 |
} else {
|
2012 |
TCGv_i64 t0, t1; |
2013 |
t0 = tcg_temp_new_i64(); |
2014 |
t1 = tcg_temp_new_i64(); |
2015 |
tcg_gen_shr_i64(t0, arg1, arg2); |
2016 |
tcg_gen_subfi_i64(t1, 64, arg2);
|
2017 |
tcg_gen_shl_i64(t1, arg1, t1); |
2018 |
tcg_gen_or_i64(ret, t0, t1); |
2019 |
tcg_temp_free_i64(t0); |
2020 |
tcg_temp_free_i64(t1); |
2021 |
} |
2022 |
} |
2023 |
|
2024 |
static inline void tcg_gen_rotri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
2025 |
{ |
2026 |
/* some cases can be optimized here */
|
2027 |
if (arg2 == 0) { |
2028 |
tcg_gen_mov_i32(ret, arg1); |
2029 |
} else {
|
2030 |
tcg_gen_rotli_i32(ret, arg1, 32 - arg2);
|
2031 |
} |
2032 |
} |
2033 |
|
2034 |
static inline void tcg_gen_rotri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
2035 |
{ |
2036 |
/* some cases can be optimized here */
|
2037 |
if (arg2 == 0) { |
2038 |
tcg_gen_mov_i64(ret, arg1); |
2039 |
} else {
|
2040 |
tcg_gen_rotli_i64(ret, arg1, 64 - arg2);
|
2041 |
} |
2042 |
} |
2043 |
|
2044 |
static inline void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1, |
2045 |
TCGv_i32 arg2, unsigned int ofs, |
2046 |
unsigned int len) |
2047 |
{ |
2048 |
uint32_t mask; |
2049 |
TCGv_i32 t1; |
2050 |
|
2051 |
if (ofs == 0 && len == 32) { |
2052 |
tcg_gen_mov_i32(ret, arg2); |
2053 |
return;
|
2054 |
} |
2055 |
if (TCG_TARGET_HAS_deposit_i32 && TCG_TARGET_deposit_i32_valid(ofs, len)) {
|
2056 |
tcg_gen_op5ii_i32(INDEX_op_deposit_i32, ret, arg1, arg2, ofs, len); |
2057 |
return;
|
2058 |
} |
2059 |
|
2060 |
mask = (1u << len) - 1; |
2061 |
t1 = tcg_temp_new_i32(); |
2062 |
|
2063 |
if (ofs + len < 32) { |
2064 |
tcg_gen_andi_i32(t1, arg2, mask); |
2065 |
tcg_gen_shli_i32(t1, t1, ofs); |
2066 |
} else {
|
2067 |
tcg_gen_shli_i32(t1, arg2, ofs); |
2068 |
} |
2069 |
tcg_gen_andi_i32(ret, arg1, ~(mask << ofs)); |
2070 |
tcg_gen_or_i32(ret, ret, t1); |
2071 |
|
2072 |
tcg_temp_free_i32(t1); |
2073 |
} |
2074 |
|
2075 |
static inline void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, |
2076 |
TCGv_i64 arg2, unsigned int ofs, |
2077 |
unsigned int len) |
2078 |
{ |
2079 |
uint64_t mask; |
2080 |
TCGv_i64 t1; |
2081 |
|
2082 |
if (ofs == 0 && len == 64) { |
2083 |
tcg_gen_mov_i64(ret, arg2); |
2084 |
return;
|
2085 |
} |
2086 |
if (TCG_TARGET_HAS_deposit_i64 && TCG_TARGET_deposit_i64_valid(ofs, len)) {
|
2087 |
tcg_gen_op5ii_i64(INDEX_op_deposit_i64, ret, arg1, arg2, ofs, len); |
2088 |
return;
|
2089 |
} |
2090 |
|
2091 |
#if TCG_TARGET_REG_BITS == 32 |
2092 |
if (ofs >= 32) { |
2093 |
tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg1)); |
2094 |
tcg_gen_deposit_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), |
2095 |
TCGV_LOW(arg2), ofs - 32, len);
|
2096 |
return;
|
2097 |
} |
2098 |
if (ofs + len <= 32) { |
2099 |
tcg_gen_deposit_i32(TCGV_LOW(ret), TCGV_LOW(arg1), |
2100 |
TCGV_LOW(arg2), ofs, len); |
2101 |
tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1)); |
2102 |
return;
|
2103 |
} |
2104 |
#endif
|
2105 |
|
2106 |
mask = (1ull << len) - 1; |
2107 |
t1 = tcg_temp_new_i64(); |
2108 |
|
2109 |
if (ofs + len < 64) { |
2110 |
tcg_gen_andi_i64(t1, arg2, mask); |
2111 |
tcg_gen_shli_i64(t1, t1, ofs); |
2112 |
} else {
|
2113 |
tcg_gen_shli_i64(t1, arg2, ofs); |
2114 |
} |
2115 |
tcg_gen_andi_i64(ret, arg1, ~(mask << ofs)); |
2116 |
tcg_gen_or_i64(ret, ret, t1); |
2117 |
|
2118 |
tcg_temp_free_i64(t1); |
2119 |
} |
2120 |
|
2121 |
/***************************************/
|
2122 |
/* QEMU specific operations. Their type depend on the QEMU CPU
|
2123 |
type. */
|
2124 |
#ifndef TARGET_LONG_BITS
|
2125 |
#error must include QEMU headers
|
2126 |
#endif
|
2127 |
|
2128 |
#if TARGET_LONG_BITS == 32 |
2129 |
#define TCGv TCGv_i32
|
2130 |
#define tcg_temp_new() tcg_temp_new_i32()
|
2131 |
#define tcg_global_reg_new tcg_global_reg_new_i32
|
2132 |
#define tcg_global_mem_new tcg_global_mem_new_i32
|
2133 |
#define tcg_temp_local_new() tcg_temp_local_new_i32()
|
2134 |
#define tcg_temp_free tcg_temp_free_i32
|
2135 |
#define tcg_gen_qemu_ldst_op tcg_gen_op3i_i32
|
2136 |
#define tcg_gen_qemu_ldst_op_i64 tcg_gen_qemu_ldst_op_i64_i32
|
2137 |
#define TCGV_UNUSED(x) TCGV_UNUSED_I32(x)
|
2138 |
#define TCGV_EQUAL(a, b) TCGV_EQUAL_I32(a, b)
|
2139 |
#else
|
2140 |
#define TCGv TCGv_i64
|
2141 |
#define tcg_temp_new() tcg_temp_new_i64()
|
2142 |
#define tcg_global_reg_new tcg_global_reg_new_i64
|
2143 |
#define tcg_global_mem_new tcg_global_mem_new_i64
|
2144 |
#define tcg_temp_local_new() tcg_temp_local_new_i64()
|
2145 |
#define tcg_temp_free tcg_temp_free_i64
|
2146 |
#define tcg_gen_qemu_ldst_op tcg_gen_op3i_i64
|
2147 |
#define tcg_gen_qemu_ldst_op_i64 tcg_gen_qemu_ldst_op_i64_i64
|
2148 |
#define TCGV_UNUSED(x) TCGV_UNUSED_I64(x)
|
2149 |
#define TCGV_EQUAL(a, b) TCGV_EQUAL_I64(a, b)
|
2150 |
#endif
|
2151 |
|
2152 |
/* debug info: write the PC of the corresponding QEMU CPU instruction */
|
2153 |
static inline void tcg_gen_debug_insn_start(uint64_t pc) |
2154 |
{ |
2155 |
/* XXX: must really use a 32 bit size for TCGArg in all cases */
|
2156 |
#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
|
2157 |
tcg_gen_op2ii(INDEX_op_debug_insn_start, |
2158 |
(uint32_t)(pc), (uint32_t)(pc >> 32));
|
2159 |
#else
|
2160 |
tcg_gen_op1i(INDEX_op_debug_insn_start, pc); |
2161 |
#endif
|
2162 |
} |
2163 |
|
2164 |
static inline void tcg_gen_exit_tb(tcg_target_long val) |
2165 |
{ |
2166 |
tcg_gen_op1i(INDEX_op_exit_tb, val); |
2167 |
} |
2168 |
|
2169 |
static inline void tcg_gen_goto_tb(int idx) |
2170 |
{ |
2171 |
tcg_gen_op1i(INDEX_op_goto_tb, idx); |
2172 |
} |
2173 |
|
2174 |
#if TCG_TARGET_REG_BITS == 32 |
2175 |
static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index) |
2176 |
{ |
2177 |
#if TARGET_LONG_BITS == 32 |
2178 |
tcg_gen_op3i_i32(INDEX_op_qemu_ld8u, ret, addr, mem_index); |
2179 |
#else
|
2180 |
tcg_gen_op4i_i32(INDEX_op_qemu_ld8u, TCGV_LOW(ret), TCGV_LOW(addr), |
2181 |
TCGV_HIGH(addr), mem_index); |
2182 |
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
2183 |
#endif
|
2184 |
} |
2185 |
|
2186 |
static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index) |
2187 |
{ |
2188 |
#if TARGET_LONG_BITS == 32 |
2189 |
tcg_gen_op3i_i32(INDEX_op_qemu_ld8s, ret, addr, mem_index); |
2190 |
#else
|
2191 |
tcg_gen_op4i_i32(INDEX_op_qemu_ld8s, TCGV_LOW(ret), TCGV_LOW(addr), |
2192 |
TCGV_HIGH(addr), mem_index); |
2193 |
tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
|
2194 |
#endif
|
2195 |
} |
2196 |
|
2197 |
static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index) |
2198 |
{ |
2199 |
#if TARGET_LONG_BITS == 32 |
2200 |
tcg_gen_op3i_i32(INDEX_op_qemu_ld16u, ret, addr, mem_index); |
2201 |
#else
|
2202 |
tcg_gen_op4i_i32(INDEX_op_qemu_ld16u, TCGV_LOW(ret), TCGV_LOW(addr), |
2203 |
TCGV_HIGH(addr), mem_index); |
2204 |
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
2205 |
#endif
|
2206 |
} |
2207 |
|
2208 |
static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index) |
2209 |
{ |
2210 |
#if TARGET_LONG_BITS == 32 |
2211 |
tcg_gen_op3i_i32(INDEX_op_qemu_ld16s, ret, addr, mem_index); |
2212 |
#else
|
2213 |
tcg_gen_op4i_i32(INDEX_op_qemu_ld16s, TCGV_LOW(ret), TCGV_LOW(addr), |
2214 |
TCGV_HIGH(addr), mem_index); |
2215 |
tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
|
2216 |
#endif
|
2217 |
} |
2218 |
|
2219 |
static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index) |
2220 |
{ |
2221 |
#if TARGET_LONG_BITS == 32 |
2222 |
tcg_gen_op3i_i32(INDEX_op_qemu_ld32, ret, addr, mem_index); |
2223 |
#else
|
2224 |
tcg_gen_op4i_i32(INDEX_op_qemu_ld32, TCGV_LOW(ret), TCGV_LOW(addr), |
2225 |
TCGV_HIGH(addr), mem_index); |
2226 |
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
2227 |
#endif
|
2228 |
} |
2229 |
|
2230 |
static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index) |
2231 |
{ |
2232 |
#if TARGET_LONG_BITS == 32 |
2233 |
tcg_gen_op3i_i32(INDEX_op_qemu_ld32, ret, addr, mem_index); |
2234 |
#else
|
2235 |
tcg_gen_op4i_i32(INDEX_op_qemu_ld32, TCGV_LOW(ret), TCGV_LOW(addr), |
2236 |
TCGV_HIGH(addr), mem_index); |
2237 |
tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
|
2238 |
#endif
|
2239 |
} |
2240 |
|
2241 |
static inline void tcg_gen_qemu_ld64(TCGv_i64 ret, TCGv addr, int mem_index) |
2242 |
{ |
2243 |
#if TARGET_LONG_BITS == 32 |
2244 |
tcg_gen_op4i_i32(INDEX_op_qemu_ld64, TCGV_LOW(ret), TCGV_HIGH(ret), addr, mem_index); |
2245 |
#else
|
2246 |
tcg_gen_op5i_i32(INDEX_op_qemu_ld64, TCGV_LOW(ret), TCGV_HIGH(ret), |
2247 |
TCGV_LOW(addr), TCGV_HIGH(addr), mem_index); |
2248 |
#endif
|
2249 |
} |
2250 |
|
2251 |
static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index) |
2252 |
{ |
2253 |
#if TARGET_LONG_BITS == 32 |
2254 |
tcg_gen_op3i_i32(INDEX_op_qemu_st8, arg, addr, mem_index); |
2255 |
#else
|
2256 |
tcg_gen_op4i_i32(INDEX_op_qemu_st8, TCGV_LOW(arg), TCGV_LOW(addr), |
2257 |
TCGV_HIGH(addr), mem_index); |
2258 |
#endif
|
2259 |
} |
2260 |
|
2261 |
static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index) |
2262 |
{ |
2263 |
#if TARGET_LONG_BITS == 32 |
2264 |
tcg_gen_op3i_i32(INDEX_op_qemu_st16, arg, addr, mem_index); |
2265 |
#else
|
2266 |
tcg_gen_op4i_i32(INDEX_op_qemu_st16, TCGV_LOW(arg), TCGV_LOW(addr), |
2267 |
TCGV_HIGH(addr), mem_index); |
2268 |
#endif
|
2269 |
} |
2270 |
|
2271 |
static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index) |
2272 |
{ |
2273 |
#if TARGET_LONG_BITS == 32 |
2274 |
tcg_gen_op3i_i32(INDEX_op_qemu_st32, arg, addr, mem_index); |
2275 |
#else
|
2276 |
tcg_gen_op4i_i32(INDEX_op_qemu_st32, TCGV_LOW(arg), TCGV_LOW(addr), |
2277 |
TCGV_HIGH(addr), mem_index); |
2278 |
#endif
|
2279 |
} |
2280 |
|
2281 |
static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index) |
2282 |
{ |
2283 |
#if TARGET_LONG_BITS == 32 |
2284 |
tcg_gen_op4i_i32(INDEX_op_qemu_st64, TCGV_LOW(arg), TCGV_HIGH(arg), addr, |
2285 |
mem_index); |
2286 |
#else
|
2287 |
tcg_gen_op5i_i32(INDEX_op_qemu_st64, TCGV_LOW(arg), TCGV_HIGH(arg), |
2288 |
TCGV_LOW(addr), TCGV_HIGH(addr), mem_index); |
2289 |
#endif
|
2290 |
} |
2291 |
|
2292 |
#define tcg_gen_ld_ptr(R, A, O) tcg_gen_ld_i32(TCGV_PTR_TO_NAT(R), (A), (O))
|
2293 |
#define tcg_gen_discard_ptr(A) tcg_gen_discard_i32(TCGV_PTR_TO_NAT(A))
|
2294 |
|
2295 |
#else /* TCG_TARGET_REG_BITS == 32 */ |
2296 |
|
2297 |
static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index) |
2298 |
{ |
2299 |
tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld8u, ret, addr, mem_index); |
2300 |
} |
2301 |
|
2302 |
static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index) |
2303 |
{ |
2304 |
tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld8s, ret, addr, mem_index); |
2305 |
} |
2306 |
|
2307 |
static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index) |
2308 |
{ |
2309 |
tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld16u, ret, addr, mem_index); |
2310 |
} |
2311 |
|
2312 |
static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index) |
2313 |
{ |
2314 |
tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld16s, ret, addr, mem_index); |
2315 |
} |
2316 |
|
2317 |
static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index) |
2318 |
{ |
2319 |
#if TARGET_LONG_BITS == 32 |
2320 |
tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32, ret, addr, mem_index); |
2321 |
#else
|
2322 |
tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32u, ret, addr, mem_index); |
2323 |
#endif
|
2324 |
} |
2325 |
|
2326 |
static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index) |
2327 |
{ |
2328 |
#if TARGET_LONG_BITS == 32 |
2329 |
tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32, ret, addr, mem_index); |
2330 |
#else
|
2331 |
tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32s, ret, addr, mem_index); |
2332 |
#endif
|
2333 |
} |
2334 |
|
2335 |
static inline void tcg_gen_qemu_ld64(TCGv_i64 ret, TCGv addr, int mem_index) |
2336 |
{ |
2337 |
tcg_gen_qemu_ldst_op_i64(INDEX_op_qemu_ld64, ret, addr, mem_index); |
2338 |
} |
2339 |
|
2340 |
static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index) |
2341 |
{ |
2342 |
tcg_gen_qemu_ldst_op(INDEX_op_qemu_st8, arg, addr, mem_index); |
2343 |
} |
2344 |
|
2345 |
static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index) |
2346 |
{ |
2347 |
tcg_gen_qemu_ldst_op(INDEX_op_qemu_st16, arg, addr, mem_index); |
2348 |
} |
2349 |
|
2350 |
static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index) |
2351 |
{ |
2352 |
tcg_gen_qemu_ldst_op(INDEX_op_qemu_st32, arg, addr, mem_index); |
2353 |
} |
2354 |
|
2355 |
static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index) |
2356 |
{ |
2357 |
tcg_gen_qemu_ldst_op_i64(INDEX_op_qemu_st64, arg, addr, mem_index); |
2358 |
} |
2359 |
|
2360 |
#define tcg_gen_ld_ptr(R, A, O) tcg_gen_ld_i64(TCGV_PTR_TO_NAT(R), (A), (O))
|
2361 |
#define tcg_gen_discard_ptr(A) tcg_gen_discard_i64(TCGV_PTR_TO_NAT(A))
|
2362 |
|
2363 |
#endif /* TCG_TARGET_REG_BITS != 32 */ |
2364 |
|
2365 |
#if TARGET_LONG_BITS == 64 |
2366 |
#define tcg_gen_movi_tl tcg_gen_movi_i64
|
2367 |
#define tcg_gen_mov_tl tcg_gen_mov_i64
|
2368 |
#define tcg_gen_ld8u_tl tcg_gen_ld8u_i64
|
2369 |
#define tcg_gen_ld8s_tl tcg_gen_ld8s_i64
|
2370 |
#define tcg_gen_ld16u_tl tcg_gen_ld16u_i64
|
2371 |
#define tcg_gen_ld16s_tl tcg_gen_ld16s_i64
|
2372 |
#define tcg_gen_ld32u_tl tcg_gen_ld32u_i64
|
2373 |
#define tcg_gen_ld32s_tl tcg_gen_ld32s_i64
|
2374 |
#define tcg_gen_ld_tl tcg_gen_ld_i64
|
2375 |
#define tcg_gen_st8_tl tcg_gen_st8_i64
|
2376 |
#define tcg_gen_st16_tl tcg_gen_st16_i64
|
2377 |
#define tcg_gen_st32_tl tcg_gen_st32_i64
|
2378 |
#define tcg_gen_st_tl tcg_gen_st_i64
|
2379 |
#define tcg_gen_add_tl tcg_gen_add_i64
|
2380 |
#define tcg_gen_addi_tl tcg_gen_addi_i64
|
2381 |
#define tcg_gen_sub_tl tcg_gen_sub_i64
|
2382 |
#define tcg_gen_neg_tl tcg_gen_neg_i64
|
2383 |
#define tcg_gen_subfi_tl tcg_gen_subfi_i64
|
2384 |
#define tcg_gen_subi_tl tcg_gen_subi_i64
|
2385 |
#define tcg_gen_and_tl tcg_gen_and_i64
|
2386 |
#define tcg_gen_andi_tl tcg_gen_andi_i64
|
2387 |
#define tcg_gen_or_tl tcg_gen_or_i64
|
2388 |
#define tcg_gen_ori_tl tcg_gen_ori_i64
|
2389 |
#define tcg_gen_xor_tl tcg_gen_xor_i64
|
2390 |
#define tcg_gen_xori_tl tcg_gen_xori_i64
|
2391 |
#define tcg_gen_not_tl tcg_gen_not_i64
|
2392 |
#define tcg_gen_shl_tl tcg_gen_shl_i64
|
2393 |
#define tcg_gen_shli_tl tcg_gen_shli_i64
|
2394 |
#define tcg_gen_shr_tl tcg_gen_shr_i64
|
2395 |
#define tcg_gen_shri_tl tcg_gen_shri_i64
|
2396 |
#define tcg_gen_sar_tl tcg_gen_sar_i64
|
2397 |
#define tcg_gen_sari_tl tcg_gen_sari_i64
|
2398 |
#define tcg_gen_brcond_tl tcg_gen_brcond_i64
|
2399 |
#define tcg_gen_brcondi_tl tcg_gen_brcondi_i64
|
2400 |
#define tcg_gen_setcond_tl tcg_gen_setcond_i64
|
2401 |
#define tcg_gen_setcondi_tl tcg_gen_setcondi_i64
|
2402 |
#define tcg_gen_mul_tl tcg_gen_mul_i64
|
2403 |
#define tcg_gen_muli_tl tcg_gen_muli_i64
|
2404 |
#define tcg_gen_div_tl tcg_gen_div_i64
|
2405 |
#define tcg_gen_rem_tl tcg_gen_rem_i64
|
2406 |
#define tcg_gen_divu_tl tcg_gen_divu_i64
|
2407 |
#define tcg_gen_remu_tl tcg_gen_remu_i64
|
2408 |
#define tcg_gen_discard_tl tcg_gen_discard_i64
|
2409 |
#define tcg_gen_trunc_tl_i32 tcg_gen_trunc_i64_i32
|
2410 |
#define tcg_gen_trunc_i64_tl tcg_gen_mov_i64
|
2411 |
#define tcg_gen_extu_i32_tl tcg_gen_extu_i32_i64
|
2412 |
#define tcg_gen_ext_i32_tl tcg_gen_ext_i32_i64
|
2413 |
#define tcg_gen_extu_tl_i64 tcg_gen_mov_i64
|
2414 |
#define tcg_gen_ext_tl_i64 tcg_gen_mov_i64
|
2415 |
#define tcg_gen_ext8u_tl tcg_gen_ext8u_i64
|
2416 |
#define tcg_gen_ext8s_tl tcg_gen_ext8s_i64
|
2417 |
#define tcg_gen_ext16u_tl tcg_gen_ext16u_i64
|
2418 |
#define tcg_gen_ext16s_tl tcg_gen_ext16s_i64
|
2419 |
#define tcg_gen_ext32u_tl tcg_gen_ext32u_i64
|
2420 |
#define tcg_gen_ext32s_tl tcg_gen_ext32s_i64
|
2421 |
#define tcg_gen_bswap16_tl tcg_gen_bswap16_i64
|
2422 |
#define tcg_gen_bswap32_tl tcg_gen_bswap32_i64
|
2423 |
#define tcg_gen_bswap64_tl tcg_gen_bswap64_i64
|
2424 |
#define tcg_gen_concat_tl_i64 tcg_gen_concat32_i64
|
2425 |
#define tcg_gen_andc_tl tcg_gen_andc_i64
|
2426 |
#define tcg_gen_eqv_tl tcg_gen_eqv_i64
|
2427 |
#define tcg_gen_nand_tl tcg_gen_nand_i64
|
2428 |
#define tcg_gen_nor_tl tcg_gen_nor_i64
|
2429 |
#define tcg_gen_orc_tl tcg_gen_orc_i64
|
2430 |
#define tcg_gen_rotl_tl tcg_gen_rotl_i64
|
2431 |
#define tcg_gen_rotli_tl tcg_gen_rotli_i64
|
2432 |
#define tcg_gen_rotr_tl tcg_gen_rotr_i64
|
2433 |
#define tcg_gen_rotri_tl tcg_gen_rotri_i64
|
2434 |
#define tcg_gen_deposit_tl tcg_gen_deposit_i64
|
2435 |
#define tcg_const_tl tcg_const_i64
|
2436 |
#define tcg_const_local_tl tcg_const_local_i64
|
2437 |
#else
|
2438 |
#define tcg_gen_movi_tl tcg_gen_movi_i32
|
2439 |
#define tcg_gen_mov_tl tcg_gen_mov_i32
|
2440 |
#define tcg_gen_ld8u_tl tcg_gen_ld8u_i32
|
2441 |
#define tcg_gen_ld8s_tl tcg_gen_ld8s_i32
|
2442 |
#define tcg_gen_ld16u_tl tcg_gen_ld16u_i32
|
2443 |
#define tcg_gen_ld16s_tl tcg_gen_ld16s_i32
|
2444 |
#define tcg_gen_ld32u_tl tcg_gen_ld_i32
|
2445 |
#define tcg_gen_ld32s_tl tcg_gen_ld_i32
|
2446 |
#define tcg_gen_ld_tl tcg_gen_ld_i32
|
2447 |
#define tcg_gen_st8_tl tcg_gen_st8_i32
|
2448 |
#define tcg_gen_st16_tl tcg_gen_st16_i32
|
2449 |
#define tcg_gen_st32_tl tcg_gen_st_i32
|
2450 |
#define tcg_gen_st_tl tcg_gen_st_i32
|
2451 |
#define tcg_gen_add_tl tcg_gen_add_i32
|
2452 |
#define tcg_gen_addi_tl tcg_gen_addi_i32
|
2453 |
#define tcg_gen_sub_tl tcg_gen_sub_i32
|
2454 |
#define tcg_gen_neg_tl tcg_gen_neg_i32
|
2455 |
#define tcg_gen_subfi_tl tcg_gen_subfi_i32
|
2456 |
#define tcg_gen_subi_tl tcg_gen_subi_i32
|
2457 |
#define tcg_gen_and_tl tcg_gen_and_i32
|
2458 |
#define tcg_gen_andi_tl tcg_gen_andi_i32
|
2459 |
#define tcg_gen_or_tl tcg_gen_or_i32
|
2460 |
#define tcg_gen_ori_tl tcg_gen_ori_i32
|
2461 |
#define tcg_gen_xor_tl tcg_gen_xor_i32
|
2462 |
#define tcg_gen_xori_tl tcg_gen_xori_i32
|
2463 |
#define tcg_gen_not_tl tcg_gen_not_i32
|
2464 |
#define tcg_gen_shl_tl tcg_gen_shl_i32
|
2465 |
#define tcg_gen_shli_tl tcg_gen_shli_i32
|
2466 |
#define tcg_gen_shr_tl tcg_gen_shr_i32
|
2467 |
#define tcg_gen_shri_tl tcg_gen_shri_i32
|
2468 |
#define tcg_gen_sar_tl tcg_gen_sar_i32
|
2469 |
#define tcg_gen_sari_tl tcg_gen_sari_i32
|
2470 |
#define tcg_gen_brcond_tl tcg_gen_brcond_i32
|
2471 |
#define tcg_gen_brcondi_tl tcg_gen_brcondi_i32
|
2472 |
#define tcg_gen_setcond_tl tcg_gen_setcond_i32
|
2473 |
#define tcg_gen_setcondi_tl tcg_gen_setcondi_i32
|
2474 |
#define tcg_gen_mul_tl tcg_gen_mul_i32
|
2475 |
#define tcg_gen_muli_tl tcg_gen_muli_i32
|
2476 |
#define tcg_gen_div_tl tcg_gen_div_i32
|
2477 |
#define tcg_gen_rem_tl tcg_gen_rem_i32
|
2478 |
#define tcg_gen_divu_tl tcg_gen_divu_i32
|
2479 |
#define tcg_gen_remu_tl tcg_gen_remu_i32
|
2480 |
#define tcg_gen_discard_tl tcg_gen_discard_i32
|
2481 |
#define tcg_gen_trunc_tl_i32 tcg_gen_mov_i32
|
2482 |
#define tcg_gen_trunc_i64_tl tcg_gen_trunc_i64_i32
|
2483 |
#define tcg_gen_extu_i32_tl tcg_gen_mov_i32
|
2484 |
#define tcg_gen_ext_i32_tl tcg_gen_mov_i32
|
2485 |
#define tcg_gen_extu_tl_i64 tcg_gen_extu_i32_i64
|
2486 |
#define tcg_gen_ext_tl_i64 tcg_gen_ext_i32_i64
|
2487 |
#define tcg_gen_ext8u_tl tcg_gen_ext8u_i32
|
2488 |
#define tcg_gen_ext8s_tl tcg_gen_ext8s_i32
|
2489 |
#define tcg_gen_ext16u_tl tcg_gen_ext16u_i32
|
2490 |
#define tcg_gen_ext16s_tl tcg_gen_ext16s_i32
|
2491 |
#define tcg_gen_ext32u_tl tcg_gen_mov_i32
|
2492 |
#define tcg_gen_ext32s_tl tcg_gen_mov_i32
|
2493 |
#define tcg_gen_bswap16_tl tcg_gen_bswap16_i32
|
2494 |
#define tcg_gen_bswap32_tl tcg_gen_bswap32_i32
|
2495 |
#define tcg_gen_concat_tl_i64 tcg_gen_concat_i32_i64
|
2496 |
#define tcg_gen_andc_tl tcg_gen_andc_i32
|
2497 |
#define tcg_gen_eqv_tl tcg_gen_eqv_i32
|
2498 |
#define tcg_gen_nand_tl tcg_gen_nand_i32
|
2499 |
#define tcg_gen_nor_tl tcg_gen_nor_i32
|
2500 |
#define tcg_gen_orc_tl tcg_gen_orc_i32
|
2501 |
#define tcg_gen_rotl_tl tcg_gen_rotl_i32
|
2502 |
#define tcg_gen_rotli_tl tcg_gen_rotli_i32
|
2503 |
#define tcg_gen_rotr_tl tcg_gen_rotr_i32
|
2504 |
#define tcg_gen_rotri_tl tcg_gen_rotri_i32
|
2505 |
#define tcg_gen_deposit_tl tcg_gen_deposit_i32
|
2506 |
#define tcg_const_tl tcg_const_i32
|
2507 |
#define tcg_const_local_tl tcg_const_local_i32
|
2508 |
#endif
|
2509 |
|
2510 |
#if TCG_TARGET_REG_BITS == 32 |
2511 |
#define tcg_gen_add_ptr(R, A, B) tcg_gen_add_i32(TCGV_PTR_TO_NAT(R), \
|
2512 |
TCGV_PTR_TO_NAT(A), \ |
2513 |
TCGV_PTR_TO_NAT(B)) |
2514 |
#define tcg_gen_addi_ptr(R, A, B) tcg_gen_addi_i32(TCGV_PTR_TO_NAT(R), \
|
2515 |
TCGV_PTR_TO_NAT(A), (B)) |
2516 |
#define tcg_gen_ext_i32_ptr(R, A) tcg_gen_mov_i32(TCGV_PTR_TO_NAT(R), (A))
|
2517 |
#else /* TCG_TARGET_REG_BITS == 32 */ |
2518 |
#define tcg_gen_add_ptr(R, A, B) tcg_gen_add_i64(TCGV_PTR_TO_NAT(R), \
|
2519 |
TCGV_PTR_TO_NAT(A), \ |
2520 |
TCGV_PTR_TO_NAT(B)) |
2521 |
#define tcg_gen_addi_ptr(R, A, B) tcg_gen_addi_i64(TCGV_PTR_TO_NAT(R), \
|
2522 |
TCGV_PTR_TO_NAT(A), (B)) |
2523 |
#define tcg_gen_ext_i32_ptr(R, A) tcg_gen_ext_i32_i64(TCGV_PTR_TO_NAT(R), (A))
|
2524 |
#endif /* TCG_TARGET_REG_BITS != 32 */ |