Revision 9619376c tcg/i386/tcg-target.c
| b/tcg/i386/tcg-target.c | ||
|---|---|---|
| 158 | 158 |
#define ARITH_XOR 6 |
| 159 | 159 |
#define ARITH_CMP 7 |
| 160 | 160 |
|
| 161 |
#define SHIFT_ROL 0 |
|
| 162 |
#define SHIFT_ROR 1 |
|
| 161 | 163 |
#define SHIFT_SHL 4 |
| 162 | 164 |
#define SHIFT_SHR 5 |
| 163 | 165 |
#define SHIFT_SAR 7 |
| ... | ... | |
| 998 | 1000 |
case INDEX_op_sar_i32: |
| 999 | 1001 |
c = SHIFT_SAR; |
| 1000 | 1002 |
goto gen_shift32; |
| 1001 |
|
|
| 1003 |
case INDEX_op_rotl_i32: |
|
| 1004 |
c = SHIFT_ROL; |
|
| 1005 |
goto gen_shift32; |
|
| 1006 |
case INDEX_op_rotr_i32: |
|
| 1007 |
c = SHIFT_ROR; |
|
| 1008 |
goto gen_shift32; |
|
| 1009 |
|
|
| 1002 | 1010 |
case INDEX_op_add2_i32: |
| 1003 | 1011 |
if (const_args[4]) |
| 1004 | 1012 |
tgen_arithi(s, ARITH_ADD, args[0], args[4]); |
| ... | ... | |
| 1026 | 1034 |
tcg_out_brcond2(s, args, const_args); |
| 1027 | 1035 |
break; |
| 1028 | 1036 |
|
| 1037 |
case INDEX_op_bswap_i32: |
|
| 1038 |
tcg_out_opc(s, (0xc8 + args[0]) | P_EXT); |
|
| 1039 |
break; |
|
| 1040 |
|
|
| 1041 |
case INDEX_op_neg_i32: |
|
| 1042 |
tcg_out_modrm(s, 0xf7, 3, args[0]); |
|
| 1043 |
break; |
|
| 1044 |
|
|
| 1045 |
case INDEX_op_not_i32: |
|
| 1046 |
tcg_out_modrm(s, 0xf7, 2, args[0]); |
|
| 1047 |
break; |
|
| 1048 |
|
|
| 1049 |
case INDEX_op_ext8s_i32: |
|
| 1050 |
tcg_out_modrm(s, 0xbe | P_EXT, args[0], args[1]); |
|
| 1051 |
break; |
|
| 1052 |
case INDEX_op_ext16s_i32: |
|
| 1053 |
tcg_out_modrm(s, 0xbf | P_EXT, args[0], args[1]); |
|
| 1054 |
break; |
|
| 1055 |
|
|
| 1029 | 1056 |
case INDEX_op_qemu_ld8u: |
| 1030 | 1057 |
tcg_out_qemu_ld(s, args, 0); |
| 1031 | 1058 |
break; |
| ... | ... | |
| 1093 | 1120 |
{ INDEX_op_shl_i32, { "r", "0", "ci" } },
|
| 1094 | 1121 |
{ INDEX_op_shr_i32, { "r", "0", "ci" } },
|
| 1095 | 1122 |
{ INDEX_op_sar_i32, { "r", "0", "ci" } },
|
| 1123 |
{ INDEX_op_sar_i32, { "r", "0", "ci" } },
|
|
| 1124 |
{ INDEX_op_rotl_i32, { "r", "0", "ci" } },
|
|
| 1125 |
{ INDEX_op_rotr_i32, { "r", "0", "ci" } },
|
|
| 1096 | 1126 |
|
| 1097 | 1127 |
{ INDEX_op_brcond_i32, { "r", "ri" } },
|
| 1098 | 1128 |
|
| ... | ... | |
| 1100 | 1130 |
{ INDEX_op_sub2_i32, { "r", "r", "0", "1", "ri", "ri" } },
|
| 1101 | 1131 |
{ INDEX_op_brcond2_i32, { "r", "r", "ri", "ri" } },
|
| 1102 | 1132 |
|
| 1133 |
{ INDEX_op_bswap_i32, { "r", "0" } },
|
|
| 1134 |
|
|
| 1135 |
{ INDEX_op_neg_i32, { "r", "0" } },
|
|
| 1136 |
|
|
| 1137 |
{ INDEX_op_not_i32, { "r", "0" } },
|
|
| 1138 |
|
|
| 1139 |
{ INDEX_op_ext8s_i32, { "r", "q" } },
|
|
| 1140 |
{ INDEX_op_ext16s_i32, { "r", "r" } },
|
|
| 1141 |
|
|
| 1103 | 1142 |
#if TARGET_LONG_BITS == 32 |
| 1104 | 1143 |
{ INDEX_op_qemu_ld8u, { "r", "L" } },
|
| 1105 | 1144 |
{ INDEX_op_qemu_ld8s, { "r", "L" } },
|
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