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1 | b00052e4 | balrog | /*
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2 | b00052e4 | balrog | * PXA270-based Clamshell PDA platforms.
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3 | b00052e4 | balrog | *
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4 | b00052e4 | balrog | * Copyright (c) 2006 Openedhand Ltd.
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5 | b00052e4 | balrog | * Written by Andrzej Zaborowski <balrog@zabor.org>
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6 | b00052e4 | balrog | *
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7 | b00052e4 | balrog | * This code is licensed under the GNU GPL v2.
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8 | b00052e4 | balrog | */
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9 | b00052e4 | balrog | |
10 | 87ecb68b | pbrook | #include "hw.h" |
11 | 87ecb68b | pbrook | #include "pxa.h" |
12 | 87ecb68b | pbrook | #include "arm-misc.h" |
13 | 87ecb68b | pbrook | #include "sysemu.h" |
14 | 87ecb68b | pbrook | #include "pcmcia.h" |
15 | 87ecb68b | pbrook | #include "i2c.h" |
16 | 87ecb68b | pbrook | #include "flash.h" |
17 | 87ecb68b | pbrook | #include "qemu-timer.h" |
18 | 87ecb68b | pbrook | #include "devices.h" |
19 | 87ecb68b | pbrook | #include "console.h" |
20 | 87ecb68b | pbrook | #include "block.h" |
21 | 87ecb68b | pbrook | #include "audio/audio.h" |
22 | 87ecb68b | pbrook | #include "boards.h" |
23 | b00052e4 | balrog | |
24 | b00052e4 | balrog | #define spitz_printf(format, ...) \
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25 | b00052e4 | balrog | fprintf(stderr, "%s: " format, __FUNCTION__, ##__VA_ARGS__) |
26 | b00052e4 | balrog | #undef REG_FMT
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27 | 444ce241 | bellard | #if TARGET_PHYS_ADDR_BITS == 32 |
28 | 444ce241 | bellard | #define REG_FMT "0x%02x" |
29 | 444ce241 | bellard | #else
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30 | b00052e4 | balrog | #define REG_FMT "0x%02lx" |
31 | 444ce241 | bellard | #endif
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32 | b00052e4 | balrog | |
33 | b00052e4 | balrog | /* Spitz Flash */
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34 | b00052e4 | balrog | #define FLASH_BASE 0x0c000000 |
35 | b00052e4 | balrog | #define FLASH_ECCLPLB 0x00 /* Line parity 7 - 0 bit */ |
36 | b00052e4 | balrog | #define FLASH_ECCLPUB 0x04 /* Line parity 15 - 8 bit */ |
37 | b00052e4 | balrog | #define FLASH_ECCCP 0x08 /* Column parity 5 - 0 bit */ |
38 | b00052e4 | balrog | #define FLASH_ECCCNTR 0x0c /* ECC byte counter */ |
39 | b00052e4 | balrog | #define FLASH_ECCCLRR 0x10 /* Clear ECC */ |
40 | b00052e4 | balrog | #define FLASH_FLASHIO 0x14 /* Flash I/O */ |
41 | b00052e4 | balrog | #define FLASH_FLASHCTL 0x18 /* Flash Control */ |
42 | b00052e4 | balrog | |
43 | b00052e4 | balrog | #define FLASHCTL_CE0 (1 << 0) |
44 | b00052e4 | balrog | #define FLASHCTL_CLE (1 << 1) |
45 | b00052e4 | balrog | #define FLASHCTL_ALE (1 << 2) |
46 | b00052e4 | balrog | #define FLASHCTL_WP (1 << 3) |
47 | b00052e4 | balrog | #define FLASHCTL_CE1 (1 << 4) |
48 | b00052e4 | balrog | #define FLASHCTL_RYBY (1 << 5) |
49 | b00052e4 | balrog | #define FLASHCTL_NCE (FLASHCTL_CE0 | FLASHCTL_CE1)
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50 | b00052e4 | balrog | |
51 | b00052e4 | balrog | struct sl_nand_s {
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52 | b00052e4 | balrog | target_phys_addr_t target_base; |
53 | b00052e4 | balrog | struct nand_flash_s *nand;
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54 | b00052e4 | balrog | uint8_t ctl; |
55 | b00052e4 | balrog | struct ecc_state_s ecc;
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56 | b00052e4 | balrog | }; |
57 | b00052e4 | balrog | |
58 | b00052e4 | balrog | static uint32_t sl_readb(void *opaque, target_phys_addr_t addr) |
59 | b00052e4 | balrog | { |
60 | b00052e4 | balrog | struct sl_nand_s *s = (struct sl_nand_s *) opaque; |
61 | b00052e4 | balrog | int ryby;
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62 | b00052e4 | balrog | addr -= s->target_base; |
63 | b00052e4 | balrog | |
64 | b00052e4 | balrog | switch (addr) {
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65 | b00052e4 | balrog | #define BSHR(byte, from, to) ((s->ecc.lp[byte] >> (from - to)) & (1 << to)) |
66 | b00052e4 | balrog | case FLASH_ECCLPLB:
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67 | b00052e4 | balrog | return BSHR(0, 4, 0) | BSHR(0, 5, 2) | BSHR(0, 6, 4) | BSHR(0, 7, 6) | |
68 | b00052e4 | balrog | BSHR(1, 4, 1) | BSHR(1, 5, 3) | BSHR(1, 6, 5) | BSHR(1, 7, 7); |
69 | b00052e4 | balrog | |
70 | b00052e4 | balrog | #define BSHL(byte, from, to) ((s->ecc.lp[byte] << (to - from)) & (1 << to)) |
71 | b00052e4 | balrog | case FLASH_ECCLPUB:
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72 | b00052e4 | balrog | return BSHL(0, 0, 0) | BSHL(0, 1, 2) | BSHL(0, 2, 4) | BSHL(0, 3, 6) | |
73 | b00052e4 | balrog | BSHL(1, 0, 1) | BSHL(1, 1, 3) | BSHL(1, 2, 5) | BSHL(1, 3, 7); |
74 | b00052e4 | balrog | |
75 | b00052e4 | balrog | case FLASH_ECCCP:
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76 | b00052e4 | balrog | return s->ecc.cp;
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77 | b00052e4 | balrog | |
78 | b00052e4 | balrog | case FLASH_ECCCNTR:
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79 | b00052e4 | balrog | return s->ecc.count & 0xff; |
80 | b00052e4 | balrog | |
81 | b00052e4 | balrog | case FLASH_FLASHCTL:
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82 | b00052e4 | balrog | nand_getpins(s->nand, &ryby); |
83 | b00052e4 | balrog | if (ryby)
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84 | b00052e4 | balrog | return s->ctl | FLASHCTL_RYBY;
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85 | b00052e4 | balrog | else
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86 | b00052e4 | balrog | return s->ctl;
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87 | b00052e4 | balrog | |
88 | b00052e4 | balrog | case FLASH_FLASHIO:
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89 | b00052e4 | balrog | return ecc_digest(&s->ecc, nand_getio(s->nand));
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90 | b00052e4 | balrog | |
91 | b00052e4 | balrog | default:
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92 | b00052e4 | balrog | spitz_printf("Bad register offset " REG_FMT "\n", addr); |
93 | b00052e4 | balrog | } |
94 | b00052e4 | balrog | return 0; |
95 | b00052e4 | balrog | } |
96 | b00052e4 | balrog | |
97 | a5236105 | balrog | static uint32_t sl_readl(void *opaque, target_phys_addr_t addr) |
98 | a5236105 | balrog | { |
99 | a5236105 | balrog | struct sl_nand_s *s = (struct sl_nand_s *) opaque; |
100 | a5236105 | balrog | addr -= s->target_base; |
101 | a5236105 | balrog | |
102 | a5236105 | balrog | if (addr == FLASH_FLASHIO)
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103 | a5236105 | balrog | return ecc_digest(&s->ecc, nand_getio(s->nand)) |
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104 | a5236105 | balrog | (ecc_digest(&s->ecc, nand_getio(s->nand)) << 16);
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105 | a5236105 | balrog | |
106 | a5236105 | balrog | return sl_readb(opaque, addr);
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107 | a5236105 | balrog | } |
108 | a5236105 | balrog | |
109 | b00052e4 | balrog | static void sl_writeb(void *opaque, target_phys_addr_t addr, |
110 | b00052e4 | balrog | uint32_t value) |
111 | b00052e4 | balrog | { |
112 | b00052e4 | balrog | struct sl_nand_s *s = (struct sl_nand_s *) opaque; |
113 | b00052e4 | balrog | addr -= s->target_base; |
114 | b00052e4 | balrog | |
115 | b00052e4 | balrog | switch (addr) {
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116 | b00052e4 | balrog | case FLASH_ECCCLRR:
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117 | b00052e4 | balrog | /* Value is ignored. */
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118 | b00052e4 | balrog | ecc_reset(&s->ecc); |
119 | b00052e4 | balrog | break;
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120 | b00052e4 | balrog | |
121 | b00052e4 | balrog | case FLASH_FLASHCTL:
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122 | b00052e4 | balrog | s->ctl = value & 0xff & ~FLASHCTL_RYBY;
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123 | b00052e4 | balrog | nand_setpins(s->nand, |
124 | b00052e4 | balrog | s->ctl & FLASHCTL_CLE, |
125 | b00052e4 | balrog | s->ctl & FLASHCTL_ALE, |
126 | b00052e4 | balrog | s->ctl & FLASHCTL_NCE, |
127 | b00052e4 | balrog | s->ctl & FLASHCTL_WP, |
128 | b00052e4 | balrog | 0);
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129 | b00052e4 | balrog | break;
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130 | b00052e4 | balrog | |
131 | b00052e4 | balrog | case FLASH_FLASHIO:
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132 | b00052e4 | balrog | nand_setio(s->nand, ecc_digest(&s->ecc, value & 0xff));
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133 | b00052e4 | balrog | break;
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134 | b00052e4 | balrog | |
135 | b00052e4 | balrog | default:
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136 | b00052e4 | balrog | spitz_printf("Bad register offset " REG_FMT "\n", addr); |
137 | b00052e4 | balrog | } |
138 | b00052e4 | balrog | } |
139 | b00052e4 | balrog | |
140 | aa941b94 | balrog | static void sl_save(QEMUFile *f, void *opaque) |
141 | aa941b94 | balrog | { |
142 | aa941b94 | balrog | struct sl_nand_s *s = (struct sl_nand_s *) opaque; |
143 | aa941b94 | balrog | |
144 | aa941b94 | balrog | qemu_put_8s(f, &s->ctl); |
145 | aa941b94 | balrog | ecc_put(f, &s->ecc); |
146 | aa941b94 | balrog | } |
147 | aa941b94 | balrog | |
148 | aa941b94 | balrog | static int sl_load(QEMUFile *f, void *opaque, int version_id) |
149 | aa941b94 | balrog | { |
150 | aa941b94 | balrog | struct sl_nand_s *s = (struct sl_nand_s *) opaque; |
151 | aa941b94 | balrog | |
152 | aa941b94 | balrog | qemu_get_8s(f, &s->ctl); |
153 | aa941b94 | balrog | ecc_get(f, &s->ecc); |
154 | aa941b94 | balrog | |
155 | aa941b94 | balrog | return 0; |
156 | aa941b94 | balrog | } |
157 | aa941b94 | balrog | |
158 | b00052e4 | balrog | enum {
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159 | b00052e4 | balrog | FLASH_128M, |
160 | b00052e4 | balrog | FLASH_1024M, |
161 | b00052e4 | balrog | }; |
162 | b00052e4 | balrog | |
163 | b00052e4 | balrog | static void sl_flash_register(struct pxa2xx_state_s *cpu, int size) |
164 | b00052e4 | balrog | { |
165 | b00052e4 | balrog | int iomemtype;
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166 | b00052e4 | balrog | struct sl_nand_s *s;
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167 | b00052e4 | balrog | CPUReadMemoryFunc *sl_readfn[] = { |
168 | b00052e4 | balrog | sl_readb, |
169 | b00052e4 | balrog | sl_readb, |
170 | a5236105 | balrog | sl_readl, |
171 | b00052e4 | balrog | }; |
172 | b00052e4 | balrog | CPUWriteMemoryFunc *sl_writefn[] = { |
173 | b00052e4 | balrog | sl_writeb, |
174 | b00052e4 | balrog | sl_writeb, |
175 | b00052e4 | balrog | sl_writeb, |
176 | b00052e4 | balrog | }; |
177 | b00052e4 | balrog | |
178 | b00052e4 | balrog | s = (struct sl_nand_s *) qemu_mallocz(sizeof(struct sl_nand_s)); |
179 | b00052e4 | balrog | s->target_base = FLASH_BASE; |
180 | b00052e4 | balrog | s->ctl = 0;
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181 | b00052e4 | balrog | if (size == FLASH_128M)
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182 | b00052e4 | balrog | s->nand = nand_init(NAND_MFR_SAMSUNG, 0x73);
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183 | b00052e4 | balrog | else if (size == FLASH_1024M) |
184 | b00052e4 | balrog | s->nand = nand_init(NAND_MFR_SAMSUNG, 0xf1);
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185 | b00052e4 | balrog | |
186 | b00052e4 | balrog | iomemtype = cpu_register_io_memory(0, sl_readfn,
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187 | b00052e4 | balrog | sl_writefn, s); |
188 | b00052e4 | balrog | cpu_register_physical_memory(s->target_base, 0x40, iomemtype);
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189 | aa941b94 | balrog | |
190 | aa941b94 | balrog | register_savevm("sl_flash", 0, 0, sl_save, sl_load, s); |
191 | b00052e4 | balrog | } |
192 | b00052e4 | balrog | |
193 | b00052e4 | balrog | /* Spitz Keyboard */
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194 | b00052e4 | balrog | |
195 | b00052e4 | balrog | #define SPITZ_KEY_STROBE_NUM 11 |
196 | b00052e4 | balrog | #define SPITZ_KEY_SENSE_NUM 7 |
197 | b00052e4 | balrog | |
198 | b00052e4 | balrog | static const int spitz_gpio_key_sense[SPITZ_KEY_SENSE_NUM] = { |
199 | b00052e4 | balrog | 12, 17, 91, 34, 36, 38, 39 |
200 | b00052e4 | balrog | }; |
201 | b00052e4 | balrog | |
202 | b00052e4 | balrog | static const int spitz_gpio_key_strobe[SPITZ_KEY_STROBE_NUM] = { |
203 | b00052e4 | balrog | 88, 23, 24, 25, 26, 27, 52, 103, 107, 108, 114 |
204 | b00052e4 | balrog | }; |
205 | b00052e4 | balrog | |
206 | b00052e4 | balrog | /* Eighth additional row maps the special keys */
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207 | b00052e4 | balrog | static int spitz_keymap[SPITZ_KEY_SENSE_NUM + 1][SPITZ_KEY_STROBE_NUM] = { |
208 | b00052e4 | balrog | { 0x1d, 0x02, 0x04, 0x06, 0x07, 0x08, 0x0a, 0x0b, 0x0e, 0x3f, 0x40 }, |
209 | b00052e4 | balrog | { -1 , 0x03, 0x05, 0x13, 0x15, 0x09, 0x17, 0x18, 0x19, 0x41, 0x42 }, |
210 | b00052e4 | balrog | { 0x0f, 0x10, 0x12, 0x14, 0x22, 0x16, 0x24, 0x25, -1 , -1 , -1 }, |
211 | b00052e4 | balrog | { 0x3c, 0x11, 0x1f, 0x21, 0x2f, 0x23, 0x32, 0x26, -1 , 0x36, -1 }, |
212 | b00052e4 | balrog | { 0x3b, 0x1e, 0x20, 0x2e, 0x30, 0x31, 0x34, -1 , 0x1c, 0x2a, -1 }, |
213 | 2b76bdc9 | balrog | { 0x44, 0x2c, 0x2d, 0x0c, 0x39, 0x33, -1 , 0x48, -1 , -1 , 0x38 }, |
214 | 2b76bdc9 | balrog | { 0x37, 0x3d, -1 , 0x45, 0x57, 0x58, 0x4b, 0x50, 0x4d, -1 , -1 }, |
215 | b00052e4 | balrog | { 0x52, 0x43, 0x01, 0x47, 0x49, -1 , -1 , -1 , -1 , -1 , -1 }, |
216 | b00052e4 | balrog | }; |
217 | b00052e4 | balrog | |
218 | b00052e4 | balrog | #define SPITZ_GPIO_AK_INT 13 /* Remote control */ |
219 | b00052e4 | balrog | #define SPITZ_GPIO_SYNC 16 /* Sync button */ |
220 | b00052e4 | balrog | #define SPITZ_GPIO_ON_KEY 95 /* Power button */ |
221 | b00052e4 | balrog | #define SPITZ_GPIO_SWA 97 /* Lid */ |
222 | b00052e4 | balrog | #define SPITZ_GPIO_SWB 96 /* Tablet mode */ |
223 | b00052e4 | balrog | |
224 | b00052e4 | balrog | /* The special buttons are mapped to unused keys */
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225 | b00052e4 | balrog | static const int spitz_gpiomap[5] = { |
226 | b00052e4 | balrog | SPITZ_GPIO_AK_INT, SPITZ_GPIO_SYNC, SPITZ_GPIO_ON_KEY, |
227 | b00052e4 | balrog | SPITZ_GPIO_SWA, SPITZ_GPIO_SWB, |
228 | b00052e4 | balrog | }; |
229 | b00052e4 | balrog | static int spitz_gpio_invert[5] = { 0, 0, 0, 0, 0, }; |
230 | b00052e4 | balrog | |
231 | b00052e4 | balrog | struct spitz_keyboard_s {
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232 | 38641a52 | balrog | qemu_irq sense[SPITZ_KEY_SENSE_NUM]; |
233 | 38641a52 | balrog | qemu_irq *strobe; |
234 | 38641a52 | balrog | qemu_irq gpiomap[5];
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235 | b00052e4 | balrog | int keymap[0x80]; |
236 | b00052e4 | balrog | uint16_t keyrow[SPITZ_KEY_SENSE_NUM]; |
237 | b00052e4 | balrog | uint16_t strobe_state; |
238 | b00052e4 | balrog | uint16_t sense_state; |
239 | b00052e4 | balrog | |
240 | b00052e4 | balrog | uint16_t pre_map[0x100];
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241 | b00052e4 | balrog | uint16_t modifiers; |
242 | b00052e4 | balrog | uint16_t imodifiers; |
243 | b00052e4 | balrog | uint8_t fifo[16];
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244 | b00052e4 | balrog | int fifopos, fifolen;
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245 | b00052e4 | balrog | QEMUTimer *kbdtimer; |
246 | b00052e4 | balrog | }; |
247 | b00052e4 | balrog | |
248 | b00052e4 | balrog | static void spitz_keyboard_sense_update(struct spitz_keyboard_s *s) |
249 | b00052e4 | balrog | { |
250 | b00052e4 | balrog | int i;
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251 | b00052e4 | balrog | uint16_t strobe, sense = 0;
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252 | b00052e4 | balrog | for (i = 0; i < SPITZ_KEY_SENSE_NUM; i ++) { |
253 | b00052e4 | balrog | strobe = s->keyrow[i] & s->strobe_state; |
254 | b00052e4 | balrog | if (strobe) {
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255 | b00052e4 | balrog | sense |= 1 << i;
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256 | b00052e4 | balrog | if (!(s->sense_state & (1 << i))) |
257 | 38641a52 | balrog | qemu_irq_raise(s->sense[i]); |
258 | b00052e4 | balrog | } else if (s->sense_state & (1 << i)) |
259 | 38641a52 | balrog | qemu_irq_lower(s->sense[i]); |
260 | b00052e4 | balrog | } |
261 | b00052e4 | balrog | |
262 | b00052e4 | balrog | s->sense_state = sense; |
263 | b00052e4 | balrog | } |
264 | b00052e4 | balrog | |
265 | 38641a52 | balrog | static void spitz_keyboard_strobe(void *opaque, int line, int level) |
266 | b00052e4 | balrog | { |
267 | 38641a52 | balrog | struct spitz_keyboard_s *s = (struct spitz_keyboard_s *) opaque; |
268 | 38641a52 | balrog | |
269 | 38641a52 | balrog | if (level)
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270 | 38641a52 | balrog | s->strobe_state |= 1 << line;
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271 | 38641a52 | balrog | else
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272 | 38641a52 | balrog | s->strobe_state &= ~(1 << line);
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273 | 38641a52 | balrog | spitz_keyboard_sense_update(s); |
274 | b00052e4 | balrog | } |
275 | b00052e4 | balrog | |
276 | b00052e4 | balrog | static void spitz_keyboard_keydown(struct spitz_keyboard_s *s, int keycode) |
277 | b00052e4 | balrog | { |
278 | b00052e4 | balrog | int spitz_keycode = s->keymap[keycode & 0x7f]; |
279 | b00052e4 | balrog | if (spitz_keycode == -1) |
280 | b00052e4 | balrog | return;
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281 | b00052e4 | balrog | |
282 | b00052e4 | balrog | /* Handle the additional keys */
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283 | b00052e4 | balrog | if ((spitz_keycode >> 4) == SPITZ_KEY_SENSE_NUM) { |
284 | 38641a52 | balrog | qemu_set_irq(s->gpiomap[spitz_keycode & 0xf], (keycode < 0x80) ^ |
285 | b00052e4 | balrog | spitz_gpio_invert[spitz_keycode & 0xf]);
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286 | b00052e4 | balrog | return;
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287 | b00052e4 | balrog | } |
288 | b00052e4 | balrog | |
289 | b00052e4 | balrog | if (keycode & 0x80) |
290 | b00052e4 | balrog | s->keyrow[spitz_keycode >> 4] &= ~(1 << (spitz_keycode & 0xf)); |
291 | b00052e4 | balrog | else
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292 | b00052e4 | balrog | s->keyrow[spitz_keycode >> 4] |= 1 << (spitz_keycode & 0xf); |
293 | b00052e4 | balrog | |
294 | b00052e4 | balrog | spitz_keyboard_sense_update(s); |
295 | b00052e4 | balrog | } |
296 | b00052e4 | balrog | |
297 | b00052e4 | balrog | #define SHIFT (1 << 7) |
298 | b00052e4 | balrog | #define CTRL (1 << 8) |
299 | b00052e4 | balrog | #define FN (1 << 9) |
300 | b00052e4 | balrog | |
301 | b00052e4 | balrog | #define QUEUE_KEY(c) s->fifo[(s->fifopos + s->fifolen ++) & 0xf] = c |
302 | b00052e4 | balrog | |
303 | b00052e4 | balrog | static void spitz_keyboard_handler(struct spitz_keyboard_s *s, int keycode) |
304 | b00052e4 | balrog | { |
305 | b00052e4 | balrog | uint16_t code; |
306 | b00052e4 | balrog | int mapcode;
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307 | b00052e4 | balrog | switch (keycode) {
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308 | b00052e4 | balrog | case 0x2a: /* Left Shift */ |
309 | b00052e4 | balrog | s->modifiers |= 1;
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310 | b00052e4 | balrog | break;
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311 | b00052e4 | balrog | case 0xaa: |
312 | b00052e4 | balrog | s->modifiers &= ~1;
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313 | b00052e4 | balrog | break;
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314 | b00052e4 | balrog | case 0x36: /* Right Shift */ |
315 | b00052e4 | balrog | s->modifiers |= 2;
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316 | b00052e4 | balrog | break;
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317 | b00052e4 | balrog | case 0xb6: |
318 | b00052e4 | balrog | s->modifiers &= ~2;
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319 | b00052e4 | balrog | break;
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320 | b00052e4 | balrog | case 0x1d: /* Control */ |
321 | b00052e4 | balrog | s->modifiers |= 4;
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322 | b00052e4 | balrog | break;
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323 | b00052e4 | balrog | case 0x9d: |
324 | b00052e4 | balrog | s->modifiers &= ~4;
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325 | b00052e4 | balrog | break;
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326 | b00052e4 | balrog | case 0x38: /* Alt */ |
327 | b00052e4 | balrog | s->modifiers |= 8;
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328 | b00052e4 | balrog | break;
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329 | b00052e4 | balrog | case 0xb8: |
330 | b00052e4 | balrog | s->modifiers &= ~8;
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331 | b00052e4 | balrog | break;
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332 | b00052e4 | balrog | } |
333 | b00052e4 | balrog | |
334 | b00052e4 | balrog | code = s->pre_map[mapcode = ((s->modifiers & 3) ?
|
335 | b00052e4 | balrog | (keycode | SHIFT) : |
336 | b00052e4 | balrog | (keycode & ~SHIFT))]; |
337 | b00052e4 | balrog | |
338 | b00052e4 | balrog | if (code != mapcode) {
|
339 | b00052e4 | balrog | #if 0
|
340 | b00052e4 | balrog | if ((code & SHIFT) && !(s->modifiers & 1))
|
341 | b00052e4 | balrog | QUEUE_KEY(0x2a | (keycode & 0x80));
|
342 | b00052e4 | balrog | if ((code & CTRL ) && !(s->modifiers & 4))
|
343 | b00052e4 | balrog | QUEUE_KEY(0x1d | (keycode & 0x80));
|
344 | b00052e4 | balrog | if ((code & FN ) && !(s->modifiers & 8))
|
345 | b00052e4 | balrog | QUEUE_KEY(0x38 | (keycode & 0x80));
|
346 | b00052e4 | balrog | if ((code & FN ) && (s->modifiers & 1))
|
347 | b00052e4 | balrog | QUEUE_KEY(0x2a | (~keycode & 0x80));
|
348 | b00052e4 | balrog | if ((code & FN ) && (s->modifiers & 2))
|
349 | b00052e4 | balrog | QUEUE_KEY(0x36 | (~keycode & 0x80));
|
350 | b00052e4 | balrog | #else
|
351 | b00052e4 | balrog | if (keycode & 0x80) { |
352 | b00052e4 | balrog | if ((s->imodifiers & 1 ) && !(s->modifiers & 1)) |
353 | b00052e4 | balrog | QUEUE_KEY(0x2a | 0x80); |
354 | b00052e4 | balrog | if ((s->imodifiers & 4 ) && !(s->modifiers & 4)) |
355 | b00052e4 | balrog | QUEUE_KEY(0x1d | 0x80); |
356 | b00052e4 | balrog | if ((s->imodifiers & 8 ) && !(s->modifiers & 8)) |
357 | b00052e4 | balrog | QUEUE_KEY(0x38 | 0x80); |
358 | b00052e4 | balrog | if ((s->imodifiers & 0x10) && (s->modifiers & 1)) |
359 | b00052e4 | balrog | QUEUE_KEY(0x2a);
|
360 | b00052e4 | balrog | if ((s->imodifiers & 0x20) && (s->modifiers & 2)) |
361 | b00052e4 | balrog | QUEUE_KEY(0x36);
|
362 | b00052e4 | balrog | s->imodifiers = 0;
|
363 | b00052e4 | balrog | } else {
|
364 | b00052e4 | balrog | if ((code & SHIFT) && !((s->modifiers | s->imodifiers) & 1)) { |
365 | b00052e4 | balrog | QUEUE_KEY(0x2a);
|
366 | b00052e4 | balrog | s->imodifiers |= 1;
|
367 | b00052e4 | balrog | } |
368 | b00052e4 | balrog | if ((code & CTRL ) && !((s->modifiers | s->imodifiers) & 4)) { |
369 | b00052e4 | balrog | QUEUE_KEY(0x1d);
|
370 | b00052e4 | balrog | s->imodifiers |= 4;
|
371 | b00052e4 | balrog | } |
372 | b00052e4 | balrog | if ((code & FN ) && !((s->modifiers | s->imodifiers) & 8)) { |
373 | b00052e4 | balrog | QUEUE_KEY(0x38);
|
374 | b00052e4 | balrog | s->imodifiers |= 8;
|
375 | b00052e4 | balrog | } |
376 | b00052e4 | balrog | if ((code & FN ) && (s->modifiers & 1) && |
377 | b00052e4 | balrog | !(s->imodifiers & 0x10)) {
|
378 | b00052e4 | balrog | QUEUE_KEY(0x2a | 0x80); |
379 | b00052e4 | balrog | s->imodifiers |= 0x10;
|
380 | b00052e4 | balrog | } |
381 | b00052e4 | balrog | if ((code & FN ) && (s->modifiers & 2) && |
382 | b00052e4 | balrog | !(s->imodifiers & 0x20)) {
|
383 | b00052e4 | balrog | QUEUE_KEY(0x36 | 0x80); |
384 | b00052e4 | balrog | s->imodifiers |= 0x20;
|
385 | b00052e4 | balrog | } |
386 | b00052e4 | balrog | } |
387 | b00052e4 | balrog | #endif
|
388 | b00052e4 | balrog | } |
389 | b00052e4 | balrog | |
390 | b00052e4 | balrog | QUEUE_KEY((code & 0x7f) | (keycode & 0x80)); |
391 | b00052e4 | balrog | } |
392 | b00052e4 | balrog | |
393 | b00052e4 | balrog | static void spitz_keyboard_tick(void *opaque) |
394 | b00052e4 | balrog | { |
395 | b00052e4 | balrog | struct spitz_keyboard_s *s = (struct spitz_keyboard_s *) opaque; |
396 | b00052e4 | balrog | |
397 | b00052e4 | balrog | if (s->fifolen) {
|
398 | b00052e4 | balrog | spitz_keyboard_keydown(s, s->fifo[s->fifopos ++]); |
399 | b00052e4 | balrog | s->fifolen --; |
400 | b00052e4 | balrog | if (s->fifopos >= 16) |
401 | b00052e4 | balrog | s->fifopos = 0;
|
402 | b00052e4 | balrog | } |
403 | b00052e4 | balrog | |
404 | b00052e4 | balrog | qemu_mod_timer(s->kbdtimer, qemu_get_clock(vm_clock) + ticks_per_sec / 32);
|
405 | b00052e4 | balrog | } |
406 | b00052e4 | balrog | |
407 | b00052e4 | balrog | static void spitz_keyboard_pre_map(struct spitz_keyboard_s *s) |
408 | b00052e4 | balrog | { |
409 | b00052e4 | balrog | int i;
|
410 | b00052e4 | balrog | for (i = 0; i < 0x100; i ++) |
411 | b00052e4 | balrog | s->pre_map[i] = i; |
412 | b00052e4 | balrog | s->pre_map[0x02 | SHIFT ] = 0x02 | SHIFT; /* exclam */ |
413 | b00052e4 | balrog | s->pre_map[0x28 | SHIFT ] = 0x03 | SHIFT; /* quotedbl */ |
414 | b00052e4 | balrog | s->pre_map[0x04 | SHIFT ] = 0x04 | SHIFT; /* numbersign */ |
415 | b00052e4 | balrog | s->pre_map[0x05 | SHIFT ] = 0x05 | SHIFT; /* dollar */ |
416 | b00052e4 | balrog | s->pre_map[0x06 | SHIFT ] = 0x06 | SHIFT; /* percent */ |
417 | b00052e4 | balrog | s->pre_map[0x08 | SHIFT ] = 0x07 | SHIFT; /* ampersand */ |
418 | b00052e4 | balrog | s->pre_map[0x28 ] = 0x08 | SHIFT; /* apostrophe */ |
419 | b00052e4 | balrog | s->pre_map[0x0a | SHIFT ] = 0x09 | SHIFT; /* parenleft */ |
420 | b00052e4 | balrog | s->pre_map[0x0b | SHIFT ] = 0x0a | SHIFT; /* parenright */ |
421 | b00052e4 | balrog | s->pre_map[0x29 | SHIFT ] = 0x0b | SHIFT; /* asciitilde */ |
422 | b00052e4 | balrog | s->pre_map[0x03 | SHIFT ] = 0x0c | SHIFT; /* at */ |
423 | b00052e4 | balrog | s->pre_map[0xd3 ] = 0x0e | FN; /* Delete */ |
424 | b00052e4 | balrog | s->pre_map[0x3a ] = 0x0f | FN; /* Caps_Lock */ |
425 | b00052e4 | balrog | s->pre_map[0x07 | SHIFT ] = 0x11 | FN; /* asciicircum */ |
426 | b00052e4 | balrog | s->pre_map[0x0d ] = 0x12 | FN; /* equal */ |
427 | b00052e4 | balrog | s->pre_map[0x0d | SHIFT ] = 0x13 | FN; /* plus */ |
428 | b00052e4 | balrog | s->pre_map[0x1a ] = 0x14 | FN; /* bracketleft */ |
429 | b00052e4 | balrog | s->pre_map[0x1b ] = 0x15 | FN; /* bracketright */ |
430 | 2b76bdc9 | balrog | s->pre_map[0x1a | SHIFT ] = 0x16 | FN; /* braceleft */ |
431 | 2b76bdc9 | balrog | s->pre_map[0x1b | SHIFT ] = 0x17 | FN; /* braceright */ |
432 | b00052e4 | balrog | s->pre_map[0x27 ] = 0x22 | FN; /* semicolon */ |
433 | b00052e4 | balrog | s->pre_map[0x27 | SHIFT ] = 0x23 | FN; /* colon */ |
434 | b00052e4 | balrog | s->pre_map[0x09 | SHIFT ] = 0x24 | FN; /* asterisk */ |
435 | b00052e4 | balrog | s->pre_map[0x2b ] = 0x25 | FN; /* backslash */ |
436 | b00052e4 | balrog | s->pre_map[0x2b | SHIFT ] = 0x26 | FN; /* bar */ |
437 | b00052e4 | balrog | s->pre_map[0x0c | SHIFT ] = 0x30 | FN; /* underscore */ |
438 | 2b76bdc9 | balrog | s->pre_map[0x33 | SHIFT ] = 0x33 | FN; /* less */ |
439 | b00052e4 | balrog | s->pre_map[0x35 ] = 0x33 | SHIFT; /* slash */ |
440 | 2b76bdc9 | balrog | s->pre_map[0x34 | SHIFT ] = 0x34 | FN; /* greater */ |
441 | b00052e4 | balrog | s->pre_map[0x35 | SHIFT ] = 0x34 | SHIFT; /* question */ |
442 | b00052e4 | balrog | s->pre_map[0x49 ] = 0x48 | FN; /* Page_Up */ |
443 | b00052e4 | balrog | s->pre_map[0x51 ] = 0x50 | FN; /* Page_Down */ |
444 | b00052e4 | balrog | |
445 | b00052e4 | balrog | s->modifiers = 0;
|
446 | b00052e4 | balrog | s->imodifiers = 0;
|
447 | b00052e4 | balrog | s->fifopos = 0;
|
448 | b00052e4 | balrog | s->fifolen = 0;
|
449 | b00052e4 | balrog | s->kbdtimer = qemu_new_timer(vm_clock, spitz_keyboard_tick, s); |
450 | b00052e4 | balrog | spitz_keyboard_tick(s); |
451 | b00052e4 | balrog | } |
452 | b00052e4 | balrog | |
453 | b00052e4 | balrog | #undef SHIFT
|
454 | b00052e4 | balrog | #undef CTRL
|
455 | b00052e4 | balrog | #undef FN
|
456 | b00052e4 | balrog | |
457 | aa941b94 | balrog | static void spitz_keyboard_save(QEMUFile *f, void *opaque) |
458 | aa941b94 | balrog | { |
459 | aa941b94 | balrog | struct spitz_keyboard_s *s = (struct spitz_keyboard_s *) opaque; |
460 | aa941b94 | balrog | int i;
|
461 | aa941b94 | balrog | |
462 | aa941b94 | balrog | qemu_put_be16s(f, &s->sense_state); |
463 | aa941b94 | balrog | qemu_put_be16s(f, &s->strobe_state); |
464 | aa941b94 | balrog | for (i = 0; i < 5; i ++) |
465 | aa941b94 | balrog | qemu_put_byte(f, spitz_gpio_invert[i]); |
466 | aa941b94 | balrog | } |
467 | aa941b94 | balrog | |
468 | aa941b94 | balrog | static int spitz_keyboard_load(QEMUFile *f, void *opaque, int version_id) |
469 | aa941b94 | balrog | { |
470 | aa941b94 | balrog | struct spitz_keyboard_s *s = (struct spitz_keyboard_s *) opaque; |
471 | aa941b94 | balrog | int i;
|
472 | aa941b94 | balrog | |
473 | aa941b94 | balrog | qemu_get_be16s(f, &s->sense_state); |
474 | aa941b94 | balrog | qemu_get_be16s(f, &s->strobe_state); |
475 | aa941b94 | balrog | for (i = 0; i < 5; i ++) |
476 | aa941b94 | balrog | spitz_gpio_invert[i] = qemu_get_byte(f); |
477 | aa941b94 | balrog | |
478 | aa941b94 | balrog | /* Release all pressed keys */
|
479 | aa941b94 | balrog | memset(s->keyrow, 0, sizeof(s->keyrow)); |
480 | aa941b94 | balrog | spitz_keyboard_sense_update(s); |
481 | aa941b94 | balrog | s->modifiers = 0;
|
482 | aa941b94 | balrog | s->imodifiers = 0;
|
483 | aa941b94 | balrog | s->fifopos = 0;
|
484 | aa941b94 | balrog | s->fifolen = 0;
|
485 | aa941b94 | balrog | |
486 | aa941b94 | balrog | return 0; |
487 | aa941b94 | balrog | } |
488 | aa941b94 | balrog | |
489 | b00052e4 | balrog | static void spitz_keyboard_register(struct pxa2xx_state_s *cpu) |
490 | b00052e4 | balrog | { |
491 | b00052e4 | balrog | int i, j;
|
492 | b00052e4 | balrog | struct spitz_keyboard_s *s;
|
493 | b00052e4 | balrog | |
494 | b00052e4 | balrog | s = (struct spitz_keyboard_s *)
|
495 | b00052e4 | balrog | qemu_mallocz(sizeof(struct spitz_keyboard_s)); |
496 | b00052e4 | balrog | memset(s, 0, sizeof(struct spitz_keyboard_s)); |
497 | b00052e4 | balrog | |
498 | b00052e4 | balrog | for (i = 0; i < 0x80; i ++) |
499 | b00052e4 | balrog | s->keymap[i] = -1;
|
500 | b00052e4 | balrog | for (i = 0; i < SPITZ_KEY_SENSE_NUM + 1; i ++) |
501 | b00052e4 | balrog | for (j = 0; j < SPITZ_KEY_STROBE_NUM; j ++) |
502 | b00052e4 | balrog | if (spitz_keymap[i][j] != -1) |
503 | b00052e4 | balrog | s->keymap[spitz_keymap[i][j]] = (i << 4) | j;
|
504 | b00052e4 | balrog | |
505 | 38641a52 | balrog | for (i = 0; i < SPITZ_KEY_SENSE_NUM; i ++) |
506 | 38641a52 | balrog | s->sense[i] = pxa2xx_gpio_in_get(cpu->gpio)[spitz_gpio_key_sense[i]]; |
507 | 38641a52 | balrog | |
508 | 38641a52 | balrog | for (i = 0; i < 5; i ++) |
509 | 38641a52 | balrog | s->gpiomap[i] = pxa2xx_gpio_in_get(cpu->gpio)[spitz_gpiomap[i]]; |
510 | 38641a52 | balrog | |
511 | 38641a52 | balrog | s->strobe = qemu_allocate_irqs(spitz_keyboard_strobe, s, |
512 | 38641a52 | balrog | SPITZ_KEY_STROBE_NUM); |
513 | b00052e4 | balrog | for (i = 0; i < SPITZ_KEY_STROBE_NUM; i ++) |
514 | 38641a52 | balrog | pxa2xx_gpio_out_set(cpu->gpio, spitz_gpio_key_strobe[i], s->strobe[i]); |
515 | b00052e4 | balrog | |
516 | b00052e4 | balrog | spitz_keyboard_pre_map(s); |
517 | b00052e4 | balrog | qemu_add_kbd_event_handler((QEMUPutKBDEvent *) spitz_keyboard_handler, s); |
518 | aa941b94 | balrog | |
519 | aa941b94 | balrog | register_savevm("spitz_keyboard", 0, 0, |
520 | aa941b94 | balrog | spitz_keyboard_save, spitz_keyboard_load, s); |
521 | b00052e4 | balrog | } |
522 | b00052e4 | balrog | |
523 | b00052e4 | balrog | /* SCOOP devices */
|
524 | b00052e4 | balrog | |
525 | b00052e4 | balrog | struct scoop_info_s {
|
526 | b00052e4 | balrog | target_phys_addr_t target_base; |
527 | 38641a52 | balrog | qemu_irq handler[16];
|
528 | 38641a52 | balrog | qemu_irq *in; |
529 | b00052e4 | balrog | uint16_t status; |
530 | b00052e4 | balrog | uint16_t power; |
531 | b00052e4 | balrog | uint32_t gpio_level; |
532 | b00052e4 | balrog | uint32_t gpio_dir; |
533 | b00052e4 | balrog | uint32_t prev_level; |
534 | b00052e4 | balrog | |
535 | b00052e4 | balrog | uint16_t mcr; |
536 | b00052e4 | balrog | uint16_t cdr; |
537 | b00052e4 | balrog | uint16_t ccr; |
538 | b00052e4 | balrog | uint16_t irr; |
539 | b00052e4 | balrog | uint16_t imr; |
540 | b00052e4 | balrog | uint16_t isr; |
541 | b00052e4 | balrog | uint16_t gprr; |
542 | b00052e4 | balrog | }; |
543 | b00052e4 | balrog | |
544 | b00052e4 | balrog | #define SCOOP_MCR 0x00 |
545 | b00052e4 | balrog | #define SCOOP_CDR 0x04 |
546 | b00052e4 | balrog | #define SCOOP_CSR 0x08 |
547 | b00052e4 | balrog | #define SCOOP_CPR 0x0c |
548 | b00052e4 | balrog | #define SCOOP_CCR 0x10 |
549 | b00052e4 | balrog | #define SCOOP_IRR_IRM 0x14 |
550 | b00052e4 | balrog | #define SCOOP_IMR 0x18 |
551 | b00052e4 | balrog | #define SCOOP_ISR 0x1c |
552 | b00052e4 | balrog | #define SCOOP_GPCR 0x20 |
553 | b00052e4 | balrog | #define SCOOP_GPWR 0x24 |
554 | b00052e4 | balrog | #define SCOOP_GPRR 0x28 |
555 | b00052e4 | balrog | |
556 | b00052e4 | balrog | static inline void scoop_gpio_handler_update(struct scoop_info_s *s) { |
557 | b00052e4 | balrog | uint32_t level, diff; |
558 | b00052e4 | balrog | int bit;
|
559 | b00052e4 | balrog | level = s->gpio_level & s->gpio_dir; |
560 | b00052e4 | balrog | |
561 | b00052e4 | balrog | for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) { |
562 | b00052e4 | balrog | bit = ffs(diff) - 1;
|
563 | 38641a52 | balrog | qemu_set_irq(s->handler[bit], (level >> bit) & 1);
|
564 | b00052e4 | balrog | } |
565 | b00052e4 | balrog | |
566 | b00052e4 | balrog | s->prev_level = level; |
567 | b00052e4 | balrog | } |
568 | b00052e4 | balrog | |
569 | b00052e4 | balrog | static uint32_t scoop_readb(void *opaque, target_phys_addr_t addr) |
570 | b00052e4 | balrog | { |
571 | b00052e4 | balrog | struct scoop_info_s *s = (struct scoop_info_s *) opaque; |
572 | b00052e4 | balrog | addr -= s->target_base; |
573 | b00052e4 | balrog | |
574 | b00052e4 | balrog | switch (addr) {
|
575 | b00052e4 | balrog | case SCOOP_MCR:
|
576 | b00052e4 | balrog | return s->mcr;
|
577 | b00052e4 | balrog | case SCOOP_CDR:
|
578 | b00052e4 | balrog | return s->cdr;
|
579 | b00052e4 | balrog | case SCOOP_CSR:
|
580 | b00052e4 | balrog | return s->status;
|
581 | b00052e4 | balrog | case SCOOP_CPR:
|
582 | b00052e4 | balrog | return s->power;
|
583 | b00052e4 | balrog | case SCOOP_CCR:
|
584 | b00052e4 | balrog | return s->ccr;
|
585 | b00052e4 | balrog | case SCOOP_IRR_IRM:
|
586 | b00052e4 | balrog | return s->irr;
|
587 | b00052e4 | balrog | case SCOOP_IMR:
|
588 | b00052e4 | balrog | return s->imr;
|
589 | b00052e4 | balrog | case SCOOP_ISR:
|
590 | b00052e4 | balrog | return s->isr;
|
591 | b00052e4 | balrog | case SCOOP_GPCR:
|
592 | b00052e4 | balrog | return s->gpio_dir;
|
593 | b00052e4 | balrog | case SCOOP_GPWR:
|
594 | b00052e4 | balrog | return s->gpio_level;
|
595 | b00052e4 | balrog | case SCOOP_GPRR:
|
596 | b00052e4 | balrog | return s->gprr;
|
597 | b00052e4 | balrog | default:
|
598 | b00052e4 | balrog | spitz_printf("Bad register offset " REG_FMT "\n", addr); |
599 | b00052e4 | balrog | } |
600 | b00052e4 | balrog | |
601 | b00052e4 | balrog | return 0; |
602 | b00052e4 | balrog | } |
603 | b00052e4 | balrog | |
604 | b00052e4 | balrog | static void scoop_writeb(void *opaque, target_phys_addr_t addr, uint32_t value) |
605 | b00052e4 | balrog | { |
606 | b00052e4 | balrog | struct scoop_info_s *s = (struct scoop_info_s *) opaque; |
607 | b00052e4 | balrog | addr -= s->target_base; |
608 | b00052e4 | balrog | value &= 0xffff;
|
609 | b00052e4 | balrog | |
610 | b00052e4 | balrog | switch (addr) {
|
611 | b00052e4 | balrog | case SCOOP_MCR:
|
612 | b00052e4 | balrog | s->mcr = value; |
613 | b00052e4 | balrog | break;
|
614 | b00052e4 | balrog | case SCOOP_CDR:
|
615 | b00052e4 | balrog | s->cdr = value; |
616 | b00052e4 | balrog | break;
|
617 | b00052e4 | balrog | case SCOOP_CPR:
|
618 | b00052e4 | balrog | s->power = value; |
619 | b00052e4 | balrog | if (value & 0x80) |
620 | b00052e4 | balrog | s->power |= 0x8040;
|
621 | b00052e4 | balrog | break;
|
622 | b00052e4 | balrog | case SCOOP_CCR:
|
623 | b00052e4 | balrog | s->ccr = value; |
624 | b00052e4 | balrog | break;
|
625 | b00052e4 | balrog | case SCOOP_IRR_IRM:
|
626 | b00052e4 | balrog | s->irr = value; |
627 | b00052e4 | balrog | break;
|
628 | b00052e4 | balrog | case SCOOP_IMR:
|
629 | b00052e4 | balrog | s->imr = value; |
630 | b00052e4 | balrog | break;
|
631 | b00052e4 | balrog | case SCOOP_ISR:
|
632 | b00052e4 | balrog | s->isr = value; |
633 | b00052e4 | balrog | break;
|
634 | b00052e4 | balrog | case SCOOP_GPCR:
|
635 | b00052e4 | balrog | s->gpio_dir = value; |
636 | b00052e4 | balrog | scoop_gpio_handler_update(s); |
637 | b00052e4 | balrog | break;
|
638 | b00052e4 | balrog | case SCOOP_GPWR:
|
639 | b00052e4 | balrog | s->gpio_level = value & s->gpio_dir; |
640 | b00052e4 | balrog | scoop_gpio_handler_update(s); |
641 | b00052e4 | balrog | break;
|
642 | b00052e4 | balrog | case SCOOP_GPRR:
|
643 | b00052e4 | balrog | s->gprr = value; |
644 | b00052e4 | balrog | break;
|
645 | b00052e4 | balrog | default:
|
646 | b00052e4 | balrog | spitz_printf("Bad register offset " REG_FMT "\n", addr); |
647 | b00052e4 | balrog | } |
648 | b00052e4 | balrog | } |
649 | b00052e4 | balrog | |
650 | b00052e4 | balrog | CPUReadMemoryFunc *scoop_readfn[] = { |
651 | b00052e4 | balrog | scoop_readb, |
652 | b00052e4 | balrog | scoop_readb, |
653 | b00052e4 | balrog | scoop_readb, |
654 | b00052e4 | balrog | }; |
655 | b00052e4 | balrog | CPUWriteMemoryFunc *scoop_writefn[] = { |
656 | b00052e4 | balrog | scoop_writeb, |
657 | b00052e4 | balrog | scoop_writeb, |
658 | b00052e4 | balrog | scoop_writeb, |
659 | b00052e4 | balrog | }; |
660 | b00052e4 | balrog | |
661 | 38641a52 | balrog | static void scoop_gpio_set(void *opaque, int line, int level) |
662 | b00052e4 | balrog | { |
663 | 38641a52 | balrog | struct scoop_info_s *s = (struct scoop_info_s *) s; |
664 | b00052e4 | balrog | |
665 | b00052e4 | balrog | if (level)
|
666 | b00052e4 | balrog | s->gpio_level |= (1 << line);
|
667 | b00052e4 | balrog | else
|
668 | b00052e4 | balrog | s->gpio_level &= ~(1 << line);
|
669 | b00052e4 | balrog | } |
670 | b00052e4 | balrog | |
671 | 38641a52 | balrog | static inline qemu_irq *scoop_gpio_in_get(struct scoop_info_s *s) |
672 | 38641a52 | balrog | { |
673 | 38641a52 | balrog | return s->in;
|
674 | 38641a52 | balrog | } |
675 | 38641a52 | balrog | |
676 | 38641a52 | balrog | static inline void scoop_gpio_out_set(struct scoop_info_s *s, int line, |
677 | 38641a52 | balrog | qemu_irq handler) { |
678 | b00052e4 | balrog | if (line >= 16) { |
679 | b00052e4 | balrog | spitz_printf("No GPIO pin %i\n", line);
|
680 | b00052e4 | balrog | return;
|
681 | b00052e4 | balrog | } |
682 | b00052e4 | balrog | |
683 | 38641a52 | balrog | s->handler[line] = handler; |
684 | b00052e4 | balrog | } |
685 | b00052e4 | balrog | |
686 | aa941b94 | balrog | static void scoop_save(QEMUFile *f, void *opaque) |
687 | aa941b94 | balrog | { |
688 | aa941b94 | balrog | struct scoop_info_s *s = (struct scoop_info_s *) opaque; |
689 | aa941b94 | balrog | qemu_put_be16s(f, &s->status); |
690 | aa941b94 | balrog | qemu_put_be16s(f, &s->power); |
691 | aa941b94 | balrog | qemu_put_be32s(f, &s->gpio_level); |
692 | aa941b94 | balrog | qemu_put_be32s(f, &s->gpio_dir); |
693 | aa941b94 | balrog | qemu_put_be32s(f, &s->prev_level); |
694 | aa941b94 | balrog | qemu_put_be16s(f, &s->mcr); |
695 | aa941b94 | balrog | qemu_put_be16s(f, &s->cdr); |
696 | aa941b94 | balrog | qemu_put_be16s(f, &s->ccr); |
697 | aa941b94 | balrog | qemu_put_be16s(f, &s->irr); |
698 | aa941b94 | balrog | qemu_put_be16s(f, &s->imr); |
699 | aa941b94 | balrog | qemu_put_be16s(f, &s->isr); |
700 | aa941b94 | balrog | qemu_put_be16s(f, &s->gprr); |
701 | aa941b94 | balrog | } |
702 | aa941b94 | balrog | |
703 | aa941b94 | balrog | static int scoop_load(QEMUFile *f, void *opaque, int version_id) |
704 | aa941b94 | balrog | { |
705 | aa941b94 | balrog | struct scoop_info_s *s = (struct scoop_info_s *) opaque; |
706 | aa941b94 | balrog | qemu_get_be16s(f, &s->status); |
707 | aa941b94 | balrog | qemu_get_be16s(f, &s->power); |
708 | aa941b94 | balrog | qemu_get_be32s(f, &s->gpio_level); |
709 | aa941b94 | balrog | qemu_get_be32s(f, &s->gpio_dir); |
710 | aa941b94 | balrog | qemu_get_be32s(f, &s->prev_level); |
711 | aa941b94 | balrog | qemu_get_be16s(f, &s->mcr); |
712 | aa941b94 | balrog | qemu_get_be16s(f, &s->cdr); |
713 | aa941b94 | balrog | qemu_get_be16s(f, &s->ccr); |
714 | aa941b94 | balrog | qemu_get_be16s(f, &s->irr); |
715 | aa941b94 | balrog | qemu_get_be16s(f, &s->imr); |
716 | aa941b94 | balrog | qemu_get_be16s(f, &s->isr); |
717 | aa941b94 | balrog | qemu_get_be16s(f, &s->gprr); |
718 | aa941b94 | balrog | |
719 | aa941b94 | balrog | return 0; |
720 | aa941b94 | balrog | } |
721 | aa941b94 | balrog | |
722 | b00052e4 | balrog | static struct scoop_info_s *spitz_scoop_init(struct pxa2xx_state_s *cpu, |
723 | b00052e4 | balrog | int count) {
|
724 | b00052e4 | balrog | int iomemtype;
|
725 | b00052e4 | balrog | struct scoop_info_s *s;
|
726 | b00052e4 | balrog | |
727 | b00052e4 | balrog | s = (struct scoop_info_s *)
|
728 | b00052e4 | balrog | qemu_mallocz(sizeof(struct scoop_info_s) * 2); |
729 | b00052e4 | balrog | memset(s, 0, sizeof(struct scoop_info_s) * count); |
730 | b00052e4 | balrog | s[0].target_base = 0x10800000; |
731 | b00052e4 | balrog | s[1].target_base = 0x08800040; |
732 | b00052e4 | balrog | |
733 | b00052e4 | balrog | /* Ready */
|
734 | b00052e4 | balrog | s[0].status = 0x02; |
735 | b00052e4 | balrog | s[1].status = 0x02; |
736 | b00052e4 | balrog | |
737 | 38641a52 | balrog | s[0].in = qemu_allocate_irqs(scoop_gpio_set, &s[0], 16); |
738 | b00052e4 | balrog | iomemtype = cpu_register_io_memory(0, scoop_readfn,
|
739 | b00052e4 | balrog | scoop_writefn, &s[0]);
|
740 | 187337f8 | pbrook | cpu_register_physical_memory(s[0].target_base, 0x1000, iomemtype); |
741 | aa941b94 | balrog | register_savevm("scoop", 0, 0, scoop_save, scoop_load, &s[0]); |
742 | b00052e4 | balrog | |
743 | b00052e4 | balrog | if (count < 2) |
744 | b00052e4 | balrog | return s;
|
745 | b00052e4 | balrog | |
746 | 38641a52 | balrog | s[1].in = qemu_allocate_irqs(scoop_gpio_set, &s[1], 16); |
747 | b00052e4 | balrog | iomemtype = cpu_register_io_memory(0, scoop_readfn,
|
748 | b00052e4 | balrog | scoop_writefn, &s[1]);
|
749 | 187337f8 | pbrook | cpu_register_physical_memory(s[1].target_base, 0x1000, iomemtype); |
750 | aa941b94 | balrog | register_savevm("scoop", 1, 0, scoop_save, scoop_load, &s[1]); |
751 | b00052e4 | balrog | |
752 | b00052e4 | balrog | return s;
|
753 | b00052e4 | balrog | } |
754 | b00052e4 | balrog | |
755 | b00052e4 | balrog | /* LCD backlight controller */
|
756 | b00052e4 | balrog | |
757 | b00052e4 | balrog | #define LCDTG_RESCTL 0x00 |
758 | b00052e4 | balrog | #define LCDTG_PHACTRL 0x01 |
759 | b00052e4 | balrog | #define LCDTG_DUTYCTRL 0x02 |
760 | b00052e4 | balrog | #define LCDTG_POWERREG0 0x03 |
761 | b00052e4 | balrog | #define LCDTG_POWERREG1 0x04 |
762 | b00052e4 | balrog | #define LCDTG_GPOR3 0x05 |
763 | b00052e4 | balrog | #define LCDTG_PICTRL 0x06 |
764 | b00052e4 | balrog | #define LCDTG_POLCTRL 0x07 |
765 | b00052e4 | balrog | |
766 | b00052e4 | balrog | static int bl_intensity, bl_power; |
767 | b00052e4 | balrog | |
768 | b00052e4 | balrog | static void spitz_bl_update(struct pxa2xx_state_s *s) |
769 | b00052e4 | balrog | { |
770 | b00052e4 | balrog | if (bl_power && bl_intensity)
|
771 | b00052e4 | balrog | spitz_printf("LCD Backlight now at %i/63\n", bl_intensity);
|
772 | b00052e4 | balrog | else
|
773 | b00052e4 | balrog | spitz_printf("LCD Backlight now off\n");
|
774 | b00052e4 | balrog | } |
775 | b00052e4 | balrog | |
776 | 38641a52 | balrog | static inline void spitz_bl_bit5(void *opaque, int line, int level) |
777 | b00052e4 | balrog | { |
778 | b00052e4 | balrog | int prev = bl_intensity;
|
779 | b00052e4 | balrog | |
780 | b00052e4 | balrog | if (level)
|
781 | b00052e4 | balrog | bl_intensity &= ~0x20;
|
782 | b00052e4 | balrog | else
|
783 | b00052e4 | balrog | bl_intensity |= 0x20;
|
784 | b00052e4 | balrog | |
785 | b00052e4 | balrog | if (bl_power && prev != bl_intensity)
|
786 | b00052e4 | balrog | spitz_bl_update((struct pxa2xx_state_s *) opaque);
|
787 | b00052e4 | balrog | } |
788 | b00052e4 | balrog | |
789 | 38641a52 | balrog | static inline void spitz_bl_power(void *opaque, int line, int level) |
790 | b00052e4 | balrog | { |
791 | b00052e4 | balrog | bl_power = !!level; |
792 | b00052e4 | balrog | spitz_bl_update((struct pxa2xx_state_s *) opaque);
|
793 | b00052e4 | balrog | } |
794 | b00052e4 | balrog | |
795 | b00052e4 | balrog | static void spitz_lcdtg_dac_put(void *opaque, uint8_t cmd) |
796 | b00052e4 | balrog | { |
797 | b00052e4 | balrog | int addr, value;
|
798 | b00052e4 | balrog | addr = cmd >> 5;
|
799 | b00052e4 | balrog | value = cmd & 0x1f;
|
800 | b00052e4 | balrog | |
801 | b00052e4 | balrog | switch (addr) {
|
802 | b00052e4 | balrog | case LCDTG_RESCTL:
|
803 | b00052e4 | balrog | if (value)
|
804 | b00052e4 | balrog | spitz_printf("LCD in QVGA mode\n");
|
805 | b00052e4 | balrog | else
|
806 | b00052e4 | balrog | spitz_printf("LCD in VGA mode\n");
|
807 | b00052e4 | balrog | break;
|
808 | b00052e4 | balrog | |
809 | b00052e4 | balrog | case LCDTG_DUTYCTRL:
|
810 | b00052e4 | balrog | bl_intensity &= ~0x1f;
|
811 | b00052e4 | balrog | bl_intensity |= value; |
812 | b00052e4 | balrog | if (bl_power)
|
813 | b00052e4 | balrog | spitz_bl_update((struct pxa2xx_state_s *) opaque);
|
814 | b00052e4 | balrog | break;
|
815 | b00052e4 | balrog | |
816 | b00052e4 | balrog | case LCDTG_POWERREG0:
|
817 | b00052e4 | balrog | /* Set common voltage to M62332FP */
|
818 | b00052e4 | balrog | break;
|
819 | b00052e4 | balrog | } |
820 | b00052e4 | balrog | } |
821 | b00052e4 | balrog | |
822 | b00052e4 | balrog | /* SSP devices */
|
823 | b00052e4 | balrog | |
824 | b00052e4 | balrog | #define CORGI_SSP_PORT 2 |
825 | b00052e4 | balrog | |
826 | b00052e4 | balrog | #define SPITZ_GPIO_LCDCON_CS 53 |
827 | b00052e4 | balrog | #define SPITZ_GPIO_ADS7846_CS 14 |
828 | b00052e4 | balrog | #define SPITZ_GPIO_MAX1111_CS 20 |
829 | b00052e4 | balrog | #define SPITZ_GPIO_TP_INT 11 |
830 | b00052e4 | balrog | |
831 | b00052e4 | balrog | static int lcd_en, ads_en, max_en; |
832 | b00052e4 | balrog | static struct max111x_s *max1111; |
833 | b00052e4 | balrog | static struct ads7846_state_s *ads7846; |
834 | b00052e4 | balrog | |
835 | b00052e4 | balrog | /* "Demux" the signal based on current chipselect */
|
836 | b00052e4 | balrog | static uint32_t corgi_ssp_read(void *opaque) |
837 | b00052e4 | balrog | { |
838 | b00052e4 | balrog | if (lcd_en)
|
839 | b00052e4 | balrog | return 0; |
840 | b00052e4 | balrog | if (ads_en)
|
841 | b00052e4 | balrog | return ads7846_read(ads7846);
|
842 | b00052e4 | balrog | if (max_en)
|
843 | b00052e4 | balrog | return max111x_read(max1111);
|
844 | b00052e4 | balrog | return 0; |
845 | b00052e4 | balrog | } |
846 | b00052e4 | balrog | |
847 | b00052e4 | balrog | static void corgi_ssp_write(void *opaque, uint32_t value) |
848 | b00052e4 | balrog | { |
849 | b00052e4 | balrog | if (lcd_en)
|
850 | b00052e4 | balrog | spitz_lcdtg_dac_put(opaque, value); |
851 | b00052e4 | balrog | if (ads_en)
|
852 | b00052e4 | balrog | ads7846_write(ads7846, value); |
853 | b00052e4 | balrog | if (max_en)
|
854 | b00052e4 | balrog | max111x_write(max1111, value); |
855 | b00052e4 | balrog | } |
856 | b00052e4 | balrog | |
857 | 38641a52 | balrog | static void corgi_ssp_gpio_cs(void *opaque, int line, int level) |
858 | b00052e4 | balrog | { |
859 | 38641a52 | balrog | switch (line) {
|
860 | 38641a52 | balrog | case 0: |
861 | b00052e4 | balrog | lcd_en = !level; |
862 | 38641a52 | balrog | break;
|
863 | 38641a52 | balrog | case 1: |
864 | b00052e4 | balrog | ads_en = !level; |
865 | 38641a52 | balrog | break;
|
866 | 38641a52 | balrog | case 2: |
867 | b00052e4 | balrog | max_en = !level; |
868 | 38641a52 | balrog | break;
|
869 | 38641a52 | balrog | } |
870 | b00052e4 | balrog | } |
871 | b00052e4 | balrog | |
872 | b00052e4 | balrog | #define MAX1111_BATT_VOLT 1 |
873 | b00052e4 | balrog | #define MAX1111_BATT_TEMP 2 |
874 | b00052e4 | balrog | #define MAX1111_ACIN_VOLT 3 |
875 | b00052e4 | balrog | |
876 | b00052e4 | balrog | #define SPITZ_BATTERY_TEMP 0xe0 /* About 2.9V */ |
877 | b00052e4 | balrog | #define SPITZ_BATTERY_VOLT 0xd0 /* About 4.0V */ |
878 | b00052e4 | balrog | #define SPITZ_CHARGEON_ACIN 0x80 /* About 5.0V */ |
879 | b00052e4 | balrog | |
880 | 38641a52 | balrog | static void spitz_adc_temp_on(void *opaque, int line, int level) |
881 | b00052e4 | balrog | { |
882 | b00052e4 | balrog | if (!max1111)
|
883 | b00052e4 | balrog | return;
|
884 | b00052e4 | balrog | |
885 | b00052e4 | balrog | if (level)
|
886 | b00052e4 | balrog | max111x_set_input(max1111, MAX1111_BATT_TEMP, SPITZ_BATTERY_TEMP); |
887 | b00052e4 | balrog | else
|
888 | b00052e4 | balrog | max111x_set_input(max1111, MAX1111_BATT_TEMP, 0);
|
889 | b00052e4 | balrog | } |
890 | b00052e4 | balrog | |
891 | aa941b94 | balrog | static void spitz_ssp_save(QEMUFile *f, void *opaque) |
892 | aa941b94 | balrog | { |
893 | aa941b94 | balrog | qemu_put_be32(f, lcd_en); |
894 | aa941b94 | balrog | qemu_put_be32(f, ads_en); |
895 | aa941b94 | balrog | qemu_put_be32(f, max_en); |
896 | aa941b94 | balrog | qemu_put_be32(f, bl_intensity); |
897 | aa941b94 | balrog | qemu_put_be32(f, bl_power); |
898 | aa941b94 | balrog | } |
899 | aa941b94 | balrog | |
900 | aa941b94 | balrog | static int spitz_ssp_load(QEMUFile *f, void *opaque, int version_id) |
901 | aa941b94 | balrog | { |
902 | aa941b94 | balrog | lcd_en = qemu_get_be32(f); |
903 | aa941b94 | balrog | ads_en = qemu_get_be32(f); |
904 | aa941b94 | balrog | max_en = qemu_get_be32(f); |
905 | aa941b94 | balrog | bl_intensity = qemu_get_be32(f); |
906 | aa941b94 | balrog | bl_power = qemu_get_be32(f); |
907 | aa941b94 | balrog | |
908 | aa941b94 | balrog | return 0; |
909 | aa941b94 | balrog | } |
910 | aa941b94 | balrog | |
911 | b00052e4 | balrog | static void spitz_ssp_attach(struct pxa2xx_state_s *cpu) |
912 | b00052e4 | balrog | { |
913 | 38641a52 | balrog | qemu_irq *chipselects; |
914 | 38641a52 | balrog | |
915 | b00052e4 | balrog | lcd_en = ads_en = max_en = 0;
|
916 | b00052e4 | balrog | |
917 | 38641a52 | balrog | ads7846 = ads7846_init(pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_TP_INT]); |
918 | b00052e4 | balrog | |
919 | b00052e4 | balrog | max1111 = max1111_init(0);
|
920 | b00052e4 | balrog | max111x_set_input(max1111, MAX1111_BATT_VOLT, SPITZ_BATTERY_VOLT); |
921 | b00052e4 | balrog | max111x_set_input(max1111, MAX1111_BATT_TEMP, 0);
|
922 | b00052e4 | balrog | max111x_set_input(max1111, MAX1111_ACIN_VOLT, SPITZ_CHARGEON_ACIN); |
923 | b00052e4 | balrog | |
924 | b00052e4 | balrog | pxa2xx_ssp_attach(cpu->ssp[CORGI_SSP_PORT - 1], corgi_ssp_read,
|
925 | b00052e4 | balrog | corgi_ssp_write, cpu); |
926 | b00052e4 | balrog | |
927 | 38641a52 | balrog | chipselects = qemu_allocate_irqs(corgi_ssp_gpio_cs, cpu, 3);
|
928 | 38641a52 | balrog | pxa2xx_gpio_out_set(cpu->gpio, SPITZ_GPIO_LCDCON_CS, chipselects[0]);
|
929 | 38641a52 | balrog | pxa2xx_gpio_out_set(cpu->gpio, SPITZ_GPIO_ADS7846_CS, chipselects[1]);
|
930 | 38641a52 | balrog | pxa2xx_gpio_out_set(cpu->gpio, SPITZ_GPIO_MAX1111_CS, chipselects[2]);
|
931 | b00052e4 | balrog | |
932 | b00052e4 | balrog | bl_intensity = 0x20;
|
933 | b00052e4 | balrog | bl_power = 0;
|
934 | aa941b94 | balrog | |
935 | aa941b94 | balrog | register_savevm("spitz_ssp", 0, 0, spitz_ssp_save, spitz_ssp_load, cpu); |
936 | b00052e4 | balrog | } |
937 | b00052e4 | balrog | |
938 | b00052e4 | balrog | /* CF Microdrive */
|
939 | b00052e4 | balrog | |
940 | b00052e4 | balrog | static void spitz_microdrive_attach(struct pxa2xx_state_s *cpu) |
941 | b00052e4 | balrog | { |
942 | b00052e4 | balrog | struct pcmcia_card_s *md;
|
943 | e4bcb14c | ths | int index;
|
944 | e4bcb14c | ths | BlockDriverState *bs; |
945 | b00052e4 | balrog | |
946 | e4bcb14c | ths | index = drive_get_index(IF_IDE, 0, 0); |
947 | e4bcb14c | ths | if (index == -1) |
948 | e4bcb14c | ths | return;
|
949 | e4bcb14c | ths | bs = drives_table[index].bdrv; |
950 | e4bcb14c | ths | if (bdrv_is_inserted(bs) && !bdrv_is_removable(bs)) {
|
951 | b00052e4 | balrog | md = dscm1xxxx_init(bs); |
952 | bf5ee248 | balrog | pxa2xx_pcmcia_attach(cpu->pcmcia[1], md);
|
953 | b00052e4 | balrog | } |
954 | b00052e4 | balrog | } |
955 | b00052e4 | balrog | |
956 | adb86c37 | balrog | /* Wm8750 and Max7310 on I2C */
|
957 | adb86c37 | balrog | |
958 | adb86c37 | balrog | #define AKITA_MAX_ADDR 0x18 |
959 | 611d7189 | balrog | #define SPITZ_WM_ADDRL 0x1b |
960 | 611d7189 | balrog | #define SPITZ_WM_ADDRH 0x1a |
961 | adb86c37 | balrog | |
962 | adb86c37 | balrog | #define SPITZ_GPIO_WM 5 |
963 | adb86c37 | balrog | |
964 | adb86c37 | balrog | #ifdef HAS_AUDIO
|
965 | 38641a52 | balrog | static void spitz_wm8750_addr(void *opaque, int line, int level) |
966 | adb86c37 | balrog | { |
967 | adb86c37 | balrog | i2c_slave *wm = (i2c_slave *) opaque; |
968 | adb86c37 | balrog | if (level)
|
969 | adb86c37 | balrog | i2c_set_slave_address(wm, SPITZ_WM_ADDRH); |
970 | adb86c37 | balrog | else
|
971 | adb86c37 | balrog | i2c_set_slave_address(wm, SPITZ_WM_ADDRL); |
972 | adb86c37 | balrog | } |
973 | adb86c37 | balrog | #endif
|
974 | adb86c37 | balrog | |
975 | adb86c37 | balrog | static void spitz_i2c_setup(struct pxa2xx_state_s *cpu) |
976 | adb86c37 | balrog | { |
977 | adb86c37 | balrog | /* Attach the CPU on one end of our I2C bus. */
|
978 | adb86c37 | balrog | i2c_bus *bus = pxa2xx_i2c_bus(cpu->i2c[0]);
|
979 | adb86c37 | balrog | |
980 | adb86c37 | balrog | #ifdef HAS_AUDIO
|
981 | adb86c37 | balrog | AudioState *audio; |
982 | adb86c37 | balrog | i2c_slave *wm; |
983 | adb86c37 | balrog | |
984 | adb86c37 | balrog | audio = AUD_init(); |
985 | adb86c37 | balrog | if (!audio)
|
986 | adb86c37 | balrog | return;
|
987 | adb86c37 | balrog | /* Attach a WM8750 to the bus */
|
988 | adb86c37 | balrog | wm = wm8750_init(bus, audio); |
989 | adb86c37 | balrog | |
990 | 38641a52 | balrog | spitz_wm8750_addr(wm, 0, 0); |
991 | 38641a52 | balrog | pxa2xx_gpio_out_set(cpu->gpio, SPITZ_GPIO_WM, |
992 | 38641a52 | balrog | qemu_allocate_irqs(spitz_wm8750_addr, wm, 1)[0]); |
993 | adb86c37 | balrog | /* .. and to the sound interface. */
|
994 | adb86c37 | balrog | cpu->i2s->opaque = wm; |
995 | adb86c37 | balrog | cpu->i2s->codec_out = wm8750_dac_dat; |
996 | adb86c37 | balrog | cpu->i2s->codec_in = wm8750_adc_dat; |
997 | adb86c37 | balrog | wm8750_data_req_set(wm, cpu->i2s->data_req, cpu->i2s); |
998 | adb86c37 | balrog | #endif
|
999 | adb86c37 | balrog | } |
1000 | adb86c37 | balrog | |
1001 | adb86c37 | balrog | static void spitz_akita_i2c_setup(struct pxa2xx_state_s *cpu) |
1002 | adb86c37 | balrog | { |
1003 | adb86c37 | balrog | /* Attach a Max7310 to Akita I2C bus. */
|
1004 | adb86c37 | balrog | i2c_set_slave_address(max7310_init(pxa2xx_i2c_bus(cpu->i2c[0])),
|
1005 | adb86c37 | balrog | AKITA_MAX_ADDR); |
1006 | adb86c37 | balrog | } |
1007 | adb86c37 | balrog | |
1008 | b00052e4 | balrog | /* Other peripherals */
|
1009 | b00052e4 | balrog | |
1010 | 38641a52 | balrog | static void spitz_out_switch(void *opaque, int line, int level) |
1011 | b00052e4 | balrog | { |
1012 | 38641a52 | balrog | switch (line) {
|
1013 | 38641a52 | balrog | case 0: |
1014 | 38641a52 | balrog | spitz_printf("Charging %s.\n", level ? "off" : "on"); |
1015 | 38641a52 | balrog | break;
|
1016 | 38641a52 | balrog | case 1: |
1017 | 38641a52 | balrog | spitz_printf("Discharging %s.\n", level ? "on" : "off"); |
1018 | 38641a52 | balrog | break;
|
1019 | 38641a52 | balrog | case 2: |
1020 | 38641a52 | balrog | spitz_printf("Green LED %s.\n", level ? "on" : "off"); |
1021 | 38641a52 | balrog | break;
|
1022 | 38641a52 | balrog | case 3: |
1023 | 38641a52 | balrog | spitz_printf("Orange LED %s.\n", level ? "on" : "off"); |
1024 | 38641a52 | balrog | break;
|
1025 | 38641a52 | balrog | case 4: |
1026 | 38641a52 | balrog | spitz_bl_bit5(opaque, line, level); |
1027 | 38641a52 | balrog | break;
|
1028 | 38641a52 | balrog | case 5: |
1029 | 38641a52 | balrog | spitz_bl_power(opaque, line, level); |
1030 | 38641a52 | balrog | break;
|
1031 | 38641a52 | balrog | case 6: |
1032 | 38641a52 | balrog | spitz_adc_temp_on(opaque, line, level); |
1033 | 38641a52 | balrog | break;
|
1034 | 38641a52 | balrog | } |
1035 | b00052e4 | balrog | } |
1036 | b00052e4 | balrog | |
1037 | b00052e4 | balrog | #define SPITZ_SCP_LED_GREEN 1 |
1038 | b00052e4 | balrog | #define SPITZ_SCP_JK_B 2 |
1039 | b00052e4 | balrog | #define SPITZ_SCP_CHRG_ON 3 |
1040 | b00052e4 | balrog | #define SPITZ_SCP_MUTE_L 4 |
1041 | b00052e4 | balrog | #define SPITZ_SCP_MUTE_R 5 |
1042 | b00052e4 | balrog | #define SPITZ_SCP_CF_POWER 6 |
1043 | b00052e4 | balrog | #define SPITZ_SCP_LED_ORANGE 7 |
1044 | b00052e4 | balrog | #define SPITZ_SCP_JK_A 8 |
1045 | b00052e4 | balrog | #define SPITZ_SCP_ADC_TEMP_ON 9 |
1046 | b00052e4 | balrog | #define SPITZ_SCP2_IR_ON 1 |
1047 | b00052e4 | balrog | #define SPITZ_SCP2_AKIN_PULLUP 2 |
1048 | b00052e4 | balrog | #define SPITZ_SCP2_BACKLIGHT_CONT 7 |
1049 | b00052e4 | balrog | #define SPITZ_SCP2_BACKLIGHT_ON 8 |
1050 | b00052e4 | balrog | #define SPITZ_SCP2_MIC_BIAS 9 |
1051 | b00052e4 | balrog | |
1052 | b00052e4 | balrog | static void spitz_scoop_gpio_setup(struct pxa2xx_state_s *cpu, |
1053 | b00052e4 | balrog | struct scoop_info_s *scp, int num) |
1054 | b00052e4 | balrog | { |
1055 | 38641a52 | balrog | qemu_irq *outsignals = qemu_allocate_irqs(spitz_out_switch, cpu, 8);
|
1056 | 38641a52 | balrog | |
1057 | 38641a52 | balrog | scoop_gpio_out_set(&scp[0], SPITZ_SCP_CHRG_ON, outsignals[0]); |
1058 | 38641a52 | balrog | scoop_gpio_out_set(&scp[0], SPITZ_SCP_JK_B, outsignals[1]); |
1059 | 38641a52 | balrog | scoop_gpio_out_set(&scp[0], SPITZ_SCP_LED_GREEN, outsignals[2]); |
1060 | 38641a52 | balrog | scoop_gpio_out_set(&scp[0], SPITZ_SCP_LED_ORANGE, outsignals[3]); |
1061 | b00052e4 | balrog | |
1062 | b00052e4 | balrog | if (num >= 2) { |
1063 | 38641a52 | balrog | scoop_gpio_out_set(&scp[1], SPITZ_SCP2_BACKLIGHT_CONT, outsignals[4]); |
1064 | 38641a52 | balrog | scoop_gpio_out_set(&scp[1], SPITZ_SCP2_BACKLIGHT_ON, outsignals[5]); |
1065 | b00052e4 | balrog | } |
1066 | b00052e4 | balrog | |
1067 | 38641a52 | balrog | scoop_gpio_out_set(&scp[0], SPITZ_SCP_ADC_TEMP_ON, outsignals[6]); |
1068 | b00052e4 | balrog | } |
1069 | b00052e4 | balrog | |
1070 | b00052e4 | balrog | #define SPITZ_GPIO_HSYNC 22 |
1071 | b00052e4 | balrog | #define SPITZ_GPIO_SD_DETECT 9 |
1072 | b00052e4 | balrog | #define SPITZ_GPIO_SD_WP 81 |
1073 | b00052e4 | balrog | #define SPITZ_GPIO_ON_RESET 89 |
1074 | b00052e4 | balrog | #define SPITZ_GPIO_BAT_COVER 90 |
1075 | b00052e4 | balrog | #define SPITZ_GPIO_CF1_IRQ 105 |
1076 | b00052e4 | balrog | #define SPITZ_GPIO_CF1_CD 94 |
1077 | b00052e4 | balrog | #define SPITZ_GPIO_CF2_IRQ 106 |
1078 | b00052e4 | balrog | #define SPITZ_GPIO_CF2_CD 93 |
1079 | b00052e4 | balrog | |
1080 | 38641a52 | balrog | static int spitz_hsync; |
1081 | b00052e4 | balrog | |
1082 | 38641a52 | balrog | static void spitz_lcd_hsync_handler(void *opaque, int line, int level) |
1083 | b00052e4 | balrog | { |
1084 | b00052e4 | balrog | struct pxa2xx_state_s *cpu = (struct pxa2xx_state_s *) opaque; |
1085 | 38641a52 | balrog | qemu_set_irq(pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_HSYNC], spitz_hsync); |
1086 | b00052e4 | balrog | spitz_hsync ^= 1;
|
1087 | b00052e4 | balrog | } |
1088 | b00052e4 | balrog | |
1089 | b00052e4 | balrog | static void spitz_gpio_setup(struct pxa2xx_state_s *cpu, int slots) |
1090 | b00052e4 | balrog | { |
1091 | 38641a52 | balrog | qemu_irq lcd_hsync; |
1092 | b00052e4 | balrog | /*
|
1093 | b00052e4 | balrog | * Bad hack: We toggle the LCD hsync GPIO on every GPIO status
|
1094 | b00052e4 | balrog | * read to satisfy broken guests that poll-wait for hsync.
|
1095 | b00052e4 | balrog | * Simulating a real hsync event would be less practical and
|
1096 | b00052e4 | balrog | * wouldn't guarantee that a guest ever exits the loop.
|
1097 | b00052e4 | balrog | */
|
1098 | b00052e4 | balrog | spitz_hsync = 0;
|
1099 | 38641a52 | balrog | lcd_hsync = qemu_allocate_irqs(spitz_lcd_hsync_handler, cpu, 1)[0]; |
1100 | 38641a52 | balrog | pxa2xx_gpio_read_notifier(cpu->gpio, lcd_hsync); |
1101 | 38641a52 | balrog | pxa2xx_lcd_vsync_notifier(cpu->lcd, lcd_hsync); |
1102 | b00052e4 | balrog | |
1103 | b00052e4 | balrog | /* MMC/SD host */
|
1104 | 02ce600c | balrog | pxa2xx_mmci_handlers(cpu->mmc, |
1105 | 02ce600c | balrog | pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_SD_WP], |
1106 | 02ce600c | balrog | pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_SD_DETECT]); |
1107 | b00052e4 | balrog | |
1108 | b00052e4 | balrog | /* Battery lock always closed */
|
1109 | 38641a52 | balrog | qemu_irq_raise(pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_BAT_COVER]); |
1110 | b00052e4 | balrog | |
1111 | b00052e4 | balrog | /* Handle reset */
|
1112 | 38641a52 | balrog | pxa2xx_gpio_out_set(cpu->gpio, SPITZ_GPIO_ON_RESET, cpu->reset); |
1113 | b00052e4 | balrog | |
1114 | b00052e4 | balrog | /* PCMCIA signals: card's IRQ and Card-Detect */
|
1115 | b00052e4 | balrog | if (slots >= 1) |
1116 | 38641a52 | balrog | pxa2xx_pcmcia_set_irq_cb(cpu->pcmcia[0],
|
1117 | 38641a52 | balrog | pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_CF1_IRQ], |
1118 | 38641a52 | balrog | pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_CF1_CD]); |
1119 | b00052e4 | balrog | if (slots >= 2) |
1120 | 38641a52 | balrog | pxa2xx_pcmcia_set_irq_cb(cpu->pcmcia[1],
|
1121 | 38641a52 | balrog | pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_CF2_IRQ], |
1122 | 38641a52 | balrog | pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_CF2_CD]); |
1123 | b00052e4 | balrog | |
1124 | b00052e4 | balrog | /* Initialise the screen rotation related signals */
|
1125 | b00052e4 | balrog | spitz_gpio_invert[3] = 0; /* Always open */ |
1126 | b00052e4 | balrog | if (graphic_rotate) { /* Tablet mode */ |
1127 | b00052e4 | balrog | spitz_gpio_invert[4] = 0; |
1128 | b00052e4 | balrog | } else { /* Portrait mode */ |
1129 | b00052e4 | balrog | spitz_gpio_invert[4] = 1; |
1130 | b00052e4 | balrog | } |
1131 | 38641a52 | balrog | qemu_set_irq(pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_SWA], |
1132 | 38641a52 | balrog | spitz_gpio_invert[3]);
|
1133 | 38641a52 | balrog | qemu_set_irq(pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_SWB], |
1134 | 38641a52 | balrog | spitz_gpio_invert[4]);
|
1135 | b00052e4 | balrog | } |
1136 | b00052e4 | balrog | |
1137 | b00052e4 | balrog | /* Write the bootloader parameters memory area. */
|
1138 | b00052e4 | balrog | |
1139 | b00052e4 | balrog | #define MAGIC_CHG(a, b, c, d) ((d << 24) | (c << 16) | (b << 8) | a) |
1140 | b00052e4 | balrog | |
1141 | b00052e4 | balrog | struct __attribute__ ((__packed__)) sl_param_info {
|
1142 | b00052e4 | balrog | uint32_t comadj_keyword; |
1143 | b00052e4 | balrog | int32_t comadj; |
1144 | b00052e4 | balrog | |
1145 | b00052e4 | balrog | uint32_t uuid_keyword; |
1146 | b00052e4 | balrog | char uuid[16]; |
1147 | b00052e4 | balrog | |
1148 | b00052e4 | balrog | uint32_t touch_keyword; |
1149 | b00052e4 | balrog | int32_t touch_xp; |
1150 | b00052e4 | balrog | int32_t touch_yp; |
1151 | b00052e4 | balrog | int32_t touch_xd; |
1152 | b00052e4 | balrog | int32_t touch_yd; |
1153 | b00052e4 | balrog | |
1154 | b00052e4 | balrog | uint32_t adadj_keyword; |
1155 | b00052e4 | balrog | int32_t adadj; |
1156 | b00052e4 | balrog | |
1157 | b00052e4 | balrog | uint32_t phad_keyword; |
1158 | b00052e4 | balrog | int32_t phadadj; |
1159 | b00052e4 | balrog | } spitz_bootparam = { |
1160 | b00052e4 | balrog | .comadj_keyword = MAGIC_CHG('C', 'M', 'A', 'D'), |
1161 | b00052e4 | balrog | .comadj = 125,
|
1162 | b00052e4 | balrog | .uuid_keyword = MAGIC_CHG('U', 'U', 'I', 'D'), |
1163 | b00052e4 | balrog | .uuid = { -1 },
|
1164 | b00052e4 | balrog | .touch_keyword = MAGIC_CHG('T', 'U', 'C', 'H'), |
1165 | b00052e4 | balrog | .touch_xp = -1,
|
1166 | b00052e4 | balrog | .adadj_keyword = MAGIC_CHG('B', 'V', 'A', 'D'), |
1167 | b00052e4 | balrog | .adadj = -1,
|
1168 | b00052e4 | balrog | .phad_keyword = MAGIC_CHG('P', 'H', 'A', 'D'), |
1169 | b00052e4 | balrog | .phadadj = 0x01,
|
1170 | b00052e4 | balrog | }; |
1171 | b00052e4 | balrog | |
1172 | b00052e4 | balrog | static void sl_bootparam_write(uint32_t ptr) |
1173 | b00052e4 | balrog | { |
1174 | b00052e4 | balrog | memcpy(phys_ram_base + ptr, &spitz_bootparam, |
1175 | b00052e4 | balrog | sizeof(struct sl_param_info)); |
1176 | b00052e4 | balrog | } |
1177 | b00052e4 | balrog | |
1178 | b00052e4 | balrog | #define SL_PXA_PARAM_BASE 0xa0000a00 |
1179 | b00052e4 | balrog | |
1180 | b00052e4 | balrog | /* Board init. */
|
1181 | b00052e4 | balrog | enum spitz_model_e { spitz, akita, borzoi, terrier };
|
1182 | b00052e4 | balrog | |
1183 | f93eb9ff | balrog | static struct arm_boot_info spitz_binfo = { |
1184 | f93eb9ff | balrog | .loader_start = PXA2XX_SDRAM_BASE, |
1185 | f93eb9ff | balrog | .ram_size = 0x04000000,
|
1186 | f93eb9ff | balrog | }; |
1187 | f93eb9ff | balrog | |
1188 | 967032c3 | aurel32 | static void spitz_common_init(ram_addr_t ram_size, int vga_ram_size, |
1189 | b00052e4 | balrog | DisplayState *ds, const char *kernel_filename, |
1190 | b00052e4 | balrog | const char *kernel_cmdline, const char *initrd_filename, |
1191 | 4207117c | balrog | const char *cpu_model, enum spitz_model_e model, int arm_id) |
1192 | b00052e4 | balrog | { |
1193 | f93eb9ff | balrog | uint32_t spitz_ram = spitz_binfo.ram_size; |
1194 | b00052e4 | balrog | uint32_t spitz_rom = 0x00800000;
|
1195 | b00052e4 | balrog | struct pxa2xx_state_s *cpu;
|
1196 | b00052e4 | balrog | struct scoop_info_s *scp;
|
1197 | b00052e4 | balrog | |
1198 | 4207117c | balrog | if (!cpu_model)
|
1199 | 4207117c | balrog | cpu_model = (model == terrier) ? "pxa270-c5" : "pxa270-c0"; |
1200 | b00052e4 | balrog | |
1201 | d95b2f8d | balrog | /* Setup CPU & memory */
|
1202 | a07dec22 | balrog | if (ram_size < spitz_ram + spitz_rom + PXA2XX_INTERNAL_SIZE) {
|
1203 | b00052e4 | balrog | fprintf(stderr, "This platform requires %i bytes of memory\n",
|
1204 | a07dec22 | balrog | spitz_ram + spitz_rom + PXA2XX_INTERNAL_SIZE); |
1205 | b00052e4 | balrog | exit(1);
|
1206 | b00052e4 | balrog | } |
1207 | d95b2f8d | balrog | cpu = pxa270_init(spitz_ram, ds, cpu_model); |
1208 | b00052e4 | balrog | |
1209 | b00052e4 | balrog | sl_flash_register(cpu, (model == spitz) ? FLASH_128M : FLASH_1024M); |
1210 | b00052e4 | balrog | |
1211 | d95b2f8d | balrog | cpu_register_physical_memory(0, spitz_rom,
|
1212 | d95b2f8d | balrog | qemu_ram_alloc(spitz_rom) | IO_MEM_ROM); |
1213 | b00052e4 | balrog | |
1214 | b00052e4 | balrog | /* Setup peripherals */
|
1215 | b00052e4 | balrog | spitz_keyboard_register(cpu); |
1216 | b00052e4 | balrog | |
1217 | b00052e4 | balrog | spitz_ssp_attach(cpu); |
1218 | b00052e4 | balrog | |
1219 | b00052e4 | balrog | scp = spitz_scoop_init(cpu, (model == akita) ? 1 : 2); |
1220 | b00052e4 | balrog | |
1221 | b00052e4 | balrog | spitz_scoop_gpio_setup(cpu, scp, (model == akita) ? 1 : 2); |
1222 | b00052e4 | balrog | |
1223 | b00052e4 | balrog | spitz_gpio_setup(cpu, (model == akita) ? 1 : 2); |
1224 | b00052e4 | balrog | |
1225 | adb86c37 | balrog | spitz_i2c_setup(cpu); |
1226 | adb86c37 | balrog | |
1227 | adb86c37 | balrog | if (model == akita)
|
1228 | adb86c37 | balrog | spitz_akita_i2c_setup(cpu); |
1229 | adb86c37 | balrog | |
1230 | b00052e4 | balrog | if (model == terrier)
|
1231 | bf5ee248 | balrog | /* A 6.0 GB microdrive is permanently sitting in CF slot 1. */
|
1232 | b00052e4 | balrog | spitz_microdrive_attach(cpu); |
1233 | b00052e4 | balrog | else if (model != akita) |
1234 | bf5ee248 | balrog | /* A 4.0 GB microdrive is permanently sitting in CF slot 1. */
|
1235 | b00052e4 | balrog | spitz_microdrive_attach(cpu); |
1236 | b00052e4 | balrog | |
1237 | b00052e4 | balrog | /* Setup initial (reset) machine state */
|
1238 | f93eb9ff | balrog | cpu->env->regs[15] = spitz_binfo.loader_start;
|
1239 | b00052e4 | balrog | |
1240 | f93eb9ff | balrog | spitz_binfo.kernel_filename = kernel_filename; |
1241 | f93eb9ff | balrog | spitz_binfo.kernel_cmdline = kernel_cmdline; |
1242 | f93eb9ff | balrog | spitz_binfo.initrd_filename = initrd_filename; |
1243 | f93eb9ff | balrog | spitz_binfo.board_id = arm_id; |
1244 | f93eb9ff | balrog | arm_load_kernel(cpu->env, &spitz_binfo); |
1245 | d95b2f8d | balrog | sl_bootparam_write(SL_PXA_PARAM_BASE - PXA2XX_SDRAM_BASE); |
1246 | b00052e4 | balrog | } |
1247 | b00052e4 | balrog | |
1248 | 967032c3 | aurel32 | static void spitz_init(ram_addr_t ram_size, int vga_ram_size, |
1249 | 6ac0e82d | balrog | const char *boot_device, DisplayState *ds, |
1250 | b00052e4 | balrog | const char *kernel_filename, const char *kernel_cmdline, |
1251 | b00052e4 | balrog | const char *initrd_filename, const char *cpu_model) |
1252 | b00052e4 | balrog | { |
1253 | b00052e4 | balrog | spitz_common_init(ram_size, vga_ram_size, ds, kernel_filename, |
1254 | 4207117c | balrog | kernel_cmdline, initrd_filename, cpu_model, spitz, 0x2c9);
|
1255 | b00052e4 | balrog | } |
1256 | b00052e4 | balrog | |
1257 | 967032c3 | aurel32 | static void borzoi_init(ram_addr_t ram_size, int vga_ram_size, |
1258 | 6ac0e82d | balrog | const char *boot_device, DisplayState *ds, |
1259 | b00052e4 | balrog | const char *kernel_filename, const char *kernel_cmdline, |
1260 | b00052e4 | balrog | const char *initrd_filename, const char *cpu_model) |
1261 | b00052e4 | balrog | { |
1262 | b00052e4 | balrog | spitz_common_init(ram_size, vga_ram_size, ds, kernel_filename, |
1263 | 4207117c | balrog | kernel_cmdline, initrd_filename, cpu_model, borzoi, 0x33f);
|
1264 | b00052e4 | balrog | } |
1265 | b00052e4 | balrog | |
1266 | 967032c3 | aurel32 | static void akita_init(ram_addr_t ram_size, int vga_ram_size, |
1267 | 6ac0e82d | balrog | const char *boot_device, DisplayState *ds, |
1268 | b00052e4 | balrog | const char *kernel_filename, const char *kernel_cmdline, |
1269 | b00052e4 | balrog | const char *initrd_filename, const char *cpu_model) |
1270 | b00052e4 | balrog | { |
1271 | b00052e4 | balrog | spitz_common_init(ram_size, vga_ram_size, ds, kernel_filename, |
1272 | 4207117c | balrog | kernel_cmdline, initrd_filename, cpu_model, akita, 0x2e8);
|
1273 | b00052e4 | balrog | } |
1274 | b00052e4 | balrog | |
1275 | 967032c3 | aurel32 | static void terrier_init(ram_addr_t ram_size, int vga_ram_size, |
1276 | 6ac0e82d | balrog | const char *boot_device, DisplayState *ds, |
1277 | b00052e4 | balrog | const char *kernel_filename, const char *kernel_cmdline, |
1278 | b00052e4 | balrog | const char *initrd_filename, const char *cpu_model) |
1279 | b00052e4 | balrog | { |
1280 | b00052e4 | balrog | spitz_common_init(ram_size, vga_ram_size, ds, kernel_filename, |
1281 | 4207117c | balrog | kernel_cmdline, initrd_filename, cpu_model, terrier, 0x33f);
|
1282 | b00052e4 | balrog | } |
1283 | b00052e4 | balrog | |
1284 | b00052e4 | balrog | QEMUMachine akitapda_machine = { |
1285 | b00052e4 | balrog | "akita",
|
1286 | b00052e4 | balrog | "Akita PDA (PXA270)",
|
1287 | b00052e4 | balrog | akita_init, |
1288 | b00052e4 | balrog | }; |
1289 | b00052e4 | balrog | |
1290 | b00052e4 | balrog | QEMUMachine spitzpda_machine = { |
1291 | b00052e4 | balrog | "spitz",
|
1292 | b00052e4 | balrog | "Spitz PDA (PXA270)",
|
1293 | b00052e4 | balrog | spitz_init, |
1294 | b00052e4 | balrog | }; |
1295 | b00052e4 | balrog | |
1296 | b00052e4 | balrog | QEMUMachine borzoipda_machine = { |
1297 | b00052e4 | balrog | "borzoi",
|
1298 | b00052e4 | balrog | "Borzoi PDA (PXA270)",
|
1299 | b00052e4 | balrog | borzoi_init, |
1300 | b00052e4 | balrog | }; |
1301 | b00052e4 | balrog | |
1302 | b00052e4 | balrog | QEMUMachine terrierpda_machine = { |
1303 | b00052e4 | balrog | "terrier",
|
1304 | b00052e4 | balrog | "Terrier PDA (PXA270)",
|
1305 | b00052e4 | balrog | terrier_init, |
1306 | b00052e4 | balrog | }; |