Revision 968d683c hw/isa_mmio.c
| b/hw/isa_mmio.c | ||
|---|---|---|
| 31 | 31 |
cpu_outb(addr & IOPORTS_MASK, val); |
| 32 | 32 |
} |
| 33 | 33 |
|
| 34 |
static void isa_mmio_writew_be(void *opaque, target_phys_addr_t addr,
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| 34 |
static void isa_mmio_writew(void *opaque, target_phys_addr_t addr, |
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| 35 | 35 |
uint32_t val) |
| 36 | 36 |
{
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val = bswap16(val); |
|
| 38 | 37 |
cpu_outw(addr & IOPORTS_MASK, val); |
| 39 | 38 |
} |
| 40 | 39 |
|
| 41 |
static void isa_mmio_writew_le(void *opaque, target_phys_addr_t addr, |
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uint32_t val) |
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{
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cpu_outw(addr & IOPORTS_MASK, val); |
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} |
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|
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static void isa_mmio_writel_be(void *opaque, target_phys_addr_t addr, |
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uint32_t val) |
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{
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val = bswap32(val); |
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cpu_outl(addr & IOPORTS_MASK, val); |
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} |
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static void isa_mmio_writel_le(void *opaque, target_phys_addr_t addr, |
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static void isa_mmio_writel(void *opaque, target_phys_addr_t addr, |
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| 55 | 41 |
uint32_t val) |
| 56 | 42 |
{
|
| 57 | 43 |
cpu_outl(addr & IOPORTS_MASK, val); |
| ... | ... | |
| 59 | 45 |
|
| 60 | 46 |
static uint32_t isa_mmio_readb (void *opaque, target_phys_addr_t addr) |
| 61 | 47 |
{
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uint32_t val; |
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val = cpu_inb(addr & IOPORTS_MASK); |
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return val; |
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return cpu_inb(addr & IOPORTS_MASK); |
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| 66 | 49 |
} |
| 67 | 50 |
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| 68 |
static uint32_t isa_mmio_readw_be(void *opaque, target_phys_addr_t addr)
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static uint32_t isa_mmio_readw(void *opaque, target_phys_addr_t addr) |
|
| 69 | 52 |
{
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uint32_t val; |
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val = cpu_inw(addr & IOPORTS_MASK); |
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val = bswap16(val); |
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return val; |
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return cpu_inw(addr & IOPORTS_MASK); |
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| 75 | 54 |
} |
| 76 | 55 |
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static uint32_t isa_mmio_readw_le(void *opaque, target_phys_addr_t addr)
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static uint32_t isa_mmio_readl(void *opaque, target_phys_addr_t addr)
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| 78 | 57 |
{
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uint32_t val; |
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val = cpu_inw(addr & IOPORTS_MASK); |
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return val; |
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return cpu_inl(addr & IOPORTS_MASK); |
|
| 83 | 59 |
} |
| 84 | 60 |
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static uint32_t isa_mmio_readl_be(void *opaque, target_phys_addr_t addr) |
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{
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uint32_t val; |
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val = cpu_inl(addr & IOPORTS_MASK); |
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val = bswap32(val); |
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return val; |
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} |
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static uint32_t isa_mmio_readl_le(void *opaque, target_phys_addr_t addr) |
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{
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uint32_t val; |
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val = cpu_inl(addr & IOPORTS_MASK); |
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return val; |
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} |
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static CPUWriteMemoryFunc * const isa_mmio_write_be[] = {
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&isa_mmio_writeb, |
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&isa_mmio_writew_be, |
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&isa_mmio_writel_be, |
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}; |
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static CPUReadMemoryFunc * const isa_mmio_read_be[] = {
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&isa_mmio_readb, |
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&isa_mmio_readw_be, |
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&isa_mmio_readl_be, |
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}; |
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static CPUWriteMemoryFunc * const isa_mmio_write_le[] = {
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static CPUWriteMemoryFunc * const isa_mmio_write[] = {
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| 115 | 62 |
&isa_mmio_writeb, |
| 116 |
&isa_mmio_writew_le,
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&isa_mmio_writel_le,
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&isa_mmio_writew, |
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&isa_mmio_writel, |
|
| 118 | 65 |
}; |
| 119 | 66 |
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static CPUReadMemoryFunc * const isa_mmio_read_le[] = {
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static CPUReadMemoryFunc * const isa_mmio_read[] = {
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| 121 | 68 |
&isa_mmio_readb, |
| 122 |
&isa_mmio_readw_le,
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&isa_mmio_readl_le,
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&isa_mmio_readw, |
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&isa_mmio_readl, |
|
| 124 | 71 |
}; |
| 125 | 72 |
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static int isa_mmio_iomemtype = 0; |
|
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|
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void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size, int be) |
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void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size) |
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| 129 | 74 |
{
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if (!isa_mmio_iomemtype) {
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if (be) {
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isa_mmio_iomemtype = cpu_register_io_memory(isa_mmio_read_be, |
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isa_mmio_write_be, |
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NULL, |
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DEVICE_NATIVE_ENDIAN); |
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} else {
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isa_mmio_iomemtype = cpu_register_io_memory(isa_mmio_read_le, |
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isa_mmio_write_le, |
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NULL, |
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DEVICE_NATIVE_ENDIAN); |
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} |
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} |
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int isa_mmio_iomemtype; |
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isa_mmio_iomemtype = cpu_register_io_memory(isa_mmio_read, |
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isa_mmio_write, |
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NULL, |
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| 80 |
DEVICE_LITTLE_ENDIAN); |
|
| 143 | 81 |
cpu_register_physical_memory(base, size, isa_mmio_iomemtype); |
| 144 | 82 |
} |
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