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/*
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 * QEMU Floppy disk emulator (Intel 82078)
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 *
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 * Copyright (c) 2003, 2007 Jocelyn Mayer
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 * Copyright (c) 2008 Herv? Poussineau
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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/*
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 * The controller is used in Sun4m systems in a slightly different
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 * way. There are changes in DOR register and DMA is not available.
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 */
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#include "hw.h"
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#include "fdc.h"
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#include "block.h"
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#include "qemu-timer.h"
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#include "isa.h"
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#include "sysbus.h"
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/********************************************************/
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/* debug Floppy devices */
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//#define DEBUG_FLOPPY
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#ifdef DEBUG_FLOPPY
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#define FLOPPY_DPRINTF(fmt, ...)                                \
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    do { printf("FLOPPY: " fmt , ## __VA_ARGS__); } while (0)
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#else
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#define FLOPPY_DPRINTF(fmt, ...)
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#endif
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#define FLOPPY_ERROR(fmt, ...)                                          \
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    do { printf("FLOPPY ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0)
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/********************************************************/
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/* Floppy drive emulation                               */
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#define GET_CUR_DRV(fdctrl) ((fdctrl)->cur_drv)
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#define SET_CUR_DRV(fdctrl, drive) ((fdctrl)->cur_drv = (drive))
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/* Will always be a fixed parameter for us */
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#define FD_SECTOR_LEN          512
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#define FD_SECTOR_SC           2   /* Sector size code */
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#define FD_RESET_SENSEI_COUNT  4   /* Number of sense interrupts on RESET */
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/* Floppy disk drive emulation */
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typedef enum fdisk_type_t {
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    FDRIVE_DISK_288   = 0x01, /* 2.88 MB disk           */
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    FDRIVE_DISK_144   = 0x02, /* 1.44 MB disk           */
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    FDRIVE_DISK_720   = 0x03, /* 720 kB disk            */
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    FDRIVE_DISK_USER  = 0x04, /* User defined geometry  */
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    FDRIVE_DISK_NONE  = 0x05, /* No disk                */
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} fdisk_type_t;
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typedef enum fdrive_type_t {
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    FDRIVE_DRV_144  = 0x00,   /* 1.44 MB 3"5 drive      */
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    FDRIVE_DRV_288  = 0x01,   /* 2.88 MB 3"5 drive      */
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    FDRIVE_DRV_120  = 0x02,   /* 1.2  MB 5"25 drive     */
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    FDRIVE_DRV_NONE = 0x03,   /* No drive connected     */
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} fdrive_type_t;
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typedef enum fdisk_flags_t {
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    FDISK_DBL_SIDES  = 0x01,
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} fdisk_flags_t;
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typedef struct fdrive_t {
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    BlockDriverState *bs;
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    /* Drive status */
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    fdrive_type_t drive;
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    uint8_t perpendicular;    /* 2.88 MB access mode    */
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    /* Position */
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    uint8_t head;
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    uint8_t track;
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    uint8_t sect;
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    /* Media */
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    fdisk_flags_t flags;
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    uint8_t last_sect;        /* Nb sector per track    */
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    uint8_t max_track;        /* Nb of tracks           */
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    uint16_t bps;             /* Bytes per sector       */
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    uint8_t ro;               /* Is read-only           */
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} fdrive_t;
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static void fd_init (fdrive_t *drv, BlockDriverState *bs)
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{
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    /* Drive */
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    drv->bs = bs;
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    drv->drive = FDRIVE_DRV_NONE;
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    drv->perpendicular = 0;
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    /* Disk */
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    drv->last_sect = 0;
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    drv->max_track = 0;
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}
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static int _fd_sector (uint8_t head, uint8_t track,
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                       uint8_t sect, uint8_t last_sect)
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{
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    return (((track * 2) + head) * last_sect) + sect - 1;
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}
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/* Returns current position, in sectors, for given drive */
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static int fd_sector (fdrive_t *drv)
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{
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    return _fd_sector(drv->head, drv->track, drv->sect, drv->last_sect);
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}
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/* Seek to a new position:
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 * returns 0 if already on right track
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 * returns 1 if track changed
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 * returns 2 if track is invalid
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 * returns 3 if sector is invalid
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 * returns 4 if seek is disabled
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 */
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static int fd_seek (fdrive_t *drv, uint8_t head, uint8_t track, uint8_t sect,
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                    int enable_seek)
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{
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    uint32_t sector;
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    int ret;
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    if (track > drv->max_track ||
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        (head != 0 && (drv->flags & FDISK_DBL_SIDES) == 0)) {
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        FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
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                       head, track, sect, 1,
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                       (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
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                       drv->max_track, drv->last_sect);
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        return 2;
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    }
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    if (sect > drv->last_sect) {
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        FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
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                       head, track, sect, 1,
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                       (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
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                       drv->max_track, drv->last_sect);
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        return 3;
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    }
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    sector = _fd_sector(head, track, sect, drv->last_sect);
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    ret = 0;
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    if (sector != fd_sector(drv)) {
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#if 0
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        if (!enable_seek) {
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            FLOPPY_ERROR("no implicit seek %d %02x %02x (max=%d %02x %02x)\n",
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                         head, track, sect, 1, drv->max_track, drv->last_sect);
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            return 4;
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        }
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#endif
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        drv->head = head;
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        if (drv->track != track)
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            ret = 1;
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        drv->track = track;
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        drv->sect = sect;
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    }
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    return ret;
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}
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/* Set drive back to track 0 */
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static void fd_recalibrate (fdrive_t *drv)
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{
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    FLOPPY_DPRINTF("recalibrate\n");
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    drv->head = 0;
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    drv->track = 0;
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    drv->sect = 1;
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}
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/* Recognize floppy formats */
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typedef struct fd_format_t {
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    fdrive_type_t drive;
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    fdisk_type_t  disk;
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    uint8_t last_sect;
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    uint8_t max_track;
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    uint8_t max_head;
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    const char *str;
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} fd_format_t;
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static const fd_format_t fd_formats[] = {
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    /* First entry is default format */
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    /* 1.44 MB 3"1/2 floppy disks */
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    { FDRIVE_DRV_144, FDRIVE_DISK_144, 18, 80, 1, "1.44 MB 3\"1/2", },
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    { FDRIVE_DRV_144, FDRIVE_DISK_144, 20, 80, 1,  "1.6 MB 3\"1/2", },
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    { FDRIVE_DRV_144, FDRIVE_DISK_144, 21, 80, 1, "1.68 MB 3\"1/2", },
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    { FDRIVE_DRV_144, FDRIVE_DISK_144, 21, 82, 1, "1.72 MB 3\"1/2", },
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    { FDRIVE_DRV_144, FDRIVE_DISK_144, 21, 83, 1, "1.74 MB 3\"1/2", },
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    { FDRIVE_DRV_144, FDRIVE_DISK_144, 22, 80, 1, "1.76 MB 3\"1/2", },
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    { FDRIVE_DRV_144, FDRIVE_DISK_144, 23, 80, 1, "1.84 MB 3\"1/2", },
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    { FDRIVE_DRV_144, FDRIVE_DISK_144, 24, 80, 1, "1.92 MB 3\"1/2", },
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    /* 2.88 MB 3"1/2 floppy disks */
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    { FDRIVE_DRV_288, FDRIVE_DISK_288, 36, 80, 1, "2.88 MB 3\"1/2", },
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    { FDRIVE_DRV_288, FDRIVE_DISK_288, 39, 80, 1, "3.12 MB 3\"1/2", },
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    { FDRIVE_DRV_288, FDRIVE_DISK_288, 40, 80, 1,  "3.2 MB 3\"1/2", },
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    { FDRIVE_DRV_288, FDRIVE_DISK_288, 44, 80, 1, "3.52 MB 3\"1/2", },
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    { FDRIVE_DRV_288, FDRIVE_DISK_288, 48, 80, 1, "3.84 MB 3\"1/2", },
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    /* 720 kB 3"1/2 floppy disks */
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    { FDRIVE_DRV_144, FDRIVE_DISK_720,  9, 80, 1,  "720 kB 3\"1/2", },
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    { FDRIVE_DRV_144, FDRIVE_DISK_720, 10, 80, 1,  "800 kB 3\"1/2", },
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    { FDRIVE_DRV_144, FDRIVE_DISK_720, 10, 82, 1,  "820 kB 3\"1/2", },
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    { FDRIVE_DRV_144, FDRIVE_DISK_720, 10, 83, 1,  "830 kB 3\"1/2", },
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    { FDRIVE_DRV_144, FDRIVE_DISK_720, 13, 80, 1, "1.04 MB 3\"1/2", },
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    { FDRIVE_DRV_144, FDRIVE_DISK_720, 14, 80, 1, "1.12 MB 3\"1/2", },
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    /* 1.2 MB 5"1/4 floppy disks */
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    { FDRIVE_DRV_120, FDRIVE_DISK_288, 15, 80, 1,  "1.2 kB 5\"1/4", },
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    { FDRIVE_DRV_120, FDRIVE_DISK_288, 18, 80, 1, "1.44 MB 5\"1/4", },
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    { FDRIVE_DRV_120, FDRIVE_DISK_288, 18, 82, 1, "1.48 MB 5\"1/4", },
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    { FDRIVE_DRV_120, FDRIVE_DISK_288, 18, 83, 1, "1.49 MB 5\"1/4", },
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    { FDRIVE_DRV_120, FDRIVE_DISK_288, 20, 80, 1,  "1.6 MB 5\"1/4", },
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    /* 720 kB 5"1/4 floppy disks */
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    { FDRIVE_DRV_120, FDRIVE_DISK_288,  9, 80, 1,  "720 kB 5\"1/4", },
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    { FDRIVE_DRV_120, FDRIVE_DISK_288, 11, 80, 1,  "880 kB 5\"1/4", },
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    /* 360 kB 5"1/4 floppy disks */
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    { FDRIVE_DRV_120, FDRIVE_DISK_288,  9, 40, 1,  "360 kB 5\"1/4", },
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    { FDRIVE_DRV_120, FDRIVE_DISK_288,  9, 40, 0,  "180 kB 5\"1/4", },
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    { FDRIVE_DRV_120, FDRIVE_DISK_288, 10, 41, 1,  "410 kB 5\"1/4", },
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    { FDRIVE_DRV_120, FDRIVE_DISK_288, 10, 42, 1,  "420 kB 5\"1/4", },
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    /* 320 kB 5"1/4 floppy disks */
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    { FDRIVE_DRV_120, FDRIVE_DISK_288,  8, 40, 1,  "320 kB 5\"1/4", },
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    { FDRIVE_DRV_120, FDRIVE_DISK_288,  8, 40, 0,  "160 kB 5\"1/4", },
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    /* 360 kB must match 5"1/4 better than 3"1/2... */
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    { FDRIVE_DRV_144, FDRIVE_DISK_720,  9, 80, 0,  "360 kB 3\"1/2", },
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    /* end */
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    { FDRIVE_DRV_NONE, FDRIVE_DISK_NONE, -1, -1, 0, NULL, },
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};
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/* Revalidate a disk drive after a disk change */
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static void fd_revalidate (fdrive_t *drv)
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{
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    const fd_format_t *parse;
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    uint64_t nb_sectors, size;
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    int i, first_match, match;
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    int nb_heads, max_track, last_sect, ro;
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    FLOPPY_DPRINTF("revalidate\n");
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    if (drv->bs != NULL && bdrv_is_inserted(drv->bs)) {
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        ro = bdrv_is_read_only(drv->bs);
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        bdrv_get_geometry_hint(drv->bs, &nb_heads, &max_track, &last_sect);
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        if (nb_heads != 0 && max_track != 0 && last_sect != 0) {
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            FLOPPY_DPRINTF("User defined disk (%d %d %d)",
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                           nb_heads - 1, max_track, last_sect);
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        } else {
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            bdrv_get_geometry(drv->bs, &nb_sectors);
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            match = -1;
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            first_match = -1;
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            for (i = 0;; i++) {
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                parse = &fd_formats[i];
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                if (parse->drive == FDRIVE_DRV_NONE)
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                    break;
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                if (drv->drive == parse->drive ||
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                    drv->drive == FDRIVE_DRV_NONE) {
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                    size = (parse->max_head + 1) * parse->max_track *
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                        parse->last_sect;
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                    if (nb_sectors == size) {
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                        match = i;
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                        break;
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                    }
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                    if (first_match == -1)
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                        first_match = i;
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                }
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            }
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            if (match == -1) {
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                if (first_match == -1)
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                    match = 1;
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                else
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                    match = first_match;
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                parse = &fd_formats[match];
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            }
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            nb_heads = parse->max_head + 1;
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            max_track = parse->max_track;
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            last_sect = parse->last_sect;
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            drv->drive = parse->drive;
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            FLOPPY_DPRINTF("%s floppy disk (%d h %d t %d s) %s\n", parse->str,
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                           nb_heads, max_track, last_sect, ro ? "ro" : "rw");
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        }
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        if (nb_heads == 1) {
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            drv->flags &= ~FDISK_DBL_SIDES;
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        } else {
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            drv->flags |= FDISK_DBL_SIDES;
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        }
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        drv->max_track = max_track;
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        drv->last_sect = last_sect;
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        drv->ro = ro;
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    } else {
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        FLOPPY_DPRINTF("No disk in drive\n");
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        drv->last_sect = 0;
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        drv->max_track = 0;
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        drv->flags &= ~FDISK_DBL_SIDES;
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    }
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}
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/********************************************************/
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/* Intel 82078 floppy disk controller emulation          */
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static void fdctrl_reset (fdctrl_t *fdctrl, int do_irq);
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static void fdctrl_reset_fifo (fdctrl_t *fdctrl);
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static int fdctrl_transfer_handler (void *opaque, int nchan,
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                                    int dma_pos, int dma_len);
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static void fdctrl_raise_irq (fdctrl_t *fdctrl, uint8_t status0);
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static uint32_t fdctrl_read_statusA (fdctrl_t *fdctrl);
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static uint32_t fdctrl_read_statusB (fdctrl_t *fdctrl);
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static uint32_t fdctrl_read_dor (fdctrl_t *fdctrl);
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static void fdctrl_write_dor (fdctrl_t *fdctrl, uint32_t value);
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static uint32_t fdctrl_read_tape (fdctrl_t *fdctrl);
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static void fdctrl_write_tape (fdctrl_t *fdctrl, uint32_t value);
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static uint32_t fdctrl_read_main_status (fdctrl_t *fdctrl);
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static void fdctrl_write_rate (fdctrl_t *fdctrl, uint32_t value);
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static uint32_t fdctrl_read_data (fdctrl_t *fdctrl);
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static void fdctrl_write_data (fdctrl_t *fdctrl, uint32_t value);
320 baca51fa bellard
static uint32_t fdctrl_read_dir (fdctrl_t *fdctrl);
321 8977f3c1 bellard
322 8977f3c1 bellard
enum {
323 8977f3c1 bellard
    FD_DIR_WRITE   = 0,
324 8977f3c1 bellard
    FD_DIR_READ    = 1,
325 8977f3c1 bellard
    FD_DIR_SCANE   = 2,
326 8977f3c1 bellard
    FD_DIR_SCANL   = 3,
327 8977f3c1 bellard
    FD_DIR_SCANH   = 4,
328 8977f3c1 bellard
};
329 8977f3c1 bellard
330 8977f3c1 bellard
enum {
331 b9b3d225 blueswir1
    FD_STATE_MULTI  = 0x01,        /* multi track flag */
332 b9b3d225 blueswir1
    FD_STATE_FORMAT = 0x02,        /* format flag */
333 b9b3d225 blueswir1
    FD_STATE_SEEK   = 0x04,        /* seek flag */
334 8977f3c1 bellard
};
335 8977f3c1 bellard
336 9fea808a blueswir1
enum {
337 8c6a4d77 blueswir1
    FD_REG_SRA = 0x00,
338 8c6a4d77 blueswir1
    FD_REG_SRB = 0x01,
339 9fea808a blueswir1
    FD_REG_DOR = 0x02,
340 9fea808a blueswir1
    FD_REG_TDR = 0x03,
341 9fea808a blueswir1
    FD_REG_MSR = 0x04,
342 9fea808a blueswir1
    FD_REG_DSR = 0x04,
343 9fea808a blueswir1
    FD_REG_FIFO = 0x05,
344 9fea808a blueswir1
    FD_REG_DIR = 0x07,
345 9fea808a blueswir1
};
346 9fea808a blueswir1
347 9fea808a blueswir1
enum {
348 65cef780 blueswir1
    FD_CMD_READ_TRACK = 0x02,
349 9fea808a blueswir1
    FD_CMD_SPECIFY = 0x03,
350 9fea808a blueswir1
    FD_CMD_SENSE_DRIVE_STATUS = 0x04,
351 65cef780 blueswir1
    FD_CMD_WRITE = 0x05,
352 65cef780 blueswir1
    FD_CMD_READ = 0x06,
353 9fea808a blueswir1
    FD_CMD_RECALIBRATE = 0x07,
354 9fea808a blueswir1
    FD_CMD_SENSE_INTERRUPT_STATUS = 0x08,
355 65cef780 blueswir1
    FD_CMD_WRITE_DELETED = 0x09,
356 65cef780 blueswir1
    FD_CMD_READ_ID = 0x0a,
357 65cef780 blueswir1
    FD_CMD_READ_DELETED = 0x0c,
358 65cef780 blueswir1
    FD_CMD_FORMAT_TRACK = 0x0d,
359 9fea808a blueswir1
    FD_CMD_DUMPREG = 0x0e,
360 9fea808a blueswir1
    FD_CMD_SEEK = 0x0f,
361 9fea808a blueswir1
    FD_CMD_VERSION = 0x10,
362 65cef780 blueswir1
    FD_CMD_SCAN_EQUAL = 0x11,
363 9fea808a blueswir1
    FD_CMD_PERPENDICULAR_MODE = 0x12,
364 9fea808a blueswir1
    FD_CMD_CONFIGURE = 0x13,
365 65cef780 blueswir1
    FD_CMD_LOCK = 0x14,
366 65cef780 blueswir1
    FD_CMD_VERIFY = 0x16,
367 9fea808a blueswir1
    FD_CMD_POWERDOWN_MODE = 0x17,
368 9fea808a blueswir1
    FD_CMD_PART_ID = 0x18,
369 65cef780 blueswir1
    FD_CMD_SCAN_LOW_OR_EQUAL = 0x19,
370 65cef780 blueswir1
    FD_CMD_SCAN_HIGH_OR_EQUAL = 0x1d,
371 9fea808a blueswir1
    FD_CMD_SAVE = 0x2c,
372 9fea808a blueswir1
    FD_CMD_OPTION = 0x33,
373 9fea808a blueswir1
    FD_CMD_RESTORE = 0x4c,
374 9fea808a blueswir1
    FD_CMD_DRIVE_SPECIFICATION_COMMAND = 0x8e,
375 9fea808a blueswir1
    FD_CMD_RELATIVE_SEEK_OUT = 0x8f,
376 9fea808a blueswir1
    FD_CMD_FORMAT_AND_WRITE = 0xcd,
377 9fea808a blueswir1
    FD_CMD_RELATIVE_SEEK_IN = 0xcf,
378 9fea808a blueswir1
};
379 9fea808a blueswir1
380 9fea808a blueswir1
enum {
381 9fea808a blueswir1
    FD_CONFIG_PRETRK = 0xff, /* Pre-compensation set to track 0 */
382 9fea808a blueswir1
    FD_CONFIG_FIFOTHR = 0x0f, /* FIFO threshold set to 1 byte */
383 9fea808a blueswir1
    FD_CONFIG_POLL  = 0x10, /* Poll enabled */
384 9fea808a blueswir1
    FD_CONFIG_EFIFO = 0x20, /* FIFO disabled */
385 9fea808a blueswir1
    FD_CONFIG_EIS   = 0x40, /* No implied seeks */
386 9fea808a blueswir1
};
387 9fea808a blueswir1
388 9fea808a blueswir1
enum {
389 9fea808a blueswir1
    FD_SR0_EQPMT    = 0x10,
390 9fea808a blueswir1
    FD_SR0_SEEK     = 0x20,
391 9fea808a blueswir1
    FD_SR0_ABNTERM  = 0x40,
392 9fea808a blueswir1
    FD_SR0_INVCMD   = 0x80,
393 9fea808a blueswir1
    FD_SR0_RDYCHG   = 0xc0,
394 9fea808a blueswir1
};
395 9fea808a blueswir1
396 9fea808a blueswir1
enum {
397 77370520 blueswir1
    FD_SR1_EC       = 0x80, /* End of cylinder */
398 77370520 blueswir1
};
399 77370520 blueswir1
400 77370520 blueswir1
enum {
401 77370520 blueswir1
    FD_SR2_SNS      = 0x04, /* Scan not satisfied */
402 77370520 blueswir1
    FD_SR2_SEH      = 0x08, /* Scan equal hit */
403 77370520 blueswir1
};
404 77370520 blueswir1
405 77370520 blueswir1
enum {
406 8c6a4d77 blueswir1
    FD_SRA_DIR      = 0x01,
407 8c6a4d77 blueswir1
    FD_SRA_nWP      = 0x02,
408 8c6a4d77 blueswir1
    FD_SRA_nINDX    = 0x04,
409 8c6a4d77 blueswir1
    FD_SRA_HDSEL    = 0x08,
410 8c6a4d77 blueswir1
    FD_SRA_nTRK0    = 0x10,
411 8c6a4d77 blueswir1
    FD_SRA_STEP     = 0x20,
412 8c6a4d77 blueswir1
    FD_SRA_nDRV2    = 0x40,
413 8c6a4d77 blueswir1
    FD_SRA_INTPEND  = 0x80,
414 8c6a4d77 blueswir1
};
415 8c6a4d77 blueswir1
416 8c6a4d77 blueswir1
enum {
417 8c6a4d77 blueswir1
    FD_SRB_MTR0     = 0x01,
418 8c6a4d77 blueswir1
    FD_SRB_MTR1     = 0x02,
419 8c6a4d77 blueswir1
    FD_SRB_WGATE    = 0x04,
420 8c6a4d77 blueswir1
    FD_SRB_RDATA    = 0x08,
421 8c6a4d77 blueswir1
    FD_SRB_WDATA    = 0x10,
422 8c6a4d77 blueswir1
    FD_SRB_DR0      = 0x20,
423 8c6a4d77 blueswir1
};
424 8c6a4d77 blueswir1
425 8c6a4d77 blueswir1
enum {
426 78ae820c blueswir1
#if MAX_FD == 4
427 78ae820c blueswir1
    FD_DOR_SELMASK  = 0x03,
428 78ae820c blueswir1
#else
429 9fea808a blueswir1
    FD_DOR_SELMASK  = 0x01,
430 78ae820c blueswir1
#endif
431 9fea808a blueswir1
    FD_DOR_nRESET   = 0x04,
432 9fea808a blueswir1
    FD_DOR_DMAEN    = 0x08,
433 9fea808a blueswir1
    FD_DOR_MOTEN0   = 0x10,
434 9fea808a blueswir1
    FD_DOR_MOTEN1   = 0x20,
435 9fea808a blueswir1
    FD_DOR_MOTEN2   = 0x40,
436 9fea808a blueswir1
    FD_DOR_MOTEN3   = 0x80,
437 9fea808a blueswir1
};
438 9fea808a blueswir1
439 9fea808a blueswir1
enum {
440 78ae820c blueswir1
#if MAX_FD == 4
441 9fea808a blueswir1
    FD_TDR_BOOTSEL  = 0x0c,
442 78ae820c blueswir1
#else
443 78ae820c blueswir1
    FD_TDR_BOOTSEL  = 0x04,
444 78ae820c blueswir1
#endif
445 9fea808a blueswir1
};
446 9fea808a blueswir1
447 9fea808a blueswir1
enum {
448 9fea808a blueswir1
    FD_DSR_DRATEMASK= 0x03,
449 9fea808a blueswir1
    FD_DSR_PWRDOWN  = 0x40,
450 9fea808a blueswir1
    FD_DSR_SWRESET  = 0x80,
451 9fea808a blueswir1
};
452 9fea808a blueswir1
453 9fea808a blueswir1
enum {
454 9fea808a blueswir1
    FD_MSR_DRV0BUSY = 0x01,
455 9fea808a blueswir1
    FD_MSR_DRV1BUSY = 0x02,
456 9fea808a blueswir1
    FD_MSR_DRV2BUSY = 0x04,
457 9fea808a blueswir1
    FD_MSR_DRV3BUSY = 0x08,
458 9fea808a blueswir1
    FD_MSR_CMDBUSY  = 0x10,
459 9fea808a blueswir1
    FD_MSR_NONDMA   = 0x20,
460 9fea808a blueswir1
    FD_MSR_DIO      = 0x40,
461 9fea808a blueswir1
    FD_MSR_RQM      = 0x80,
462 9fea808a blueswir1
};
463 9fea808a blueswir1
464 9fea808a blueswir1
enum {
465 9fea808a blueswir1
    FD_DIR_DSKCHG   = 0x80,
466 9fea808a blueswir1
};
467 9fea808a blueswir1
468 8977f3c1 bellard
#define FD_MULTI_TRACK(state) ((state) & FD_STATE_MULTI)
469 8977f3c1 bellard
#define FD_DID_SEEK(state) ((state) & FD_STATE_SEEK)
470 baca51fa bellard
#define FD_FORMAT_CMD(state) ((state) & FD_STATE_FORMAT)
471 8977f3c1 bellard
472 baca51fa bellard
struct fdctrl_t {
473 f64ab228 Blue Swirl
    SysBusDevice busdev;
474 4b19ec0c bellard
    /* Controller's identification */
475 8977f3c1 bellard
    uint8_t version;
476 8977f3c1 bellard
    /* HW */
477 d537cf6c pbrook
    qemu_irq irq;
478 8977f3c1 bellard
    int dma_chann;
479 5dcb6b91 blueswir1
    target_phys_addr_t io_base;
480 4b19ec0c bellard
    /* Controller state */
481 ed5fd2cc bellard
    QEMUTimer *result_timer;
482 8c6a4d77 blueswir1
    uint8_t sra;
483 8c6a4d77 blueswir1
    uint8_t srb;
484 368df94d blueswir1
    uint8_t dor;
485 46d3233b blueswir1
    uint8_t tdr;
486 b9b3d225 blueswir1
    uint8_t dsr;
487 368df94d blueswir1
    uint8_t msr;
488 8977f3c1 bellard
    uint8_t cur_drv;
489 77370520 blueswir1
    uint8_t status0;
490 77370520 blueswir1
    uint8_t status1;
491 77370520 blueswir1
    uint8_t status2;
492 8977f3c1 bellard
    /* Command FIFO */
493 33f00271 balrog
    uint8_t *fifo;
494 8977f3c1 bellard
    uint32_t data_pos;
495 8977f3c1 bellard
    uint32_t data_len;
496 8977f3c1 bellard
    uint8_t data_state;
497 8977f3c1 bellard
    uint8_t data_dir;
498 890fa6be bellard
    uint8_t eot; /* last wanted sector */
499 8977f3c1 bellard
    /* States kept only to be returned back */
500 8977f3c1 bellard
    /* Timers state */
501 8977f3c1 bellard
    uint8_t timer0;
502 8977f3c1 bellard
    uint8_t timer1;
503 8977f3c1 bellard
    /* precompensation */
504 8977f3c1 bellard
    uint8_t precomp_trk;
505 8977f3c1 bellard
    uint8_t config;
506 8977f3c1 bellard
    uint8_t lock;
507 8977f3c1 bellard
    /* Power down config (also with status regB access mode */
508 8977f3c1 bellard
    uint8_t pwrd;
509 741402f9 blueswir1
    /* Sun4m quirks? */
510 a06e5a3c blueswir1
    int sun4m;
511 8977f3c1 bellard
    /* Floppy drives */
512 78ae820c blueswir1
    fdrive_t drives[MAX_FD];
513 f2d81b33 blueswir1
    int reset_sensei;
514 ee6847d1 Gerd Hoffmann
    uint32_t strict_io;
515 ee6847d1 Gerd Hoffmann
    uint32_t mem_mapped;
516 baca51fa bellard
};
517 baca51fa bellard
518 baca51fa bellard
static uint32_t fdctrl_read (void *opaque, uint32_t reg)
519 baca51fa bellard
{
520 baca51fa bellard
    fdctrl_t *fdctrl = opaque;
521 baca51fa bellard
    uint32_t retval;
522 baca51fa bellard
523 e64d7d59 blueswir1
    switch (reg) {
524 8c6a4d77 blueswir1
    case FD_REG_SRA:
525 8c6a4d77 blueswir1
        retval = fdctrl_read_statusA(fdctrl);
526 4f431960 j_mayer
        break;
527 8c6a4d77 blueswir1
    case FD_REG_SRB:
528 4f431960 j_mayer
        retval = fdctrl_read_statusB(fdctrl);
529 4f431960 j_mayer
        break;
530 9fea808a blueswir1
    case FD_REG_DOR:
531 4f431960 j_mayer
        retval = fdctrl_read_dor(fdctrl);
532 4f431960 j_mayer
        break;
533 9fea808a blueswir1
    case FD_REG_TDR:
534 baca51fa bellard
        retval = fdctrl_read_tape(fdctrl);
535 4f431960 j_mayer
        break;
536 9fea808a blueswir1
    case FD_REG_MSR:
537 baca51fa bellard
        retval = fdctrl_read_main_status(fdctrl);
538 4f431960 j_mayer
        break;
539 9fea808a blueswir1
    case FD_REG_FIFO:
540 baca51fa bellard
        retval = fdctrl_read_data(fdctrl);
541 4f431960 j_mayer
        break;
542 9fea808a blueswir1
    case FD_REG_DIR:
543 baca51fa bellard
        retval = fdctrl_read_dir(fdctrl);
544 4f431960 j_mayer
        break;
545 a541f297 bellard
    default:
546 4f431960 j_mayer
        retval = (uint32_t)(-1);
547 4f431960 j_mayer
        break;
548 a541f297 bellard
    }
549 ed5fd2cc bellard
    FLOPPY_DPRINTF("read reg%d: 0x%02x\n", reg & 7, retval);
550 baca51fa bellard
551 baca51fa bellard
    return retval;
552 baca51fa bellard
}
553 baca51fa bellard
554 baca51fa bellard
static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value)
555 baca51fa bellard
{
556 baca51fa bellard
    fdctrl_t *fdctrl = opaque;
557 baca51fa bellard
558 ed5fd2cc bellard
    FLOPPY_DPRINTF("write reg%d: 0x%02x\n", reg & 7, value);
559 ed5fd2cc bellard
560 e64d7d59 blueswir1
    switch (reg) {
561 9fea808a blueswir1
    case FD_REG_DOR:
562 4f431960 j_mayer
        fdctrl_write_dor(fdctrl, value);
563 4f431960 j_mayer
        break;
564 9fea808a blueswir1
    case FD_REG_TDR:
565 baca51fa bellard
        fdctrl_write_tape(fdctrl, value);
566 4f431960 j_mayer
        break;
567 9fea808a blueswir1
    case FD_REG_DSR:
568 baca51fa bellard
        fdctrl_write_rate(fdctrl, value);
569 4f431960 j_mayer
        break;
570 9fea808a blueswir1
    case FD_REG_FIFO:
571 baca51fa bellard
        fdctrl_write_data(fdctrl, value);
572 4f431960 j_mayer
        break;
573 a541f297 bellard
    default:
574 4f431960 j_mayer
        break;
575 a541f297 bellard
    }
576 baca51fa bellard
}
577 baca51fa bellard
578 e64d7d59 blueswir1
static uint32_t fdctrl_read_port (void *opaque, uint32_t reg)
579 e64d7d59 blueswir1
{
580 e64d7d59 blueswir1
    return fdctrl_read(opaque, reg & 7);
581 e64d7d59 blueswir1
}
582 e64d7d59 blueswir1
583 e64d7d59 blueswir1
static void fdctrl_write_port (void *opaque, uint32_t reg, uint32_t value)
584 e64d7d59 blueswir1
{
585 e64d7d59 blueswir1
    fdctrl_write(opaque, reg & 7, value);
586 e64d7d59 blueswir1
}
587 e64d7d59 blueswir1
588 62a46c61 bellard
static uint32_t fdctrl_read_mem (void *opaque, target_phys_addr_t reg)
589 62a46c61 bellard
{
590 5dcb6b91 blueswir1
    return fdctrl_read(opaque, (uint32_t)reg);
591 62a46c61 bellard
}
592 62a46c61 bellard
593 5fafdf24 ths
static void fdctrl_write_mem (void *opaque,
594 62a46c61 bellard
                              target_phys_addr_t reg, uint32_t value)
595 62a46c61 bellard
{
596 5dcb6b91 blueswir1
    fdctrl_write(opaque, (uint32_t)reg, value);
597 62a46c61 bellard
}
598 62a46c61 bellard
599 e80cfcfc bellard
static CPUReadMemoryFunc *fdctrl_mem_read[3] = {
600 62a46c61 bellard
    fdctrl_read_mem,
601 62a46c61 bellard
    fdctrl_read_mem,
602 62a46c61 bellard
    fdctrl_read_mem,
603 e80cfcfc bellard
};
604 e80cfcfc bellard
605 e80cfcfc bellard
static CPUWriteMemoryFunc *fdctrl_mem_write[3] = {
606 62a46c61 bellard
    fdctrl_write_mem,
607 62a46c61 bellard
    fdctrl_write_mem,
608 62a46c61 bellard
    fdctrl_write_mem,
609 e80cfcfc bellard
};
610 e80cfcfc bellard
611 7c560456 blueswir1
static CPUReadMemoryFunc *fdctrl_mem_read_strict[3] = {
612 7c560456 blueswir1
    fdctrl_read_mem,
613 7c560456 blueswir1
    NULL,
614 7c560456 blueswir1
    NULL,
615 7c560456 blueswir1
};
616 7c560456 blueswir1
617 7c560456 blueswir1
static CPUWriteMemoryFunc *fdctrl_mem_write_strict[3] = {
618 7c560456 blueswir1
    fdctrl_write_mem,
619 7c560456 blueswir1
    NULL,
620 7c560456 blueswir1
    NULL,
621 7c560456 blueswir1
};
622 7c560456 blueswir1
623 3ccacc4a blueswir1
static void fd_save (QEMUFile *f, fdrive_t *fd)
624 3ccacc4a blueswir1
{
625 3ccacc4a blueswir1
    qemu_put_8s(f, &fd->head);
626 3ccacc4a blueswir1
    qemu_put_8s(f, &fd->track);
627 3ccacc4a blueswir1
    qemu_put_8s(f, &fd->sect);
628 3ccacc4a blueswir1
}
629 3ccacc4a blueswir1
630 3ccacc4a blueswir1
static void fdc_save (QEMUFile *f, void *opaque)
631 3ccacc4a blueswir1
{
632 3ccacc4a blueswir1
    fdctrl_t *s = opaque;
633 78ae820c blueswir1
    uint8_t tmp;
634 78ae820c blueswir1
    int i;
635 cefec4f5 blueswir1
    uint8_t dor = s->dor | GET_CUR_DRV(s);
636 3ccacc4a blueswir1
637 8c6a4d77 blueswir1
    /* Controller state */
638 8c6a4d77 blueswir1
    qemu_put_8s(f, &s->sra);
639 8c6a4d77 blueswir1
    qemu_put_8s(f, &s->srb);
640 cefec4f5 blueswir1
    qemu_put_8s(f, &dor);
641 46d3233b blueswir1
    qemu_put_8s(f, &s->tdr);
642 77370520 blueswir1
    qemu_put_8s(f, &s->dsr);
643 77370520 blueswir1
    qemu_put_8s(f, &s->msr);
644 77370520 blueswir1
    qemu_put_8s(f, &s->status0);
645 77370520 blueswir1
    qemu_put_8s(f, &s->status1);
646 77370520 blueswir1
    qemu_put_8s(f, &s->status2);
647 77370520 blueswir1
    /* Command FIFO */
648 3ccacc4a blueswir1
    qemu_put_buffer(f, s->fifo, FD_SECTOR_LEN);
649 3ccacc4a blueswir1
    qemu_put_be32s(f, &s->data_pos);
650 3ccacc4a blueswir1
    qemu_put_be32s(f, &s->data_len);
651 3ccacc4a blueswir1
    qemu_put_8s(f, &s->data_state);
652 3ccacc4a blueswir1
    qemu_put_8s(f, &s->data_dir);
653 3ccacc4a blueswir1
    qemu_put_8s(f, &s->eot);
654 77370520 blueswir1
    /* States kept only to be returned back */
655 3ccacc4a blueswir1
    qemu_put_8s(f, &s->timer0);
656 3ccacc4a blueswir1
    qemu_put_8s(f, &s->timer1);
657 3ccacc4a blueswir1
    qemu_put_8s(f, &s->precomp_trk);
658 3ccacc4a blueswir1
    qemu_put_8s(f, &s->config);
659 3ccacc4a blueswir1
    qemu_put_8s(f, &s->lock);
660 3ccacc4a blueswir1
    qemu_put_8s(f, &s->pwrd);
661 78ae820c blueswir1
662 78ae820c blueswir1
    tmp = MAX_FD;
663 78ae820c blueswir1
    qemu_put_8s(f, &tmp);
664 78ae820c blueswir1
    for (i = 0; i < MAX_FD; i++)
665 78ae820c blueswir1
        fd_save(f, &s->drives[i]);
666 3ccacc4a blueswir1
}
667 3ccacc4a blueswir1
668 3ccacc4a blueswir1
static int fd_load (QEMUFile *f, fdrive_t *fd)
669 3ccacc4a blueswir1
{
670 3ccacc4a blueswir1
    qemu_get_8s(f, &fd->head);
671 3ccacc4a blueswir1
    qemu_get_8s(f, &fd->track);
672 3ccacc4a blueswir1
    qemu_get_8s(f, &fd->sect);
673 3ccacc4a blueswir1
674 3ccacc4a blueswir1
    return 0;
675 3ccacc4a blueswir1
}
676 3ccacc4a blueswir1
677 3ccacc4a blueswir1
static int fdc_load (QEMUFile *f, void *opaque, int version_id)
678 3ccacc4a blueswir1
{
679 3ccacc4a blueswir1
    fdctrl_t *s = opaque;
680 78ae820c blueswir1
    int i, ret = 0;
681 78ae820c blueswir1
    uint8_t n;
682 3ccacc4a blueswir1
683 77370520 blueswir1
    if (version_id != 2)
684 3ccacc4a blueswir1
        return -EINVAL;
685 3ccacc4a blueswir1
686 8c6a4d77 blueswir1
    /* Controller state */
687 8c6a4d77 blueswir1
    qemu_get_8s(f, &s->sra);
688 8c6a4d77 blueswir1
    qemu_get_8s(f, &s->srb);
689 cefec4f5 blueswir1
    qemu_get_8s(f, &s->dor);
690 cefec4f5 blueswir1
    SET_CUR_DRV(s, s->dor & FD_DOR_SELMASK);
691 cefec4f5 blueswir1
    s->dor &= ~FD_DOR_SELMASK;
692 46d3233b blueswir1
    qemu_get_8s(f, &s->tdr);
693 77370520 blueswir1
    qemu_get_8s(f, &s->dsr);
694 77370520 blueswir1
    qemu_get_8s(f, &s->msr);
695 77370520 blueswir1
    qemu_get_8s(f, &s->status0);
696 77370520 blueswir1
    qemu_get_8s(f, &s->status1);
697 77370520 blueswir1
    qemu_get_8s(f, &s->status2);
698 77370520 blueswir1
    /* Command FIFO */
699 3ccacc4a blueswir1
    qemu_get_buffer(f, s->fifo, FD_SECTOR_LEN);
700 3ccacc4a blueswir1
    qemu_get_be32s(f, &s->data_pos);
701 3ccacc4a blueswir1
    qemu_get_be32s(f, &s->data_len);
702 3ccacc4a blueswir1
    qemu_get_8s(f, &s->data_state);
703 3ccacc4a blueswir1
    qemu_get_8s(f, &s->data_dir);
704 3ccacc4a blueswir1
    qemu_get_8s(f, &s->eot);
705 77370520 blueswir1
    /* States kept only to be returned back */
706 3ccacc4a blueswir1
    qemu_get_8s(f, &s->timer0);
707 3ccacc4a blueswir1
    qemu_get_8s(f, &s->timer1);
708 3ccacc4a blueswir1
    qemu_get_8s(f, &s->precomp_trk);
709 3ccacc4a blueswir1
    qemu_get_8s(f, &s->config);
710 3ccacc4a blueswir1
    qemu_get_8s(f, &s->lock);
711 3ccacc4a blueswir1
    qemu_get_8s(f, &s->pwrd);
712 78ae820c blueswir1
    qemu_get_8s(f, &n);
713 3ccacc4a blueswir1
714 78ae820c blueswir1
    if (n > MAX_FD)
715 78ae820c blueswir1
        return -EINVAL;
716 78ae820c blueswir1
717 78ae820c blueswir1
    for (i = 0; i < n; i++) {
718 78ae820c blueswir1
        ret = fd_load(f, &s->drives[i]);
719 78ae820c blueswir1
        if (ret != 0)
720 78ae820c blueswir1
            break;
721 78ae820c blueswir1
    }
722 3ccacc4a blueswir1
723 3ccacc4a blueswir1
    return ret;
724 3ccacc4a blueswir1
}
725 3ccacc4a blueswir1
726 3ccacc4a blueswir1
static void fdctrl_external_reset(void *opaque)
727 3ccacc4a blueswir1
{
728 3ccacc4a blueswir1
    fdctrl_t *s = opaque;
729 3ccacc4a blueswir1
730 3ccacc4a blueswir1
    fdctrl_reset(s, 0);
731 3ccacc4a blueswir1
}
732 3ccacc4a blueswir1
733 2be17ebd blueswir1
static void fdctrl_handle_tc(void *opaque, int irq, int level)
734 2be17ebd blueswir1
{
735 2be17ebd blueswir1
    //fdctrl_t *s = opaque;
736 2be17ebd blueswir1
737 2be17ebd blueswir1
    if (level) {
738 2be17ebd blueswir1
        // XXX
739 2be17ebd blueswir1
        FLOPPY_DPRINTF("TC pulsed\n");
740 2be17ebd blueswir1
    }
741 2be17ebd blueswir1
}
742 2be17ebd blueswir1
743 baca51fa bellard
/* XXX: may change if moved to bdrv */
744 baca51fa bellard
int fdctrl_get_drive_type(fdctrl_t *fdctrl, int drive_num)
745 caed8802 bellard
{
746 baca51fa bellard
    return fdctrl->drives[drive_num].drive;
747 8977f3c1 bellard
}
748 8977f3c1 bellard
749 8977f3c1 bellard
/* Change IRQ state */
750 baca51fa bellard
static void fdctrl_reset_irq (fdctrl_t *fdctrl)
751 8977f3c1 bellard
{
752 8c6a4d77 blueswir1
    if (!(fdctrl->sra & FD_SRA_INTPEND))
753 8c6a4d77 blueswir1
        return;
754 ed5fd2cc bellard
    FLOPPY_DPRINTF("Reset interrupt\n");
755 d537cf6c pbrook
    qemu_set_irq(fdctrl->irq, 0);
756 8c6a4d77 blueswir1
    fdctrl->sra &= ~FD_SRA_INTPEND;
757 8977f3c1 bellard
}
758 8977f3c1 bellard
759 77370520 blueswir1
static void fdctrl_raise_irq (fdctrl_t *fdctrl, uint8_t status0)
760 8977f3c1 bellard
{
761 b9b3d225 blueswir1
    /* Sparc mutation */
762 b9b3d225 blueswir1
    if (fdctrl->sun4m && (fdctrl->msr & FD_MSR_CMDBUSY)) {
763 b9b3d225 blueswir1
        /* XXX: not sure */
764 b9b3d225 blueswir1
        fdctrl->msr &= ~FD_MSR_CMDBUSY;
765 b9b3d225 blueswir1
        fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
766 77370520 blueswir1
        fdctrl->status0 = status0;
767 4f431960 j_mayer
        return;
768 6f7e9aec bellard
    }
769 8c6a4d77 blueswir1
    if (!(fdctrl->sra & FD_SRA_INTPEND)) {
770 d537cf6c pbrook
        qemu_set_irq(fdctrl->irq, 1);
771 8c6a4d77 blueswir1
        fdctrl->sra |= FD_SRA_INTPEND;
772 8977f3c1 bellard
    }
773 f2d81b33 blueswir1
    fdctrl->reset_sensei = 0;
774 77370520 blueswir1
    fdctrl->status0 = status0;
775 77370520 blueswir1
    FLOPPY_DPRINTF("Set interrupt status to 0x%02x\n", fdctrl->status0);
776 8977f3c1 bellard
}
777 8977f3c1 bellard
778 4b19ec0c bellard
/* Reset controller */
779 baca51fa bellard
static void fdctrl_reset (fdctrl_t *fdctrl, int do_irq)
780 8977f3c1 bellard
{
781 8977f3c1 bellard
    int i;
782 8977f3c1 bellard
783 4b19ec0c bellard
    FLOPPY_DPRINTF("reset controller\n");
784 baca51fa bellard
    fdctrl_reset_irq(fdctrl);
785 4b19ec0c bellard
    /* Initialise controller */
786 8c6a4d77 blueswir1
    fdctrl->sra = 0;
787 8c6a4d77 blueswir1
    fdctrl->srb = 0xc0;
788 8c6a4d77 blueswir1
    if (!fdctrl->drives[1].bs)
789 8c6a4d77 blueswir1
        fdctrl->sra |= FD_SRA_nDRV2;
790 baca51fa bellard
    fdctrl->cur_drv = 0;
791 1c346df2 blueswir1
    fdctrl->dor = FD_DOR_nRESET;
792 368df94d blueswir1
    fdctrl->dor |= (fdctrl->dma_chann != -1) ? FD_DOR_DMAEN : 0;
793 b9b3d225 blueswir1
    fdctrl->msr = FD_MSR_RQM;
794 8977f3c1 bellard
    /* FIFO state */
795 baca51fa bellard
    fdctrl->data_pos = 0;
796 baca51fa bellard
    fdctrl->data_len = 0;
797 b9b3d225 blueswir1
    fdctrl->data_state = 0;
798 baca51fa bellard
    fdctrl->data_dir = FD_DIR_WRITE;
799 8977f3c1 bellard
    for (i = 0; i < MAX_FD; i++)
800 1c346df2 blueswir1
        fd_recalibrate(&fdctrl->drives[i]);
801 baca51fa bellard
    fdctrl_reset_fifo(fdctrl);
802 77370520 blueswir1
    if (do_irq) {
803 9fea808a blueswir1
        fdctrl_raise_irq(fdctrl, FD_SR0_RDYCHG);
804 f2d81b33 blueswir1
        fdctrl->reset_sensei = FD_RESET_SENSEI_COUNT;
805 77370520 blueswir1
    }
806 baca51fa bellard
}
807 baca51fa bellard
808 baca51fa bellard
static inline fdrive_t *drv0 (fdctrl_t *fdctrl)
809 baca51fa bellard
{
810 46d3233b blueswir1
    return &fdctrl->drives[(fdctrl->tdr & FD_TDR_BOOTSEL) >> 2];
811 baca51fa bellard
}
812 baca51fa bellard
813 baca51fa bellard
static inline fdrive_t *drv1 (fdctrl_t *fdctrl)
814 baca51fa bellard
{
815 46d3233b blueswir1
    if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (1 << 2))
816 46d3233b blueswir1
        return &fdctrl->drives[1];
817 46d3233b blueswir1
    else
818 46d3233b blueswir1
        return &fdctrl->drives[0];
819 baca51fa bellard
}
820 baca51fa bellard
821 78ae820c blueswir1
#if MAX_FD == 4
822 78ae820c blueswir1
static inline fdrive_t *drv2 (fdctrl_t *fdctrl)
823 78ae820c blueswir1
{
824 78ae820c blueswir1
    if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (2 << 2))
825 78ae820c blueswir1
        return &fdctrl->drives[2];
826 78ae820c blueswir1
    else
827 78ae820c blueswir1
        return &fdctrl->drives[1];
828 78ae820c blueswir1
}
829 78ae820c blueswir1
830 78ae820c blueswir1
static inline fdrive_t *drv3 (fdctrl_t *fdctrl)
831 78ae820c blueswir1
{
832 78ae820c blueswir1
    if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (3 << 2))
833 78ae820c blueswir1
        return &fdctrl->drives[3];
834 78ae820c blueswir1
    else
835 78ae820c blueswir1
        return &fdctrl->drives[2];
836 78ae820c blueswir1
}
837 78ae820c blueswir1
#endif
838 78ae820c blueswir1
839 baca51fa bellard
static fdrive_t *get_cur_drv (fdctrl_t *fdctrl)
840 baca51fa bellard
{
841 78ae820c blueswir1
    switch (fdctrl->cur_drv) {
842 78ae820c blueswir1
        case 0: return drv0(fdctrl);
843 78ae820c blueswir1
        case 1: return drv1(fdctrl);
844 78ae820c blueswir1
#if MAX_FD == 4
845 78ae820c blueswir1
        case 2: return drv2(fdctrl);
846 78ae820c blueswir1
        case 3: return drv3(fdctrl);
847 78ae820c blueswir1
#endif
848 78ae820c blueswir1
        default: return NULL;
849 78ae820c blueswir1
    }
850 8977f3c1 bellard
}
851 8977f3c1 bellard
852 8c6a4d77 blueswir1
/* Status A register : 0x00 (read-only) */
853 8c6a4d77 blueswir1
static uint32_t fdctrl_read_statusA (fdctrl_t *fdctrl)
854 8c6a4d77 blueswir1
{
855 8c6a4d77 blueswir1
    uint32_t retval = fdctrl->sra;
856 8c6a4d77 blueswir1
857 8c6a4d77 blueswir1
    FLOPPY_DPRINTF("status register A: 0x%02x\n", retval);
858 8c6a4d77 blueswir1
859 8c6a4d77 blueswir1
    return retval;
860 8c6a4d77 blueswir1
}
861 8c6a4d77 blueswir1
862 8977f3c1 bellard
/* Status B register : 0x01 (read-only) */
863 baca51fa bellard
static uint32_t fdctrl_read_statusB (fdctrl_t *fdctrl)
864 8977f3c1 bellard
{
865 8c6a4d77 blueswir1
    uint32_t retval = fdctrl->srb;
866 8c6a4d77 blueswir1
867 8c6a4d77 blueswir1
    FLOPPY_DPRINTF("status register B: 0x%02x\n", retval);
868 8c6a4d77 blueswir1
869 8c6a4d77 blueswir1
    return retval;
870 8977f3c1 bellard
}
871 8977f3c1 bellard
872 8977f3c1 bellard
/* Digital output register : 0x02 */
873 baca51fa bellard
static uint32_t fdctrl_read_dor (fdctrl_t *fdctrl)
874 8977f3c1 bellard
{
875 1c346df2 blueswir1
    uint32_t retval = fdctrl->dor;
876 8977f3c1 bellard
877 8977f3c1 bellard
    /* Selected drive */
878 baca51fa bellard
    retval |= fdctrl->cur_drv;
879 8977f3c1 bellard
    FLOPPY_DPRINTF("digital output register: 0x%02x\n", retval);
880 8977f3c1 bellard
881 8977f3c1 bellard
    return retval;
882 8977f3c1 bellard
}
883 8977f3c1 bellard
884 baca51fa bellard
static void fdctrl_write_dor (fdctrl_t *fdctrl, uint32_t value)
885 8977f3c1 bellard
{
886 8977f3c1 bellard
    FLOPPY_DPRINTF("digital output register set to 0x%02x\n", value);
887 8c6a4d77 blueswir1
888 8c6a4d77 blueswir1
    /* Motors */
889 8c6a4d77 blueswir1
    if (value & FD_DOR_MOTEN0)
890 8c6a4d77 blueswir1
        fdctrl->srb |= FD_SRB_MTR0;
891 8c6a4d77 blueswir1
    else
892 8c6a4d77 blueswir1
        fdctrl->srb &= ~FD_SRB_MTR0;
893 8c6a4d77 blueswir1
    if (value & FD_DOR_MOTEN1)
894 8c6a4d77 blueswir1
        fdctrl->srb |= FD_SRB_MTR1;
895 8c6a4d77 blueswir1
    else
896 8c6a4d77 blueswir1
        fdctrl->srb &= ~FD_SRB_MTR1;
897 8c6a4d77 blueswir1
898 8c6a4d77 blueswir1
    /* Drive */
899 8c6a4d77 blueswir1
    if (value & 1)
900 8c6a4d77 blueswir1
        fdctrl->srb |= FD_SRB_DR0;
901 8c6a4d77 blueswir1
    else
902 8c6a4d77 blueswir1
        fdctrl->srb &= ~FD_SRB_DR0;
903 8c6a4d77 blueswir1
904 8977f3c1 bellard
    /* Reset */
905 9fea808a blueswir1
    if (!(value & FD_DOR_nRESET)) {
906 1c346df2 blueswir1
        if (fdctrl->dor & FD_DOR_nRESET) {
907 4b19ec0c bellard
            FLOPPY_DPRINTF("controller enter RESET state\n");
908 8977f3c1 bellard
        }
909 8977f3c1 bellard
    } else {
910 1c346df2 blueswir1
        if (!(fdctrl->dor & FD_DOR_nRESET)) {
911 4b19ec0c bellard
            FLOPPY_DPRINTF("controller out of RESET state\n");
912 fb6cf1d0 bellard
            fdctrl_reset(fdctrl, 1);
913 b9b3d225 blueswir1
            fdctrl->dsr &= ~FD_DSR_PWRDOWN;
914 8977f3c1 bellard
        }
915 8977f3c1 bellard
    }
916 8977f3c1 bellard
    /* Selected drive */
917 9fea808a blueswir1
    fdctrl->cur_drv = value & FD_DOR_SELMASK;
918 368df94d blueswir1
919 368df94d blueswir1
    fdctrl->dor = value;
920 8977f3c1 bellard
}
921 8977f3c1 bellard
922 8977f3c1 bellard
/* Tape drive register : 0x03 */
923 baca51fa bellard
static uint32_t fdctrl_read_tape (fdctrl_t *fdctrl)
924 8977f3c1 bellard
{
925 46d3233b blueswir1
    uint32_t retval = fdctrl->tdr;
926 8977f3c1 bellard
927 8977f3c1 bellard
    FLOPPY_DPRINTF("tape drive register: 0x%02x\n", retval);
928 8977f3c1 bellard
929 8977f3c1 bellard
    return retval;
930 8977f3c1 bellard
}
931 8977f3c1 bellard
932 baca51fa bellard
static void fdctrl_write_tape (fdctrl_t *fdctrl, uint32_t value)
933 8977f3c1 bellard
{
934 8977f3c1 bellard
    /* Reset mode */
935 1c346df2 blueswir1
    if (!(fdctrl->dor & FD_DOR_nRESET)) {
936 4b19ec0c bellard
        FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
937 8977f3c1 bellard
        return;
938 8977f3c1 bellard
    }
939 8977f3c1 bellard
    FLOPPY_DPRINTF("tape drive register set to 0x%02x\n", value);
940 8977f3c1 bellard
    /* Disk boot selection indicator */
941 46d3233b blueswir1
    fdctrl->tdr = value & FD_TDR_BOOTSEL;
942 8977f3c1 bellard
    /* Tape indicators: never allow */
943 8977f3c1 bellard
}
944 8977f3c1 bellard
945 8977f3c1 bellard
/* Main status register : 0x04 (read) */
946 baca51fa bellard
static uint32_t fdctrl_read_main_status (fdctrl_t *fdctrl)
947 8977f3c1 bellard
{
948 b9b3d225 blueswir1
    uint32_t retval = fdctrl->msr;
949 8977f3c1 bellard
950 b9b3d225 blueswir1
    fdctrl->dsr &= ~FD_DSR_PWRDOWN;
951 1c346df2 blueswir1
    fdctrl->dor |= FD_DOR_nRESET;
952 b9b3d225 blueswir1
953 8977f3c1 bellard
    FLOPPY_DPRINTF("main status register: 0x%02x\n", retval);
954 8977f3c1 bellard
955 8977f3c1 bellard
    return retval;
956 8977f3c1 bellard
}
957 8977f3c1 bellard
958 8977f3c1 bellard
/* Data select rate register : 0x04 (write) */
959 baca51fa bellard
static void fdctrl_write_rate (fdctrl_t *fdctrl, uint32_t value)
960 8977f3c1 bellard
{
961 8977f3c1 bellard
    /* Reset mode */
962 1c346df2 blueswir1
    if (!(fdctrl->dor & FD_DOR_nRESET)) {
963 4f431960 j_mayer
        FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
964 4f431960 j_mayer
        return;
965 4f431960 j_mayer
    }
966 8977f3c1 bellard
    FLOPPY_DPRINTF("select rate register set to 0x%02x\n", value);
967 8977f3c1 bellard
    /* Reset: autoclear */
968 9fea808a blueswir1
    if (value & FD_DSR_SWRESET) {
969 1c346df2 blueswir1
        fdctrl->dor &= ~FD_DOR_nRESET;
970 baca51fa bellard
        fdctrl_reset(fdctrl, 1);
971 1c346df2 blueswir1
        fdctrl->dor |= FD_DOR_nRESET;
972 8977f3c1 bellard
    }
973 9fea808a blueswir1
    if (value & FD_DSR_PWRDOWN) {
974 baca51fa bellard
        fdctrl_reset(fdctrl, 1);
975 8977f3c1 bellard
    }
976 b9b3d225 blueswir1
    fdctrl->dsr = value;
977 8977f3c1 bellard
}
978 8977f3c1 bellard
979 ea185bbd bellard
static int fdctrl_media_changed(fdrive_t *drv)
980 ea185bbd bellard
{
981 ea185bbd bellard
    int ret;
982 4f431960 j_mayer
983 5fafdf24 ths
    if (!drv->bs)
984 ea185bbd bellard
        return 0;
985 ea185bbd bellard
    ret = bdrv_media_changed(drv->bs);
986 ea185bbd bellard
    if (ret) {
987 ea185bbd bellard
        fd_revalidate(drv);
988 ea185bbd bellard
    }
989 ea185bbd bellard
    return ret;
990 ea185bbd bellard
}
991 ea185bbd bellard
992 8977f3c1 bellard
/* Digital input register : 0x07 (read-only) */
993 baca51fa bellard
static uint32_t fdctrl_read_dir (fdctrl_t *fdctrl)
994 8977f3c1 bellard
{
995 8977f3c1 bellard
    uint32_t retval = 0;
996 8977f3c1 bellard
997 78ae820c blueswir1
    if (fdctrl_media_changed(drv0(fdctrl))
998 78ae820c blueswir1
     || fdctrl_media_changed(drv1(fdctrl))
999 78ae820c blueswir1
#if MAX_FD == 4
1000 78ae820c blueswir1
     || fdctrl_media_changed(drv2(fdctrl))
1001 78ae820c blueswir1
     || fdctrl_media_changed(drv3(fdctrl))
1002 78ae820c blueswir1
#endif
1003 78ae820c blueswir1
        )
1004 9fea808a blueswir1
        retval |= FD_DIR_DSKCHG;
1005 8977f3c1 bellard
    if (retval != 0)
1006 baca51fa bellard
        FLOPPY_DPRINTF("Floppy digital input register: 0x%02x\n", retval);
1007 8977f3c1 bellard
1008 8977f3c1 bellard
    return retval;
1009 8977f3c1 bellard
}
1010 8977f3c1 bellard
1011 8977f3c1 bellard
/* FIFO state control */
1012 baca51fa bellard
static void fdctrl_reset_fifo (fdctrl_t *fdctrl)
1013 8977f3c1 bellard
{
1014 baca51fa bellard
    fdctrl->data_dir = FD_DIR_WRITE;
1015 baca51fa bellard
    fdctrl->data_pos = 0;
1016 b9b3d225 blueswir1
    fdctrl->msr &= ~(FD_MSR_CMDBUSY | FD_MSR_DIO);
1017 8977f3c1 bellard
}
1018 8977f3c1 bellard
1019 8977f3c1 bellard
/* Set FIFO status for the host to read */
1020 baca51fa bellard
static void fdctrl_set_fifo (fdctrl_t *fdctrl, int fifo_len, int do_irq)
1021 8977f3c1 bellard
{
1022 baca51fa bellard
    fdctrl->data_dir = FD_DIR_READ;
1023 baca51fa bellard
    fdctrl->data_len = fifo_len;
1024 baca51fa bellard
    fdctrl->data_pos = 0;
1025 b9b3d225 blueswir1
    fdctrl->msr |= FD_MSR_CMDBUSY | FD_MSR_RQM | FD_MSR_DIO;
1026 8977f3c1 bellard
    if (do_irq)
1027 baca51fa bellard
        fdctrl_raise_irq(fdctrl, 0x00);
1028 8977f3c1 bellard
}
1029 8977f3c1 bellard
1030 8977f3c1 bellard
/* Set an error: unimplemented/unknown command */
1031 65cef780 blueswir1
static void fdctrl_unimplemented (fdctrl_t *fdctrl, int direction)
1032 8977f3c1 bellard
{
1033 77370520 blueswir1
    FLOPPY_ERROR("unimplemented command 0x%02x\n", fdctrl->fifo[0]);
1034 9fea808a blueswir1
    fdctrl->fifo[0] = FD_SR0_INVCMD;
1035 baca51fa bellard
    fdctrl_set_fifo(fdctrl, 1, 0);
1036 8977f3c1 bellard
}
1037 8977f3c1 bellard
1038 746d6de7 blueswir1
/* Seek to next sector */
1039 746d6de7 blueswir1
static int fdctrl_seek_to_next_sect (fdctrl_t *fdctrl, fdrive_t *cur_drv)
1040 746d6de7 blueswir1
{
1041 746d6de7 blueswir1
    FLOPPY_DPRINTF("seek to next sector (%d %02x %02x => %d)\n",
1042 746d6de7 blueswir1
                   cur_drv->head, cur_drv->track, cur_drv->sect,
1043 746d6de7 blueswir1
                   fd_sector(cur_drv));
1044 746d6de7 blueswir1
    /* XXX: cur_drv->sect >= cur_drv->last_sect should be an
1045 746d6de7 blueswir1
       error in fact */
1046 746d6de7 blueswir1
    if (cur_drv->sect >= cur_drv->last_sect ||
1047 746d6de7 blueswir1
        cur_drv->sect == fdctrl->eot) {
1048 746d6de7 blueswir1
        cur_drv->sect = 1;
1049 746d6de7 blueswir1
        if (FD_MULTI_TRACK(fdctrl->data_state)) {
1050 746d6de7 blueswir1
            if (cur_drv->head == 0 &&
1051 746d6de7 blueswir1
                (cur_drv->flags & FDISK_DBL_SIDES) != 0) {
1052 746d6de7 blueswir1
                cur_drv->head = 1;
1053 746d6de7 blueswir1
            } else {
1054 746d6de7 blueswir1
                cur_drv->head = 0;
1055 746d6de7 blueswir1
                cur_drv->track++;
1056 746d6de7 blueswir1
                if ((cur_drv->flags & FDISK_DBL_SIDES) == 0)
1057 746d6de7 blueswir1
                    return 0;
1058 746d6de7 blueswir1
            }
1059 746d6de7 blueswir1
        } else {
1060 746d6de7 blueswir1
            cur_drv->track++;
1061 746d6de7 blueswir1
            return 0;
1062 746d6de7 blueswir1
        }
1063 746d6de7 blueswir1
        FLOPPY_DPRINTF("seek to next track (%d %02x %02x => %d)\n",
1064 746d6de7 blueswir1
                       cur_drv->head, cur_drv->track,
1065 746d6de7 blueswir1
                       cur_drv->sect, fd_sector(cur_drv));
1066 746d6de7 blueswir1
    } else {
1067 746d6de7 blueswir1
        cur_drv->sect++;
1068 746d6de7 blueswir1
    }
1069 746d6de7 blueswir1
    return 1;
1070 746d6de7 blueswir1
}
1071 746d6de7 blueswir1
1072 8977f3c1 bellard
/* Callback for transfer end (stop or abort) */
1073 baca51fa bellard
static void fdctrl_stop_transfer (fdctrl_t *fdctrl, uint8_t status0,
1074 4f431960 j_mayer
                                  uint8_t status1, uint8_t status2)
1075 8977f3c1 bellard
{
1076 baca51fa bellard
    fdrive_t *cur_drv;
1077 8977f3c1 bellard
1078 baca51fa bellard
    cur_drv = get_cur_drv(fdctrl);
1079 8977f3c1 bellard
    FLOPPY_DPRINTF("transfer status: %02x %02x %02x (%02x)\n",
1080 8977f3c1 bellard
                   status0, status1, status2,
1081 cefec4f5 blueswir1
                   status0 | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl));
1082 cefec4f5 blueswir1
    fdctrl->fifo[0] = status0 | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1083 baca51fa bellard
    fdctrl->fifo[1] = status1;
1084 baca51fa bellard
    fdctrl->fifo[2] = status2;
1085 baca51fa bellard
    fdctrl->fifo[3] = cur_drv->track;
1086 baca51fa bellard
    fdctrl->fifo[4] = cur_drv->head;
1087 baca51fa bellard
    fdctrl->fifo[5] = cur_drv->sect;
1088 baca51fa bellard
    fdctrl->fifo[6] = FD_SECTOR_SC;
1089 baca51fa bellard
    fdctrl->data_dir = FD_DIR_READ;
1090 368df94d blueswir1
    if (!(fdctrl->msr & FD_MSR_NONDMA)) {
1091 baca51fa bellard
        DMA_release_DREQ(fdctrl->dma_chann);
1092 ed5fd2cc bellard
    }
1093 b9b3d225 blueswir1
    fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
1094 368df94d blueswir1
    fdctrl->msr &= ~FD_MSR_NONDMA;
1095 baca51fa bellard
    fdctrl_set_fifo(fdctrl, 7, 1);
1096 8977f3c1 bellard
}
1097 8977f3c1 bellard
1098 8977f3c1 bellard
/* Prepare a data transfer (either DMA or FIFO) */
1099 baca51fa bellard
static void fdctrl_start_transfer (fdctrl_t *fdctrl, int direction)
1100 8977f3c1 bellard
{
1101 baca51fa bellard
    fdrive_t *cur_drv;
1102 8977f3c1 bellard
    uint8_t kh, kt, ks;
1103 77370520 blueswir1
    int did_seek = 0;
1104 8977f3c1 bellard
1105 cefec4f5 blueswir1
    SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1106 baca51fa bellard
    cur_drv = get_cur_drv(fdctrl);
1107 baca51fa bellard
    kt = fdctrl->fifo[2];
1108 baca51fa bellard
    kh = fdctrl->fifo[3];
1109 baca51fa bellard
    ks = fdctrl->fifo[4];
1110 4b19ec0c bellard
    FLOPPY_DPRINTF("Start transfer at %d %d %02x %02x (%d)\n",
1111 cefec4f5 blueswir1
                   GET_CUR_DRV(fdctrl), kh, kt, ks,
1112 8977f3c1 bellard
                   _fd_sector(kh, kt, ks, cur_drv->last_sect));
1113 77370520 blueswir1
    switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
1114 8977f3c1 bellard
    case 2:
1115 8977f3c1 bellard
        /* sect too big */
1116 9fea808a blueswir1
        fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1117 baca51fa bellard
        fdctrl->fifo[3] = kt;
1118 baca51fa bellard
        fdctrl->fifo[4] = kh;
1119 baca51fa bellard
        fdctrl->fifo[5] = ks;
1120 8977f3c1 bellard
        return;
1121 8977f3c1 bellard
    case 3:
1122 8977f3c1 bellard
        /* track too big */
1123 77370520 blueswir1
        fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
1124 baca51fa bellard
        fdctrl->fifo[3] = kt;
1125 baca51fa bellard
        fdctrl->fifo[4] = kh;
1126 baca51fa bellard
        fdctrl->fifo[5] = ks;
1127 8977f3c1 bellard
        return;
1128 8977f3c1 bellard
    case 4:
1129 8977f3c1 bellard
        /* No seek enabled */
1130 9fea808a blueswir1
        fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1131 baca51fa bellard
        fdctrl->fifo[3] = kt;
1132 baca51fa bellard
        fdctrl->fifo[4] = kh;
1133 baca51fa bellard
        fdctrl->fifo[5] = ks;
1134 8977f3c1 bellard
        return;
1135 8977f3c1 bellard
    case 1:
1136 8977f3c1 bellard
        did_seek = 1;
1137 8977f3c1 bellard
        break;
1138 8977f3c1 bellard
    default:
1139 8977f3c1 bellard
        break;
1140 8977f3c1 bellard
    }
1141 b9b3d225 blueswir1
1142 8977f3c1 bellard
    /* Set the FIFO state */
1143 baca51fa bellard
    fdctrl->data_dir = direction;
1144 baca51fa bellard
    fdctrl->data_pos = 0;
1145 b9b3d225 blueswir1
    fdctrl->msr |= FD_MSR_CMDBUSY;
1146 baca51fa bellard
    if (fdctrl->fifo[0] & 0x80)
1147 baca51fa bellard
        fdctrl->data_state |= FD_STATE_MULTI;
1148 baca51fa bellard
    else
1149 baca51fa bellard
        fdctrl->data_state &= ~FD_STATE_MULTI;
1150 8977f3c1 bellard
    if (did_seek)
1151 baca51fa bellard
        fdctrl->data_state |= FD_STATE_SEEK;
1152 baca51fa bellard
    else
1153 baca51fa bellard
        fdctrl->data_state &= ~FD_STATE_SEEK;
1154 baca51fa bellard
    if (fdctrl->fifo[5] == 00) {
1155 baca51fa bellard
        fdctrl->data_len = fdctrl->fifo[8];
1156 baca51fa bellard
    } else {
1157 4f431960 j_mayer
        int tmp;
1158 3bcb80f1 ths
        fdctrl->data_len = 128 << (fdctrl->fifo[5] > 7 ? 7 : fdctrl->fifo[5]);
1159 771effeb blueswir1
        tmp = (fdctrl->fifo[6] - ks + 1);
1160 baca51fa bellard
        if (fdctrl->fifo[0] & 0x80)
1161 771effeb blueswir1
            tmp += fdctrl->fifo[6];
1162 4f431960 j_mayer
        fdctrl->data_len *= tmp;
1163 baca51fa bellard
    }
1164 890fa6be bellard
    fdctrl->eot = fdctrl->fifo[6];
1165 368df94d blueswir1
    if (fdctrl->dor & FD_DOR_DMAEN) {
1166 8977f3c1 bellard
        int dma_mode;
1167 8977f3c1 bellard
        /* DMA transfer are enabled. Check if DMA channel is well programmed */
1168 baca51fa bellard
        dma_mode = DMA_get_channel_mode(fdctrl->dma_chann);
1169 8977f3c1 bellard
        dma_mode = (dma_mode >> 2) & 3;
1170 baca51fa bellard
        FLOPPY_DPRINTF("dma_mode=%d direction=%d (%d - %d)\n",
1171 4f431960 j_mayer
                       dma_mode, direction,
1172 baca51fa bellard
                       (128 << fdctrl->fifo[5]) *
1173 4f431960 j_mayer
                       (cur_drv->last_sect - ks + 1), fdctrl->data_len);
1174 8977f3c1 bellard
        if (((direction == FD_DIR_SCANE || direction == FD_DIR_SCANL ||
1175 8977f3c1 bellard
              direction == FD_DIR_SCANH) && dma_mode == 0) ||
1176 8977f3c1 bellard
            (direction == FD_DIR_WRITE && dma_mode == 2) ||
1177 8977f3c1 bellard
            (direction == FD_DIR_READ && dma_mode == 1)) {
1178 8977f3c1 bellard
            /* No access is allowed until DMA transfer has completed */
1179 b9b3d225 blueswir1
            fdctrl->msr &= ~FD_MSR_RQM;
1180 4b19ec0c bellard
            /* Now, we just have to wait for the DMA controller to
1181 8977f3c1 bellard
             * recall us...
1182 8977f3c1 bellard
             */
1183 baca51fa bellard
            DMA_hold_DREQ(fdctrl->dma_chann);
1184 baca51fa bellard
            DMA_schedule(fdctrl->dma_chann);
1185 8977f3c1 bellard
            return;
1186 baca51fa bellard
        } else {
1187 4f431960 j_mayer
            FLOPPY_ERROR("dma_mode=%d direction=%d\n", dma_mode, direction);
1188 8977f3c1 bellard
        }
1189 8977f3c1 bellard
    }
1190 8977f3c1 bellard
    FLOPPY_DPRINTF("start non-DMA transfer\n");
1191 368df94d blueswir1
    fdctrl->msr |= FD_MSR_NONDMA;
1192 b9b3d225 blueswir1
    if (direction != FD_DIR_WRITE)
1193 b9b3d225 blueswir1
        fdctrl->msr |= FD_MSR_DIO;
1194 8977f3c1 bellard
    /* IO based transfer: calculate len */
1195 baca51fa bellard
    fdctrl_raise_irq(fdctrl, 0x00);
1196 8977f3c1 bellard
1197 8977f3c1 bellard
    return;
1198 8977f3c1 bellard
}
1199 8977f3c1 bellard
1200 8977f3c1 bellard
/* Prepare a transfer of deleted data */
1201 baca51fa bellard
static void fdctrl_start_transfer_del (fdctrl_t *fdctrl, int direction)
1202 8977f3c1 bellard
{
1203 77370520 blueswir1
    FLOPPY_ERROR("fdctrl_start_transfer_del() unimplemented\n");
1204 77370520 blueswir1
1205 8977f3c1 bellard
    /* We don't handle deleted data,
1206 8977f3c1 bellard
     * so we don't return *ANYTHING*
1207 8977f3c1 bellard
     */
1208 9fea808a blueswir1
    fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1209 8977f3c1 bellard
}
1210 8977f3c1 bellard
1211 8977f3c1 bellard
/* handlers for DMA transfers */
1212 85571bc7 bellard
static int fdctrl_transfer_handler (void *opaque, int nchan,
1213 85571bc7 bellard
                                    int dma_pos, int dma_len)
1214 8977f3c1 bellard
{
1215 baca51fa bellard
    fdctrl_t *fdctrl;
1216 baca51fa bellard
    fdrive_t *cur_drv;
1217 baca51fa bellard
    int len, start_pos, rel_pos;
1218 8977f3c1 bellard
    uint8_t status0 = 0x00, status1 = 0x00, status2 = 0x00;
1219 8977f3c1 bellard
1220 baca51fa bellard
    fdctrl = opaque;
1221 b9b3d225 blueswir1
    if (fdctrl->msr & FD_MSR_RQM) {
1222 8977f3c1 bellard
        FLOPPY_DPRINTF("Not in DMA transfer mode !\n");
1223 8977f3c1 bellard
        return 0;
1224 8977f3c1 bellard
    }
1225 baca51fa bellard
    cur_drv = get_cur_drv(fdctrl);
1226 baca51fa bellard
    if (fdctrl->data_dir == FD_DIR_SCANE || fdctrl->data_dir == FD_DIR_SCANL ||
1227 baca51fa bellard
        fdctrl->data_dir == FD_DIR_SCANH)
1228 77370520 blueswir1
        status2 = FD_SR2_SNS;
1229 85571bc7 bellard
    if (dma_len > fdctrl->data_len)
1230 85571bc7 bellard
        dma_len = fdctrl->data_len;
1231 890fa6be bellard
    if (cur_drv->bs == NULL) {
1232 4f431960 j_mayer
        if (fdctrl->data_dir == FD_DIR_WRITE)
1233 9fea808a blueswir1
            fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1234 4f431960 j_mayer
        else
1235 9fea808a blueswir1
            fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1236 4f431960 j_mayer
        len = 0;
1237 890fa6be bellard
        goto transfer_error;
1238 890fa6be bellard
    }
1239 baca51fa bellard
    rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1240 85571bc7 bellard
    for (start_pos = fdctrl->data_pos; fdctrl->data_pos < dma_len;) {
1241 85571bc7 bellard
        len = dma_len - fdctrl->data_pos;
1242 baca51fa bellard
        if (len + rel_pos > FD_SECTOR_LEN)
1243 baca51fa bellard
            len = FD_SECTOR_LEN - rel_pos;
1244 6f7e9aec bellard
        FLOPPY_DPRINTF("copy %d bytes (%d %d %d) %d pos %d %02x "
1245 6f7e9aec bellard
                       "(%d-0x%08x 0x%08x)\n", len, dma_len, fdctrl->data_pos,
1246 cefec4f5 blueswir1
                       fdctrl->data_len, GET_CUR_DRV(fdctrl), cur_drv->head,
1247 baca51fa bellard
                       cur_drv->track, cur_drv->sect, fd_sector(cur_drv),
1248 9fea808a blueswir1
                       fd_sector(cur_drv) * FD_SECTOR_LEN);
1249 baca51fa bellard
        if (fdctrl->data_dir != FD_DIR_WRITE ||
1250 4f431960 j_mayer
            len < FD_SECTOR_LEN || rel_pos != 0) {
1251 baca51fa bellard
            /* READ & SCAN commands and realign to a sector for WRITE */
1252 baca51fa bellard
            if (bdrv_read(cur_drv->bs, fd_sector(cur_drv),
1253 4f431960 j_mayer
                          fdctrl->fifo, 1) < 0) {
1254 8977f3c1 bellard
                FLOPPY_DPRINTF("Floppy: error getting sector %d\n",
1255 8977f3c1 bellard
                               fd_sector(cur_drv));
1256 8977f3c1 bellard
                /* Sure, image size is too small... */
1257 baca51fa bellard
                memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1258 8977f3c1 bellard
            }
1259 890fa6be bellard
        }
1260 4f431960 j_mayer
        switch (fdctrl->data_dir) {
1261 4f431960 j_mayer
        case FD_DIR_READ:
1262 4f431960 j_mayer
            /* READ commands */
1263 85571bc7 bellard
            DMA_write_memory (nchan, fdctrl->fifo + rel_pos,
1264 85571bc7 bellard
                              fdctrl->data_pos, len);
1265 4f431960 j_mayer
            break;
1266 4f431960 j_mayer
        case FD_DIR_WRITE:
1267 baca51fa bellard
            /* WRITE commands */
1268 85571bc7 bellard
            DMA_read_memory (nchan, fdctrl->fifo + rel_pos,
1269 85571bc7 bellard
                             fdctrl->data_pos, len);
1270 baca51fa bellard
            if (bdrv_write(cur_drv->bs, fd_sector(cur_drv),
1271 4f431960 j_mayer
                           fdctrl->fifo, 1) < 0) {
1272 77370520 blueswir1
                FLOPPY_ERROR("writing sector %d\n", fd_sector(cur_drv));
1273 9fea808a blueswir1
                fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1274 baca51fa bellard
                goto transfer_error;
1275 890fa6be bellard
            }
1276 4f431960 j_mayer
            break;
1277 4f431960 j_mayer
        default:
1278 4f431960 j_mayer
            /* SCAN commands */
1279 baca51fa bellard
            {
1280 4f431960 j_mayer
                uint8_t tmpbuf[FD_SECTOR_LEN];
1281 baca51fa bellard
                int ret;
1282 85571bc7 bellard
                DMA_read_memory (nchan, tmpbuf, fdctrl->data_pos, len);
1283 baca51fa bellard
                ret = memcmp(tmpbuf, fdctrl->fifo + rel_pos, len);
1284 8977f3c1 bellard
                if (ret == 0) {
1285 77370520 blueswir1
                    status2 = FD_SR2_SEH;
1286 8977f3c1 bellard
                    goto end_transfer;
1287 8977f3c1 bellard
                }
1288 baca51fa bellard
                if ((ret < 0 && fdctrl->data_dir == FD_DIR_SCANL) ||
1289 baca51fa bellard
                    (ret > 0 && fdctrl->data_dir == FD_DIR_SCANH)) {
1290 8977f3c1 bellard
                    status2 = 0x00;
1291 8977f3c1 bellard
                    goto end_transfer;
1292 8977f3c1 bellard
                }
1293 8977f3c1 bellard
            }
1294 4f431960 j_mayer
            break;
1295 8977f3c1 bellard
        }
1296 4f431960 j_mayer
        fdctrl->data_pos += len;
1297 4f431960 j_mayer
        rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1298 baca51fa bellard
        if (rel_pos == 0) {
1299 8977f3c1 bellard
            /* Seek to next sector */
1300 746d6de7 blueswir1
            if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv))
1301 746d6de7 blueswir1
                break;
1302 8977f3c1 bellard
        }
1303 8977f3c1 bellard
    }
1304 4f431960 j_mayer
 end_transfer:
1305 baca51fa bellard
    len = fdctrl->data_pos - start_pos;
1306 baca51fa bellard
    FLOPPY_DPRINTF("end transfer %d %d %d\n",
1307 4f431960 j_mayer
                   fdctrl->data_pos, len, fdctrl->data_len);
1308 baca51fa bellard
    if (fdctrl->data_dir == FD_DIR_SCANE ||
1309 baca51fa bellard
        fdctrl->data_dir == FD_DIR_SCANL ||
1310 baca51fa bellard
        fdctrl->data_dir == FD_DIR_SCANH)
1311 77370520 blueswir1
        status2 = FD_SR2_SEH;
1312 baca51fa bellard
    if (FD_DID_SEEK(fdctrl->data_state))
1313 9fea808a blueswir1
        status0 |= FD_SR0_SEEK;
1314 baca51fa bellard
    fdctrl->data_len -= len;
1315 890fa6be bellard
    fdctrl_stop_transfer(fdctrl, status0, status1, status2);
1316 4f431960 j_mayer
 transfer_error:
1317 8977f3c1 bellard
1318 baca51fa bellard
    return len;
1319 8977f3c1 bellard
}
1320 8977f3c1 bellard
1321 8977f3c1 bellard
/* Data register : 0x05 */
1322 baca51fa bellard
static uint32_t fdctrl_read_data (fdctrl_t *fdctrl)
1323 8977f3c1 bellard
{
1324 baca51fa bellard
    fdrive_t *cur_drv;
1325 8977f3c1 bellard
    uint32_t retval = 0;
1326 746d6de7 blueswir1
    int pos;
1327 8977f3c1 bellard
1328 baca51fa bellard
    cur_drv = get_cur_drv(fdctrl);
1329 b9b3d225 blueswir1
    fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1330 b9b3d225 blueswir1
    if (!(fdctrl->msr & FD_MSR_RQM) || !(fdctrl->msr & FD_MSR_DIO)) {
1331 b9b3d225 blueswir1
        FLOPPY_ERROR("controller not ready for reading\n");
1332 8977f3c1 bellard
        return 0;
1333 8977f3c1 bellard
    }
1334 baca51fa bellard
    pos = fdctrl->data_pos;
1335 368df94d blueswir1
    if (fdctrl->msr & FD_MSR_NONDMA) {
1336 8977f3c1 bellard
        pos %= FD_SECTOR_LEN;
1337 8977f3c1 bellard
        if (pos == 0) {
1338 746d6de7 blueswir1
            if (fdctrl->data_pos != 0)
1339 746d6de7 blueswir1
                if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1340 746d6de7 blueswir1
                    FLOPPY_DPRINTF("error seeking to next sector %d\n",
1341 746d6de7 blueswir1
                                   fd_sector(cur_drv));
1342 746d6de7 blueswir1
                    return 0;
1343 746d6de7 blueswir1
                }
1344 77370520 blueswir1
            if (bdrv_read(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1345 77370520 blueswir1
                FLOPPY_DPRINTF("error getting sector %d\n",
1346 77370520 blueswir1
                               fd_sector(cur_drv));
1347 77370520 blueswir1
                /* Sure, image size is too small... */
1348 77370520 blueswir1
                memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1349 77370520 blueswir1
            }
1350 8977f3c1 bellard
        }
1351 8977f3c1 bellard
    }
1352 baca51fa bellard
    retval = fdctrl->fifo[pos];
1353 baca51fa bellard
    if (++fdctrl->data_pos == fdctrl->data_len) {
1354 baca51fa bellard
        fdctrl->data_pos = 0;
1355 890fa6be bellard
        /* Switch from transfer mode to status mode
1356 8977f3c1 bellard
         * then from status mode to command mode
1357 8977f3c1 bellard
         */
1358 368df94d blueswir1
        if (fdctrl->msr & FD_MSR_NONDMA) {
1359 9fea808a blueswir1
            fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1360 ed5fd2cc bellard
        } else {
1361 baca51fa bellard
            fdctrl_reset_fifo(fdctrl);
1362 ed5fd2cc bellard
            fdctrl_reset_irq(fdctrl);
1363 ed5fd2cc bellard
        }
1364 8977f3c1 bellard
    }
1365 8977f3c1 bellard
    FLOPPY_DPRINTF("data register: 0x%02x\n", retval);
1366 8977f3c1 bellard
1367 8977f3c1 bellard
    return retval;
1368 8977f3c1 bellard
}
1369 8977f3c1 bellard
1370 baca51fa bellard
static void fdctrl_format_sector (fdctrl_t *fdctrl)
1371 8977f3c1 bellard
{
1372 baca51fa bellard
    fdrive_t *cur_drv;
1373 baca51fa bellard
    uint8_t kh, kt, ks;
1374 8977f3c1 bellard
1375 cefec4f5 blueswir1
    SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1376 baca51fa bellard
    cur_drv = get_cur_drv(fdctrl);
1377 baca51fa bellard
    kt = fdctrl->fifo[6];
1378 baca51fa bellard
    kh = fdctrl->fifo[7];
1379 baca51fa bellard
    ks = fdctrl->fifo[8];
1380 baca51fa bellard
    FLOPPY_DPRINTF("format sector at %d %d %02x %02x (%d)\n",
1381 cefec4f5 blueswir1
                   GET_CUR_DRV(fdctrl), kh, kt, ks,
1382 baca51fa bellard
                   _fd_sector(kh, kt, ks, cur_drv->last_sect));
1383 9fea808a blueswir1
    switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
1384 baca51fa bellard
    case 2:
1385 baca51fa bellard
        /* sect too big */
1386 9fea808a blueswir1
        fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1387 baca51fa bellard
        fdctrl->fifo[3] = kt;
1388 baca51fa bellard
        fdctrl->fifo[4] = kh;
1389 baca51fa bellard
        fdctrl->fifo[5] = ks;
1390 baca51fa bellard
        return;
1391 baca51fa bellard
    case 3:
1392 baca51fa bellard
        /* track too big */
1393 77370520 blueswir1
        fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
1394 baca51fa bellard
        fdctrl->fifo[3] = kt;
1395 baca51fa bellard
        fdctrl->fifo[4] = kh;
1396 baca51fa bellard
        fdctrl->fifo[5] = ks;
1397 baca51fa bellard
        return;
1398 baca51fa bellard
    case 4:
1399 baca51fa bellard
        /* No seek enabled */
1400 9fea808a blueswir1
        fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1401 baca51fa bellard
        fdctrl->fifo[3] = kt;
1402 baca51fa bellard
        fdctrl->fifo[4] = kh;
1403 baca51fa bellard
        fdctrl->fifo[5] = ks;
1404 baca51fa bellard
        return;
1405 baca51fa bellard
    case 1:
1406 baca51fa bellard
        fdctrl->data_state |= FD_STATE_SEEK;
1407 baca51fa bellard
        break;
1408 baca51fa bellard
    default:
1409 baca51fa bellard
        break;
1410 baca51fa bellard
    }
1411 baca51fa bellard
    memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1412 baca51fa bellard
    if (cur_drv->bs == NULL ||
1413 baca51fa bellard
        bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1414 37a4c539 ths
        FLOPPY_ERROR("formatting sector %d\n", fd_sector(cur_drv));
1415 9fea808a blueswir1
        fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1416 baca51fa bellard
    } else {
1417 4f431960 j_mayer
        if (cur_drv->sect == cur_drv->last_sect) {
1418 4f431960 j_mayer
            fdctrl->data_state &= ~FD_STATE_FORMAT;
1419 4f431960 j_mayer
            /* Last sector done */
1420 4f431960 j_mayer
            if (FD_DID_SEEK(fdctrl->data_state))
1421 9fea808a blueswir1
                fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1422 4f431960 j_mayer
            else
1423 4f431960 j_mayer
                fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1424 4f431960 j_mayer
        } else {
1425 4f431960 j_mayer
            /* More to do */
1426 4f431960 j_mayer
            fdctrl->data_pos = 0;
1427 4f431960 j_mayer
            fdctrl->data_len = 4;
1428 4f431960 j_mayer
        }
1429 baca51fa bellard
    }
1430 baca51fa bellard
}
1431 baca51fa bellard
1432 65cef780 blueswir1
static void fdctrl_handle_lock (fdctrl_t *fdctrl, int direction)
1433 65cef780 blueswir1
{
1434 65cef780 blueswir1
    fdctrl->lock = (fdctrl->fifo[0] & 0x80) ? 1 : 0;
1435 65cef780 blueswir1
    fdctrl->fifo[0] = fdctrl->lock << 4;
1436 65cef780 blueswir1
    fdctrl_set_fifo(fdctrl, 1, fdctrl->lock);
1437 65cef780 blueswir1
}
1438 65cef780 blueswir1
1439 65cef780 blueswir1
static void fdctrl_handle_dumpreg (fdctrl_t *fdctrl, int direction)
1440 65cef780 blueswir1
{
1441 65cef780 blueswir1
    fdrive_t *cur_drv = get_cur_drv(fdctrl);
1442 65cef780 blueswir1
1443 65cef780 blueswir1
    /* Drives position */
1444 65cef780 blueswir1
    fdctrl->fifo[0] = drv0(fdctrl)->track;
1445 65cef780 blueswir1
    fdctrl->fifo[1] = drv1(fdctrl)->track;
1446 78ae820c blueswir1
#if MAX_FD == 4
1447 78ae820c blueswir1
    fdctrl->fifo[2] = drv2(fdctrl)->track;
1448 78ae820c blueswir1
    fdctrl->fifo[3] = drv3(fdctrl)->track;
1449 78ae820c blueswir1
#else
1450 65cef780 blueswir1
    fdctrl->fifo[2] = 0;
1451 65cef780 blueswir1
    fdctrl->fifo[3] = 0;
1452 78ae820c blueswir1
#endif
1453 65cef780 blueswir1
    /* timers */
1454 65cef780 blueswir1
    fdctrl->fifo[4] = fdctrl->timer0;
1455 368df94d blueswir1
    fdctrl->fifo[5] = (fdctrl->timer1 << 1) | (fdctrl->dor & FD_DOR_DMAEN ? 1 : 0);
1456 65cef780 blueswir1
    fdctrl->fifo[6] = cur_drv->last_sect;
1457 65cef780 blueswir1
    fdctrl->fifo[7] = (fdctrl->lock << 7) |
1458 65cef780 blueswir1
        (cur_drv->perpendicular << 2);
1459 65cef780 blueswir1
    fdctrl->fifo[8] = fdctrl->config;
1460 65cef780 blueswir1
    fdctrl->fifo[9] = fdctrl->precomp_trk;
1461 65cef780 blueswir1
    fdctrl_set_fifo(fdctrl, 10, 0);
1462 65cef780 blueswir1
}
1463 65cef780 blueswir1
1464 65cef780 blueswir1
static void fdctrl_handle_version (fdctrl_t *fdctrl, int direction)
1465 65cef780 blueswir1
{
1466 65cef780 blueswir1
    /* Controller's version */
1467 65cef780 blueswir1
    fdctrl->fifo[0] = fdctrl->version;
1468 65cef780 blueswir1
    fdctrl_set_fifo(fdctrl, 1, 1);
1469 65cef780 blueswir1
}
1470 65cef780 blueswir1
1471 65cef780 blueswir1
static void fdctrl_handle_partid (fdctrl_t *fdctrl, int direction)
1472 65cef780 blueswir1
{
1473 65cef780 blueswir1
    fdctrl->fifo[0] = 0x41; /* Stepping 1 */
1474 65cef780 blueswir1
    fdctrl_set_fifo(fdctrl, 1, 0);
1475 65cef780 blueswir1
}
1476 65cef780 blueswir1
1477 65cef780 blueswir1
static void fdctrl_handle_restore (fdctrl_t *fdctrl, int direction)
1478 65cef780 blueswir1
{
1479 65cef780 blueswir1
    fdrive_t *cur_drv = get_cur_drv(fdctrl);
1480 65cef780 blueswir1
1481 65cef780 blueswir1
    /* Drives position */
1482 65cef780 blueswir1
    drv0(fdctrl)->track = fdctrl->fifo[3];
1483 65cef780 blueswir1
    drv1(fdctrl)->track = fdctrl->fifo[4];
1484 78ae820c blueswir1
#if MAX_FD == 4
1485 78ae820c blueswir1
    drv2(fdctrl)->track = fdctrl->fifo[5];
1486 78ae820c blueswir1
    drv3(fdctrl)->track = fdctrl->fifo[6];
1487 78ae820c blueswir1
#endif
1488 65cef780 blueswir1
    /* timers */
1489 65cef780 blueswir1
    fdctrl->timer0 = fdctrl->fifo[7];
1490 65cef780 blueswir1
    fdctrl->timer1 = fdctrl->fifo[8];
1491 65cef780 blueswir1
    cur_drv->last_sect = fdctrl->fifo[9];
1492 65cef780 blueswir1
    fdctrl->lock = fdctrl->fifo[10] >> 7;
1493 65cef780 blueswir1
    cur_drv->perpendicular = (fdctrl->fifo[10] >> 2) & 0xF;
1494 65cef780 blueswir1
    fdctrl->config = fdctrl->fifo[11];
1495 65cef780 blueswir1
    fdctrl->precomp_trk = fdctrl->fifo[12];
1496 65cef780 blueswir1
    fdctrl->pwrd = fdctrl->fifo[13];
1497 65cef780 blueswir1
    fdctrl_reset_fifo(fdctrl);
1498 65cef780 blueswir1
}
1499 65cef780 blueswir1
1500 65cef780 blueswir1
static void fdctrl_handle_save (fdctrl_t *fdctrl, int direction)
1501 65cef780 blueswir1
{
1502 65cef780 blueswir1
    fdrive_t *cur_drv = get_cur_drv(fdctrl);
1503 65cef780 blueswir1
1504 65cef780 blueswir1
    fdctrl->fifo[0] = 0;
1505 65cef780 blueswir1
    fdctrl->fifo[1] = 0;
1506 65cef780 blueswir1
    /* Drives position */
1507 65cef780 blueswir1
    fdctrl->fifo[2] = drv0(fdctrl)->track;
1508 65cef780 blueswir1
    fdctrl->fifo[3] = drv1(fdctrl)->track;
1509 78ae820c blueswir1
#if MAX_FD == 4
1510 78ae820c blueswir1
    fdctrl->fifo[4] = drv2(fdctrl)->track;
1511 78ae820c blueswir1
    fdctrl->fifo[5] = drv3(fdctrl)->track;
1512 78ae820c blueswir1
#else
1513 65cef780 blueswir1
    fdctrl->fifo[4] = 0;
1514 65cef780 blueswir1
    fdctrl->fifo[5] = 0;
1515 78ae820c blueswir1
#endif
1516 65cef780 blueswir1
    /* timers */
1517 65cef780 blueswir1
    fdctrl->fifo[6] = fdctrl->timer0;
1518 65cef780 blueswir1
    fdctrl->fifo[7] = fdctrl->timer1;
1519 65cef780 blueswir1
    fdctrl->fifo[8] = cur_drv->last_sect;
1520 65cef780 blueswir1
    fdctrl->fifo[9] = (fdctrl->lock << 7) |
1521 65cef780 blueswir1
        (cur_drv->perpendicular << 2);
1522 65cef780 blueswir1
    fdctrl->fifo[10] = fdctrl->config;
1523 65cef780 blueswir1
    fdctrl->fifo[11] = fdctrl->precomp_trk;
1524 65cef780 blueswir1
    fdctrl->fifo[12] = fdctrl->pwrd;
1525 65cef780 blueswir1
    fdctrl->fifo[13] = 0;
1526 65cef780 blueswir1
    fdctrl->fifo[14] = 0;
1527 65cef780 blueswir1
    fdctrl_set_fifo(fdctrl, 15, 1);
1528 65cef780 blueswir1
}
1529 65cef780 blueswir1
1530 65cef780 blueswir1
static void fdctrl_handle_readid (fdctrl_t *fdctrl, int direction)
1531 65cef780 blueswir1
{
1532 65cef780 blueswir1
    fdrive_t *cur_drv = get_cur_drv(fdctrl);
1533 65cef780 blueswir1
1534 65cef780 blueswir1
    /* XXX: should set main status register to busy */
1535 65cef780 blueswir1
    cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
1536 65cef780 blueswir1
    qemu_mod_timer(fdctrl->result_timer,
1537 65cef780 blueswir1
                   qemu_get_clock(vm_clock) + (ticks_per_sec / 50));
1538 65cef780 blueswir1
}
1539 65cef780 blueswir1
1540 65cef780 blueswir1
static void fdctrl_handle_format_track (fdctrl_t *fdctrl, int direction)
1541 65cef780 blueswir1
{
1542 65cef780 blueswir1
    fdrive_t *cur_drv;
1543 65cef780 blueswir1
1544 cefec4f5 blueswir1
    SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1545 65cef780 blueswir1
    cur_drv = get_cur_drv(fdctrl);
1546 65cef780 blueswir1
    fdctrl->data_state |= FD_STATE_FORMAT;
1547 65cef780 blueswir1
    if (fdctrl->fifo[0] & 0x80)
1548 65cef780 blueswir1
        fdctrl->data_state |= FD_STATE_MULTI;
1549 65cef780 blueswir1
    else
1550 65cef780 blueswir1
        fdctrl->data_state &= ~FD_STATE_MULTI;
1551 65cef780 blueswir1
    fdctrl->data_state &= ~FD_STATE_SEEK;
1552 65cef780 blueswir1
    cur_drv->bps =
1553 65cef780 blueswir1
        fdctrl->fifo[2] > 7 ? 16384 : 128 << fdctrl->fifo[2];
1554 65cef780 blueswir1
#if 0
1555 65cef780 blueswir1
    cur_drv->last_sect =
1556 65cef780 blueswir1
        cur_drv->flags & FDISK_DBL_SIDES ? fdctrl->fifo[3] :
1557 65cef780 blueswir1
        fdctrl->fifo[3] / 2;
1558 65cef780 blueswir1
#else
1559 65cef780 blueswir1
    cur_drv->last_sect = fdctrl->fifo[3];
1560 65cef780 blueswir1
#endif
1561 65cef780 blueswir1
    /* TODO: implement format using DMA expected by the Bochs BIOS
1562 65cef780 blueswir1
     * and Linux fdformat (read 3 bytes per sector via DMA and fill
1563 65cef780 blueswir1
     * the sector with the specified fill byte
1564 65cef780 blueswir1
     */
1565 65cef780 blueswir1
    fdctrl->data_state &= ~FD_STATE_FORMAT;
1566 65cef780 blueswir1
    fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1567 65cef780 blueswir1
}
1568 65cef780 blueswir1
1569 65cef780 blueswir1
static void fdctrl_handle_specify (fdctrl_t *fdctrl, int direction)
1570 65cef780 blueswir1
{
1571 65cef780 blueswir1
    fdctrl->timer0 = (fdctrl->fifo[1] >> 4) & 0xF;
1572 65cef780 blueswir1
    fdctrl->timer1 = fdctrl->fifo[2] >> 1;
1573 368df94d blueswir1
    if (fdctrl->fifo[2] & 1)
1574 368df94d blueswir1
        fdctrl->dor &= ~FD_DOR_DMAEN;
1575 368df94d blueswir1
    else
1576 368df94d blueswir1
        fdctrl->dor |= FD_DOR_DMAEN;
1577 65cef780 blueswir1
    /* No result back */
1578 65cef780 blueswir1
    fdctrl_reset_fifo(fdctrl);
1579 65cef780 blueswir1
}
1580 65cef780 blueswir1
1581 65cef780 blueswir1
static void fdctrl_handle_sense_drive_status (fdctrl_t *fdctrl, int direction)
1582 65cef780 blueswir1
{
1583 65cef780 blueswir1
    fdrive_t *cur_drv;
1584 65cef780 blueswir1
1585 cefec4f5 blueswir1
    SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1586 65cef780 blueswir1
    cur_drv = get_cur_drv(fdctrl);
1587 65cef780 blueswir1
    cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
1588 65cef780 blueswir1
    /* 1 Byte status back */
1589 65cef780 blueswir1
    fdctrl->fifo[0] = (cur_drv->ro << 6) |
1590 65cef780 blueswir1
        (cur_drv->track == 0 ? 0x10 : 0x00) |
1591 65cef780 blueswir1
        (cur_drv->head << 2) |
1592 cefec4f5 blueswir1
        GET_CUR_DRV(fdctrl) |
1593 65cef780 blueswir1
        0x28;
1594 65cef780 blueswir1
    fdctrl_set_fifo(fdctrl, 1, 0);
1595 65cef780 blueswir1
}
1596 65cef780 blueswir1
1597 65cef780 blueswir1
static void fdctrl_handle_recalibrate (fdctrl_t *fdctrl, int direction)
1598 65cef780 blueswir1
{
1599 65cef780 blueswir1
    fdrive_t *cur_drv;
1600 65cef780 blueswir1
1601 cefec4f5 blueswir1
    SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1602 65cef780 blueswir1
    cur_drv = get_cur_drv(fdctrl);
1603 65cef780 blueswir1
    fd_recalibrate(cur_drv);
1604 65cef780 blueswir1
    fdctrl_reset_fifo(fdctrl);
1605 65cef780 blueswir1
    /* Raise Interrupt */
1606 65cef780 blueswir1
    fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1607 65cef780 blueswir1
}
1608 65cef780 blueswir1
1609 65cef780 blueswir1
static void fdctrl_handle_sense_interrupt_status (fdctrl_t *fdctrl, int direction)
1610 65cef780 blueswir1
{
1611 65cef780 blueswir1
    fdrive_t *cur_drv = get_cur_drv(fdctrl);
1612 65cef780 blueswir1
1613 f2d81b33 blueswir1
    if(fdctrl->reset_sensei > 0) {
1614 f2d81b33 blueswir1
        fdctrl->fifo[0] =
1615 f2d81b33 blueswir1
            FD_SR0_RDYCHG + FD_RESET_SENSEI_COUNT - fdctrl->reset_sensei;
1616 f2d81b33 blueswir1
        fdctrl->reset_sensei--;
1617 f2d81b33 blueswir1
    } else {
1618 f2d81b33 blueswir1
        /* XXX: status0 handling is broken for read/write
1619 f2d81b33 blueswir1
           commands, so we do this hack. It should be suppressed
1620 f2d81b33 blueswir1
           ASAP */
1621 f2d81b33 blueswir1
        fdctrl->fifo[0] =
1622 f2d81b33 blueswir1
            FD_SR0_SEEK | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1623 f2d81b33 blueswir1
    }
1624 f2d81b33 blueswir1
1625 65cef780 blueswir1
    fdctrl->fifo[1] = cur_drv->track;
1626 65cef780 blueswir1
    fdctrl_set_fifo(fdctrl, 2, 0);
1627 65cef780 blueswir1
    fdctrl_reset_irq(fdctrl);
1628 77370520 blueswir1
    fdctrl->status0 = FD_SR0_RDYCHG;
1629 65cef780 blueswir1
}
1630 65cef780 blueswir1
1631 65cef780 blueswir1
static void fdctrl_handle_seek (fdctrl_t *fdctrl, int direction)
1632 65cef780 blueswir1
{
1633 65cef780 blueswir1
    fdrive_t *cur_drv;
1634 65cef780 blueswir1
1635 cefec4f5 blueswir1
    SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1636 65cef780 blueswir1
    cur_drv = get_cur_drv(fdctrl);
1637 65cef780 blueswir1
    fdctrl_reset_fifo(fdctrl);
1638 65cef780 blueswir1
    if (fdctrl->fifo[2] > cur_drv->max_track) {
1639 65cef780 blueswir1
        fdctrl_raise_irq(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK);
1640 65cef780 blueswir1
    } else {
1641 65cef780 blueswir1
        cur_drv->track = fdctrl->fifo[2];
1642 65cef780 blueswir1
        /* Raise Interrupt */
1643 65cef780 blueswir1
        fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1644 65cef780 blueswir1
    }
1645 65cef780 blueswir1
}
1646 65cef780 blueswir1
1647 65cef780 blueswir1
static void fdctrl_handle_perpendicular_mode (fdctrl_t *fdctrl, int direction)
1648 65cef780 blueswir1
{
1649 65cef780 blueswir1
    fdrive_t *cur_drv = get_cur_drv(fdctrl);
1650 65cef780 blueswir1
1651 65cef780 blueswir1
    if (fdctrl->fifo[1] & 0x80)
1652 65cef780 blueswir1
        cur_drv->perpendicular = fdctrl->fifo[1] & 0x7;
1653 65cef780 blueswir1
    /* No result back */
1654 1c346df2 blueswir1
    fdctrl_reset_fifo(fdctrl);
1655 65cef780 blueswir1
}
1656 65cef780 blueswir1
1657 65cef780 blueswir1
static void fdctrl_handle_configure (fdctrl_t *fdctrl, int direction)
1658 65cef780 blueswir1
{
1659 65cef780 blueswir1
    fdctrl->config = fdctrl->fifo[2];
1660 65cef780 blueswir1
    fdctrl->precomp_trk =  fdctrl->fifo[3];
1661 65cef780 blueswir1
    /* No result back */
1662 65cef780 blueswir1
    fdctrl_reset_fifo(fdctrl);
1663 65cef780 blueswir1
}
1664 65cef780 blueswir1
1665 65cef780 blueswir1
static void fdctrl_handle_powerdown_mode (fdctrl_t *fdctrl, int direction)
1666 65cef780 blueswir1
{
1667 65cef780 blueswir1
    fdctrl->pwrd = fdctrl->fifo[1];
1668 65cef780 blueswir1
    fdctrl->fifo[0] = fdctrl->fifo[1];
1669 65cef780 blueswir1
    fdctrl_set_fifo(fdctrl, 1, 1);
1670 65cef780 blueswir1
}
1671 65cef780 blueswir1
1672 65cef780 blueswir1
static void fdctrl_handle_option (fdctrl_t *fdctrl, int direction)
1673 65cef780 blueswir1
{
1674 65cef780 blueswir1
    /* No result back */
1675 65cef780 blueswir1
    fdctrl_reset_fifo(fdctrl);
1676 65cef780 blueswir1
}
1677 65cef780 blueswir1
1678 65cef780 blueswir1
static void fdctrl_handle_drive_specification_command (fdctrl_t *fdctrl, int direction)
1679 65cef780 blueswir1
{
1680 65cef780 blueswir1
    fdrive_t *cur_drv = get_cur_drv(fdctrl);
1681 65cef780 blueswir1
1682 65cef780 blueswir1
    if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x80) {
1683 65cef780 blueswir1
        /* Command parameters done */
1684 65cef780 blueswir1
        if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x40) {
1685 65cef780 blueswir1
            fdctrl->fifo[0] = fdctrl->fifo[1];
1686 65cef780 blueswir1
            fdctrl->fifo[2] = 0;
1687 65cef780 blueswir1
            fdctrl->fifo[3] = 0;
1688 65cef780 blueswir1
            fdctrl_set_fifo(fdctrl, 4, 1);
1689 65cef780 blueswir1
        } else {
1690 65cef780 blueswir1
            fdctrl_reset_fifo(fdctrl);
1691 65cef780 blueswir1
        }
1692 65cef780 blueswir1
    } else if (fdctrl->data_len > 7) {
1693 65cef780 blueswir1
        /* ERROR */
1694 65cef780 blueswir1
        fdctrl->fifo[0] = 0x80 |
1695 cefec4f5 blueswir1
            (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1696 65cef780 blueswir1
        fdctrl_set_fifo(fdctrl, 1, 1);
1697 65cef780 blueswir1
    }
1698 65cef780 blueswir1
}
1699 65cef780 blueswir1
1700 65cef780 blueswir1
static void fdctrl_handle_relative_seek_out (fdctrl_t *fdctrl, int direction)
1701 65cef780 blueswir1
{
1702 77370520 blueswir1
    fdrive_t *cur_drv;
1703 65cef780 blueswir1
1704 cefec4f5 blueswir1
    SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1705 65cef780 blueswir1
    cur_drv = get_cur_drv(fdctrl);
1706 65cef780 blueswir1
    if (fdctrl->fifo[2] + cur_drv->track >= cur_drv->max_track) {
1707 65cef780 blueswir1
        cur_drv->track = cur_drv->max_track - 1;
1708 65cef780 blueswir1
    } else {
1709 65cef780 blueswir1
        cur_drv->track += fdctrl->fifo[2];
1710 65cef780 blueswir1
    }
1711 65cef780 blueswir1
    fdctrl_reset_fifo(fdctrl);
1712 77370520 blueswir1
    /* Raise Interrupt */
1713 65cef780 blueswir1
    fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1714 65cef780 blueswir1
}
1715 65cef780 blueswir1
1716 65cef780 blueswir1
static void fdctrl_handle_relative_seek_in (fdctrl_t *fdctrl, int direction)
1717 65cef780 blueswir1
{
1718 77370520 blueswir1
    fdrive_t *cur_drv;
1719 65cef780 blueswir1
1720 cefec4f5 blueswir1
    SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1721 65cef780 blueswir1
    cur_drv = get_cur_drv(fdctrl);
1722 65cef780 blueswir1
    if (fdctrl->fifo[2] > cur_drv->track) {
1723 65cef780 blueswir1
        cur_drv->track = 0;
1724 65cef780 blueswir1
    } else {
1725 65cef780 blueswir1
        cur_drv->track -= fdctrl->fifo[2];
1726 65cef780 blueswir1
    }
1727 65cef780 blueswir1
    fdctrl_reset_fifo(fdctrl);
1728 65cef780 blueswir1
    /* Raise Interrupt */
1729 65cef780 blueswir1
    fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1730 65cef780 blueswir1
}
1731 65cef780 blueswir1
1732 678803ab blueswir1
static const struct {
1733 678803ab blueswir1
    uint8_t value;
1734 678803ab blueswir1
    uint8_t mask;
1735 678803ab blueswir1
    const char* name;
1736 678803ab blueswir1
    int parameters;
1737 678803ab blueswir1
    void (*handler)(fdctrl_t *fdctrl, int direction);
1738 678803ab blueswir1
    int direction;
1739 678803ab blueswir1
} handlers[] = {
1740 678803ab blueswir1
    { FD_CMD_READ, 0x1f, "READ", 8, fdctrl_start_transfer, FD_DIR_READ },
1741 678803ab blueswir1
    { FD_CMD_WRITE, 0x3f, "WRITE", 8, fdctrl_start_transfer, FD_DIR_WRITE },
1742 678803ab blueswir1
    { FD_CMD_SEEK, 0xff, "SEEK", 2, fdctrl_handle_seek },
1743 678803ab blueswir1
    { FD_CMD_SENSE_INTERRUPT_STATUS, 0xff, "SENSE INTERRUPT STATUS", 0, fdctrl_handle_sense_interrupt_status },
1744 678803ab blueswir1
    { FD_CMD_RECALIBRATE, 0xff, "RECALIBRATE", 1, fdctrl_handle_recalibrate },
1745 678803ab blueswir1
    { FD_CMD_FORMAT_TRACK, 0xbf, "FORMAT TRACK", 5, fdctrl_handle_format_track },
1746 678803ab blueswir1
    { FD_CMD_READ_TRACK, 0xbf, "READ TRACK", 8, fdctrl_start_transfer, FD_DIR_READ },
1747 678803ab blueswir1
    { FD_CMD_RESTORE, 0xff, "RESTORE", 17, fdctrl_handle_restore }, /* part of READ DELETED DATA */
1748 678803ab blueswir1
    { FD_CMD_SAVE, 0xff, "SAVE", 0, fdctrl_handle_save }, /* part of READ DELETED DATA */
1749 678803ab blueswir1
    { FD_CMD_READ_DELETED, 0x1f, "READ DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_READ },
1750 678803ab blueswir1
    { FD_CMD_SCAN_EQUAL, 0x1f, "SCAN EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANE },
1751 678803ab blueswir1
    { FD_CMD_VERIFY, 0x1f, "VERIFY", 8, fdctrl_unimplemented },
1752 678803ab blueswir1
    { FD_CMD_SCAN_LOW_OR_EQUAL, 0x1f, "SCAN LOW OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANL },
1753 678803ab blueswir1
    { FD_CMD_SCAN_HIGH_OR_EQUAL, 0x1f, "SCAN HIGH OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANH },
1754 678803ab blueswir1
    { FD_CMD_WRITE_DELETED, 0x3f, "WRITE DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_WRITE },
1755 678803ab blueswir1
    { FD_CMD_READ_ID, 0xbf, "READ ID", 1, fdctrl_handle_readid },
1756 678803ab blueswir1
    { FD_CMD_SPECIFY, 0xff, "SPECIFY", 2, fdctrl_handle_specify },
1757 678803ab blueswir1
    { FD_CMD_SENSE_DRIVE_STATUS, 0xff, "SENSE DRIVE STATUS", 1, fdctrl_handle_sense_drive_status },
1758 678803ab blueswir1
    { FD_CMD_PERPENDICULAR_MODE, 0xff, "PERPENDICULAR MODE", 1, fdctrl_handle_perpendicular_mode },
1759 678803ab blueswir1
    { FD_CMD_CONFIGURE, 0xff, "CONFIGURE", 3, fdctrl_handle_configure },
1760 678803ab blueswir1
    { FD_CMD_POWERDOWN_MODE, 0xff, "POWERDOWN MODE", 2, fdctrl_handle_powerdown_mode },
1761 678803ab blueswir1
    { FD_CMD_OPTION, 0xff, "OPTION", 1, fdctrl_handle_option },
1762 678803ab blueswir1
    { FD_CMD_DRIVE_SPECIFICATION_COMMAND, 0xff, "DRIVE SPECIFICATION COMMAND", 5, fdctrl_handle_drive_specification_command },
1763 678803ab blueswir1
    { FD_CMD_RELATIVE_SEEK_OUT, 0xff, "RELATIVE SEEK OUT", 2, fdctrl_handle_relative_seek_out },
1764 678803ab blueswir1
    { FD_CMD_FORMAT_AND_WRITE, 0xff, "FORMAT AND WRITE", 10, fdctrl_unimplemented },
1765 678803ab blueswir1
    { FD_CMD_RELATIVE_SEEK_IN, 0xff, "RELATIVE SEEK IN", 2, fdctrl_handle_relative_seek_in },
1766 678803ab blueswir1
    { FD_CMD_LOCK, 0x7f, "LOCK", 0, fdctrl_handle_lock },
1767 678803ab blueswir1
    { FD_CMD_DUMPREG, 0xff, "DUMPREG", 0, fdctrl_handle_dumpreg },
1768 678803ab blueswir1
    { FD_CMD_VERSION, 0xff, "VERSION", 0, fdctrl_handle_version },
1769 678803ab blueswir1
    { FD_CMD_PART_ID, 0xff, "PART ID", 0, fdctrl_handle_partid },
1770 678803ab blueswir1
    { FD_CMD_WRITE, 0x1f, "WRITE (BeOS)", 8, fdctrl_start_transfer, FD_DIR_WRITE }, /* not in specification ; BeOS 4.5 bug */
1771 678803ab blueswir1
    { 0, 0, "unknown", 0, fdctrl_unimplemented }, /* default handler */
1772 678803ab blueswir1
};
1773 678803ab blueswir1
/* Associate command to an index in the 'handlers' array */
1774 678803ab blueswir1
static uint8_t command_to_handler[256];
1775 678803ab blueswir1
1776 baca51fa bellard
static void fdctrl_write_data (fdctrl_t *fdctrl, uint32_t value)
1777 baca51fa bellard
{
1778 baca51fa bellard
    fdrive_t *cur_drv;
1779 65cef780 blueswir1
    int pos;
1780 baca51fa bellard
1781 8977f3c1 bellard
    /* Reset mode */
1782 1c346df2 blueswir1
    if (!(fdctrl->dor & FD_DOR_nRESET)) {
1783 4b19ec0c bellard
        FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
1784 8977f3c1 bellard
        return;
1785 8977f3c1 bellard
    }
1786 b9b3d225 blueswir1
    if (!(fdctrl->msr & FD_MSR_RQM) || (fdctrl->msr & FD_MSR_DIO)) {
1787 b9b3d225 blueswir1
        FLOPPY_ERROR("controller not ready for writing\n");
1788 8977f3c1 bellard
        return;
1789 8977f3c1 bellard
    }
1790 b9b3d225 blueswir1
    fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1791 8977f3c1 bellard
    /* Is it write command time ? */
1792 368df94d blueswir1
    if (fdctrl->msr & FD_MSR_NONDMA) {
1793 8977f3c1 bellard
        /* FIFO data write */
1794 b3bc1540 blueswir1
        pos = fdctrl->data_pos++;
1795 b3bc1540 blueswir1
        pos %= FD_SECTOR_LEN;
1796 b3bc1540 blueswir1
        fdctrl->fifo[pos] = value;
1797 b3bc1540 blueswir1
        if (pos == FD_SECTOR_LEN - 1 ||
1798 baca51fa bellard
            fdctrl->data_pos == fdctrl->data_len) {
1799 77370520 blueswir1
            cur_drv = get_cur_drv(fdctrl);
1800 77370520 blueswir1
            if (bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1801 77370520 blueswir1
                FLOPPY_ERROR("writing sector %d\n", fd_sector(cur_drv));
1802 77370520 blueswir1
                return;
1803 77370520 blueswir1
            }
1804 746d6de7 blueswir1
            if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1805 746d6de7 blueswir1
                FLOPPY_DPRINTF("error seeking to next sector %d\n",
1806 746d6de7 blueswir1
                               fd_sector(cur_drv));
1807 746d6de7 blueswir1
                return;
1808 746d6de7 blueswir1
            }
1809 8977f3c1 bellard
        }
1810 890fa6be bellard
        /* Switch from transfer mode to status mode
1811 8977f3c1 bellard
         * then from status mode to command mode
1812 8977f3c1 bellard
         */
1813 b9b3d225 blueswir1
        if (fdctrl->data_pos == fdctrl->data_len)
1814 9fea808a blueswir1
            fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1815 8977f3c1 bellard
        return;
1816 8977f3c1 bellard
    }
1817 baca51fa bellard
    if (fdctrl->data_pos == 0) {
1818 8977f3c1 bellard
        /* Command */
1819 678803ab blueswir1
        pos = command_to_handler[value & 0xff];
1820 678803ab blueswir1
        FLOPPY_DPRINTF("%s command\n", handlers[pos].name);
1821 678803ab blueswir1
        fdctrl->data_len = handlers[pos].parameters + 1;
1822 8977f3c1 bellard
    }
1823 678803ab blueswir1
1824 baca51fa bellard
    FLOPPY_DPRINTF("%s: %02x\n", __func__, value);
1825 77370520 blueswir1
    fdctrl->fifo[fdctrl->data_pos++] = value;
1826 77370520 blueswir1
    if (fdctrl->data_pos == fdctrl->data_len) {
1827 8977f3c1 bellard
        /* We now have all parameters
1828 8977f3c1 bellard
         * and will be able to treat the command
1829 8977f3c1 bellard
         */
1830 4f431960 j_mayer
        if (fdctrl->data_state & FD_STATE_FORMAT) {
1831 4f431960 j_mayer
            fdctrl_format_sector(fdctrl);
1832 8977f3c1 bellard
            return;
1833 8977f3c1 bellard
        }
1834 65cef780 blueswir1
1835 678803ab blueswir1
        pos = command_to_handler[fdctrl->fifo[0] & 0xff];
1836 678803ab blueswir1
        FLOPPY_DPRINTF("treat %s command\n", handlers[pos].name);
1837 678803ab blueswir1
        (*handlers[pos].handler)(fdctrl, handlers[pos].direction);
1838 8977f3c1 bellard
    }
1839 8977f3c1 bellard
}
1840 ed5fd2cc bellard
1841 ed5fd2cc bellard
static void fdctrl_result_timer(void *opaque)
1842 ed5fd2cc bellard
{
1843 ed5fd2cc bellard
    fdctrl_t *fdctrl = opaque;
1844 b7ffa3b1 ths
    fdrive_t *cur_drv = get_cur_drv(fdctrl);
1845 4f431960 j_mayer
1846 b7ffa3b1 ths
    /* Pretend we are spinning.
1847 b7ffa3b1 ths
     * This is needed for Coherent, which uses READ ID to check for
1848 b7ffa3b1 ths
     * sector interleaving.
1849 b7ffa3b1 ths
     */
1850 b7ffa3b1 ths
    if (cur_drv->last_sect != 0) {
1851 b7ffa3b1 ths
        cur_drv->sect = (cur_drv->sect % cur_drv->last_sect) + 1;
1852 b7ffa3b1 ths
    }
1853 ed5fd2cc bellard
    fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1854 ed5fd2cc bellard
}
1855 678803ab blueswir1
1856 678803ab blueswir1
/* Init functions */
1857 f64ab228 Blue Swirl
static void fdctrl_init_common (fdctrl_t *fdctrl, int dma_chann,
1858 f64ab228 Blue Swirl
                                target_phys_addr_t io_base,
1859 f64ab228 Blue Swirl
                                BlockDriverState **fds)
1860 678803ab blueswir1
{
1861 678803ab blueswir1
    int i, j;
1862 678803ab blueswir1
1863 678803ab blueswir1
    /* Fill 'command_to_handler' lookup table */
1864 b1503cda malc
    for (i = ARRAY_SIZE(handlers) - 1; i >= 0; i--) {
1865 678803ab blueswir1
        for (j = 0; j < sizeof(command_to_handler); j++) {
1866 678803ab blueswir1
            if ((j & handlers[i].mask) == handlers[i].value)
1867 678803ab blueswir1
                command_to_handler[j] = i;
1868 678803ab blueswir1
        }
1869 678803ab blueswir1
    }
1870 678803ab blueswir1
1871 678803ab blueswir1
    FLOPPY_DPRINTF("init controller\n");
1872 678803ab blueswir1
    fdctrl->fifo = qemu_memalign(512, FD_SECTOR_LEN);
1873 678803ab blueswir1
    fdctrl->result_timer = qemu_new_timer(vm_clock,
1874 678803ab blueswir1
                                          fdctrl_result_timer, fdctrl);
1875 678803ab blueswir1
1876 678803ab blueswir1
    fdctrl->version = 0x90; /* Intel 82078 controller */
1877 678803ab blueswir1
    fdctrl->dma_chann = dma_chann;
1878 678803ab blueswir1
    fdctrl->io_base = io_base;
1879 678803ab blueswir1
    fdctrl->config = FD_CONFIG_EIS | FD_CONFIG_EFIFO; /* Implicit seek, polling & FIFO enabled */
1880 678803ab blueswir1
    if (fdctrl->dma_chann != -1) {
1881 678803ab blueswir1
        DMA_register_channel(dma_chann, &fdctrl_transfer_handler, fdctrl);
1882 678803ab blueswir1
    }
1883 678803ab blueswir1
    for (i = 0; i < MAX_FD; i++) {
1884 678803ab blueswir1
        fd_init(&fdctrl->drives[i], fds[i]);
1885 678803ab blueswir1
    }
1886 77370520 blueswir1
    fdctrl_external_reset(fdctrl);
1887 77370520 blueswir1
    register_savevm("fdc", io_base, 2, fdc_save, fdc_load, fdctrl);
1888 a08d4367 Jan Kiszka
    qemu_register_reset(fdctrl_external_reset, fdctrl);
1889 678803ab blueswir1
    for (i = 0; i < MAX_FD; i++) {
1890 678803ab blueswir1
        fd_revalidate(&fdctrl->drives[i]);
1891 678803ab blueswir1
    }
1892 678803ab blueswir1
}
1893 678803ab blueswir1
1894 678803ab blueswir1
fdctrl_t *fdctrl_init (qemu_irq irq, int dma_chann, int mem_mapped,
1895 678803ab blueswir1
                       target_phys_addr_t io_base,
1896 678803ab blueswir1
                       BlockDriverState **fds)
1897 678803ab blueswir1
{
1898 f64ab228 Blue Swirl
    DeviceState *dev;
1899 f64ab228 Blue Swirl
    SysBusDevice *s;
1900 678803ab blueswir1
    fdctrl_t *fdctrl;
1901 678803ab blueswir1
1902 f64ab228 Blue Swirl
    dev = qdev_create(NULL, "fdc");
1903 ee6847d1 Gerd Hoffmann
    qdev_prop_set_uint32(dev, "strict_io", 0);
1904 ee6847d1 Gerd Hoffmann
    qdev_prop_set_uint32(dev, "mem_mapped", mem_mapped);
1905 ee6847d1 Gerd Hoffmann
    qdev_prop_set_uint32(dev, "sun4m", 0);
1906 f64ab228 Blue Swirl
    qdev_init(dev);
1907 f64ab228 Blue Swirl
    s = sysbus_from_qdev(dev);
1908 f64ab228 Blue Swirl
    sysbus_connect_irq(s, 0, irq);
1909 f64ab228 Blue Swirl
    fdctrl = FROM_SYSBUS(fdctrl_t, s);
1910 678803ab blueswir1
    if (mem_mapped) {
1911 f64ab228 Blue Swirl
        sysbus_mmio_map(s, 0, io_base);
1912 678803ab blueswir1
    } else {
1913 e64d7d59 blueswir1
        register_ioport_read((uint32_t)io_base + 0x01, 5, 1,
1914 e64d7d59 blueswir1
                             &fdctrl_read_port, fdctrl);
1915 e64d7d59 blueswir1
        register_ioport_read((uint32_t)io_base + 0x07, 1, 1,
1916 e64d7d59 blueswir1
                             &fdctrl_read_port, fdctrl);
1917 e64d7d59 blueswir1
        register_ioport_write((uint32_t)io_base + 0x01, 5, 1,
1918 e64d7d59 blueswir1
                              &fdctrl_write_port, fdctrl);
1919 e64d7d59 blueswir1
        register_ioport_write((uint32_t)io_base + 0x07, 1, 1,
1920 e64d7d59 blueswir1
                              &fdctrl_write_port, fdctrl);
1921 678803ab blueswir1
    }
1922 678803ab blueswir1
1923 f64ab228 Blue Swirl
    fdctrl_init_common(fdctrl, dma_chann, io_base, fds);
1924 f64ab228 Blue Swirl
1925 678803ab blueswir1
    return fdctrl;
1926 678803ab blueswir1
}
1927 678803ab blueswir1
1928 678803ab blueswir1
fdctrl_t *sun4m_fdctrl_init (qemu_irq irq, target_phys_addr_t io_base,
1929 678803ab blueswir1
                             BlockDriverState **fds, qemu_irq *fdc_tc)
1930 678803ab blueswir1
{
1931 f64ab228 Blue Swirl
    DeviceState *dev;
1932 f64ab228 Blue Swirl
    SysBusDevice *s;
1933 678803ab blueswir1
    fdctrl_t *fdctrl;
1934 678803ab blueswir1
1935 f64ab228 Blue Swirl
    dev = qdev_create(NULL, "fdc");
1936 ee6847d1 Gerd Hoffmann
    qdev_prop_set_uint32(dev, "strict_io", 1);
1937 ee6847d1 Gerd Hoffmann
    qdev_prop_set_uint32(dev, "mem_mapped", 1);
1938 ee6847d1 Gerd Hoffmann
    qdev_prop_set_uint32(dev, "sun4m", 1);
1939 f64ab228 Blue Swirl
    qdev_init(dev);
1940 f64ab228 Blue Swirl
    s = sysbus_from_qdev(dev);
1941 f64ab228 Blue Swirl
    sysbus_connect_irq(s, 0, irq);
1942 f64ab228 Blue Swirl
    sysbus_mmio_map(s, 0, io_base);
1943 f64ab228 Blue Swirl
    *fdc_tc = qdev_get_gpio_in(dev, 0);
1944 f64ab228 Blue Swirl
1945 f64ab228 Blue Swirl
    fdctrl = FROM_SYSBUS(fdctrl_t, s);
1946 f64ab228 Blue Swirl
    fdctrl_init_common(fdctrl, -1, io_base, fds);
1947 678803ab blueswir1
1948 678803ab blueswir1
    return fdctrl;
1949 678803ab blueswir1
}
1950 f64ab228 Blue Swirl
1951 f64ab228 Blue Swirl
static void fdc_init1(SysBusDevice *dev)
1952 f64ab228 Blue Swirl
{
1953 f64ab228 Blue Swirl
    fdctrl_t *s = FROM_SYSBUS(fdctrl_t, dev);
1954 f64ab228 Blue Swirl
    int io;
1955 f64ab228 Blue Swirl
1956 f64ab228 Blue Swirl
    sysbus_init_irq(dev, &s->irq);
1957 f64ab228 Blue Swirl
    qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1);
1958 ee6847d1 Gerd Hoffmann
    if (s->strict_io) {
1959 f64ab228 Blue Swirl
        io = cpu_register_io_memory(fdctrl_mem_read_strict,
1960 f64ab228 Blue Swirl
                                    fdctrl_mem_write_strict, s);
1961 f64ab228 Blue Swirl
    } else {
1962 f64ab228 Blue Swirl
        io = cpu_register_io_memory(fdctrl_mem_read, fdctrl_mem_write, s);
1963 f64ab228 Blue Swirl
    }
1964 f64ab228 Blue Swirl
    sysbus_init_mmio(dev, 0x08, io);
1965 f64ab228 Blue Swirl
}
1966 f64ab228 Blue Swirl
1967 f64ab228 Blue Swirl
1968 f64ab228 Blue Swirl
static SysBusDeviceInfo fdc_info = {
1969 f64ab228 Blue Swirl
    .init = fdc_init1,
1970 f64ab228 Blue Swirl
    .qdev.name  = "fdc",
1971 f64ab228 Blue Swirl
    .qdev.size  = sizeof(fdctrl_t),
1972 ee6847d1 Gerd Hoffmann
    .qdev.props = (Property[]) {
1973 ee6847d1 Gerd Hoffmann
        {
1974 ee6847d1 Gerd Hoffmann
            .name = "io_base",
1975 ee6847d1 Gerd Hoffmann
            .info = &qdev_prop_uint32,
1976 ee6847d1 Gerd Hoffmann
            .offset = offsetof(fdctrl_t, io_base),
1977 ee6847d1 Gerd Hoffmann
        },
1978 ee6847d1 Gerd Hoffmann
        {
1979 ee6847d1 Gerd Hoffmann
            .name = "strict_io",
1980 ee6847d1 Gerd Hoffmann
            .info = &qdev_prop_uint32,
1981 ee6847d1 Gerd Hoffmann
            .offset = offsetof(fdctrl_t, strict_io),
1982 ee6847d1 Gerd Hoffmann
        },
1983 ee6847d1 Gerd Hoffmann
        {
1984 ee6847d1 Gerd Hoffmann
            .name = "mem_mapped",
1985 ee6847d1 Gerd Hoffmann
            .info = &qdev_prop_uint32,
1986 ee6847d1 Gerd Hoffmann
            .offset = offsetof(fdctrl_t, mem_mapped),
1987 ee6847d1 Gerd Hoffmann
        },
1988 ee6847d1 Gerd Hoffmann
        {
1989 ee6847d1 Gerd Hoffmann
            .name = "sun4m",
1990 ee6847d1 Gerd Hoffmann
            .info = &qdev_prop_uint32,
1991 ee6847d1 Gerd Hoffmann
            .offset = offsetof(fdctrl_t, sun4m),
1992 ee6847d1 Gerd Hoffmann
        },
1993 ee6847d1 Gerd Hoffmann
        {/* end of properties */}
1994 f64ab228 Blue Swirl
    }
1995 f64ab228 Blue Swirl
};
1996 f64ab228 Blue Swirl
1997 f64ab228 Blue Swirl
static void fdc_register_devices(void)
1998 f64ab228 Blue Swirl
{
1999 f64ab228 Blue Swirl
    sysbus_register_withprop(&fdc_info);
2000 f64ab228 Blue Swirl
}
2001 f64ab228 Blue Swirl
2002 f64ab228 Blue Swirl
device_init(fdc_register_devices)