root / hw / ppc4xx_devs.c @ 96cc1810
History | View | Annotate | Download (24.6 kB)
1 | 008ff9d7 | j_mayer | /*
|
---|---|---|---|
2 | 008ff9d7 | j_mayer | * QEMU PowerPC 4xx embedded processors shared devices emulation
|
3 | 008ff9d7 | j_mayer | *
|
4 | 008ff9d7 | j_mayer | * Copyright (c) 2007 Jocelyn Mayer
|
5 | 008ff9d7 | j_mayer | *
|
6 | 008ff9d7 | j_mayer | * Permission is hereby granted, free of charge, to any person obtaining a copy
|
7 | 008ff9d7 | j_mayer | * of this software and associated documentation files (the "Software"), to deal
|
8 | 008ff9d7 | j_mayer | * in the Software without restriction, including without limitation the rights
|
9 | 008ff9d7 | j_mayer | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
10 | 008ff9d7 | j_mayer | * copies of the Software, and to permit persons to whom the Software is
|
11 | 008ff9d7 | j_mayer | * furnished to do so, subject to the following conditions:
|
12 | 008ff9d7 | j_mayer | *
|
13 | 008ff9d7 | j_mayer | * The above copyright notice and this permission notice shall be included in
|
14 | 008ff9d7 | j_mayer | * all copies or substantial portions of the Software.
|
15 | 008ff9d7 | j_mayer | *
|
16 | 008ff9d7 | j_mayer | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
17 | 008ff9d7 | j_mayer | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
18 | 008ff9d7 | j_mayer | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
19 | 008ff9d7 | j_mayer | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
20 | 008ff9d7 | j_mayer | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
21 | 008ff9d7 | j_mayer | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
22 | 008ff9d7 | j_mayer | * THE SOFTWARE.
|
23 | 008ff9d7 | j_mayer | */
|
24 | 87ecb68b | pbrook | #include "hw.h" |
25 | 87ecb68b | pbrook | #include "ppc.h" |
26 | 008ff9d7 | j_mayer | #include "ppc4xx.h" |
27 | 87ecb68b | pbrook | #include "sysemu.h" |
28 | 3b3fb322 | blueswir1 | #include "qemu-log.h" |
29 | 008ff9d7 | j_mayer | |
30 | 008ff9d7 | j_mayer | //#define DEBUG_MMIO
|
31 | aae9366a | j_mayer | //#define DEBUG_UNASSIGNED
|
32 | 008ff9d7 | j_mayer | #define DEBUG_UIC
|
33 | 008ff9d7 | j_mayer | |
34 | d12d51d5 | aliguori | |
35 | d12d51d5 | aliguori | #ifdef DEBUG_UIC
|
36 | 93fcfe39 | aliguori | # define LOG_UIC(...) qemu_log_mask(CPU_LOG_INT, ## __VA_ARGS__) |
37 | d12d51d5 | aliguori | #else
|
38 | d12d51d5 | aliguori | # define LOG_UIC(...) do { } while (0) |
39 | d12d51d5 | aliguori | #endif
|
40 | d12d51d5 | aliguori | |
41 | 008ff9d7 | j_mayer | /*****************************************************************************/
|
42 | 008ff9d7 | j_mayer | /* Generic PowerPC 4xx processor instanciation */
|
43 | b55266b5 | blueswir1 | CPUState *ppc4xx_init (const char *cpu_model, |
44 | 008ff9d7 | j_mayer | clk_setup_t *cpu_clk, clk_setup_t *tb_clk, |
45 | 008ff9d7 | j_mayer | uint32_t sysclk) |
46 | 008ff9d7 | j_mayer | { |
47 | 008ff9d7 | j_mayer | CPUState *env; |
48 | 008ff9d7 | j_mayer | |
49 | 008ff9d7 | j_mayer | /* init CPUs */
|
50 | aaed909a | bellard | env = cpu_init(cpu_model); |
51 | aaed909a | bellard | if (!env) {
|
52 | aaed909a | bellard | fprintf(stderr, "Unable to find PowerPC %s CPU definition\n",
|
53 | aaed909a | bellard | cpu_model); |
54 | aaed909a | bellard | exit(1);
|
55 | 008ff9d7 | j_mayer | } |
56 | 008ff9d7 | j_mayer | cpu_clk->cb = NULL; /* We don't care about CPU clock frequency changes */ |
57 | 008ff9d7 | j_mayer | cpu_clk->opaque = env; |
58 | 008ff9d7 | j_mayer | /* Set time-base frequency to sysclk */
|
59 | 008ff9d7 | j_mayer | tb_clk->cb = ppc_emb_timers_init(env, sysclk); |
60 | 008ff9d7 | j_mayer | tb_clk->opaque = env; |
61 | 008ff9d7 | j_mayer | ppc_dcr_init(env, NULL, NULL); |
62 | 008ff9d7 | j_mayer | /* Register qemu callbacks */
|
63 | a08d4367 | Jan Kiszka | qemu_register_reset(&cpu_ppc_reset, env); |
64 | 008ff9d7 | j_mayer | |
65 | 008ff9d7 | j_mayer | return env;
|
66 | 008ff9d7 | j_mayer | } |
67 | 008ff9d7 | j_mayer | |
68 | 008ff9d7 | j_mayer | /*****************************************************************************/
|
69 | 008ff9d7 | j_mayer | /* Fake device used to map multiple devices in a single memory page */
|
70 | 008ff9d7 | j_mayer | #define MMIO_AREA_BITS 8 |
71 | 008ff9d7 | j_mayer | #define MMIO_AREA_LEN (1 << MMIO_AREA_BITS) |
72 | 008ff9d7 | j_mayer | #define MMIO_AREA_NB (1 << (TARGET_PAGE_BITS - MMIO_AREA_BITS)) |
73 | 008ff9d7 | j_mayer | #define MMIO_IDX(addr) (((addr) >> MMIO_AREA_BITS) & (MMIO_AREA_NB - 1)) |
74 | 008ff9d7 | j_mayer | struct ppc4xx_mmio_t {
|
75 | 008ff9d7 | j_mayer | target_phys_addr_t base; |
76 | 008ff9d7 | j_mayer | CPUReadMemoryFunc **mem_read[MMIO_AREA_NB]; |
77 | 008ff9d7 | j_mayer | CPUWriteMemoryFunc **mem_write[MMIO_AREA_NB]; |
78 | 008ff9d7 | j_mayer | void *opaque[MMIO_AREA_NB];
|
79 | 008ff9d7 | j_mayer | }; |
80 | 008ff9d7 | j_mayer | |
81 | 008ff9d7 | j_mayer | static uint32_t unassigned_mmio_readb (void *opaque, target_phys_addr_t addr) |
82 | 008ff9d7 | j_mayer | { |
83 | 008ff9d7 | j_mayer | #ifdef DEBUG_UNASSIGNED
|
84 | 008ff9d7 | j_mayer | ppc4xx_mmio_t *mmio; |
85 | 008ff9d7 | j_mayer | |
86 | 008ff9d7 | j_mayer | mmio = opaque; |
87 | 008ff9d7 | j_mayer | printf("Unassigned mmio read 0x" PADDRX " base " PADDRX "\n", |
88 | 008ff9d7 | j_mayer | addr, mmio->base); |
89 | 008ff9d7 | j_mayer | #endif
|
90 | 008ff9d7 | j_mayer | |
91 | 008ff9d7 | j_mayer | return 0; |
92 | 008ff9d7 | j_mayer | } |
93 | 008ff9d7 | j_mayer | |
94 | 008ff9d7 | j_mayer | static void unassigned_mmio_writeb (void *opaque, |
95 | 008ff9d7 | j_mayer | target_phys_addr_t addr, uint32_t val) |
96 | 008ff9d7 | j_mayer | { |
97 | 008ff9d7 | j_mayer | #ifdef DEBUG_UNASSIGNED
|
98 | 008ff9d7 | j_mayer | ppc4xx_mmio_t *mmio; |
99 | 008ff9d7 | j_mayer | |
100 | 008ff9d7 | j_mayer | mmio = opaque; |
101 | 008ff9d7 | j_mayer | printf("Unassigned mmio write 0x" PADDRX " = 0x%x base " PADDRX "\n", |
102 | 008ff9d7 | j_mayer | addr, val, mmio->base); |
103 | 008ff9d7 | j_mayer | #endif
|
104 | 008ff9d7 | j_mayer | } |
105 | 008ff9d7 | j_mayer | |
106 | 008ff9d7 | j_mayer | static CPUReadMemoryFunc *unassigned_mmio_read[3] = { |
107 | 008ff9d7 | j_mayer | unassigned_mmio_readb, |
108 | 008ff9d7 | j_mayer | unassigned_mmio_readb, |
109 | 008ff9d7 | j_mayer | unassigned_mmio_readb, |
110 | 008ff9d7 | j_mayer | }; |
111 | 008ff9d7 | j_mayer | |
112 | 008ff9d7 | j_mayer | static CPUWriteMemoryFunc *unassigned_mmio_write[3] = { |
113 | 008ff9d7 | j_mayer | unassigned_mmio_writeb, |
114 | 008ff9d7 | j_mayer | unassigned_mmio_writeb, |
115 | 008ff9d7 | j_mayer | unassigned_mmio_writeb, |
116 | 008ff9d7 | j_mayer | }; |
117 | 008ff9d7 | j_mayer | |
118 | 008ff9d7 | j_mayer | static uint32_t mmio_readlen (ppc4xx_mmio_t *mmio,
|
119 | 008ff9d7 | j_mayer | target_phys_addr_t addr, int len)
|
120 | 008ff9d7 | j_mayer | { |
121 | 008ff9d7 | j_mayer | CPUReadMemoryFunc **mem_read; |
122 | 008ff9d7 | j_mayer | uint32_t ret; |
123 | 008ff9d7 | j_mayer | int idx;
|
124 | 008ff9d7 | j_mayer | |
125 | 8da3ff18 | pbrook | idx = MMIO_IDX(addr); |
126 | 008ff9d7 | j_mayer | #if defined(DEBUG_MMIO)
|
127 | 008ff9d7 | j_mayer | printf("%s: mmio %p len %d addr " PADDRX " idx %d\n", __func__, |
128 | 008ff9d7 | j_mayer | mmio, len, addr, idx); |
129 | 008ff9d7 | j_mayer | #endif
|
130 | 008ff9d7 | j_mayer | mem_read = mmio->mem_read[idx]; |
131 | 8da3ff18 | pbrook | ret = (*mem_read[len])(mmio->opaque[idx], addr); |
132 | 008ff9d7 | j_mayer | |
133 | 008ff9d7 | j_mayer | return ret;
|
134 | 008ff9d7 | j_mayer | } |
135 | 008ff9d7 | j_mayer | |
136 | 008ff9d7 | j_mayer | static void mmio_writelen (ppc4xx_mmio_t *mmio, |
137 | 008ff9d7 | j_mayer | target_phys_addr_t addr, uint32_t value, int len)
|
138 | 008ff9d7 | j_mayer | { |
139 | 008ff9d7 | j_mayer | CPUWriteMemoryFunc **mem_write; |
140 | 008ff9d7 | j_mayer | int idx;
|
141 | 008ff9d7 | j_mayer | |
142 | 8da3ff18 | pbrook | idx = MMIO_IDX(addr); |
143 | 008ff9d7 | j_mayer | #if defined(DEBUG_MMIO)
|
144 | aae9366a | j_mayer | printf("%s: mmio %p len %d addr " PADDRX " idx %d value %08" PRIx32 "\n", |
145 | aae9366a | j_mayer | __func__, mmio, len, addr, idx, value); |
146 | 008ff9d7 | j_mayer | #endif
|
147 | 008ff9d7 | j_mayer | mem_write = mmio->mem_write[idx]; |
148 | 8da3ff18 | pbrook | (*mem_write[len])(mmio->opaque[idx], addr, value); |
149 | 008ff9d7 | j_mayer | } |
150 | 008ff9d7 | j_mayer | |
151 | 008ff9d7 | j_mayer | static uint32_t mmio_readb (void *opaque, target_phys_addr_t addr) |
152 | 008ff9d7 | j_mayer | { |
153 | 008ff9d7 | j_mayer | #if defined(DEBUG_MMIO)
|
154 | 008ff9d7 | j_mayer | printf("%s: addr " PADDRX "\n", __func__, addr); |
155 | 008ff9d7 | j_mayer | #endif
|
156 | 008ff9d7 | j_mayer | |
157 | 008ff9d7 | j_mayer | return mmio_readlen(opaque, addr, 0); |
158 | 008ff9d7 | j_mayer | } |
159 | 008ff9d7 | j_mayer | |
160 | 008ff9d7 | j_mayer | static void mmio_writeb (void *opaque, |
161 | 008ff9d7 | j_mayer | target_phys_addr_t addr, uint32_t value) |
162 | 008ff9d7 | j_mayer | { |
163 | 008ff9d7 | j_mayer | #if defined(DEBUG_MMIO)
|
164 | aae9366a | j_mayer | printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value); |
165 | 008ff9d7 | j_mayer | #endif
|
166 | 008ff9d7 | j_mayer | mmio_writelen(opaque, addr, value, 0);
|
167 | 008ff9d7 | j_mayer | } |
168 | 008ff9d7 | j_mayer | |
169 | 008ff9d7 | j_mayer | static uint32_t mmio_readw (void *opaque, target_phys_addr_t addr) |
170 | 008ff9d7 | j_mayer | { |
171 | 008ff9d7 | j_mayer | #if defined(DEBUG_MMIO)
|
172 | 008ff9d7 | j_mayer | printf("%s: addr " PADDRX "\n", __func__, addr); |
173 | 008ff9d7 | j_mayer | #endif
|
174 | 008ff9d7 | j_mayer | |
175 | 008ff9d7 | j_mayer | return mmio_readlen(opaque, addr, 1); |
176 | 008ff9d7 | j_mayer | } |
177 | 008ff9d7 | j_mayer | |
178 | 008ff9d7 | j_mayer | static void mmio_writew (void *opaque, |
179 | 008ff9d7 | j_mayer | target_phys_addr_t addr, uint32_t value) |
180 | 008ff9d7 | j_mayer | { |
181 | 008ff9d7 | j_mayer | #if defined(DEBUG_MMIO)
|
182 | aae9366a | j_mayer | printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value); |
183 | 008ff9d7 | j_mayer | #endif
|
184 | 008ff9d7 | j_mayer | mmio_writelen(opaque, addr, value, 1);
|
185 | 008ff9d7 | j_mayer | } |
186 | 008ff9d7 | j_mayer | |
187 | 008ff9d7 | j_mayer | static uint32_t mmio_readl (void *opaque, target_phys_addr_t addr) |
188 | 008ff9d7 | j_mayer | { |
189 | 008ff9d7 | j_mayer | #if defined(DEBUG_MMIO)
|
190 | 008ff9d7 | j_mayer | printf("%s: addr " PADDRX "\n", __func__, addr); |
191 | 008ff9d7 | j_mayer | #endif
|
192 | 008ff9d7 | j_mayer | |
193 | 008ff9d7 | j_mayer | return mmio_readlen(opaque, addr, 2); |
194 | 008ff9d7 | j_mayer | } |
195 | 008ff9d7 | j_mayer | |
196 | 008ff9d7 | j_mayer | static void mmio_writel (void *opaque, |
197 | 008ff9d7 | j_mayer | target_phys_addr_t addr, uint32_t value) |
198 | 008ff9d7 | j_mayer | { |
199 | 008ff9d7 | j_mayer | #if defined(DEBUG_MMIO)
|
200 | aae9366a | j_mayer | printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value); |
201 | 008ff9d7 | j_mayer | #endif
|
202 | 008ff9d7 | j_mayer | mmio_writelen(opaque, addr, value, 2);
|
203 | 008ff9d7 | j_mayer | } |
204 | 008ff9d7 | j_mayer | |
205 | 008ff9d7 | j_mayer | static CPUReadMemoryFunc *mmio_read[] = {
|
206 | 008ff9d7 | j_mayer | &mmio_readb, |
207 | 008ff9d7 | j_mayer | &mmio_readw, |
208 | 008ff9d7 | j_mayer | &mmio_readl, |
209 | 008ff9d7 | j_mayer | }; |
210 | 008ff9d7 | j_mayer | |
211 | 008ff9d7 | j_mayer | static CPUWriteMemoryFunc *mmio_write[] = {
|
212 | 008ff9d7 | j_mayer | &mmio_writeb, |
213 | 008ff9d7 | j_mayer | &mmio_writew, |
214 | 008ff9d7 | j_mayer | &mmio_writel, |
215 | 008ff9d7 | j_mayer | }; |
216 | 008ff9d7 | j_mayer | |
217 | 008ff9d7 | j_mayer | int ppc4xx_mmio_register (CPUState *env, ppc4xx_mmio_t *mmio,
|
218 | 008ff9d7 | j_mayer | target_phys_addr_t offset, uint32_t len, |
219 | 008ff9d7 | j_mayer | CPUReadMemoryFunc **mem_read, |
220 | 008ff9d7 | j_mayer | CPUWriteMemoryFunc **mem_write, void *opaque)
|
221 | 008ff9d7 | j_mayer | { |
222 | aae9366a | j_mayer | target_phys_addr_t end; |
223 | 008ff9d7 | j_mayer | int idx, eidx;
|
224 | 008ff9d7 | j_mayer | |
225 | 008ff9d7 | j_mayer | if ((offset + len) > TARGET_PAGE_SIZE)
|
226 | 008ff9d7 | j_mayer | return -1; |
227 | 008ff9d7 | j_mayer | idx = MMIO_IDX(offset); |
228 | 008ff9d7 | j_mayer | end = offset + len - 1;
|
229 | 008ff9d7 | j_mayer | eidx = MMIO_IDX(end); |
230 | 008ff9d7 | j_mayer | #if defined(DEBUG_MMIO)
|
231 | aae9366a | j_mayer | printf("%s: offset " PADDRX " len %08" PRIx32 " " PADDRX " %d %d\n", |
232 | aae9366a | j_mayer | __func__, offset, len, end, idx, eidx); |
233 | 008ff9d7 | j_mayer | #endif
|
234 | 008ff9d7 | j_mayer | for (; idx <= eidx; idx++) {
|
235 | 008ff9d7 | j_mayer | mmio->mem_read[idx] = mem_read; |
236 | 008ff9d7 | j_mayer | mmio->mem_write[idx] = mem_write; |
237 | 008ff9d7 | j_mayer | mmio->opaque[idx] = opaque; |
238 | 008ff9d7 | j_mayer | } |
239 | 008ff9d7 | j_mayer | |
240 | 008ff9d7 | j_mayer | return 0; |
241 | 008ff9d7 | j_mayer | } |
242 | 008ff9d7 | j_mayer | |
243 | 008ff9d7 | j_mayer | ppc4xx_mmio_t *ppc4xx_mmio_init (CPUState *env, target_phys_addr_t base) |
244 | 008ff9d7 | j_mayer | { |
245 | 008ff9d7 | j_mayer | ppc4xx_mmio_t *mmio; |
246 | 008ff9d7 | j_mayer | int mmio_memory;
|
247 | 008ff9d7 | j_mayer | |
248 | 008ff9d7 | j_mayer | mmio = qemu_mallocz(sizeof(ppc4xx_mmio_t));
|
249 | 487414f1 | aliguori | mmio->base = base; |
250 | 1eed09cb | Avi Kivity | mmio_memory = cpu_register_io_memory(mmio_read, mmio_write, mmio); |
251 | 008ff9d7 | j_mayer | #if defined(DEBUG_MMIO)
|
252 | 487414f1 | aliguori | printf("%s: base " PADDRX " len %08x %d\n", __func__, |
253 | 487414f1 | aliguori | base, TARGET_PAGE_SIZE, mmio_memory); |
254 | 008ff9d7 | j_mayer | #endif
|
255 | 487414f1 | aliguori | cpu_register_physical_memory(base, TARGET_PAGE_SIZE, mmio_memory); |
256 | 487414f1 | aliguori | ppc4xx_mmio_register(env, mmio, 0, TARGET_PAGE_SIZE,
|
257 | 487414f1 | aliguori | unassigned_mmio_read, unassigned_mmio_write, |
258 | 487414f1 | aliguori | mmio); |
259 | 008ff9d7 | j_mayer | |
260 | 008ff9d7 | j_mayer | return mmio;
|
261 | 008ff9d7 | j_mayer | } |
262 | 008ff9d7 | j_mayer | |
263 | 008ff9d7 | j_mayer | /*****************************************************************************/
|
264 | 008ff9d7 | j_mayer | /* "Universal" Interrupt controller */
|
265 | 008ff9d7 | j_mayer | enum {
|
266 | 008ff9d7 | j_mayer | DCR_UICSR = 0x000,
|
267 | 008ff9d7 | j_mayer | DCR_UICSRS = 0x001,
|
268 | 008ff9d7 | j_mayer | DCR_UICER = 0x002,
|
269 | 008ff9d7 | j_mayer | DCR_UICCR = 0x003,
|
270 | 008ff9d7 | j_mayer | DCR_UICPR = 0x004,
|
271 | 008ff9d7 | j_mayer | DCR_UICTR = 0x005,
|
272 | 008ff9d7 | j_mayer | DCR_UICMSR = 0x006,
|
273 | 008ff9d7 | j_mayer | DCR_UICVR = 0x007,
|
274 | 008ff9d7 | j_mayer | DCR_UICVCR = 0x008,
|
275 | 008ff9d7 | j_mayer | DCR_UICMAX = 0x009,
|
276 | 008ff9d7 | j_mayer | }; |
277 | 008ff9d7 | j_mayer | |
278 | 008ff9d7 | j_mayer | #define UIC_MAX_IRQ 32 |
279 | 008ff9d7 | j_mayer | typedef struct ppcuic_t ppcuic_t; |
280 | 008ff9d7 | j_mayer | struct ppcuic_t {
|
281 | 008ff9d7 | j_mayer | uint32_t dcr_base; |
282 | 008ff9d7 | j_mayer | int use_vectors;
|
283 | 4c54e875 | aurel32 | uint32_t level; /* Remembers the state of level-triggered interrupts. */
|
284 | 008ff9d7 | j_mayer | uint32_t uicsr; /* Status register */
|
285 | 008ff9d7 | j_mayer | uint32_t uicer; /* Enable register */
|
286 | 008ff9d7 | j_mayer | uint32_t uiccr; /* Critical register */
|
287 | 008ff9d7 | j_mayer | uint32_t uicpr; /* Polarity register */
|
288 | 008ff9d7 | j_mayer | uint32_t uictr; /* Triggering register */
|
289 | 008ff9d7 | j_mayer | uint32_t uicvcr; /* Vector configuration register */
|
290 | 008ff9d7 | j_mayer | uint32_t uicvr; |
291 | 008ff9d7 | j_mayer | qemu_irq *irqs; |
292 | 008ff9d7 | j_mayer | }; |
293 | 008ff9d7 | j_mayer | |
294 | 008ff9d7 | j_mayer | static void ppcuic_trigger_irq (ppcuic_t *uic) |
295 | 008ff9d7 | j_mayer | { |
296 | 008ff9d7 | j_mayer | uint32_t ir, cr; |
297 | 008ff9d7 | j_mayer | int start, end, inc, i;
|
298 | 008ff9d7 | j_mayer | |
299 | 008ff9d7 | j_mayer | /* Trigger interrupt if any is pending */
|
300 | 008ff9d7 | j_mayer | ir = uic->uicsr & uic->uicer & (~uic->uiccr); |
301 | 008ff9d7 | j_mayer | cr = uic->uicsr & uic->uicer & uic->uiccr; |
302 | d12d51d5 | aliguori | LOG_UIC("%s: uicsr %08" PRIx32 " uicer %08" PRIx32 |
303 | aae9366a | j_mayer | " uiccr %08" PRIx32 "\n" |
304 | aae9366a | j_mayer | " %08" PRIx32 " ir %08" PRIx32 " cr %08" PRIx32 "\n", |
305 | aae9366a | j_mayer | __func__, uic->uicsr, uic->uicer, uic->uiccr, |
306 | 008ff9d7 | j_mayer | uic->uicsr & uic->uicer, ir, cr); |
307 | 008ff9d7 | j_mayer | if (ir != 0x0000000) { |
308 | d12d51d5 | aliguori | LOG_UIC("Raise UIC interrupt\n");
|
309 | 008ff9d7 | j_mayer | qemu_irq_raise(uic->irqs[PPCUIC_OUTPUT_INT]); |
310 | 008ff9d7 | j_mayer | } else {
|
311 | d12d51d5 | aliguori | LOG_UIC("Lower UIC interrupt\n");
|
312 | 008ff9d7 | j_mayer | qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_INT]); |
313 | 008ff9d7 | j_mayer | } |
314 | 008ff9d7 | j_mayer | /* Trigger critical interrupt if any is pending and update vector */
|
315 | 008ff9d7 | j_mayer | if (cr != 0x0000000) { |
316 | 008ff9d7 | j_mayer | qemu_irq_raise(uic->irqs[PPCUIC_OUTPUT_CINT]); |
317 | 008ff9d7 | j_mayer | if (uic->use_vectors) {
|
318 | 008ff9d7 | j_mayer | /* Compute critical IRQ vector */
|
319 | 008ff9d7 | j_mayer | if (uic->uicvcr & 1) { |
320 | 008ff9d7 | j_mayer | start = 31;
|
321 | 008ff9d7 | j_mayer | end = 0;
|
322 | 008ff9d7 | j_mayer | inc = -1;
|
323 | 008ff9d7 | j_mayer | } else {
|
324 | 008ff9d7 | j_mayer | start = 0;
|
325 | 008ff9d7 | j_mayer | end = 31;
|
326 | 008ff9d7 | j_mayer | inc = 1;
|
327 | 008ff9d7 | j_mayer | } |
328 | 008ff9d7 | j_mayer | uic->uicvr = uic->uicvcr & 0xFFFFFFFC;
|
329 | 008ff9d7 | j_mayer | for (i = start; i <= end; i += inc) {
|
330 | 008ff9d7 | j_mayer | if (cr & (1 << i)) { |
331 | 008ff9d7 | j_mayer | uic->uicvr += (i - start) * 512 * inc;
|
332 | 008ff9d7 | j_mayer | break;
|
333 | 008ff9d7 | j_mayer | } |
334 | 008ff9d7 | j_mayer | } |
335 | 008ff9d7 | j_mayer | } |
336 | d12d51d5 | aliguori | LOG_UIC("Raise UIC critical interrupt - "
|
337 | aae9366a | j_mayer | "vector %08" PRIx32 "\n", uic->uicvr); |
338 | 008ff9d7 | j_mayer | } else {
|
339 | d12d51d5 | aliguori | LOG_UIC("Lower UIC critical interrupt\n");
|
340 | 008ff9d7 | j_mayer | qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_CINT]); |
341 | 008ff9d7 | j_mayer | uic->uicvr = 0x00000000;
|
342 | 008ff9d7 | j_mayer | } |
343 | 008ff9d7 | j_mayer | } |
344 | 008ff9d7 | j_mayer | |
345 | 008ff9d7 | j_mayer | static void ppcuic_set_irq (void *opaque, int irq_num, int level) |
346 | 008ff9d7 | j_mayer | { |
347 | 008ff9d7 | j_mayer | ppcuic_t *uic; |
348 | 008ff9d7 | j_mayer | uint32_t mask, sr; |
349 | 008ff9d7 | j_mayer | |
350 | 008ff9d7 | j_mayer | uic = opaque; |
351 | 923e5e33 | aurel32 | mask = 1 << (31-irq_num); |
352 | d12d51d5 | aliguori | LOG_UIC("%s: irq %d level %d uicsr %08" PRIx32
|
353 | aae9366a | j_mayer | " mask %08" PRIx32 " => %08" PRIx32 " %08" PRIx32 "\n", |
354 | aae9366a | j_mayer | __func__, irq_num, level, |
355 | 008ff9d7 | j_mayer | uic->uicsr, mask, uic->uicsr & mask, level << irq_num); |
356 | 008ff9d7 | j_mayer | if (irq_num < 0 || irq_num > 31) |
357 | 008ff9d7 | j_mayer | return;
|
358 | 008ff9d7 | j_mayer | sr = uic->uicsr; |
359 | 50bf72b3 | aurel32 | |
360 | 008ff9d7 | j_mayer | /* Update status register */
|
361 | 008ff9d7 | j_mayer | if (uic->uictr & mask) {
|
362 | 008ff9d7 | j_mayer | /* Edge sensitive interrupt */
|
363 | 008ff9d7 | j_mayer | if (level == 1) |
364 | 008ff9d7 | j_mayer | uic->uicsr |= mask; |
365 | 008ff9d7 | j_mayer | } else {
|
366 | 008ff9d7 | j_mayer | /* Level sensitive interrupt */
|
367 | 4c54e875 | aurel32 | if (level == 1) { |
368 | 008ff9d7 | j_mayer | uic->uicsr |= mask; |
369 | 4c54e875 | aurel32 | uic->level |= mask; |
370 | 4c54e875 | aurel32 | } else {
|
371 | 008ff9d7 | j_mayer | uic->uicsr &= ~mask; |
372 | 4c54e875 | aurel32 | uic->level &= ~mask; |
373 | 4c54e875 | aurel32 | } |
374 | 008ff9d7 | j_mayer | } |
375 | d12d51d5 | aliguori | LOG_UIC("%s: irq %d level %d sr %" PRIx32 " => " |
376 | aae9366a | j_mayer | "%08" PRIx32 "\n", __func__, irq_num, level, uic->uicsr, sr); |
377 | 008ff9d7 | j_mayer | if (sr != uic->uicsr)
|
378 | 008ff9d7 | j_mayer | ppcuic_trigger_irq(uic); |
379 | 008ff9d7 | j_mayer | } |
380 | 008ff9d7 | j_mayer | |
381 | 008ff9d7 | j_mayer | static target_ulong dcr_read_uic (void *opaque, int dcrn) |
382 | 008ff9d7 | j_mayer | { |
383 | 008ff9d7 | j_mayer | ppcuic_t *uic; |
384 | 008ff9d7 | j_mayer | target_ulong ret; |
385 | 008ff9d7 | j_mayer | |
386 | 008ff9d7 | j_mayer | uic = opaque; |
387 | 008ff9d7 | j_mayer | dcrn -= uic->dcr_base; |
388 | 008ff9d7 | j_mayer | switch (dcrn) {
|
389 | 008ff9d7 | j_mayer | case DCR_UICSR:
|
390 | 008ff9d7 | j_mayer | case DCR_UICSRS:
|
391 | 008ff9d7 | j_mayer | ret = uic->uicsr; |
392 | 008ff9d7 | j_mayer | break;
|
393 | 008ff9d7 | j_mayer | case DCR_UICER:
|
394 | 008ff9d7 | j_mayer | ret = uic->uicer; |
395 | 008ff9d7 | j_mayer | break;
|
396 | 008ff9d7 | j_mayer | case DCR_UICCR:
|
397 | 008ff9d7 | j_mayer | ret = uic->uiccr; |
398 | 008ff9d7 | j_mayer | break;
|
399 | 008ff9d7 | j_mayer | case DCR_UICPR:
|
400 | 008ff9d7 | j_mayer | ret = uic->uicpr; |
401 | 008ff9d7 | j_mayer | break;
|
402 | 008ff9d7 | j_mayer | case DCR_UICTR:
|
403 | 008ff9d7 | j_mayer | ret = uic->uictr; |
404 | 008ff9d7 | j_mayer | break;
|
405 | 008ff9d7 | j_mayer | case DCR_UICMSR:
|
406 | 008ff9d7 | j_mayer | ret = uic->uicsr & uic->uicer; |
407 | 008ff9d7 | j_mayer | break;
|
408 | 008ff9d7 | j_mayer | case DCR_UICVR:
|
409 | 008ff9d7 | j_mayer | if (!uic->use_vectors)
|
410 | 008ff9d7 | j_mayer | goto no_read;
|
411 | 008ff9d7 | j_mayer | ret = uic->uicvr; |
412 | 008ff9d7 | j_mayer | break;
|
413 | 008ff9d7 | j_mayer | case DCR_UICVCR:
|
414 | 008ff9d7 | j_mayer | if (!uic->use_vectors)
|
415 | 008ff9d7 | j_mayer | goto no_read;
|
416 | 008ff9d7 | j_mayer | ret = uic->uicvcr; |
417 | 008ff9d7 | j_mayer | break;
|
418 | 008ff9d7 | j_mayer | default:
|
419 | 008ff9d7 | j_mayer | no_read:
|
420 | 008ff9d7 | j_mayer | ret = 0x00000000;
|
421 | 008ff9d7 | j_mayer | break;
|
422 | 008ff9d7 | j_mayer | } |
423 | 008ff9d7 | j_mayer | |
424 | 008ff9d7 | j_mayer | return ret;
|
425 | 008ff9d7 | j_mayer | } |
426 | 008ff9d7 | j_mayer | |
427 | 008ff9d7 | j_mayer | static void dcr_write_uic (void *opaque, int dcrn, target_ulong val) |
428 | 008ff9d7 | j_mayer | { |
429 | 008ff9d7 | j_mayer | ppcuic_t *uic; |
430 | 008ff9d7 | j_mayer | |
431 | 008ff9d7 | j_mayer | uic = opaque; |
432 | 008ff9d7 | j_mayer | dcrn -= uic->dcr_base; |
433 | d12d51d5 | aliguori | LOG_UIC("%s: dcr %d val " ADDRX "\n", __func__, dcrn, val); |
434 | 008ff9d7 | j_mayer | switch (dcrn) {
|
435 | 008ff9d7 | j_mayer | case DCR_UICSR:
|
436 | 008ff9d7 | j_mayer | uic->uicsr &= ~val; |
437 | 4c54e875 | aurel32 | uic->uicsr |= uic->level; |
438 | 008ff9d7 | j_mayer | ppcuic_trigger_irq(uic); |
439 | 008ff9d7 | j_mayer | break;
|
440 | 008ff9d7 | j_mayer | case DCR_UICSRS:
|
441 | 008ff9d7 | j_mayer | uic->uicsr |= val; |
442 | 008ff9d7 | j_mayer | ppcuic_trigger_irq(uic); |
443 | 008ff9d7 | j_mayer | break;
|
444 | 008ff9d7 | j_mayer | case DCR_UICER:
|
445 | 008ff9d7 | j_mayer | uic->uicer = val; |
446 | 008ff9d7 | j_mayer | ppcuic_trigger_irq(uic); |
447 | 008ff9d7 | j_mayer | break;
|
448 | 008ff9d7 | j_mayer | case DCR_UICCR:
|
449 | 008ff9d7 | j_mayer | uic->uiccr = val; |
450 | 008ff9d7 | j_mayer | ppcuic_trigger_irq(uic); |
451 | 008ff9d7 | j_mayer | break;
|
452 | 008ff9d7 | j_mayer | case DCR_UICPR:
|
453 | 008ff9d7 | j_mayer | uic->uicpr = val; |
454 | 008ff9d7 | j_mayer | break;
|
455 | 008ff9d7 | j_mayer | case DCR_UICTR:
|
456 | 008ff9d7 | j_mayer | uic->uictr = val; |
457 | 008ff9d7 | j_mayer | ppcuic_trigger_irq(uic); |
458 | 008ff9d7 | j_mayer | break;
|
459 | 008ff9d7 | j_mayer | case DCR_UICMSR:
|
460 | 008ff9d7 | j_mayer | break;
|
461 | 008ff9d7 | j_mayer | case DCR_UICVR:
|
462 | 008ff9d7 | j_mayer | break;
|
463 | 008ff9d7 | j_mayer | case DCR_UICVCR:
|
464 | 008ff9d7 | j_mayer | uic->uicvcr = val & 0xFFFFFFFD;
|
465 | 008ff9d7 | j_mayer | ppcuic_trigger_irq(uic); |
466 | 008ff9d7 | j_mayer | break;
|
467 | 008ff9d7 | j_mayer | } |
468 | 008ff9d7 | j_mayer | } |
469 | 008ff9d7 | j_mayer | |
470 | 008ff9d7 | j_mayer | static void ppcuic_reset (void *opaque) |
471 | 008ff9d7 | j_mayer | { |
472 | 008ff9d7 | j_mayer | ppcuic_t *uic; |
473 | 008ff9d7 | j_mayer | |
474 | 008ff9d7 | j_mayer | uic = opaque; |
475 | 008ff9d7 | j_mayer | uic->uiccr = 0x00000000;
|
476 | 008ff9d7 | j_mayer | uic->uicer = 0x00000000;
|
477 | 008ff9d7 | j_mayer | uic->uicpr = 0x00000000;
|
478 | 008ff9d7 | j_mayer | uic->uicsr = 0x00000000;
|
479 | 008ff9d7 | j_mayer | uic->uictr = 0x00000000;
|
480 | 008ff9d7 | j_mayer | if (uic->use_vectors) {
|
481 | 008ff9d7 | j_mayer | uic->uicvcr = 0x00000000;
|
482 | 008ff9d7 | j_mayer | uic->uicvr = 0x0000000;
|
483 | 008ff9d7 | j_mayer | } |
484 | 008ff9d7 | j_mayer | } |
485 | 008ff9d7 | j_mayer | |
486 | 008ff9d7 | j_mayer | qemu_irq *ppcuic_init (CPUState *env, qemu_irq *irqs, |
487 | 008ff9d7 | j_mayer | uint32_t dcr_base, int has_ssr, int has_vr) |
488 | 008ff9d7 | j_mayer | { |
489 | 008ff9d7 | j_mayer | ppcuic_t *uic; |
490 | 008ff9d7 | j_mayer | int i;
|
491 | 008ff9d7 | j_mayer | |
492 | 008ff9d7 | j_mayer | uic = qemu_mallocz(sizeof(ppcuic_t));
|
493 | 487414f1 | aliguori | uic->dcr_base = dcr_base; |
494 | 487414f1 | aliguori | uic->irqs = irqs; |
495 | 487414f1 | aliguori | if (has_vr)
|
496 | 487414f1 | aliguori | uic->use_vectors = 1;
|
497 | 487414f1 | aliguori | for (i = 0; i < DCR_UICMAX; i++) { |
498 | 487414f1 | aliguori | ppc_dcr_register(env, dcr_base + i, uic, |
499 | 487414f1 | aliguori | &dcr_read_uic, &dcr_write_uic); |
500 | 008ff9d7 | j_mayer | } |
501 | a08d4367 | Jan Kiszka | qemu_register_reset(ppcuic_reset, uic); |
502 | 487414f1 | aliguori | ppcuic_reset(uic); |
503 | 008ff9d7 | j_mayer | |
504 | 008ff9d7 | j_mayer | return qemu_allocate_irqs(&ppcuic_set_irq, uic, UIC_MAX_IRQ);
|
505 | 008ff9d7 | j_mayer | } |
506 | 61b24405 | aurel32 | |
507 | 61b24405 | aurel32 | /*****************************************************************************/
|
508 | 61b24405 | aurel32 | /* SDRAM controller */
|
509 | 61b24405 | aurel32 | typedef struct ppc4xx_sdram_t ppc4xx_sdram_t; |
510 | 61b24405 | aurel32 | struct ppc4xx_sdram_t {
|
511 | 61b24405 | aurel32 | uint32_t addr; |
512 | 61b24405 | aurel32 | int nbanks;
|
513 | 61b24405 | aurel32 | target_phys_addr_t ram_bases[4];
|
514 | 61b24405 | aurel32 | target_phys_addr_t ram_sizes[4];
|
515 | 61b24405 | aurel32 | uint32_t besr0; |
516 | 61b24405 | aurel32 | uint32_t besr1; |
517 | 61b24405 | aurel32 | uint32_t bear; |
518 | 61b24405 | aurel32 | uint32_t cfg; |
519 | 61b24405 | aurel32 | uint32_t status; |
520 | 61b24405 | aurel32 | uint32_t rtr; |
521 | 61b24405 | aurel32 | uint32_t pmit; |
522 | 61b24405 | aurel32 | uint32_t bcr[4];
|
523 | 61b24405 | aurel32 | uint32_t tr; |
524 | 61b24405 | aurel32 | uint32_t ecccfg; |
525 | 61b24405 | aurel32 | uint32_t eccesr; |
526 | 61b24405 | aurel32 | qemu_irq irq; |
527 | 61b24405 | aurel32 | }; |
528 | 61b24405 | aurel32 | |
529 | 61b24405 | aurel32 | enum {
|
530 | 61b24405 | aurel32 | SDRAM0_CFGADDR = 0x010,
|
531 | 61b24405 | aurel32 | SDRAM0_CFGDATA = 0x011,
|
532 | 61b24405 | aurel32 | }; |
533 | 61b24405 | aurel32 | |
534 | 61b24405 | aurel32 | /* XXX: TOFIX: some patches have made this code become inconsistent:
|
535 | 61b24405 | aurel32 | * there are type inconsistencies, mixing target_phys_addr_t, target_ulong
|
536 | 61b24405 | aurel32 | * and uint32_t
|
537 | 61b24405 | aurel32 | */
|
538 | 61b24405 | aurel32 | static uint32_t sdram_bcr (target_phys_addr_t ram_base,
|
539 | 61b24405 | aurel32 | target_phys_addr_t ram_size) |
540 | 61b24405 | aurel32 | { |
541 | 61b24405 | aurel32 | uint32_t bcr; |
542 | 61b24405 | aurel32 | |
543 | 61b24405 | aurel32 | switch (ram_size) {
|
544 | 61b24405 | aurel32 | case (4 * 1024 * 1024): |
545 | 61b24405 | aurel32 | bcr = 0x00000000;
|
546 | 61b24405 | aurel32 | break;
|
547 | 61b24405 | aurel32 | case (8 * 1024 * 1024): |
548 | 61b24405 | aurel32 | bcr = 0x00020000;
|
549 | 61b24405 | aurel32 | break;
|
550 | 61b24405 | aurel32 | case (16 * 1024 * 1024): |
551 | 61b24405 | aurel32 | bcr = 0x00040000;
|
552 | 61b24405 | aurel32 | break;
|
553 | 61b24405 | aurel32 | case (32 * 1024 * 1024): |
554 | 61b24405 | aurel32 | bcr = 0x00060000;
|
555 | 61b24405 | aurel32 | break;
|
556 | 61b24405 | aurel32 | case (64 * 1024 * 1024): |
557 | 61b24405 | aurel32 | bcr = 0x00080000;
|
558 | 61b24405 | aurel32 | break;
|
559 | 61b24405 | aurel32 | case (128 * 1024 * 1024): |
560 | 61b24405 | aurel32 | bcr = 0x000A0000;
|
561 | 61b24405 | aurel32 | break;
|
562 | 61b24405 | aurel32 | case (256 * 1024 * 1024): |
563 | 61b24405 | aurel32 | bcr = 0x000C0000;
|
564 | 61b24405 | aurel32 | break;
|
565 | 61b24405 | aurel32 | default:
|
566 | 61b24405 | aurel32 | printf("%s: invalid RAM size " PADDRX "\n", __func__, ram_size); |
567 | 61b24405 | aurel32 | return 0x00000000; |
568 | 61b24405 | aurel32 | } |
569 | 61b24405 | aurel32 | bcr |= ram_base & 0xFF800000;
|
570 | 61b24405 | aurel32 | bcr |= 1;
|
571 | 61b24405 | aurel32 | |
572 | 61b24405 | aurel32 | return bcr;
|
573 | 61b24405 | aurel32 | } |
574 | 61b24405 | aurel32 | |
575 | 61b24405 | aurel32 | static always_inline target_phys_addr_t sdram_base (uint32_t bcr)
|
576 | 61b24405 | aurel32 | { |
577 | 61b24405 | aurel32 | return bcr & 0xFF800000; |
578 | 61b24405 | aurel32 | } |
579 | 61b24405 | aurel32 | |
580 | 61b24405 | aurel32 | static target_ulong sdram_size (uint32_t bcr)
|
581 | 61b24405 | aurel32 | { |
582 | 61b24405 | aurel32 | target_ulong size; |
583 | 61b24405 | aurel32 | int sh;
|
584 | 61b24405 | aurel32 | |
585 | 61b24405 | aurel32 | sh = (bcr >> 17) & 0x7; |
586 | 61b24405 | aurel32 | if (sh == 7) |
587 | 61b24405 | aurel32 | size = -1;
|
588 | 61b24405 | aurel32 | else
|
589 | 61b24405 | aurel32 | size = (4 * 1024 * 1024) << sh; |
590 | 61b24405 | aurel32 | |
591 | 61b24405 | aurel32 | return size;
|
592 | 61b24405 | aurel32 | } |
593 | 61b24405 | aurel32 | |
594 | 61b24405 | aurel32 | static void sdram_set_bcr (uint32_t *bcrp, uint32_t bcr, int enabled) |
595 | 61b24405 | aurel32 | { |
596 | 61b24405 | aurel32 | if (*bcrp & 0x00000001) { |
597 | 61b24405 | aurel32 | /* Unmap RAM */
|
598 | 61b24405 | aurel32 | #ifdef DEBUG_SDRAM
|
599 | 61b24405 | aurel32 | printf("%s: unmap RAM area " PADDRX " " ADDRX "\n", |
600 | 61b24405 | aurel32 | __func__, sdram_base(*bcrp), sdram_size(*bcrp)); |
601 | 61b24405 | aurel32 | #endif
|
602 | 61b24405 | aurel32 | cpu_register_physical_memory(sdram_base(*bcrp), sdram_size(*bcrp), |
603 | 61b24405 | aurel32 | IO_MEM_UNASSIGNED); |
604 | 61b24405 | aurel32 | } |
605 | 61b24405 | aurel32 | *bcrp = bcr & 0xFFDEE001;
|
606 | 61b24405 | aurel32 | if (enabled && (bcr & 0x00000001)) { |
607 | 61b24405 | aurel32 | #ifdef DEBUG_SDRAM
|
608 | 61b24405 | aurel32 | printf("%s: Map RAM area " PADDRX " " ADDRX "\n", |
609 | 61b24405 | aurel32 | __func__, sdram_base(bcr), sdram_size(bcr)); |
610 | 61b24405 | aurel32 | #endif
|
611 | 61b24405 | aurel32 | cpu_register_physical_memory(sdram_base(bcr), sdram_size(bcr), |
612 | 61b24405 | aurel32 | sdram_base(bcr) | IO_MEM_RAM); |
613 | 61b24405 | aurel32 | } |
614 | 61b24405 | aurel32 | } |
615 | 61b24405 | aurel32 | |
616 | 61b24405 | aurel32 | static void sdram_map_bcr (ppc4xx_sdram_t *sdram) |
617 | 61b24405 | aurel32 | { |
618 | 61b24405 | aurel32 | int i;
|
619 | 61b24405 | aurel32 | |
620 | 61b24405 | aurel32 | for (i = 0; i < sdram->nbanks; i++) { |
621 | 61b24405 | aurel32 | if (sdram->ram_sizes[i] != 0) { |
622 | 61b24405 | aurel32 | sdram_set_bcr(&sdram->bcr[i], |
623 | 61b24405 | aurel32 | sdram_bcr(sdram->ram_bases[i], sdram->ram_sizes[i]), |
624 | 61b24405 | aurel32 | 1);
|
625 | 61b24405 | aurel32 | } else {
|
626 | 61b24405 | aurel32 | sdram_set_bcr(&sdram->bcr[i], 0x00000000, 0); |
627 | 61b24405 | aurel32 | } |
628 | 61b24405 | aurel32 | } |
629 | 61b24405 | aurel32 | } |
630 | 61b24405 | aurel32 | |
631 | 61b24405 | aurel32 | static void sdram_unmap_bcr (ppc4xx_sdram_t *sdram) |
632 | 61b24405 | aurel32 | { |
633 | 61b24405 | aurel32 | int i;
|
634 | 61b24405 | aurel32 | |
635 | 61b24405 | aurel32 | for (i = 0; i < sdram->nbanks; i++) { |
636 | 61b24405 | aurel32 | #ifdef DEBUG_SDRAM
|
637 | 61b24405 | aurel32 | printf("%s: Unmap RAM area " PADDRX " " ADDRX "\n", |
638 | 61b24405 | aurel32 | __func__, sdram_base(sdram->bcr[i]), sdram_size(sdram->bcr[i])); |
639 | 61b24405 | aurel32 | #endif
|
640 | 61b24405 | aurel32 | cpu_register_physical_memory(sdram_base(sdram->bcr[i]), |
641 | 61b24405 | aurel32 | sdram_size(sdram->bcr[i]), |
642 | 61b24405 | aurel32 | IO_MEM_UNASSIGNED); |
643 | 61b24405 | aurel32 | } |
644 | 61b24405 | aurel32 | } |
645 | 61b24405 | aurel32 | |
646 | 61b24405 | aurel32 | static target_ulong dcr_read_sdram (void *opaque, int dcrn) |
647 | 61b24405 | aurel32 | { |
648 | 61b24405 | aurel32 | ppc4xx_sdram_t *sdram; |
649 | 61b24405 | aurel32 | target_ulong ret; |
650 | 61b24405 | aurel32 | |
651 | 61b24405 | aurel32 | sdram = opaque; |
652 | 61b24405 | aurel32 | switch (dcrn) {
|
653 | 61b24405 | aurel32 | case SDRAM0_CFGADDR:
|
654 | 61b24405 | aurel32 | ret = sdram->addr; |
655 | 61b24405 | aurel32 | break;
|
656 | 61b24405 | aurel32 | case SDRAM0_CFGDATA:
|
657 | 61b24405 | aurel32 | switch (sdram->addr) {
|
658 | 61b24405 | aurel32 | case 0x00: /* SDRAM_BESR0 */ |
659 | 61b24405 | aurel32 | ret = sdram->besr0; |
660 | 61b24405 | aurel32 | break;
|
661 | 61b24405 | aurel32 | case 0x08: /* SDRAM_BESR1 */ |
662 | 61b24405 | aurel32 | ret = sdram->besr1; |
663 | 61b24405 | aurel32 | break;
|
664 | 61b24405 | aurel32 | case 0x10: /* SDRAM_BEAR */ |
665 | 61b24405 | aurel32 | ret = sdram->bear; |
666 | 61b24405 | aurel32 | break;
|
667 | 61b24405 | aurel32 | case 0x20: /* SDRAM_CFG */ |
668 | 61b24405 | aurel32 | ret = sdram->cfg; |
669 | 61b24405 | aurel32 | break;
|
670 | 61b24405 | aurel32 | case 0x24: /* SDRAM_STATUS */ |
671 | 61b24405 | aurel32 | ret = sdram->status; |
672 | 61b24405 | aurel32 | break;
|
673 | 61b24405 | aurel32 | case 0x30: /* SDRAM_RTR */ |
674 | 61b24405 | aurel32 | ret = sdram->rtr; |
675 | 61b24405 | aurel32 | break;
|
676 | 61b24405 | aurel32 | case 0x34: /* SDRAM_PMIT */ |
677 | 61b24405 | aurel32 | ret = sdram->pmit; |
678 | 61b24405 | aurel32 | break;
|
679 | 61b24405 | aurel32 | case 0x40: /* SDRAM_B0CR */ |
680 | 61b24405 | aurel32 | ret = sdram->bcr[0];
|
681 | 61b24405 | aurel32 | break;
|
682 | 61b24405 | aurel32 | case 0x44: /* SDRAM_B1CR */ |
683 | 61b24405 | aurel32 | ret = sdram->bcr[1];
|
684 | 61b24405 | aurel32 | break;
|
685 | 61b24405 | aurel32 | case 0x48: /* SDRAM_B2CR */ |
686 | 61b24405 | aurel32 | ret = sdram->bcr[2];
|
687 | 61b24405 | aurel32 | break;
|
688 | 61b24405 | aurel32 | case 0x4C: /* SDRAM_B3CR */ |
689 | 61b24405 | aurel32 | ret = sdram->bcr[3];
|
690 | 61b24405 | aurel32 | break;
|
691 | 61b24405 | aurel32 | case 0x80: /* SDRAM_TR */ |
692 | 61b24405 | aurel32 | ret = -1; /* ? */ |
693 | 61b24405 | aurel32 | break;
|
694 | 61b24405 | aurel32 | case 0x94: /* SDRAM_ECCCFG */ |
695 | 61b24405 | aurel32 | ret = sdram->ecccfg; |
696 | 61b24405 | aurel32 | break;
|
697 | 61b24405 | aurel32 | case 0x98: /* SDRAM_ECCESR */ |
698 | 61b24405 | aurel32 | ret = sdram->eccesr; |
699 | 61b24405 | aurel32 | break;
|
700 | 61b24405 | aurel32 | default: /* Error */ |
701 | 61b24405 | aurel32 | ret = -1;
|
702 | 61b24405 | aurel32 | break;
|
703 | 61b24405 | aurel32 | } |
704 | 61b24405 | aurel32 | break;
|
705 | 61b24405 | aurel32 | default:
|
706 | 61b24405 | aurel32 | /* Avoid gcc warning */
|
707 | 61b24405 | aurel32 | ret = 0x00000000;
|
708 | 61b24405 | aurel32 | break;
|
709 | 61b24405 | aurel32 | } |
710 | 61b24405 | aurel32 | |
711 | 61b24405 | aurel32 | return ret;
|
712 | 61b24405 | aurel32 | } |
713 | 61b24405 | aurel32 | |
714 | 61b24405 | aurel32 | static void dcr_write_sdram (void *opaque, int dcrn, target_ulong val) |
715 | 61b24405 | aurel32 | { |
716 | 61b24405 | aurel32 | ppc4xx_sdram_t *sdram; |
717 | 61b24405 | aurel32 | |
718 | 61b24405 | aurel32 | sdram = opaque; |
719 | 61b24405 | aurel32 | switch (dcrn) {
|
720 | 61b24405 | aurel32 | case SDRAM0_CFGADDR:
|
721 | 61b24405 | aurel32 | sdram->addr = val; |
722 | 61b24405 | aurel32 | break;
|
723 | 61b24405 | aurel32 | case SDRAM0_CFGDATA:
|
724 | 61b24405 | aurel32 | switch (sdram->addr) {
|
725 | 61b24405 | aurel32 | case 0x00: /* SDRAM_BESR0 */ |
726 | 61b24405 | aurel32 | sdram->besr0 &= ~val; |
727 | 61b24405 | aurel32 | break;
|
728 | 61b24405 | aurel32 | case 0x08: /* SDRAM_BESR1 */ |
729 | 61b24405 | aurel32 | sdram->besr1 &= ~val; |
730 | 61b24405 | aurel32 | break;
|
731 | 61b24405 | aurel32 | case 0x10: /* SDRAM_BEAR */ |
732 | 61b24405 | aurel32 | sdram->bear = val; |
733 | 61b24405 | aurel32 | break;
|
734 | 61b24405 | aurel32 | case 0x20: /* SDRAM_CFG */ |
735 | 61b24405 | aurel32 | val &= 0xFFE00000;
|
736 | 61b24405 | aurel32 | if (!(sdram->cfg & 0x80000000) && (val & 0x80000000)) { |
737 | 61b24405 | aurel32 | #ifdef DEBUG_SDRAM
|
738 | 61b24405 | aurel32 | printf("%s: enable SDRAM controller\n", __func__);
|
739 | 61b24405 | aurel32 | #endif
|
740 | 61b24405 | aurel32 | /* validate all RAM mappings */
|
741 | 61b24405 | aurel32 | sdram_map_bcr(sdram); |
742 | 61b24405 | aurel32 | sdram->status &= ~0x80000000;
|
743 | 61b24405 | aurel32 | } else if ((sdram->cfg & 0x80000000) && !(val & 0x80000000)) { |
744 | 61b24405 | aurel32 | #ifdef DEBUG_SDRAM
|
745 | 61b24405 | aurel32 | printf("%s: disable SDRAM controller\n", __func__);
|
746 | 61b24405 | aurel32 | #endif
|
747 | 61b24405 | aurel32 | /* invalidate all RAM mappings */
|
748 | 61b24405 | aurel32 | sdram_unmap_bcr(sdram); |
749 | 61b24405 | aurel32 | sdram->status |= 0x80000000;
|
750 | 61b24405 | aurel32 | } |
751 | 61b24405 | aurel32 | if (!(sdram->cfg & 0x40000000) && (val & 0x40000000)) |
752 | 61b24405 | aurel32 | sdram->status |= 0x40000000;
|
753 | 61b24405 | aurel32 | else if ((sdram->cfg & 0x40000000) && !(val & 0x40000000)) |
754 | 61b24405 | aurel32 | sdram->status &= ~0x40000000;
|
755 | 61b24405 | aurel32 | sdram->cfg = val; |
756 | 61b24405 | aurel32 | break;
|
757 | 61b24405 | aurel32 | case 0x24: /* SDRAM_STATUS */ |
758 | 61b24405 | aurel32 | /* Read-only register */
|
759 | 61b24405 | aurel32 | break;
|
760 | 61b24405 | aurel32 | case 0x30: /* SDRAM_RTR */ |
761 | 61b24405 | aurel32 | sdram->rtr = val & 0x3FF80000;
|
762 | 61b24405 | aurel32 | break;
|
763 | 61b24405 | aurel32 | case 0x34: /* SDRAM_PMIT */ |
764 | 61b24405 | aurel32 | sdram->pmit = (val & 0xF8000000) | 0x07C00000; |
765 | 61b24405 | aurel32 | break;
|
766 | 61b24405 | aurel32 | case 0x40: /* SDRAM_B0CR */ |
767 | 61b24405 | aurel32 | sdram_set_bcr(&sdram->bcr[0], val, sdram->cfg & 0x80000000); |
768 | 61b24405 | aurel32 | break;
|
769 | 61b24405 | aurel32 | case 0x44: /* SDRAM_B1CR */ |
770 | 61b24405 | aurel32 | sdram_set_bcr(&sdram->bcr[1], val, sdram->cfg & 0x80000000); |
771 | 61b24405 | aurel32 | break;
|
772 | 61b24405 | aurel32 | case 0x48: /* SDRAM_B2CR */ |
773 | 61b24405 | aurel32 | sdram_set_bcr(&sdram->bcr[2], val, sdram->cfg & 0x80000000); |
774 | 61b24405 | aurel32 | break;
|
775 | 61b24405 | aurel32 | case 0x4C: /* SDRAM_B3CR */ |
776 | 61b24405 | aurel32 | sdram_set_bcr(&sdram->bcr[3], val, sdram->cfg & 0x80000000); |
777 | 61b24405 | aurel32 | break;
|
778 | 61b24405 | aurel32 | case 0x80: /* SDRAM_TR */ |
779 | 61b24405 | aurel32 | sdram->tr = val & 0x018FC01F;
|
780 | 61b24405 | aurel32 | break;
|
781 | 61b24405 | aurel32 | case 0x94: /* SDRAM_ECCCFG */ |
782 | 61b24405 | aurel32 | sdram->ecccfg = val & 0x00F00000;
|
783 | 61b24405 | aurel32 | break;
|
784 | 61b24405 | aurel32 | case 0x98: /* SDRAM_ECCESR */ |
785 | 61b24405 | aurel32 | val &= 0xFFF0F000;
|
786 | 61b24405 | aurel32 | if (sdram->eccesr == 0 && val != 0) |
787 | 61b24405 | aurel32 | qemu_irq_raise(sdram->irq); |
788 | 61b24405 | aurel32 | else if (sdram->eccesr != 0 && val == 0) |
789 | 61b24405 | aurel32 | qemu_irq_lower(sdram->irq); |
790 | 61b24405 | aurel32 | sdram->eccesr = val; |
791 | 61b24405 | aurel32 | break;
|
792 | 61b24405 | aurel32 | default: /* Error */ |
793 | 61b24405 | aurel32 | break;
|
794 | 61b24405 | aurel32 | } |
795 | 61b24405 | aurel32 | break;
|
796 | 61b24405 | aurel32 | } |
797 | 61b24405 | aurel32 | } |
798 | 61b24405 | aurel32 | |
799 | 61b24405 | aurel32 | static void sdram_reset (void *opaque) |
800 | 61b24405 | aurel32 | { |
801 | 61b24405 | aurel32 | ppc4xx_sdram_t *sdram; |
802 | 61b24405 | aurel32 | |
803 | 61b24405 | aurel32 | sdram = opaque; |
804 | 61b24405 | aurel32 | sdram->addr = 0x00000000;
|
805 | 61b24405 | aurel32 | sdram->bear = 0x00000000;
|
806 | 61b24405 | aurel32 | sdram->besr0 = 0x00000000; /* No error */ |
807 | 61b24405 | aurel32 | sdram->besr1 = 0x00000000; /* No error */ |
808 | 61b24405 | aurel32 | sdram->cfg = 0x00000000;
|
809 | 61b24405 | aurel32 | sdram->ecccfg = 0x00000000; /* No ECC */ |
810 | 61b24405 | aurel32 | sdram->eccesr = 0x00000000; /* No error */ |
811 | 61b24405 | aurel32 | sdram->pmit = 0x07C00000;
|
812 | 61b24405 | aurel32 | sdram->rtr = 0x05F00000;
|
813 | 61b24405 | aurel32 | sdram->tr = 0x00854009;
|
814 | 61b24405 | aurel32 | /* We pre-initialize RAM banks */
|
815 | 61b24405 | aurel32 | sdram->status = 0x00000000;
|
816 | 61b24405 | aurel32 | sdram->cfg = 0x00800000;
|
817 | 61b24405 | aurel32 | sdram_unmap_bcr(sdram); |
818 | 61b24405 | aurel32 | } |
819 | 61b24405 | aurel32 | |
820 | 80e8bd2b | aurel32 | void ppc4xx_sdram_init (CPUState *env, qemu_irq irq, int nbanks, |
821 | 61b24405 | aurel32 | target_phys_addr_t *ram_bases, |
822 | 61b24405 | aurel32 | target_phys_addr_t *ram_sizes, |
823 | 61b24405 | aurel32 | int do_init)
|
824 | 61b24405 | aurel32 | { |
825 | 61b24405 | aurel32 | ppc4xx_sdram_t *sdram; |
826 | 61b24405 | aurel32 | |
827 | 61b24405 | aurel32 | sdram = qemu_mallocz(sizeof(ppc4xx_sdram_t));
|
828 | 487414f1 | aliguori | sdram->irq = irq; |
829 | 487414f1 | aliguori | sdram->nbanks = nbanks; |
830 | 487414f1 | aliguori | memset(sdram->ram_bases, 0, 4 * sizeof(target_phys_addr_t)); |
831 | 487414f1 | aliguori | memcpy(sdram->ram_bases, ram_bases, |
832 | 487414f1 | aliguori | nbanks * sizeof(target_phys_addr_t));
|
833 | 487414f1 | aliguori | memset(sdram->ram_sizes, 0, 4 * sizeof(target_phys_addr_t)); |
834 | 487414f1 | aliguori | memcpy(sdram->ram_sizes, ram_sizes, |
835 | 487414f1 | aliguori | nbanks * sizeof(target_phys_addr_t));
|
836 | 487414f1 | aliguori | sdram_reset(sdram); |
837 | a08d4367 | Jan Kiszka | qemu_register_reset(&sdram_reset, sdram); |
838 | 487414f1 | aliguori | ppc_dcr_register(env, SDRAM0_CFGADDR, |
839 | 487414f1 | aliguori | sdram, &dcr_read_sdram, &dcr_write_sdram); |
840 | 487414f1 | aliguori | ppc_dcr_register(env, SDRAM0_CFGDATA, |
841 | 487414f1 | aliguori | sdram, &dcr_read_sdram, &dcr_write_sdram); |
842 | 487414f1 | aliguori | if (do_init)
|
843 | 487414f1 | aliguori | sdram_map_bcr(sdram); |
844 | 61b24405 | aurel32 | } |
845 | b7da58fd | aurel32 | |
846 | b7da58fd | aurel32 | /* Fill in consecutive SDRAM banks with 'ram_size' bytes of memory.
|
847 | b7da58fd | aurel32 | *
|
848 | b7da58fd | aurel32 | * sdram_bank_sizes[] must be 0-terminated.
|
849 | b7da58fd | aurel32 | *
|
850 | b7da58fd | aurel32 | * The 4xx SDRAM controller supports a small number of banks, and each bank
|
851 | b7da58fd | aurel32 | * must be one of a small set of sizes. The number of banks and the supported
|
852 | b7da58fd | aurel32 | * sizes varies by SoC. */
|
853 | b7da58fd | aurel32 | ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks,
|
854 | b7da58fd | aurel32 | target_phys_addr_t ram_bases[], |
855 | b7da58fd | aurel32 | target_phys_addr_t ram_sizes[], |
856 | b7da58fd | aurel32 | const unsigned int sdram_bank_sizes[]) |
857 | b7da58fd | aurel32 | { |
858 | 5c130f65 | pbrook | ram_addr_t size_left = ram_size; |
859 | b7da58fd | aurel32 | int i;
|
860 | b7da58fd | aurel32 | int j;
|
861 | b7da58fd | aurel32 | |
862 | b7da58fd | aurel32 | for (i = 0; i < nr_banks; i++) { |
863 | b7da58fd | aurel32 | for (j = 0; sdram_bank_sizes[j] != 0; j++) { |
864 | b7da58fd | aurel32 | unsigned int bank_size = sdram_bank_sizes[j]; |
865 | b7da58fd | aurel32 | |
866 | 5c130f65 | pbrook | if (bank_size <= size_left) {
|
867 | 5c130f65 | pbrook | ram_bases[i] = qemu_ram_alloc(bank_size); |
868 | b7da58fd | aurel32 | ram_sizes[i] = bank_size; |
869 | 5c130f65 | pbrook | size_left -= bank_size; |
870 | b7da58fd | aurel32 | break;
|
871 | b7da58fd | aurel32 | } |
872 | b7da58fd | aurel32 | } |
873 | b7da58fd | aurel32 | |
874 | 5c130f65 | pbrook | if (!size_left) {
|
875 | b7da58fd | aurel32 | /* No need to use the remaining banks. */
|
876 | b7da58fd | aurel32 | break;
|
877 | b7da58fd | aurel32 | } |
878 | b7da58fd | aurel32 | } |
879 | b7da58fd | aurel32 | |
880 | 5c130f65 | pbrook | ram_size -= size_left; |
881 | b7da58fd | aurel32 | if (ram_size)
|
882 | b7da58fd | aurel32 | printf("Truncating memory to %d MiB to fit SDRAM controller limits.\n",
|
883 | 5c130f65 | pbrook | (int)(ram_size >> 20)); |
884 | b7da58fd | aurel32 | |
885 | 5c130f65 | pbrook | return ram_size;
|
886 | b7da58fd | aurel32 | } |