root / hw / m48t59.c @ 97237e0a
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/*
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* QEMU M48T59 and M48T08 NVRAM emulation for PPC PREP and Sparc platforms
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*
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* Copyright (c) 2003-2005, 2007 Jocelyn Mayer
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h" |
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#include "nvram.h" |
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#include "qemu-timer.h" |
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#include "sysemu.h" |
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#include "sysbus.h" |
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#include "isa.h" |
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//#define DEBUG_NVRAM
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#if defined(DEBUG_NVRAM)
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#define NVRAM_PRINTF(fmt, ...) do { printf(fmt , ## __VA_ARGS__); } while (0) |
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#else
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#define NVRAM_PRINTF(fmt, ...) do { } while (0) |
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#endif
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/*
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* The M48T02, M48T08 and M48T59 chips are very similar. The newer '59 has
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* alarm and a watchdog timer and related control registers. In the
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* PPC platform there is also a nvram lock function.
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*/
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/*
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* Chipset docs:
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* http://www.st.com/stonline/products/literature/ds/2410/m48t02.pdf
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* http://www.st.com/stonline/products/literature/ds/2411/m48t08.pdf
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* http://www.st.com/stonline/products/literature/od/7001/m48t59y.pdf
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*/
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struct M48t59State {
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/* Hardware parameters */
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qemu_irq IRQ; |
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uint32_t io_base; |
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uint32_t size; |
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/* RTC management */
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time_t time_offset; |
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time_t stop_time; |
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/* Alarm & watchdog */
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struct tm alarm;
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struct QEMUTimer *alrm_timer;
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struct QEMUTimer *wd_timer;
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/* NVRAM storage */
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uint8_t *buffer; |
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/* Model parameters */
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uint32_t type; /* 2 = m48t02, 8 = m48t08, 59 = m48t59 */
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/* NVRAM storage */
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uint16_t addr; |
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uint8_t lock; |
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}; |
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typedef struct M48t59ISAState { |
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ISADevice busdev; |
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M48t59State state; |
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} M48t59ISAState; |
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typedef struct M48t59SysBusState { |
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SysBusDevice busdev; |
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M48t59State state; |
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} M48t59SysBusState; |
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/* Fake timer functions */
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|
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/* Alarm management */
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static void alarm_cb (void *opaque) |
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{ |
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struct tm tm;
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uint64_t next_time; |
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M48t59State *NVRAM = opaque; |
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qemu_set_irq(NVRAM->IRQ, 1);
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if ((NVRAM->buffer[0x1FF5] & 0x80) == 0 && |
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(NVRAM->buffer[0x1FF4] & 0x80) == 0 && |
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(NVRAM->buffer[0x1FF3] & 0x80) == 0 && |
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(NVRAM->buffer[0x1FF2] & 0x80) == 0) { |
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/* Repeat once a month */
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qemu_get_timedate(&tm, NVRAM->time_offset); |
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tm.tm_mon++; |
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if (tm.tm_mon == 13) { |
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tm.tm_mon = 1;
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tm.tm_year++; |
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} |
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next_time = qemu_timedate_diff(&tm) - NVRAM->time_offset; |
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} else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 && |
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(NVRAM->buffer[0x1FF4] & 0x80) == 0 && |
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(NVRAM->buffer[0x1FF3] & 0x80) == 0 && |
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(NVRAM->buffer[0x1FF2] & 0x80) == 0) { |
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/* Repeat once a day */
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next_time = 24 * 60 * 60; |
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} else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 && |
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(NVRAM->buffer[0x1FF4] & 0x80) != 0 && |
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(NVRAM->buffer[0x1FF3] & 0x80) == 0 && |
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(NVRAM->buffer[0x1FF2] & 0x80) == 0) { |
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/* Repeat once an hour */
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next_time = 60 * 60; |
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} else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 && |
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(NVRAM->buffer[0x1FF4] & 0x80) != 0 && |
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(NVRAM->buffer[0x1FF3] & 0x80) != 0 && |
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(NVRAM->buffer[0x1FF2] & 0x80) == 0) { |
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/* Repeat once a minute */
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next_time = 60;
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} else {
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/* Repeat once a second */
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next_time = 1;
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} |
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qemu_mod_timer(NVRAM->alrm_timer, qemu_get_clock_ns(vm_clock) + |
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next_time * 1000);
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qemu_set_irq(NVRAM->IRQ, 0);
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} |
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static void set_alarm(M48t59State *NVRAM) |
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{ |
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int diff;
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if (NVRAM->alrm_timer != NULL) { |
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qemu_del_timer(NVRAM->alrm_timer); |
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diff = qemu_timedate_diff(&NVRAM->alarm) - NVRAM->time_offset; |
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if (diff > 0) |
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qemu_mod_timer(NVRAM->alrm_timer, diff * 1000);
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} |
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} |
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/* RTC management helpers */
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static inline void get_time(M48t59State *NVRAM, struct tm *tm) |
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{ |
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qemu_get_timedate(tm, NVRAM->time_offset); |
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} |
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static void set_time(M48t59State *NVRAM, struct tm *tm) |
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{ |
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NVRAM->time_offset = qemu_timedate_diff(tm); |
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set_alarm(NVRAM); |
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} |
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/* Watchdog management */
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static void watchdog_cb (void *opaque) |
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{ |
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M48t59State *NVRAM = opaque; |
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NVRAM->buffer[0x1FF0] |= 0x80; |
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if (NVRAM->buffer[0x1FF7] & 0x80) { |
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NVRAM->buffer[0x1FF7] = 0x00; |
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NVRAM->buffer[0x1FFC] &= ~0x40; |
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/* May it be a hw CPU Reset instead ? */
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qemu_system_reset_request(); |
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} else {
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qemu_set_irq(NVRAM->IRQ, 1);
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qemu_set_irq(NVRAM->IRQ, 0);
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} |
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} |
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static void set_up_watchdog(M48t59State *NVRAM, uint8_t value) |
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{ |
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uint64_t interval; /* in 1/16 seconds */
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NVRAM->buffer[0x1FF0] &= ~0x80; |
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if (NVRAM->wd_timer != NULL) { |
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qemu_del_timer(NVRAM->wd_timer); |
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if (value != 0) { |
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interval = (1 << (2 * (value & 0x03))) * ((value >> 2) & 0x1F); |
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qemu_mod_timer(NVRAM->wd_timer, ((uint64_t)time(NULL) * 1000) + |
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((interval * 1000) >> 4)); |
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} |
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} |
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} |
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/* Direct access to NVRAM */
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void m48t59_write (void *opaque, uint32_t addr, uint32_t val) |
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{ |
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M48t59State *NVRAM = opaque; |
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struct tm tm;
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int tmp;
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if (addr > 0x1FF8 && addr < 0x2000) |
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NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
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/* check for NVRAM access */
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if ((NVRAM->type == 2 && addr < 0x7f8) || |
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(NVRAM->type == 8 && addr < 0x1ff8) || |
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(NVRAM->type == 59 && addr < 0x1ff0)) |
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goto do_write;
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/* TOD access */
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switch (addr) {
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case 0x1FF0: |
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/* flags register : read-only */
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break;
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case 0x1FF1: |
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/* unused */
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break;
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case 0x1FF2: |
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/* alarm seconds */
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tmp = from_bcd(val & 0x7F);
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if (tmp >= 0 && tmp <= 59) { |
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NVRAM->alarm.tm_sec = tmp; |
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NVRAM->buffer[0x1FF2] = val;
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set_alarm(NVRAM); |
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} |
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break;
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case 0x1FF3: |
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/* alarm minutes */
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tmp = from_bcd(val & 0x7F);
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if (tmp >= 0 && tmp <= 59) { |
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NVRAM->alarm.tm_min = tmp; |
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NVRAM->buffer[0x1FF3] = val;
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set_alarm(NVRAM); |
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} |
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break;
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case 0x1FF4: |
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/* alarm hours */
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tmp = from_bcd(val & 0x3F);
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if (tmp >= 0 && tmp <= 23) { |
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NVRAM->alarm.tm_hour = tmp; |
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NVRAM->buffer[0x1FF4] = val;
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set_alarm(NVRAM); |
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} |
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break;
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case 0x1FF5: |
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/* alarm date */
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tmp = from_bcd(val & 0x1F);
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if (tmp != 0) { |
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NVRAM->alarm.tm_mday = tmp; |
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NVRAM->buffer[0x1FF5] = val;
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set_alarm(NVRAM); |
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} |
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break;
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case 0x1FF6: |
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/* interrupts */
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NVRAM->buffer[0x1FF6] = val;
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break;
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case 0x1FF7: |
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/* watchdog */
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NVRAM->buffer[0x1FF7] = val;
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set_up_watchdog(NVRAM, val); |
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break;
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case 0x1FF8: |
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case 0x07F8: |
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/* control */
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NVRAM->buffer[addr] = (val & ~0xA0) | 0x90; |
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break;
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case 0x1FF9: |
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case 0x07F9: |
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/* seconds (BCD) */
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tmp = from_bcd(val & 0x7F);
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if (tmp >= 0 && tmp <= 59) { |
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get_time(NVRAM, &tm); |
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tm.tm_sec = tmp; |
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set_time(NVRAM, &tm); |
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} |
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if ((val & 0x80) ^ (NVRAM->buffer[addr] & 0x80)) { |
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if (val & 0x80) { |
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NVRAM->stop_time = time(NULL);
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} else {
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NVRAM->time_offset += NVRAM->stop_time - time(NULL);
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NVRAM->stop_time = 0;
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} |
277 |
} |
278 |
NVRAM->buffer[addr] = val & 0x80;
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break;
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case 0x1FFA: |
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case 0x07FA: |
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/* minutes (BCD) */
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tmp = from_bcd(val & 0x7F);
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if (tmp >= 0 && tmp <= 59) { |
285 |
get_time(NVRAM, &tm); |
286 |
tm.tm_min = tmp; |
287 |
set_time(NVRAM, &tm); |
288 |
} |
289 |
break;
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case 0x1FFB: |
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case 0x07FB: |
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/* hours (BCD) */
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tmp = from_bcd(val & 0x3F);
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if (tmp >= 0 && tmp <= 23) { |
295 |
get_time(NVRAM, &tm); |
296 |
tm.tm_hour = tmp; |
297 |
set_time(NVRAM, &tm); |
298 |
} |
299 |
break;
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case 0x1FFC: |
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case 0x07FC: |
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/* day of the week / century */
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tmp = from_bcd(val & 0x07);
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get_time(NVRAM, &tm); |
305 |
tm.tm_wday = tmp; |
306 |
set_time(NVRAM, &tm); |
307 |
NVRAM->buffer[addr] = val & 0x40;
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break;
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case 0x1FFD: |
310 |
case 0x07FD: |
311 |
/* date */
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312 |
tmp = from_bcd(val & 0x1F);
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313 |
if (tmp != 0) { |
314 |
get_time(NVRAM, &tm); |
315 |
tm.tm_mday = tmp; |
316 |
set_time(NVRAM, &tm); |
317 |
} |
318 |
break;
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319 |
case 0x1FFE: |
320 |
case 0x07FE: |
321 |
/* month */
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322 |
tmp = from_bcd(val & 0x1F);
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323 |
if (tmp >= 1 && tmp <= 12) { |
324 |
get_time(NVRAM, &tm); |
325 |
tm.tm_mon = tmp - 1;
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326 |
set_time(NVRAM, &tm); |
327 |
} |
328 |
break;
|
329 |
case 0x1FFF: |
330 |
case 0x07FF: |
331 |
/* year */
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332 |
tmp = from_bcd(val); |
333 |
if (tmp >= 0 && tmp <= 99) { |
334 |
get_time(NVRAM, &tm); |
335 |
if (NVRAM->type == 8) |
336 |
tm.tm_year = from_bcd(val) + 68; // Base year is 1968 |
337 |
else
|
338 |
tm.tm_year = from_bcd(val); |
339 |
set_time(NVRAM, &tm); |
340 |
} |
341 |
break;
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342 |
default:
|
343 |
/* Check lock registers state */
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344 |
if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1)) |
345 |
break;
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346 |
if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2)) |
347 |
break;
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348 |
do_write:
|
349 |
if (addr < NVRAM->size) {
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350 |
NVRAM->buffer[addr] = val & 0xFF;
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351 |
} |
352 |
break;
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353 |
} |
354 |
} |
355 |
|
356 |
uint32_t m48t59_read (void *opaque, uint32_t addr)
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357 |
{ |
358 |
M48t59State *NVRAM = opaque; |
359 |
struct tm tm;
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360 |
uint32_t retval = 0xFF;
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361 |
|
362 |
/* check for NVRAM access */
|
363 |
if ((NVRAM->type == 2 && addr < 0x078f) || |
364 |
(NVRAM->type == 8 && addr < 0x1ff8) || |
365 |
(NVRAM->type == 59 && addr < 0x1ff0)) |
366 |
goto do_read;
|
367 |
|
368 |
/* TOD access */
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369 |
switch (addr) {
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370 |
case 0x1FF0: |
371 |
/* flags register */
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372 |
goto do_read;
|
373 |
case 0x1FF1: |
374 |
/* unused */
|
375 |
retval = 0;
|
376 |
break;
|
377 |
case 0x1FF2: |
378 |
/* alarm seconds */
|
379 |
goto do_read;
|
380 |
case 0x1FF3: |
381 |
/* alarm minutes */
|
382 |
goto do_read;
|
383 |
case 0x1FF4: |
384 |
/* alarm hours */
|
385 |
goto do_read;
|
386 |
case 0x1FF5: |
387 |
/* alarm date */
|
388 |
goto do_read;
|
389 |
case 0x1FF6: |
390 |
/* interrupts */
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391 |
goto do_read;
|
392 |
case 0x1FF7: |
393 |
/* A read resets the watchdog */
|
394 |
set_up_watchdog(NVRAM, NVRAM->buffer[0x1FF7]);
|
395 |
goto do_read;
|
396 |
case 0x1FF8: |
397 |
case 0x07F8: |
398 |
/* control */
|
399 |
goto do_read;
|
400 |
case 0x1FF9: |
401 |
case 0x07F9: |
402 |
/* seconds (BCD) */
|
403 |
get_time(NVRAM, &tm); |
404 |
retval = (NVRAM->buffer[addr] & 0x80) | to_bcd(tm.tm_sec);
|
405 |
break;
|
406 |
case 0x1FFA: |
407 |
case 0x07FA: |
408 |
/* minutes (BCD) */
|
409 |
get_time(NVRAM, &tm); |
410 |
retval = to_bcd(tm.tm_min); |
411 |
break;
|
412 |
case 0x1FFB: |
413 |
case 0x07FB: |
414 |
/* hours (BCD) */
|
415 |
get_time(NVRAM, &tm); |
416 |
retval = to_bcd(tm.tm_hour); |
417 |
break;
|
418 |
case 0x1FFC: |
419 |
case 0x07FC: |
420 |
/* day of the week / century */
|
421 |
get_time(NVRAM, &tm); |
422 |
retval = NVRAM->buffer[addr] | tm.tm_wday; |
423 |
break;
|
424 |
case 0x1FFD: |
425 |
case 0x07FD: |
426 |
/* date */
|
427 |
get_time(NVRAM, &tm); |
428 |
retval = to_bcd(tm.tm_mday); |
429 |
break;
|
430 |
case 0x1FFE: |
431 |
case 0x07FE: |
432 |
/* month */
|
433 |
get_time(NVRAM, &tm); |
434 |
retval = to_bcd(tm.tm_mon + 1);
|
435 |
break;
|
436 |
case 0x1FFF: |
437 |
case 0x07FF: |
438 |
/* year */
|
439 |
get_time(NVRAM, &tm); |
440 |
if (NVRAM->type == 8) |
441 |
retval = to_bcd(tm.tm_year - 68); // Base year is 1968 |
442 |
else
|
443 |
retval = to_bcd(tm.tm_year); |
444 |
break;
|
445 |
default:
|
446 |
/* Check lock registers state */
|
447 |
if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1)) |
448 |
break;
|
449 |
if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2)) |
450 |
break;
|
451 |
do_read:
|
452 |
if (addr < NVRAM->size) {
|
453 |
retval = NVRAM->buffer[addr]; |
454 |
} |
455 |
break;
|
456 |
} |
457 |
if (addr > 0x1FF9 && addr < 0x2000) |
458 |
NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__, addr, retval);
|
459 |
|
460 |
return retval;
|
461 |
} |
462 |
|
463 |
void m48t59_set_addr (void *opaque, uint32_t addr) |
464 |
{ |
465 |
M48t59State *NVRAM = opaque; |
466 |
|
467 |
NVRAM->addr = addr; |
468 |
} |
469 |
|
470 |
void m48t59_toggle_lock (void *opaque, int lock) |
471 |
{ |
472 |
M48t59State *NVRAM = opaque; |
473 |
|
474 |
NVRAM->lock ^= 1 << lock;
|
475 |
} |
476 |
|
477 |
/* IO access to NVRAM */
|
478 |
static void NVRAM_writeb (void *opaque, uint32_t addr, uint32_t val) |
479 |
{ |
480 |
M48t59State *NVRAM = opaque; |
481 |
|
482 |
addr -= NVRAM->io_base; |
483 |
NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
|
484 |
switch (addr) {
|
485 |
case 0: |
486 |
NVRAM->addr &= ~0x00FF;
|
487 |
NVRAM->addr |= val; |
488 |
break;
|
489 |
case 1: |
490 |
NVRAM->addr &= ~0xFF00;
|
491 |
NVRAM->addr |= val << 8;
|
492 |
break;
|
493 |
case 3: |
494 |
m48t59_write(NVRAM, val, NVRAM->addr); |
495 |
NVRAM->addr = 0x0000;
|
496 |
break;
|
497 |
default:
|
498 |
break;
|
499 |
} |
500 |
} |
501 |
|
502 |
static uint32_t NVRAM_readb (void *opaque, uint32_t addr) |
503 |
{ |
504 |
M48t59State *NVRAM = opaque; |
505 |
uint32_t retval; |
506 |
|
507 |
addr -= NVRAM->io_base; |
508 |
switch (addr) {
|
509 |
case 3: |
510 |
retval = m48t59_read(NVRAM, NVRAM->addr); |
511 |
break;
|
512 |
default:
|
513 |
retval = -1;
|
514 |
break;
|
515 |
} |
516 |
NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__, addr, retval);
|
517 |
|
518 |
return retval;
|
519 |
} |
520 |
|
521 |
static void nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t value) |
522 |
{ |
523 |
M48t59State *NVRAM = opaque; |
524 |
|
525 |
m48t59_write(NVRAM, addr, value & 0xff);
|
526 |
} |
527 |
|
528 |
static void nvram_writew (void *opaque, target_phys_addr_t addr, uint32_t value) |
529 |
{ |
530 |
M48t59State *NVRAM = opaque; |
531 |
|
532 |
m48t59_write(NVRAM, addr, (value >> 8) & 0xff); |
533 |
m48t59_write(NVRAM, addr + 1, value & 0xff); |
534 |
} |
535 |
|
536 |
static void nvram_writel (void *opaque, target_phys_addr_t addr, uint32_t value) |
537 |
{ |
538 |
M48t59State *NVRAM = opaque; |
539 |
|
540 |
m48t59_write(NVRAM, addr, (value >> 24) & 0xff); |
541 |
m48t59_write(NVRAM, addr + 1, (value >> 16) & 0xff); |
542 |
m48t59_write(NVRAM, addr + 2, (value >> 8) & 0xff); |
543 |
m48t59_write(NVRAM, addr + 3, value & 0xff); |
544 |
} |
545 |
|
546 |
static uint32_t nvram_readb (void *opaque, target_phys_addr_t addr) |
547 |
{ |
548 |
M48t59State *NVRAM = opaque; |
549 |
uint32_t retval; |
550 |
|
551 |
retval = m48t59_read(NVRAM, addr); |
552 |
return retval;
|
553 |
} |
554 |
|
555 |
static uint32_t nvram_readw (void *opaque, target_phys_addr_t addr) |
556 |
{ |
557 |
M48t59State *NVRAM = opaque; |
558 |
uint32_t retval; |
559 |
|
560 |
retval = m48t59_read(NVRAM, addr) << 8;
|
561 |
retval |= m48t59_read(NVRAM, addr + 1);
|
562 |
return retval;
|
563 |
} |
564 |
|
565 |
static uint32_t nvram_readl (void *opaque, target_phys_addr_t addr) |
566 |
{ |
567 |
M48t59State *NVRAM = opaque; |
568 |
uint32_t retval; |
569 |
|
570 |
retval = m48t59_read(NVRAM, addr) << 24;
|
571 |
retval |= m48t59_read(NVRAM, addr + 1) << 16; |
572 |
retval |= m48t59_read(NVRAM, addr + 2) << 8; |
573 |
retval |= m48t59_read(NVRAM, addr + 3);
|
574 |
return retval;
|
575 |
} |
576 |
|
577 |
static CPUWriteMemoryFunc * const nvram_write[] = { |
578 |
&nvram_writeb, |
579 |
&nvram_writew, |
580 |
&nvram_writel, |
581 |
}; |
582 |
|
583 |
static CPUReadMemoryFunc * const nvram_read[] = { |
584 |
&nvram_readb, |
585 |
&nvram_readw, |
586 |
&nvram_readl, |
587 |
}; |
588 |
|
589 |
static const VMStateDescription vmstate_m48t59 = { |
590 |
.name = "m48t59",
|
591 |
.version_id = 1,
|
592 |
.minimum_version_id = 1,
|
593 |
.minimum_version_id_old = 1,
|
594 |
.fields = (VMStateField[]) { |
595 |
VMSTATE_UINT8(lock, M48t59State), |
596 |
VMSTATE_UINT16(addr, M48t59State), |
597 |
VMSTATE_VBUFFER_UINT32(buffer, M48t59State, 0, NULL, 0, size), |
598 |
VMSTATE_END_OF_LIST() |
599 |
} |
600 |
}; |
601 |
|
602 |
static void m48t59_reset_common(M48t59State *NVRAM) |
603 |
{ |
604 |
NVRAM->addr = 0;
|
605 |
NVRAM->lock = 0;
|
606 |
if (NVRAM->alrm_timer != NULL) |
607 |
qemu_del_timer(NVRAM->alrm_timer); |
608 |
|
609 |
if (NVRAM->wd_timer != NULL) |
610 |
qemu_del_timer(NVRAM->wd_timer); |
611 |
} |
612 |
|
613 |
static void m48t59_reset_isa(DeviceState *d) |
614 |
{ |
615 |
M48t59ISAState *isa = container_of(d, M48t59ISAState, busdev.qdev); |
616 |
M48t59State *NVRAM = &isa->state; |
617 |
|
618 |
m48t59_reset_common(NVRAM); |
619 |
} |
620 |
|
621 |
static void m48t59_reset_sysbus(DeviceState *d) |
622 |
{ |
623 |
M48t59SysBusState *sys = container_of(d, M48t59SysBusState, busdev.qdev); |
624 |
M48t59State *NVRAM = &sys->state; |
625 |
|
626 |
m48t59_reset_common(NVRAM); |
627 |
} |
628 |
|
629 |
/* Initialisation routine */
|
630 |
M48t59State *m48t59_init(qemu_irq IRQ, target_phys_addr_t mem_base, |
631 |
uint32_t io_base, uint16_t size, int type)
|
632 |
{ |
633 |
DeviceState *dev; |
634 |
SysBusDevice *s; |
635 |
M48t59SysBusState *d; |
636 |
M48t59State *state; |
637 |
|
638 |
dev = qdev_create(NULL, "m48t59"); |
639 |
qdev_prop_set_uint32(dev, "type", type);
|
640 |
qdev_prop_set_uint32(dev, "size", size);
|
641 |
qdev_prop_set_uint32(dev, "io_base", io_base);
|
642 |
qdev_init_nofail(dev); |
643 |
s = sysbus_from_qdev(dev); |
644 |
d = FROM_SYSBUS(M48t59SysBusState, s); |
645 |
state = &d->state; |
646 |
sysbus_connect_irq(s, 0, IRQ);
|
647 |
if (io_base != 0) { |
648 |
register_ioport_read(io_base, 0x04, 1, NVRAM_readb, state); |
649 |
register_ioport_write(io_base, 0x04, 1, NVRAM_writeb, state); |
650 |
} |
651 |
if (mem_base != 0) { |
652 |
sysbus_mmio_map(s, 0, mem_base);
|
653 |
} |
654 |
|
655 |
return state;
|
656 |
} |
657 |
|
658 |
M48t59State *m48t59_init_isa(uint32_t io_base, uint16_t size, int type)
|
659 |
{ |
660 |
M48t59ISAState *d; |
661 |
ISADevice *dev; |
662 |
M48t59State *s; |
663 |
|
664 |
dev = isa_create("m48t59_isa");
|
665 |
qdev_prop_set_uint32(&dev->qdev, "type", type);
|
666 |
qdev_prop_set_uint32(&dev->qdev, "size", size);
|
667 |
qdev_prop_set_uint32(&dev->qdev, "io_base", io_base);
|
668 |
qdev_init_nofail(&dev->qdev); |
669 |
d = DO_UPCAST(M48t59ISAState, busdev, dev); |
670 |
s = &d->state; |
671 |
|
672 |
if (io_base != 0) { |
673 |
register_ioport_read(io_base, 0x04, 1, NVRAM_readb, s); |
674 |
register_ioport_write(io_base, 0x04, 1, NVRAM_writeb, s); |
675 |
isa_init_ioport_range(dev, io_base, 4);
|
676 |
} |
677 |
|
678 |
return s;
|
679 |
} |
680 |
|
681 |
static void m48t59_init_common(M48t59State *s) |
682 |
{ |
683 |
s->buffer = g_malloc0(s->size); |
684 |
if (s->type == 59) { |
685 |
s->alrm_timer = qemu_new_timer_ns(vm_clock, &alarm_cb, s); |
686 |
s->wd_timer = qemu_new_timer_ns(vm_clock, &watchdog_cb, s); |
687 |
} |
688 |
qemu_get_timedate(&s->alarm, 0);
|
689 |
|
690 |
vmstate_register(NULL, -1, &vmstate_m48t59, s); |
691 |
} |
692 |
|
693 |
static int m48t59_init_isa1(ISADevice *dev) |
694 |
{ |
695 |
M48t59ISAState *d = DO_UPCAST(M48t59ISAState, busdev, dev); |
696 |
M48t59State *s = &d->state; |
697 |
|
698 |
isa_init_irq(dev, &s->IRQ, 8);
|
699 |
m48t59_init_common(s); |
700 |
|
701 |
return 0; |
702 |
} |
703 |
|
704 |
static int m48t59_init1(SysBusDevice *dev) |
705 |
{ |
706 |
M48t59SysBusState *d = FROM_SYSBUS(M48t59SysBusState, dev); |
707 |
M48t59State *s = &d->state; |
708 |
int mem_index;
|
709 |
|
710 |
sysbus_init_irq(dev, &s->IRQ); |
711 |
|
712 |
mem_index = cpu_register_io_memory(nvram_read, nvram_write, s, |
713 |
DEVICE_NATIVE_ENDIAN); |
714 |
sysbus_init_mmio(dev, s->size, mem_index); |
715 |
m48t59_init_common(s); |
716 |
|
717 |
return 0; |
718 |
} |
719 |
|
720 |
static ISADeviceInfo m48t59_isa_info = {
|
721 |
.init = m48t59_init_isa1, |
722 |
.qdev.name = "m48t59_isa",
|
723 |
.qdev.size = sizeof(M48t59ISAState),
|
724 |
.qdev.reset = m48t59_reset_isa, |
725 |
.qdev.no_user = 1,
|
726 |
.qdev.props = (Property[]) { |
727 |
DEFINE_PROP_UINT32("size", M48t59ISAState, state.size, -1), |
728 |
DEFINE_PROP_UINT32("type", M48t59ISAState, state.type, -1), |
729 |
DEFINE_PROP_HEX32( "io_base", M48t59ISAState, state.io_base, 0), |
730 |
DEFINE_PROP_END_OF_LIST(), |
731 |
} |
732 |
}; |
733 |
|
734 |
static SysBusDeviceInfo m48t59_info = {
|
735 |
.init = m48t59_init1, |
736 |
.qdev.name = "m48t59",
|
737 |
.qdev.size = sizeof(M48t59SysBusState),
|
738 |
.qdev.reset = m48t59_reset_sysbus, |
739 |
.qdev.props = (Property[]) { |
740 |
DEFINE_PROP_UINT32("size", M48t59SysBusState, state.size, -1), |
741 |
DEFINE_PROP_UINT32("type", M48t59SysBusState, state.type, -1), |
742 |
DEFINE_PROP_HEX32( "io_base", M48t59SysBusState, state.io_base, 0), |
743 |
DEFINE_PROP_END_OF_LIST(), |
744 |
} |
745 |
}; |
746 |
|
747 |
static void m48t59_register_devices(void) |
748 |
{ |
749 |
sysbus_register_withprop(&m48t59_info); |
750 |
isa_qdev_register(&m48t59_isa_info); |
751 |
} |
752 |
|
753 |
device_init(m48t59_register_devices) |