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1 | 6af0bf9c | bellard | /*
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2 | 6af0bf9c | bellard | * MIPS emulation helpers for qemu.
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3 | 6af0bf9c | bellard | *
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4 | 6af0bf9c | bellard | * Copyright (c) 2004-2005 Jocelyn Mayer
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5 | 6af0bf9c | bellard | *
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6 | 6af0bf9c | bellard | * This library is free software; you can redistribute it and/or
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7 | 6af0bf9c | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 6af0bf9c | bellard | * License as published by the Free Software Foundation; either
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9 | 6af0bf9c | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 6af0bf9c | bellard | *
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11 | 6af0bf9c | bellard | * This library is distributed in the hope that it will be useful,
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12 | 6af0bf9c | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 6af0bf9c | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 6af0bf9c | bellard | * Lesser General Public License for more details.
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15 | 6af0bf9c | bellard | *
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16 | 6af0bf9c | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 6af0bf9c | bellard | * License along with this library; if not, write to the Free Software
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18 | 6af0bf9c | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | 6af0bf9c | bellard | */
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20 | 2d0e944d | ths | #include <stdlib.h> |
21 | 6af0bf9c | bellard | #include "exec.h" |
22 | 6af0bf9c | bellard | |
23 | 6af0bf9c | bellard | #define MIPS_DEBUG_DISAS
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24 | 6af0bf9c | bellard | |
25 | 4ad40f36 | bellard | #define GETPC() (__builtin_return_address(0)) |
26 | 4ad40f36 | bellard | |
27 | 6af0bf9c | bellard | /*****************************************************************************/
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28 | 6af0bf9c | bellard | /* Exceptions processing helpers */
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29 | 6af0bf9c | bellard | void cpu_loop_exit(void) |
30 | 6af0bf9c | bellard | { |
31 | 6af0bf9c | bellard | longjmp(env->jmp_env, 1);
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32 | 6af0bf9c | bellard | } |
33 | 6af0bf9c | bellard | |
34 | 6af0bf9c | bellard | void do_raise_exception_err (uint32_t exception, int error_code) |
35 | 6af0bf9c | bellard | { |
36 | 6af0bf9c | bellard | #if 1 |
37 | 6af0bf9c | bellard | if (logfile && exception < 0x100) |
38 | 6af0bf9c | bellard | fprintf(logfile, "%s: %d %d\n", __func__, exception, error_code);
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39 | 6af0bf9c | bellard | #endif
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40 | 6af0bf9c | bellard | env->exception_index = exception; |
41 | 6af0bf9c | bellard | env->error_code = error_code; |
42 | 6af0bf9c | bellard | T0 = 0;
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43 | 6af0bf9c | bellard | cpu_loop_exit(); |
44 | 6af0bf9c | bellard | } |
45 | 6af0bf9c | bellard | |
46 | 6af0bf9c | bellard | void do_raise_exception (uint32_t exception)
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47 | 6af0bf9c | bellard | { |
48 | 6af0bf9c | bellard | do_raise_exception_err(exception, 0);
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49 | 6af0bf9c | bellard | } |
50 | 6af0bf9c | bellard | |
51 | 4ad40f36 | bellard | void do_restore_state (void *pc_ptr) |
52 | 4ad40f36 | bellard | { |
53 | 4ad40f36 | bellard | TranslationBlock *tb; |
54 | 4ad40f36 | bellard | unsigned long pc = (unsigned long) pc_ptr; |
55 | 4ad40f36 | bellard | |
56 | 4ad40f36 | bellard | tb = tb_find_pc (pc); |
57 | 4ad40f36 | bellard | cpu_restore_state (tb, env, pc, NULL);
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58 | 4ad40f36 | bellard | } |
59 | 4ad40f36 | bellard | |
60 | e397ee33 | ths | void do_raise_exception_direct_err (uint32_t exception, int error_code) |
61 | 4ad40f36 | bellard | { |
62 | 4ad40f36 | bellard | do_restore_state (GETPC ()); |
63 | e397ee33 | ths | do_raise_exception_err (exception, error_code); |
64 | e397ee33 | ths | } |
65 | e397ee33 | ths | |
66 | e397ee33 | ths | void do_raise_exception_direct (uint32_t exception)
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67 | e397ee33 | ths | { |
68 | e397ee33 | ths | do_raise_exception_direct_err (exception, 0);
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69 | 4ad40f36 | bellard | } |
70 | 4ad40f36 | bellard | |
71 | 6af0bf9c | bellard | #define MEMSUFFIX _raw
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72 | 6af0bf9c | bellard | #include "op_helper_mem.c" |
73 | 6af0bf9c | bellard | #undef MEMSUFFIX
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74 | 6af0bf9c | bellard | #if !defined(CONFIG_USER_ONLY)
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75 | 6af0bf9c | bellard | #define MEMSUFFIX _user
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76 | 6af0bf9c | bellard | #include "op_helper_mem.c" |
77 | 6af0bf9c | bellard | #undef MEMSUFFIX
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78 | 6af0bf9c | bellard | #define MEMSUFFIX _kernel
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79 | 6af0bf9c | bellard | #include "op_helper_mem.c" |
80 | 6af0bf9c | bellard | #undef MEMSUFFIX
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81 | 6af0bf9c | bellard | #endif
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82 | 6af0bf9c | bellard | |
83 | 60aa19ab | ths | #ifdef TARGET_MIPS64
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84 | c570fd16 | ths | #if TARGET_LONG_BITS > HOST_LONG_BITS
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85 | c570fd16 | ths | /* Those might call libgcc functions. */
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86 | c570fd16 | ths | void do_dsll (void) |
87 | c570fd16 | ths | { |
88 | c570fd16 | ths | T0 = T0 << T1; |
89 | c570fd16 | ths | } |
90 | c570fd16 | ths | |
91 | c570fd16 | ths | void do_dsll32 (void) |
92 | c570fd16 | ths | { |
93 | c570fd16 | ths | T0 = T0 << (T1 + 32);
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94 | c570fd16 | ths | } |
95 | c570fd16 | ths | |
96 | c570fd16 | ths | void do_dsra (void) |
97 | c570fd16 | ths | { |
98 | c570fd16 | ths | T0 = (int64_t)T0 >> T1; |
99 | c570fd16 | ths | } |
100 | c570fd16 | ths | |
101 | c570fd16 | ths | void do_dsra32 (void) |
102 | c570fd16 | ths | { |
103 | c570fd16 | ths | T0 = (int64_t)T0 >> (T1 + 32);
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104 | c570fd16 | ths | } |
105 | c570fd16 | ths | |
106 | c570fd16 | ths | void do_dsrl (void) |
107 | c570fd16 | ths | { |
108 | c570fd16 | ths | T0 = T0 >> T1; |
109 | c570fd16 | ths | } |
110 | c570fd16 | ths | |
111 | c570fd16 | ths | void do_dsrl32 (void) |
112 | c570fd16 | ths | { |
113 | c570fd16 | ths | T0 = T0 >> (T1 + 32);
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114 | c570fd16 | ths | } |
115 | c570fd16 | ths | |
116 | c570fd16 | ths | void do_drotr (void) |
117 | c570fd16 | ths | { |
118 | c570fd16 | ths | target_ulong tmp; |
119 | c570fd16 | ths | |
120 | c570fd16 | ths | if (T1) {
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121 | c570fd16 | ths | tmp = T0 << (0x40 - T1);
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122 | c570fd16 | ths | T0 = (T0 >> T1) | tmp; |
123 | 5a63bcb2 | ths | } |
124 | c570fd16 | ths | } |
125 | c570fd16 | ths | |
126 | c570fd16 | ths | void do_drotr32 (void) |
127 | c570fd16 | ths | { |
128 | c570fd16 | ths | target_ulong tmp; |
129 | c570fd16 | ths | |
130 | c570fd16 | ths | if (T1) {
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131 | c570fd16 | ths | tmp = T0 << (0x40 - (32 + T1)); |
132 | c570fd16 | ths | T0 = (T0 >> (32 + T1)) | tmp;
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133 | 5a63bcb2 | ths | } |
134 | c570fd16 | ths | } |
135 | c570fd16 | ths | |
136 | c570fd16 | ths | void do_dsllv (void) |
137 | c570fd16 | ths | { |
138 | c570fd16 | ths | T0 = T1 << (T0 & 0x3F);
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139 | c570fd16 | ths | } |
140 | c570fd16 | ths | |
141 | c570fd16 | ths | void do_dsrav (void) |
142 | c570fd16 | ths | { |
143 | c570fd16 | ths | T0 = (int64_t)T1 >> (T0 & 0x3F);
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144 | c570fd16 | ths | } |
145 | c570fd16 | ths | |
146 | c570fd16 | ths | void do_dsrlv (void) |
147 | c570fd16 | ths | { |
148 | c570fd16 | ths | T0 = T1 >> (T0 & 0x3F);
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149 | c570fd16 | ths | } |
150 | c570fd16 | ths | |
151 | c570fd16 | ths | void do_drotrv (void) |
152 | c570fd16 | ths | { |
153 | c570fd16 | ths | target_ulong tmp; |
154 | c570fd16 | ths | |
155 | c570fd16 | ths | T0 &= 0x3F;
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156 | c570fd16 | ths | if (T0) {
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157 | c570fd16 | ths | tmp = T1 << (0x40 - T0);
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158 | c570fd16 | ths | T0 = (T1 >> T0) | tmp; |
159 | c570fd16 | ths | } else
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160 | c570fd16 | ths | T0 = T1; |
161 | c570fd16 | ths | } |
162 | c570fd16 | ths | #endif /* TARGET_LONG_BITS > HOST_LONG_BITS */ |
163 | 60aa19ab | ths | #endif /* TARGET_MIPS64 */ |
164 | c570fd16 | ths | |
165 | 6af0bf9c | bellard | /* 64 bits arithmetic for 32 bits hosts */
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166 | c570fd16 | ths | #if TARGET_LONG_BITS > HOST_LONG_BITS
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167 | 6af0bf9c | bellard | static inline uint64_t get_HILO (void) |
168 | 6af0bf9c | bellard | { |
169 | 7495fd0f | ths | return (env->HI << 32) | (uint32_t)env->LO; |
170 | 6af0bf9c | bellard | } |
171 | 6af0bf9c | bellard | |
172 | 6af0bf9c | bellard | static inline void set_HILO (uint64_t HILO) |
173 | 6af0bf9c | bellard | { |
174 | 7495fd0f | ths | env->LO = (int32_t)HILO; |
175 | 5dc4b744 | ths | env->HI = (int32_t)(HILO >> 32);
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176 | 6af0bf9c | bellard | } |
177 | 6af0bf9c | bellard | |
178 | 6af0bf9c | bellard | void do_mult (void) |
179 | 6af0bf9c | bellard | { |
180 | 4ad40f36 | bellard | set_HILO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); |
181 | 6af0bf9c | bellard | } |
182 | 6af0bf9c | bellard | |
183 | 6af0bf9c | bellard | void do_multu (void) |
184 | 6af0bf9c | bellard | { |
185 | c570fd16 | ths | set_HILO((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1); |
186 | 6af0bf9c | bellard | } |
187 | 6af0bf9c | bellard | |
188 | 6af0bf9c | bellard | void do_madd (void) |
189 | 6af0bf9c | bellard | { |
190 | 6af0bf9c | bellard | int64_t tmp; |
191 | 6af0bf9c | bellard | |
192 | 4ad40f36 | bellard | tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); |
193 | 6af0bf9c | bellard | set_HILO((int64_t)get_HILO() + tmp); |
194 | 6af0bf9c | bellard | } |
195 | 6af0bf9c | bellard | |
196 | 6af0bf9c | bellard | void do_maddu (void) |
197 | 6af0bf9c | bellard | { |
198 | 6af0bf9c | bellard | uint64_t tmp; |
199 | 6af0bf9c | bellard | |
200 | c570fd16 | ths | tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1); |
201 | 6af0bf9c | bellard | set_HILO(get_HILO() + tmp); |
202 | 6af0bf9c | bellard | } |
203 | 6af0bf9c | bellard | |
204 | 6af0bf9c | bellard | void do_msub (void) |
205 | 6af0bf9c | bellard | { |
206 | 6af0bf9c | bellard | int64_t tmp; |
207 | 6af0bf9c | bellard | |
208 | 4ad40f36 | bellard | tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); |
209 | 6af0bf9c | bellard | set_HILO((int64_t)get_HILO() - tmp); |
210 | 6af0bf9c | bellard | } |
211 | 6af0bf9c | bellard | |
212 | 6af0bf9c | bellard | void do_msubu (void) |
213 | 6af0bf9c | bellard | { |
214 | 6af0bf9c | bellard | uint64_t tmp; |
215 | 6af0bf9c | bellard | |
216 | c570fd16 | ths | tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1); |
217 | 6af0bf9c | bellard | set_HILO(get_HILO() - tmp); |
218 | 6af0bf9c | bellard | } |
219 | 6af0bf9c | bellard | #endif
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220 | 6af0bf9c | bellard | |
221 | 60aa19ab | ths | #ifdef TARGET_MIPS64
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222 | c570fd16 | ths | void do_dmult (void) |
223 | c570fd16 | ths | { |
224 | 2d0e944d | ths | env->LO = (int64_t)T0 * (int64_t)T1; |
225 | c570fd16 | ths | /* XXX */
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226 | 2d0e944d | ths | env->HI = (env->LO | (1ULL << 63)) ? ~0ULL : 0ULL; |
227 | c570fd16 | ths | } |
228 | c570fd16 | ths | |
229 | c570fd16 | ths | void do_dmultu (void) |
230 | c570fd16 | ths | { |
231 | 2d0e944d | ths | env->LO = T0 * T1; |
232 | c570fd16 | ths | /* XXX */
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233 | 2d0e944d | ths | env->HI = 0;
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234 | c570fd16 | ths | } |
235 | c570fd16 | ths | |
236 | c570fd16 | ths | void do_ddiv (void) |
237 | c570fd16 | ths | { |
238 | c570fd16 | ths | if (T1 != 0) { |
239 | 2d0e944d | ths | lldiv_t res = lldiv((int64_t)T0, (int64_t)T1); |
240 | 2d0e944d | ths | env->LO = res.quot; |
241 | 2d0e944d | ths | env->HI = res.rem; |
242 | c570fd16 | ths | } |
243 | c570fd16 | ths | } |
244 | c570fd16 | ths | |
245 | c570fd16 | ths | void do_ddivu (void) |
246 | c570fd16 | ths | { |
247 | c570fd16 | ths | if (T1 != 0) { |
248 | 2d0e944d | ths | /* XXX: lldivu? */
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249 | 2d0e944d | ths | lldiv_t res = lldiv(T0, T1); |
250 | 2d0e944d | ths | env->LO = (uint64_t)res.quot; |
251 | 2d0e944d | ths | env->HI = (uint64_t)res.rem; |
252 | c570fd16 | ths | } |
253 | c570fd16 | ths | } |
254 | c570fd16 | ths | #endif
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255 | c570fd16 | ths | |
256 | 048f6b4d | bellard | #if defined(CONFIG_USER_ONLY)
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257 | 873eb012 | ths | void do_mfc0_random (void) |
258 | 048f6b4d | bellard | { |
259 | 873eb012 | ths | cpu_abort(env, "mfc0 random\n");
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260 | 048f6b4d | bellard | } |
261 | 873eb012 | ths | |
262 | 873eb012 | ths | void do_mfc0_count (void) |
263 | 873eb012 | ths | { |
264 | 873eb012 | ths | cpu_abort(env, "mfc0 count\n");
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265 | 873eb012 | ths | } |
266 | 873eb012 | ths | |
267 | 8c0fdd85 | ths | void cpu_mips_store_count(CPUState *env, uint32_t value)
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268 | 048f6b4d | bellard | { |
269 | 8c0fdd85 | ths | cpu_abort(env, "mtc0 count\n");
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270 | 8c0fdd85 | ths | } |
271 | 8c0fdd85 | ths | |
272 | 8c0fdd85 | ths | void cpu_mips_store_compare(CPUState *env, uint32_t value)
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273 | 8c0fdd85 | ths | { |
274 | 8c0fdd85 | ths | cpu_abort(env, "mtc0 compare\n");
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275 | 8c0fdd85 | ths | } |
276 | 8c0fdd85 | ths | |
277 | 4de9b249 | ths | void cpu_mips_update_irq(CPUState *env)
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278 | 4de9b249 | ths | { |
279 | 4de9b249 | ths | cpu_abort(env, "mtc0 status / mtc0 cause\n");
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280 | 4de9b249 | ths | } |
281 | 4de9b249 | ths | |
282 | 8c0fdd85 | ths | void do_mtc0_status_debug(uint32_t old, uint32_t val)
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283 | 8c0fdd85 | ths | { |
284 | 7a387fff | ths | cpu_abort(env, "mtc0 status debug\n");
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285 | 8c0fdd85 | ths | } |
286 | 8c0fdd85 | ths | |
287 | 7a387fff | ths | void do_mtc0_status_irqraise_debug (void) |
288 | 8c0fdd85 | ths | { |
289 | 7a387fff | ths | cpu_abort(env, "mtc0 status irqraise debug\n");
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290 | 048f6b4d | bellard | } |
291 | 048f6b4d | bellard | |
292 | 048f6b4d | bellard | void do_tlbwi (void) |
293 | 048f6b4d | bellard | { |
294 | 048f6b4d | bellard | cpu_abort(env, "tlbwi\n");
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295 | 048f6b4d | bellard | } |
296 | 048f6b4d | bellard | |
297 | 048f6b4d | bellard | void do_tlbwr (void) |
298 | 048f6b4d | bellard | { |
299 | 048f6b4d | bellard | cpu_abort(env, "tlbwr\n");
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300 | 048f6b4d | bellard | } |
301 | 048f6b4d | bellard | |
302 | 048f6b4d | bellard | void do_tlbp (void) |
303 | 048f6b4d | bellard | { |
304 | 048f6b4d | bellard | cpu_abort(env, "tlbp\n");
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305 | 048f6b4d | bellard | } |
306 | 048f6b4d | bellard | |
307 | 048f6b4d | bellard | void do_tlbr (void) |
308 | 048f6b4d | bellard | { |
309 | 048f6b4d | bellard | cpu_abort(env, "tlbr\n");
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310 | 048f6b4d | bellard | } |
311 | 873eb012 | ths | |
312 | 8c0fdd85 | ths | void cpu_mips_tlb_flush (CPUState *env, int flush_global) |
313 | 8c0fdd85 | ths | { |
314 | 8c0fdd85 | ths | cpu_abort(env, "mips_tlb_flush\n");
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315 | 8c0fdd85 | ths | } |
316 | 8c0fdd85 | ths | |
317 | 048f6b4d | bellard | #else
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318 | 048f6b4d | bellard | |
319 | 6af0bf9c | bellard | /* CP0 helpers */
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320 | 873eb012 | ths | void do_mfc0_random (void) |
321 | 6af0bf9c | bellard | { |
322 | 5dc4b744 | ths | T0 = (int32_t)cpu_mips_get_random(env); |
323 | 873eb012 | ths | } |
324 | 6af0bf9c | bellard | |
325 | 873eb012 | ths | void do_mfc0_count (void) |
326 | 873eb012 | ths | { |
327 | 5dc4b744 | ths | T0 = (int32_t)cpu_mips_get_count(env); |
328 | 6af0bf9c | bellard | } |
329 | 6af0bf9c | bellard | |
330 | 8c0fdd85 | ths | void do_mtc0_status_debug(uint32_t old, uint32_t val)
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331 | 6af0bf9c | bellard | { |
332 | f41c52f1 | ths | fprintf(logfile, "Status %08x (%08x) => %08x (%08x) Cause %08x",
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333 | f41c52f1 | ths | old, old & env->CP0_Cause & CP0Ca_IP_mask, |
334 | f41c52f1 | ths | val, val & env->CP0_Cause & CP0Ca_IP_mask, |
335 | f41c52f1 | ths | env->CP0_Cause); |
336 | f41c52f1 | ths | (env->hflags & MIPS_HFLAG_UM) ? fputs(", UM\n", logfile)
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337 | f41c52f1 | ths | : fputs("\n", logfile);
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338 | 8c0fdd85 | ths | } |
339 | 8c0fdd85 | ths | |
340 | 8c0fdd85 | ths | void do_mtc0_status_irqraise_debug(void) |
341 | 8c0fdd85 | ths | { |
342 | 8c0fdd85 | ths | fprintf(logfile, "Raise pending IRQs\n");
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343 | 6af0bf9c | bellard | } |
344 | 6af0bf9c | bellard | |
345 | 6ea83fed | bellard | void fpu_handle_exception(void) |
346 | 6ea83fed | bellard | { |
347 | 6ea83fed | bellard | #ifdef CONFIG_SOFTFLOAT
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348 | 6ea83fed | bellard | int flags = get_float_exception_flags(&env->fp_status);
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349 | 6ea83fed | bellard | unsigned int cpuflags = 0, enable, cause = 0; |
350 | 6ea83fed | bellard | |
351 | 6ea83fed | bellard | enable = GET_FP_ENABLE(env->fcr31); |
352 | 6ea83fed | bellard | |
353 | 6ea83fed | bellard | /* determine current flags */
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354 | 6ea83fed | bellard | if (flags & float_flag_invalid) {
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355 | 6ea83fed | bellard | cpuflags |= FP_INVALID; |
356 | 6ea83fed | bellard | cause |= FP_INVALID & enable; |
357 | 6ea83fed | bellard | } |
358 | 6ea83fed | bellard | if (flags & float_flag_divbyzero) {
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359 | 6ea83fed | bellard | cpuflags |= FP_DIV0; |
360 | 6ea83fed | bellard | cause |= FP_DIV0 & enable; |
361 | 6ea83fed | bellard | } |
362 | 6ea83fed | bellard | if (flags & float_flag_overflow) {
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363 | 6ea83fed | bellard | cpuflags |= FP_OVERFLOW; |
364 | 6ea83fed | bellard | cause |= FP_OVERFLOW & enable; |
365 | 6ea83fed | bellard | } |
366 | 6ea83fed | bellard | if (flags & float_flag_underflow) {
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367 | 6ea83fed | bellard | cpuflags |= FP_UNDERFLOW; |
368 | 6ea83fed | bellard | cause |= FP_UNDERFLOW & enable; |
369 | 6ea83fed | bellard | } |
370 | 6ea83fed | bellard | if (flags & float_flag_inexact) {
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371 | 6ea83fed | bellard | cpuflags |= FP_INEXACT; |
372 | 6ea83fed | bellard | cause |= FP_INEXACT & enable; |
373 | 6ea83fed | bellard | } |
374 | 6ea83fed | bellard | SET_FP_FLAGS(env->fcr31, cpuflags); |
375 | 6ea83fed | bellard | SET_FP_CAUSE(env->fcr31, cause); |
376 | 6ea83fed | bellard | #else
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377 | 6ea83fed | bellard | SET_FP_FLAGS(env->fcr31, 0);
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378 | 6ea83fed | bellard | SET_FP_CAUSE(env->fcr31, 0);
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379 | 6ea83fed | bellard | #endif
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380 | 6ea83fed | bellard | } |
381 | 6ea83fed | bellard | |
382 | 6af0bf9c | bellard | /* TLB management */
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383 | 6af0bf9c | bellard | #if defined(MIPS_USES_R4K_TLB)
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384 | 814b9a47 | ths | void cpu_mips_tlb_flush (CPUState *env, int flush_global) |
385 | 814b9a47 | ths | { |
386 | 814b9a47 | ths | /* Flush qemu's TLB and discard all shadowed entries. */
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387 | 814b9a47 | ths | tlb_flush (env, flush_global); |
388 | 814b9a47 | ths | env->tlb_in_use = MIPS_TLB_NB; |
389 | 814b9a47 | ths | } |
390 | 814b9a47 | ths | |
391 | 814b9a47 | ths | static void mips_tlb_flush_extra (CPUState *env, int first) |
392 | 814b9a47 | ths | { |
393 | 814b9a47 | ths | /* Discard entries from env->tlb[first] onwards. */
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394 | 814b9a47 | ths | while (env->tlb_in_use > first) {
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395 | 2ee4aed8 | bellard | invalidate_tlb(env, --env->tlb_in_use, 0);
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396 | 814b9a47 | ths | } |
397 | 814b9a47 | ths | } |
398 | 814b9a47 | ths | |
399 | 98c1b82b | pbrook | static void fill_tlb (int idx) |
400 | 6af0bf9c | bellard | { |
401 | 6af0bf9c | bellard | tlb_t *tlb; |
402 | 6af0bf9c | bellard | |
403 | 6af0bf9c | bellard | /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
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404 | 6af0bf9c | bellard | tlb = &env->tlb[idx]; |
405 | 925fd0f2 | ths | tlb->VPN = env->CP0_EntryHi & ~(target_ulong)0x1FFF;
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406 | 98c1b82b | pbrook | tlb->ASID = env->CP0_EntryHi & 0xFF;
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407 | 3b1c8be4 | ths | tlb->PageMask = env->CP0_PageMask; |
408 | 6af0bf9c | bellard | tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
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409 | 98c1b82b | pbrook | tlb->V0 = (env->CP0_EntryLo0 & 2) != 0; |
410 | 98c1b82b | pbrook | tlb->D0 = (env->CP0_EntryLo0 & 4) != 0; |
411 | 98c1b82b | pbrook | tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7; |
412 | 6af0bf9c | bellard | tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12; |
413 | 98c1b82b | pbrook | tlb->V1 = (env->CP0_EntryLo1 & 2) != 0; |
414 | 98c1b82b | pbrook | tlb->D1 = (env->CP0_EntryLo1 & 4) != 0; |
415 | 98c1b82b | pbrook | tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7; |
416 | 6af0bf9c | bellard | tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12; |
417 | 6af0bf9c | bellard | } |
418 | 6af0bf9c | bellard | |
419 | 6af0bf9c | bellard | void do_tlbwi (void) |
420 | 6af0bf9c | bellard | { |
421 | 814b9a47 | ths | /* Discard cached TLB entries. We could avoid doing this if the
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422 | 814b9a47 | ths | tlbwi is just upgrading access permissions on the current entry;
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423 | 814b9a47 | ths | that might be a further win. */
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424 | 814b9a47 | ths | mips_tlb_flush_extra (env, MIPS_TLB_NB); |
425 | 814b9a47 | ths | |
426 | 9c2149c8 | ths | /* Wildly undefined effects for CP0_Index containing a too high value and
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427 | 7a962d30 | bellard | MIPS_TLB_NB not being a power of two. But so does real silicon. */
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428 | 9c2149c8 | ths | invalidate_tlb(env, env->CP0_Index & (MIPS_TLB_NB - 1), 0); |
429 | 9c2149c8 | ths | fill_tlb(env->CP0_Index & (MIPS_TLB_NB - 1));
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430 | 6af0bf9c | bellard | } |
431 | 6af0bf9c | bellard | |
432 | 6af0bf9c | bellard | void do_tlbwr (void) |
433 | 6af0bf9c | bellard | { |
434 | 6af0bf9c | bellard | int r = cpu_mips_get_random(env);
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435 | 6af0bf9c | bellard | |
436 | 2ee4aed8 | bellard | invalidate_tlb(env, r, 1);
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437 | 98c1b82b | pbrook | fill_tlb(r); |
438 | 6af0bf9c | bellard | } |
439 | 6af0bf9c | bellard | |
440 | 6af0bf9c | bellard | void do_tlbp (void) |
441 | 6af0bf9c | bellard | { |
442 | 6af0bf9c | bellard | tlb_t *tlb; |
443 | 6af0bf9c | bellard | target_ulong tag; |
444 | 6af0bf9c | bellard | uint8_t ASID; |
445 | 6af0bf9c | bellard | int i;
|
446 | 6af0bf9c | bellard | |
447 | 5dc4b744 | ths | tag = env->CP0_EntryHi & (int32_t)0xFFFFE000;
|
448 | 3d9fb9fe | bellard | ASID = env->CP0_EntryHi & 0xFF;
|
449 | 3d9fb9fe | bellard | for (i = 0; i < MIPS_TLB_NB; i++) { |
450 | 6af0bf9c | bellard | tlb = &env->tlb[i]; |
451 | 6af0bf9c | bellard | /* Check ASID, virtual page number & size */
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452 | 6af0bf9c | bellard | if ((tlb->G == 1 || tlb->ASID == ASID) && tlb->VPN == tag) { |
453 | 6af0bf9c | bellard | /* TLB match */
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454 | 9c2149c8 | ths | env->CP0_Index = i; |
455 | 6af0bf9c | bellard | break;
|
456 | 6af0bf9c | bellard | } |
457 | 6af0bf9c | bellard | } |
458 | 7a962d30 | bellard | if (i == MIPS_TLB_NB) {
|
459 | 814b9a47 | ths | /* No match. Discard any shadow entries, if any of them match. */
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460 | 814b9a47 | ths | for (i = MIPS_TLB_NB; i < env->tlb_in_use; i++) {
|
461 | 814b9a47 | ths | tlb = &env->tlb[i]; |
462 | 814b9a47 | ths | |
463 | 814b9a47 | ths | /* Check ASID, virtual page number & size */
|
464 | 814b9a47 | ths | if ((tlb->G == 1 || tlb->ASID == ASID) && tlb->VPN == tag) { |
465 | 814b9a47 | ths | mips_tlb_flush_extra (env, i); |
466 | 814b9a47 | ths | break;
|
467 | 814b9a47 | ths | } |
468 | 814b9a47 | ths | } |
469 | 814b9a47 | ths | |
470 | 9c2149c8 | ths | env->CP0_Index |= 0x80000000;
|
471 | 6af0bf9c | bellard | } |
472 | 6af0bf9c | bellard | } |
473 | 6af0bf9c | bellard | |
474 | 6af0bf9c | bellard | void do_tlbr (void) |
475 | 6af0bf9c | bellard | { |
476 | 6af0bf9c | bellard | tlb_t *tlb; |
477 | 09c56b84 | pbrook | uint8_t ASID; |
478 | 6af0bf9c | bellard | |
479 | 09c56b84 | pbrook | ASID = env->CP0_EntryHi & 0xFF;
|
480 | 9c2149c8 | ths | tlb = &env->tlb[env->CP0_Index & (MIPS_TLB_NB - 1)];
|
481 | 4ad40f36 | bellard | |
482 | 4ad40f36 | bellard | /* If this will change the current ASID, flush qemu's TLB. */
|
483 | 814b9a47 | ths | if (ASID != tlb->ASID)
|
484 | 814b9a47 | ths | cpu_mips_tlb_flush (env, 1);
|
485 | 814b9a47 | ths | |
486 | 814b9a47 | ths | mips_tlb_flush_extra(env, MIPS_TLB_NB); |
487 | 4ad40f36 | bellard | |
488 | 6af0bf9c | bellard | env->CP0_EntryHi = tlb->VPN | tlb->ASID; |
489 | 3b1c8be4 | ths | env->CP0_PageMask = tlb->PageMask; |
490 | 7495fd0f | ths | env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) | |
491 | 7495fd0f | ths | (tlb->C0 << 3) | (tlb->PFN[0] >> 6); |
492 | 7495fd0f | ths | env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) | |
493 | 7495fd0f | ths | (tlb->C1 << 3) | (tlb->PFN[1] >> 6); |
494 | 6af0bf9c | bellard | } |
495 | 6af0bf9c | bellard | #endif
|
496 | 6af0bf9c | bellard | |
497 | 048f6b4d | bellard | #endif /* !CONFIG_USER_ONLY */ |
498 | 048f6b4d | bellard | |
499 | c570fd16 | ths | void dump_ldst (const unsigned char *func) |
500 | 6af0bf9c | bellard | { |
501 | 6af0bf9c | bellard | if (loglevel)
|
502 | 3594c774 | ths | fprintf(logfile, "%s => " TARGET_FMT_lx " " TARGET_FMT_lx "\n", __func__, T0, T1); |
503 | 6af0bf9c | bellard | } |
504 | 6af0bf9c | bellard | |
505 | 6af0bf9c | bellard | void dump_sc (void) |
506 | 6af0bf9c | bellard | { |
507 | 6af0bf9c | bellard | if (loglevel) {
|
508 | 3594c774 | ths | fprintf(logfile, "%s " TARGET_FMT_lx " at " TARGET_FMT_lx " (" TARGET_FMT_lx ")\n", __func__, |
509 | 6af0bf9c | bellard | T1, T0, env->CP0_LLAddr); |
510 | 6af0bf9c | bellard | } |
511 | 6af0bf9c | bellard | } |
512 | 6af0bf9c | bellard | |
513 | f41c52f1 | ths | void debug_pre_eret (void) |
514 | 6af0bf9c | bellard | { |
515 | f41c52f1 | ths | fprintf(logfile, "ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, |
516 | f41c52f1 | ths | env->PC, env->CP0_EPC); |
517 | f41c52f1 | ths | if (env->CP0_Status & (1 << CP0St_ERL)) |
518 | f41c52f1 | ths | fprintf(logfile, " ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
|
519 | f41c52f1 | ths | if (env->hflags & MIPS_HFLAG_DM)
|
520 | f41c52f1 | ths | fprintf(logfile, " DEPC " TARGET_FMT_lx, env->CP0_DEPC);
|
521 | f41c52f1 | ths | fputs("\n", logfile);
|
522 | f41c52f1 | ths | } |
523 | f41c52f1 | ths | |
524 | f41c52f1 | ths | void debug_post_eret (void) |
525 | f41c52f1 | ths | { |
526 | f41c52f1 | ths | fprintf(logfile, " => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, |
527 | f41c52f1 | ths | env->PC, env->CP0_EPC); |
528 | f41c52f1 | ths | if (env->CP0_Status & (1 << CP0St_ERL)) |
529 | f41c52f1 | ths | fprintf(logfile, " ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
|
530 | f41c52f1 | ths | if (env->hflags & MIPS_HFLAG_DM)
|
531 | f41c52f1 | ths | fprintf(logfile, " DEPC " TARGET_FMT_lx, env->CP0_DEPC);
|
532 | f41c52f1 | ths | if (env->hflags & MIPS_HFLAG_UM)
|
533 | f41c52f1 | ths | fputs(", UM\n", logfile);
|
534 | f41c52f1 | ths | else
|
535 | 24c7b0e3 | ths | fputs("\n", logfile);
|
536 | 6af0bf9c | bellard | } |
537 | 6af0bf9c | bellard | |
538 | 6af0bf9c | bellard | void do_pmon (int function) |
539 | 6af0bf9c | bellard | { |
540 | 6af0bf9c | bellard | function /= 2;
|
541 | 6af0bf9c | bellard | switch (function) {
|
542 | 6af0bf9c | bellard | case 2: /* TODO: char inbyte(int waitflag); */ |
543 | 6af0bf9c | bellard | if (env->gpr[4] == 0) |
544 | 6af0bf9c | bellard | env->gpr[2] = -1; |
545 | 6af0bf9c | bellard | /* Fall through */
|
546 | 6af0bf9c | bellard | case 11: /* TODO: char inbyte (void); */ |
547 | 6af0bf9c | bellard | env->gpr[2] = -1; |
548 | 6af0bf9c | bellard | break;
|
549 | 6af0bf9c | bellard | case 3: |
550 | 6af0bf9c | bellard | case 12: |
551 | c570fd16 | ths | printf("%c", (char)(env->gpr[4] & 0xFF)); |
552 | 6af0bf9c | bellard | break;
|
553 | 6af0bf9c | bellard | case 17: |
554 | 6af0bf9c | bellard | break;
|
555 | 6af0bf9c | bellard | case 158: |
556 | 6af0bf9c | bellard | { |
557 | c570fd16 | ths | unsigned char *fmt = (void *)(unsigned long)env->gpr[4]; |
558 | 6af0bf9c | bellard | printf("%s", fmt);
|
559 | 6af0bf9c | bellard | } |
560 | 6af0bf9c | bellard | break;
|
561 | 6af0bf9c | bellard | } |
562 | 6af0bf9c | bellard | } |
563 | e37e863f | bellard | |
564 | e37e863f | bellard | #if !defined(CONFIG_USER_ONLY)
|
565 | e37e863f | bellard | |
566 | 4ad40f36 | bellard | static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr); |
567 | 4ad40f36 | bellard | |
568 | e37e863f | bellard | #define MMUSUFFIX _mmu
|
569 | 4ad40f36 | bellard | #define ALIGNED_ONLY
|
570 | e37e863f | bellard | |
571 | e37e863f | bellard | #define SHIFT 0 |
572 | e37e863f | bellard | #include "softmmu_template.h" |
573 | e37e863f | bellard | |
574 | e37e863f | bellard | #define SHIFT 1 |
575 | e37e863f | bellard | #include "softmmu_template.h" |
576 | e37e863f | bellard | |
577 | e37e863f | bellard | #define SHIFT 2 |
578 | e37e863f | bellard | #include "softmmu_template.h" |
579 | e37e863f | bellard | |
580 | e37e863f | bellard | #define SHIFT 3 |
581 | e37e863f | bellard | #include "softmmu_template.h" |
582 | e37e863f | bellard | |
583 | 4ad40f36 | bellard | static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr) |
584 | 4ad40f36 | bellard | { |
585 | 4ad40f36 | bellard | env->CP0_BadVAddr = addr; |
586 | 4ad40f36 | bellard | do_restore_state (retaddr); |
587 | 4ad40f36 | bellard | do_raise_exception ((is_write == 1) ? EXCP_AdES : EXCP_AdEL);
|
588 | 4ad40f36 | bellard | } |
589 | 4ad40f36 | bellard | |
590 | e37e863f | bellard | void tlb_fill (target_ulong addr, int is_write, int is_user, void *retaddr) |
591 | e37e863f | bellard | { |
592 | e37e863f | bellard | TranslationBlock *tb; |
593 | e37e863f | bellard | CPUState *saved_env; |
594 | e37e863f | bellard | unsigned long pc; |
595 | e37e863f | bellard | int ret;
|
596 | e37e863f | bellard | |
597 | e37e863f | bellard | /* XXX: hack to restore env in all cases, even if not called from
|
598 | e37e863f | bellard | generated code */
|
599 | e37e863f | bellard | saved_env = env; |
600 | e37e863f | bellard | env = cpu_single_env; |
601 | e37e863f | bellard | ret = cpu_mips_handle_mmu_fault(env, addr, is_write, is_user, 1);
|
602 | e37e863f | bellard | if (ret) {
|
603 | e37e863f | bellard | if (retaddr) {
|
604 | e37e863f | bellard | /* now we have a real cpu fault */
|
605 | e37e863f | bellard | pc = (unsigned long)retaddr; |
606 | e37e863f | bellard | tb = tb_find_pc(pc); |
607 | e37e863f | bellard | if (tb) {
|
608 | e37e863f | bellard | /* the PC is inside the translated code. It means that we have
|
609 | e37e863f | bellard | a virtual CPU fault */
|
610 | e37e863f | bellard | cpu_restore_state(tb, env, pc, NULL);
|
611 | e37e863f | bellard | } |
612 | e37e863f | bellard | } |
613 | e37e863f | bellard | do_raise_exception_err(env->exception_index, env->error_code); |
614 | e37e863f | bellard | } |
615 | e37e863f | bellard | env = saved_env; |
616 | e37e863f | bellard | } |
617 | e37e863f | bellard | |
618 | e37e863f | bellard | #endif |