Revision 97428a4d target-mips/translate.c

b/target-mips/translate.c
4825 4825 
        case OPC_RDHWR:
4826 4826 
            switch (rd) {
4827 4827 
            case 0:
4828 
                save_cpu_state(ctx, 1);
4828 4829 
                gen_op_rdhwr_cpunum();
4829 4830 
                break;
4830 4831 
            case 1:
4832 
                save_cpu_state(ctx, 1);
4831 4833 
                gen_op_rdhwr_synci_step();
4832 4834 
                break;
4833 4835 
            case 2:
4836 
                save_cpu_state(ctx, 1);
4834 4837 
                gen_op_rdhwr_cc();
4835 4838 
                break;
4836 4839 
            case 3:
4840 
                save_cpu_state(ctx, 1);
4837 4841 
                gen_op_rdhwr_ccres();
4838 4842 
                break;
4839 4843 
            case 29:
4840 4844 
#if defined (CONFIG_USER_ONLY)
4841 4845 
                gen_op_tls_value ();
4842 
#else
4843 
                generate_exception(ctx, EXCP_RI);
4844 
#endif
4845 
                break;
4846 
            case 30:
4847 
                /* Implementation dependent */;
4848 
                gen_op_rdhwr_unimpl30();
4849 
                break;
4850 
            case 31:
4851 
                /* Implementation dependent */;
4852 
                gen_op_rdhwr_unimpl31();
4853 4846 
                break;
4847 
#endif
4854 4848 
            default:            /* Invalid */
4855 4849 
                MIPS_INVAL("rdhwr");
4856 4850 
                generate_exception(ctx, EXCP_RI);

Also available in: Unified diff