root / hw / ppc_chrp.c @ 977d5710
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1 | 64201201 | bellard | /*
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2 | 64201201 | bellard | * QEMU PPC CHRP/PMAC hardware System Emulator
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3 | 64201201 | bellard | *
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4 | 64201201 | bellard | * Copyright (c) 2004 Fabrice Bellard
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5 | 64201201 | bellard | *
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6 | 64201201 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 64201201 | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 64201201 | bellard | * in the Software without restriction, including without limitation the rights
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9 | 64201201 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 64201201 | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 64201201 | bellard | * furnished to do so, subject to the following conditions:
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12 | 64201201 | bellard | *
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13 | 64201201 | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 64201201 | bellard | * all copies or substantial portions of the Software.
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15 | 64201201 | bellard | *
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16 | 64201201 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 64201201 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 64201201 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 64201201 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 64201201 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 64201201 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 64201201 | bellard | * THE SOFTWARE.
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23 | 64201201 | bellard | */
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24 | 64201201 | bellard | #include "vl.h" |
25 | 64201201 | bellard | |
26 | 64201201 | bellard | #define BIOS_FILENAME "ppc_rom.bin" |
27 | 64201201 | bellard | #define NVRAM_SIZE 0x2000 |
28 | 64201201 | bellard | |
29 | b6b8bd18 | bellard | #define KERNEL_LOAD_ADDR 0x01000000 |
30 | b6b8bd18 | bellard | #define INITRD_LOAD_ADDR 0x01800000 |
31 | b6b8bd18 | bellard | |
32 | 267002cd | bellard | /* MacIO devices (mapped inside the MacIO address space): CUDA, DBDMA,
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33 | 267002cd | bellard | NVRAM (not implemented). */
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34 | 267002cd | bellard | |
35 | 267002cd | bellard | static int dbdma_mem_index; |
36 | 267002cd | bellard | static int cuda_mem_index; |
37 | b6b8bd18 | bellard | static int ide0_mem_index; |
38 | b6b8bd18 | bellard | static int ide1_mem_index; |
39 | 91d848eb | bellard | static int openpic_mem_index; |
40 | 267002cd | bellard | |
41 | 267002cd | bellard | /* DBDMA: currently no op - should suffice right now */
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42 | 267002cd | bellard | |
43 | 267002cd | bellard | static void dbdma_writeb (void *opaque, target_phys_addr_t addr, uint32_t value) |
44 | 267002cd | bellard | { |
45 | b6b8bd18 | bellard | printf("%s: 0x%08x <= 0x%08x\n", __func__, addr, value);
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46 | 267002cd | bellard | } |
47 | 267002cd | bellard | |
48 | 267002cd | bellard | static void dbdma_writew (void *opaque, target_phys_addr_t addr, uint32_t value) |
49 | 267002cd | bellard | { |
50 | 267002cd | bellard | } |
51 | 267002cd | bellard | |
52 | 267002cd | bellard | static void dbdma_writel (void *opaque, target_phys_addr_t addr, uint32_t value) |
53 | 267002cd | bellard | { |
54 | 267002cd | bellard | } |
55 | 267002cd | bellard | |
56 | 267002cd | bellard | static uint32_t dbdma_readb (void *opaque, target_phys_addr_t addr) |
57 | 267002cd | bellard | { |
58 | b6b8bd18 | bellard | printf("%s: 0x%08x => 0x00000000\n", __func__, addr);
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59 | 267002cd | bellard | return 0; |
60 | 267002cd | bellard | } |
61 | 267002cd | bellard | |
62 | 267002cd | bellard | static uint32_t dbdma_readw (void *opaque, target_phys_addr_t addr) |
63 | 267002cd | bellard | { |
64 | 267002cd | bellard | return 0; |
65 | 267002cd | bellard | } |
66 | 267002cd | bellard | |
67 | 267002cd | bellard | static uint32_t dbdma_readl (void *opaque, target_phys_addr_t addr) |
68 | 267002cd | bellard | { |
69 | 267002cd | bellard | return 0; |
70 | 267002cd | bellard | } |
71 | 267002cd | bellard | |
72 | 267002cd | bellard | static CPUWriteMemoryFunc *dbdma_write[] = {
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73 | 267002cd | bellard | &dbdma_writeb, |
74 | 267002cd | bellard | &dbdma_writew, |
75 | 267002cd | bellard | &dbdma_writel, |
76 | 267002cd | bellard | }; |
77 | 267002cd | bellard | |
78 | 267002cd | bellard | static CPUReadMemoryFunc *dbdma_read[] = {
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79 | 267002cd | bellard | &dbdma_readb, |
80 | 267002cd | bellard | &dbdma_readw, |
81 | 267002cd | bellard | &dbdma_readl, |
82 | 267002cd | bellard | }; |
83 | 267002cd | bellard | |
84 | 267002cd | bellard | static void macio_map(PCIDevice *pci_dev, int region_num, |
85 | 267002cd | bellard | uint32_t addr, uint32_t size, int type)
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86 | 267002cd | bellard | { |
87 | 267002cd | bellard | cpu_register_physical_memory(addr + 0x08000, 0x1000, dbdma_mem_index); |
88 | 267002cd | bellard | cpu_register_physical_memory(addr + 0x16000, 0x2000, cuda_mem_index); |
89 | b6b8bd18 | bellard | cpu_register_physical_memory(addr + 0x1f000, 0x1000, ide0_mem_index); |
90 | b6b8bd18 | bellard | cpu_register_physical_memory(addr + 0x20000, 0x1000, ide1_mem_index); |
91 | 91d848eb | bellard | cpu_register_physical_memory(addr + 0x40000, 0x40000, openpic_mem_index); |
92 | 267002cd | bellard | } |
93 | 267002cd | bellard | |
94 | 46e50e9d | bellard | static void macio_init(PCIBus *bus) |
95 | 267002cd | bellard | { |
96 | 267002cd | bellard | PCIDevice *d; |
97 | 267002cd | bellard | |
98 | 46e50e9d | bellard | d = pci_register_device(bus, "macio", sizeof(PCIDevice), |
99 | 46e50e9d | bellard | -1, NULL, NULL); |
100 | 267002cd | bellard | /* Note: this code is strongly inspirated from the corresponding code
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101 | 267002cd | bellard | in PearPC */
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102 | 267002cd | bellard | d->config[0x00] = 0x6b; // vendor_id |
103 | 267002cd | bellard | d->config[0x01] = 0x10; |
104 | b6b8bd18 | bellard | d->config[0x02] = 0x22; |
105 | 267002cd | bellard | d->config[0x03] = 0x00; |
106 | 267002cd | bellard | |
107 | 267002cd | bellard | d->config[0x0a] = 0x00; // class_sub = pci2pci |
108 | 267002cd | bellard | d->config[0x0b] = 0xff; // class_base = bridge |
109 | 267002cd | bellard | d->config[0x0e] = 0x00; // header_type |
110 | 267002cd | bellard | |
111 | 267002cd | bellard | d->config[0x3d] = 0x01; // interrupt on pin 1 |
112 | 267002cd | bellard | |
113 | 267002cd | bellard | dbdma_mem_index = cpu_register_io_memory(0, dbdma_read, dbdma_write, NULL); |
114 | 267002cd | bellard | |
115 | 267002cd | bellard | pci_register_io_region(d, 0, 0x80000, |
116 | 267002cd | bellard | PCI_ADDRESS_SPACE_MEM, macio_map); |
117 | 267002cd | bellard | } |
118 | 267002cd | bellard | |
119 | 64201201 | bellard | /* PowerPC PREP hardware initialisation */
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120 | 64201201 | bellard | void ppc_chrp_init(int ram_size, int vga_ram_size, int boot_device, |
121 | 64201201 | bellard | DisplayState *ds, const char **fd_filename, int snapshot, |
122 | 64201201 | bellard | const char *kernel_filename, const char *kernel_cmdline, |
123 | 64201201 | bellard | const char *initrd_filename) |
124 | 64201201 | bellard | { |
125 | 64201201 | bellard | char buf[1024]; |
126 | b6b8bd18 | bellard | openpic_t *openpic; |
127 | 64201201 | bellard | m48t59_t *nvram; |
128 | 64201201 | bellard | int PPC_io_memory;
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129 | 82c643ff | bellard | int ret, linux_boot, i;
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130 | 64201201 | bellard | unsigned long bios_offset; |
131 | b6b8bd18 | bellard | uint32_t kernel_base, kernel_size, initrd_base, initrd_size; |
132 | 46e50e9d | bellard | PCIBus *pci_bus; |
133 | 46e50e9d | bellard | |
134 | 64201201 | bellard | linux_boot = (kernel_filename != NULL);
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135 | 64201201 | bellard | |
136 | 64201201 | bellard | /* allocate RAM */
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137 | 64201201 | bellard | cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
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138 | 64201201 | bellard | |
139 | 64201201 | bellard | /* allocate and load BIOS */
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140 | 64201201 | bellard | bios_offset = ram_size + vga_ram_size; |
141 | 64201201 | bellard | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME); |
142 | 64201201 | bellard | ret = load_image(buf, phys_ram_base + bios_offset); |
143 | 64201201 | bellard | if (ret != BIOS_SIZE) {
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144 | 64201201 | bellard | fprintf(stderr, "qemu: could not load PPC PREP bios '%s'\n", buf);
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145 | 64201201 | bellard | exit(1);
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146 | 64201201 | bellard | } |
147 | 64201201 | bellard | cpu_register_physical_memory((uint32_t)(-BIOS_SIZE), |
148 | 64201201 | bellard | BIOS_SIZE, bios_offset | IO_MEM_ROM); |
149 | 64201201 | bellard | cpu_single_env->nip = 0xfffffffc;
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150 | 64201201 | bellard | |
151 | b6b8bd18 | bellard | if (linux_boot) {
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152 | b6b8bd18 | bellard | kernel_base = KERNEL_LOAD_ADDR; |
153 | b6b8bd18 | bellard | /* now we can load the kernel */
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154 | b6b8bd18 | bellard | kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base); |
155 | b6b8bd18 | bellard | if (kernel_size < 0) { |
156 | b6b8bd18 | bellard | fprintf(stderr, "qemu: could not load kernel '%s'\n",
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157 | b6b8bd18 | bellard | kernel_filename); |
158 | b6b8bd18 | bellard | exit(1);
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159 | b6b8bd18 | bellard | } |
160 | b6b8bd18 | bellard | /* load initrd */
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161 | b6b8bd18 | bellard | if (initrd_filename) {
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162 | b6b8bd18 | bellard | initrd_base = INITRD_LOAD_ADDR; |
163 | b6b8bd18 | bellard | initrd_size = load_image(initrd_filename, |
164 | b6b8bd18 | bellard | phys_ram_base + initrd_base); |
165 | b6b8bd18 | bellard | if (initrd_size < 0) { |
166 | b6b8bd18 | bellard | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
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167 | b6b8bd18 | bellard | initrd_filename); |
168 | b6b8bd18 | bellard | exit(1);
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169 | b6b8bd18 | bellard | } |
170 | b6b8bd18 | bellard | } else {
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171 | b6b8bd18 | bellard | initrd_base = 0;
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172 | b6b8bd18 | bellard | initrd_size = 0;
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173 | b6b8bd18 | bellard | } |
174 | b6b8bd18 | bellard | boot_device = 'm';
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175 | b6b8bd18 | bellard | } else {
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176 | b6b8bd18 | bellard | kernel_base = 0;
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177 | b6b8bd18 | bellard | kernel_size = 0;
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178 | b6b8bd18 | bellard | initrd_base = 0;
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179 | b6b8bd18 | bellard | initrd_size = 0;
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180 | b6b8bd18 | bellard | } |
181 | 64201201 | bellard | /* Register CPU as a 74x/75x */
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182 | 64201201 | bellard | cpu_ppc_register(cpu_single_env, 0x00080000);
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183 | 64201201 | bellard | /* Set time-base frequency to 100 Mhz */
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184 | 64201201 | bellard | cpu_ppc_tb_init(cpu_single_env, 100UL * 1000UL * 1000UL); |
185 | 64201201 | bellard | |
186 | b6b8bd18 | bellard | isa_mem_base = 0x80000000;
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187 | 46e50e9d | bellard | pci_bus = pci_pmac_init(); |
188 | 64201201 | bellard | |
189 | b6b8bd18 | bellard | /* Register 8 MB of ISA IO space */
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190 | a4193c8a | bellard | PPC_io_memory = cpu_register_io_memory(0, PPC_io_read, PPC_io_write, NULL); |
191 | b6b8bd18 | bellard | cpu_register_physical_memory(0xF2000000, 0x00800000, PPC_io_memory); |
192 | 64201201 | bellard | |
193 | 64201201 | bellard | /* init basic PC hardware */
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194 | 46e50e9d | bellard | vga_initialize(pci_bus, ds, phys_ram_base + ram_size, ram_size, |
195 | 46e50e9d | bellard | vga_ram_size); |
196 | 91d848eb | bellard | openpic = openpic_init(NULL, &openpic_mem_index, 1); |
197 | 46e50e9d | bellard | pci_pmac_set_openpic(pci_bus, openpic); |
198 | 46e50e9d | bellard | |
199 | b6b8bd18 | bellard | /* XXX: suppress that */
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200 | 64201201 | bellard | pic_init(); |
201 | 64201201 | bellard | |
202 | 64201201 | bellard | /* XXX: use Mac Serial port */
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203 | 8d11df9e | bellard | serial_init(0x3f8, 4, serial_hds[0]); |
204 | 64201201 | bellard | |
205 | 64201201 | bellard | for(i = 0; i < nb_nics; i++) { |
206 | 46e50e9d | bellard | pci_ne2000_init(pci_bus, &nd_table[i]); |
207 | 64201201 | bellard | } |
208 | 64201201 | bellard | |
209 | b6b8bd18 | bellard | ide0_mem_index = pmac_ide_init(&bs_table[0], openpic, 0x13); |
210 | b6b8bd18 | bellard | ide1_mem_index = pmac_ide_init(&bs_table[2], openpic, 0x13); |
211 | 64201201 | bellard | |
212 | 267002cd | bellard | /* cuda also initialize ADB */
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213 | b6b8bd18 | bellard | cuda_mem_index = cuda_init(openpic, 0x19);
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214 | 267002cd | bellard | |
215 | 267002cd | bellard | adb_kbd_init(&adb_bus); |
216 | 267002cd | bellard | adb_mouse_init(&adb_bus); |
217 | 267002cd | bellard | |
218 | 46e50e9d | bellard | macio_init(pci_bus); |
219 | 64201201 | bellard | |
220 | b6b8bd18 | bellard | nvram = m48t59_init(8, 0xFFF04000, 0x0074, NVRAM_SIZE); |
221 | b6b8bd18 | bellard | |
222 | b6b8bd18 | bellard | if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8) |
223 | b6b8bd18 | bellard | graphic_depth = 15;
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224 | 64201201 | bellard | |
225 | b6b8bd18 | bellard | PPC_NVRAM_set_params(nvram, NVRAM_SIZE, "CHRP", ram_size, boot_device,
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226 | b6b8bd18 | bellard | kernel_base, kernel_size, |
227 | b6b8bd18 | bellard | kernel_cmdline, |
228 | b6b8bd18 | bellard | initrd_base, initrd_size, |
229 | 64201201 | bellard | /* XXX: need an option to load a NVRAM image */
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230 | b6b8bd18 | bellard | 0,
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231 | b6b8bd18 | bellard | graphic_width, graphic_height, graphic_depth); |
232 | b6b8bd18 | bellard | /* No PCI init: the BIOS will do it */
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233 | 64201201 | bellard | } |