root / target-ppc / translate.c @ 977d5710
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1 | 79aceca5 | bellard | /*
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2 | 79aceca5 | bellard | * PPC emulation for qemu: main translation routines.
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3 | 79aceca5 | bellard | *
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4 | 79aceca5 | bellard | * Copyright (c) 2003 Jocelyn Mayer
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5 | 79aceca5 | bellard | *
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6 | 79aceca5 | bellard | * This library is free software; you can redistribute it and/or
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7 | 79aceca5 | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 79aceca5 | bellard | * License as published by the Free Software Foundation; either
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9 | 79aceca5 | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 79aceca5 | bellard | *
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11 | 79aceca5 | bellard | * This library is distributed in the hope that it will be useful,
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12 | 79aceca5 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 79aceca5 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 79aceca5 | bellard | * Lesser General Public License for more details.
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15 | 79aceca5 | bellard | *
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16 | 79aceca5 | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 79aceca5 | bellard | * License along with this library; if not, write to the Free Software
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18 | 79aceca5 | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | 79aceca5 | bellard | */
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20 | c6a1c22b | bellard | #include <stdarg.h> |
21 | c6a1c22b | bellard | #include <stdlib.h> |
22 | c6a1c22b | bellard | #include <stdio.h> |
23 | c6a1c22b | bellard | #include <string.h> |
24 | c6a1c22b | bellard | #include <inttypes.h> |
25 | c6a1c22b | bellard | |
26 | 79aceca5 | bellard | #include "cpu.h" |
27 | c6a1c22b | bellard | #include "exec-all.h" |
28 | 79aceca5 | bellard | #include "disas.h" |
29 | 79aceca5 | bellard | |
30 | 79aceca5 | bellard | //#define DO_SINGLE_STEP
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31 | 9fddaa0c | bellard | //#define PPC_DEBUG_DISAS
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32 | 79aceca5 | bellard | |
33 | 79aceca5 | bellard | enum {
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34 | 79aceca5 | bellard | #define DEF(s, n, copy_size) INDEX_op_ ## s, |
35 | 79aceca5 | bellard | #include "opc.h" |
36 | 79aceca5 | bellard | #undef DEF
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37 | 79aceca5 | bellard | NB_OPS, |
38 | 79aceca5 | bellard | }; |
39 | 79aceca5 | bellard | |
40 | 79aceca5 | bellard | static uint16_t *gen_opc_ptr;
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41 | 79aceca5 | bellard | static uint32_t *gen_opparam_ptr;
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42 | 79aceca5 | bellard | |
43 | 79aceca5 | bellard | #include "gen-op.h" |
44 | 28b6751f | bellard | |
45 | 28b6751f | bellard | #define GEN8(func, NAME) \
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46 | 9a64fbe4 | bellard | static GenOpFunc *NAME ## _table [8] = { \ |
47 | 9a64fbe4 | bellard | NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \ |
48 | 9a64fbe4 | bellard | NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \ |
49 | 9a64fbe4 | bellard | }; \ |
50 | 9a64fbe4 | bellard | static inline void func(int n) \ |
51 | 9a64fbe4 | bellard | { \ |
52 | 9a64fbe4 | bellard | NAME ## _table[n](); \ |
53 | 9a64fbe4 | bellard | } |
54 | 9a64fbe4 | bellard | |
55 | 9a64fbe4 | bellard | #define GEN16(func, NAME) \
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56 | 9a64fbe4 | bellard | static GenOpFunc *NAME ## _table [16] = { \ |
57 | 9a64fbe4 | bellard | NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \ |
58 | 9a64fbe4 | bellard | NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \ |
59 | 9a64fbe4 | bellard | NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \ |
60 | 9a64fbe4 | bellard | NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \ |
61 | 9a64fbe4 | bellard | }; \ |
62 | 9a64fbe4 | bellard | static inline void func(int n) \ |
63 | 9a64fbe4 | bellard | { \ |
64 | 9a64fbe4 | bellard | NAME ## _table[n](); \ |
65 | 28b6751f | bellard | } |
66 | 28b6751f | bellard | |
67 | 28b6751f | bellard | #define GEN32(func, NAME) \
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68 | 9a64fbe4 | bellard | static GenOpFunc *NAME ## _table [32] = { \ |
69 | 9a64fbe4 | bellard | NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \ |
70 | 9a64fbe4 | bellard | NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \ |
71 | 9a64fbe4 | bellard | NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \ |
72 | 9a64fbe4 | bellard | NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \ |
73 | 9a64fbe4 | bellard | NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \ |
74 | 9a64fbe4 | bellard | NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \ |
75 | 9a64fbe4 | bellard | NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \ |
76 | 9a64fbe4 | bellard | NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \ |
77 | 9a64fbe4 | bellard | }; \ |
78 | 9a64fbe4 | bellard | static inline void func(int n) \ |
79 | 9a64fbe4 | bellard | { \ |
80 | 9a64fbe4 | bellard | NAME ## _table[n](); \ |
81 | 9a64fbe4 | bellard | } |
82 | 9a64fbe4 | bellard | |
83 | 9a64fbe4 | bellard | /* Condition register moves */
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84 | 9a64fbe4 | bellard | GEN8(gen_op_load_crf_T0, gen_op_load_crf_T0_crf); |
85 | 9a64fbe4 | bellard | GEN8(gen_op_load_crf_T1, gen_op_load_crf_T1_crf); |
86 | 9a64fbe4 | bellard | GEN8(gen_op_store_T0_crf, gen_op_store_T0_crf_crf); |
87 | 9a64fbe4 | bellard | GEN8(gen_op_store_T1_crf, gen_op_store_T1_crf_crf); |
88 | 28b6751f | bellard | |
89 | fb0eaffc | bellard | /* Floating point condition and status register moves */
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90 | fb0eaffc | bellard | GEN8(gen_op_load_fpscr_T0, gen_op_load_fpscr_T0_fpscr); |
91 | fb0eaffc | bellard | GEN8(gen_op_store_T0_fpscr, gen_op_store_T0_fpscr_fpscr); |
92 | fb0eaffc | bellard | GEN8(gen_op_clear_fpscr, gen_op_clear_fpscr_fpscr); |
93 | fb0eaffc | bellard | static GenOpFunc1 *gen_op_store_T0_fpscri_fpscr_table[8] = { |
94 | fb0eaffc | bellard | &gen_op_store_T0_fpscri_fpscr0, |
95 | fb0eaffc | bellard | &gen_op_store_T0_fpscri_fpscr1, |
96 | fb0eaffc | bellard | &gen_op_store_T0_fpscri_fpscr2, |
97 | fb0eaffc | bellard | &gen_op_store_T0_fpscri_fpscr3, |
98 | fb0eaffc | bellard | &gen_op_store_T0_fpscri_fpscr4, |
99 | fb0eaffc | bellard | &gen_op_store_T0_fpscri_fpscr5, |
100 | fb0eaffc | bellard | &gen_op_store_T0_fpscri_fpscr6, |
101 | fb0eaffc | bellard | &gen_op_store_T0_fpscri_fpscr7, |
102 | fb0eaffc | bellard | }; |
103 | fb0eaffc | bellard | static inline void gen_op_store_T0_fpscri(int n, uint8_t param) |
104 | fb0eaffc | bellard | { |
105 | fb0eaffc | bellard | (*gen_op_store_T0_fpscri_fpscr_table[n])(param); |
106 | fb0eaffc | bellard | } |
107 | fb0eaffc | bellard | |
108 | 9a64fbe4 | bellard | /* Segment register moves */
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109 | 9a64fbe4 | bellard | GEN16(gen_op_load_sr, gen_op_load_sr); |
110 | 9a64fbe4 | bellard | GEN16(gen_op_store_sr, gen_op_store_sr); |
111 | 28b6751f | bellard | |
112 | 9a64fbe4 | bellard | /* General purpose registers moves */
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113 | 9a64fbe4 | bellard | GEN32(gen_op_load_gpr_T0, gen_op_load_gpr_T0_gpr); |
114 | 9a64fbe4 | bellard | GEN32(gen_op_load_gpr_T1, gen_op_load_gpr_T1_gpr); |
115 | 9a64fbe4 | bellard | GEN32(gen_op_load_gpr_T2, gen_op_load_gpr_T2_gpr); |
116 | 9a64fbe4 | bellard | |
117 | 9a64fbe4 | bellard | GEN32(gen_op_store_T0_gpr, gen_op_store_T0_gpr_gpr); |
118 | 9a64fbe4 | bellard | GEN32(gen_op_store_T1_gpr, gen_op_store_T1_gpr_gpr); |
119 | 9a64fbe4 | bellard | GEN32(gen_op_store_T2_gpr, gen_op_store_T2_gpr_gpr); |
120 | 28b6751f | bellard | |
121 | fb0eaffc | bellard | /* floating point registers moves */
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122 | fb0eaffc | bellard | GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fpr); |
123 | fb0eaffc | bellard | GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fpr); |
124 | fb0eaffc | bellard | GEN32(gen_op_load_fpr_FT2, gen_op_load_fpr_FT2_fpr); |
125 | fb0eaffc | bellard | GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fpr); |
126 | fb0eaffc | bellard | GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fpr); |
127 | fb0eaffc | bellard | GEN32(gen_op_store_FT2_fpr, gen_op_store_FT2_fpr_fpr); |
128 | 79aceca5 | bellard | |
129 | 79aceca5 | bellard | static uint8_t spr_access[1024 / 2]; |
130 | 79aceca5 | bellard | |
131 | 79aceca5 | bellard | /* internal defines */
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132 | 79aceca5 | bellard | typedef struct DisasContext { |
133 | 79aceca5 | bellard | struct TranslationBlock *tb;
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134 | 0fa85d43 | bellard | target_ulong nip; |
135 | 79aceca5 | bellard | uint32_t opcode; |
136 | 9a64fbe4 | bellard | uint32_t exception; |
137 | 9a64fbe4 | bellard | /* Execution mode */
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138 | 9a64fbe4 | bellard | #if !defined(CONFIG_USER_ONLY)
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139 | 79aceca5 | bellard | int supervisor;
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140 | 9a64fbe4 | bellard | #endif
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141 | 9a64fbe4 | bellard | /* Routine used to access memory */
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142 | 9a64fbe4 | bellard | int mem_idx;
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143 | 79aceca5 | bellard | } DisasContext; |
144 | 79aceca5 | bellard | |
145 | 79aceca5 | bellard | typedef struct opc_handler_t { |
146 | 79aceca5 | bellard | /* invalid bits */
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147 | 79aceca5 | bellard | uint32_t inval; |
148 | 9a64fbe4 | bellard | /* instruction type */
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149 | 9a64fbe4 | bellard | uint32_t type; |
150 | 79aceca5 | bellard | /* handler */
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151 | 79aceca5 | bellard | void (*handler)(DisasContext *ctx);
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152 | 79aceca5 | bellard | } opc_handler_t; |
153 | 79aceca5 | bellard | |
154 | 9fddaa0c | bellard | #define RET_EXCP(ctx, excp, error) \
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155 | 79aceca5 | bellard | do { \
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156 | 9fddaa0c | bellard | if ((ctx)->exception == EXCP_NONE) { \
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157 | 9fddaa0c | bellard | gen_op_update_nip((ctx)->nip); \ |
158 | 9fddaa0c | bellard | } \ |
159 | 9fddaa0c | bellard | gen_op_raise_exception_err((excp), (error)); \ |
160 | 9fddaa0c | bellard | ctx->exception = (excp); \ |
161 | 79aceca5 | bellard | } while (0) |
162 | 79aceca5 | bellard | |
163 | 9fddaa0c | bellard | #define RET_INVAL(ctx) \
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164 | 9fddaa0c | bellard | RET_EXCP((ctx), EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_INVAL) |
165 | 9fddaa0c | bellard | |
166 | 9fddaa0c | bellard | #define RET_PRIVOPC(ctx) \
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167 | 9fddaa0c | bellard | RET_EXCP((ctx), EXCP_PROGRAM, EXCP_INVAL | EXCP_PRIV_OPC) |
168 | 9a64fbe4 | bellard | |
169 | 9fddaa0c | bellard | #define RET_PRIVREG(ctx) \
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170 | 9fddaa0c | bellard | RET_EXCP((ctx), EXCP_PROGRAM, EXCP_INVAL | EXCP_PRIV_REG) |
171 | 9a64fbe4 | bellard | |
172 | 9fddaa0c | bellard | #define RET_MTMSR(ctx) \
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173 | 9fddaa0c | bellard | RET_EXCP((ctx), EXCP_MTMSR, 0)
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174 | 79aceca5 | bellard | |
175 | 79aceca5 | bellard | #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
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176 | 79aceca5 | bellard | static void gen_##name (DisasContext *ctx); \ |
177 | 79aceca5 | bellard | GEN_OPCODE(name, opc1, opc2, opc3, inval, type); \ |
178 | 79aceca5 | bellard | static void gen_##name (DisasContext *ctx) |
179 | 79aceca5 | bellard | |
180 | 79aceca5 | bellard | typedef struct opcode_t { |
181 | 79aceca5 | bellard | unsigned char opc1, opc2, opc3; |
182 | 79aceca5 | bellard | opc_handler_t handler; |
183 | 79aceca5 | bellard | } opcode_t; |
184 | 79aceca5 | bellard | |
185 | 79aceca5 | bellard | /*** Instruction decoding ***/
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186 | 79aceca5 | bellard | #define EXTRACT_HELPER(name, shift, nb) \
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187 | 79aceca5 | bellard | static inline uint32_t name (uint32_t opcode) \ |
188 | 79aceca5 | bellard | { \ |
189 | 79aceca5 | bellard | return (opcode >> (shift)) & ((1 << (nb)) - 1); \ |
190 | 79aceca5 | bellard | } |
191 | 79aceca5 | bellard | |
192 | 79aceca5 | bellard | #define EXTRACT_SHELPER(name, shift, nb) \
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193 | 79aceca5 | bellard | static inline int32_t name (uint32_t opcode) \ |
194 | 79aceca5 | bellard | { \ |
195 | 79aceca5 | bellard | return s_ext16((opcode >> (shift)) & ((1 << (nb)) - 1)); \ |
196 | 79aceca5 | bellard | } |
197 | 79aceca5 | bellard | |
198 | 79aceca5 | bellard | /* Opcode part 1 */
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199 | 79aceca5 | bellard | EXTRACT_HELPER(opc1, 26, 6); |
200 | 79aceca5 | bellard | /* Opcode part 2 */
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201 | 79aceca5 | bellard | EXTRACT_HELPER(opc2, 1, 5); |
202 | 79aceca5 | bellard | /* Opcode part 3 */
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203 | 79aceca5 | bellard | EXTRACT_HELPER(opc3, 6, 5); |
204 | 79aceca5 | bellard | /* Update Cr0 flags */
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205 | 79aceca5 | bellard | EXTRACT_HELPER(Rc, 0, 1); |
206 | 79aceca5 | bellard | /* Destination */
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207 | 79aceca5 | bellard | EXTRACT_HELPER(rD, 21, 5); |
208 | 79aceca5 | bellard | /* Source */
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209 | 79aceca5 | bellard | EXTRACT_HELPER(rS, 21, 5); |
210 | 79aceca5 | bellard | /* First operand */
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211 | 79aceca5 | bellard | EXTRACT_HELPER(rA, 16, 5); |
212 | 79aceca5 | bellard | /* Second operand */
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213 | 79aceca5 | bellard | EXTRACT_HELPER(rB, 11, 5); |
214 | 79aceca5 | bellard | /* Third operand */
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215 | 79aceca5 | bellard | EXTRACT_HELPER(rC, 6, 5); |
216 | 79aceca5 | bellard | /*** Get CRn ***/
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217 | 79aceca5 | bellard | EXTRACT_HELPER(crfD, 23, 3); |
218 | 79aceca5 | bellard | EXTRACT_HELPER(crfS, 18, 3); |
219 | 79aceca5 | bellard | EXTRACT_HELPER(crbD, 21, 5); |
220 | 79aceca5 | bellard | EXTRACT_HELPER(crbA, 16, 5); |
221 | 79aceca5 | bellard | EXTRACT_HELPER(crbB, 11, 5); |
222 | 79aceca5 | bellard | /* SPR / TBL */
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223 | 79aceca5 | bellard | EXTRACT_HELPER(SPR, 11, 10); |
224 | 79aceca5 | bellard | /*** Get constants ***/
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225 | 79aceca5 | bellard | EXTRACT_HELPER(IMM, 12, 8); |
226 | 79aceca5 | bellard | /* 16 bits signed immediate value */
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227 | 79aceca5 | bellard | EXTRACT_SHELPER(SIMM, 0, 16); |
228 | 79aceca5 | bellard | /* 16 bits unsigned immediate value */
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229 | 79aceca5 | bellard | EXTRACT_HELPER(UIMM, 0, 16); |
230 | 79aceca5 | bellard | /* Bit count */
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231 | 79aceca5 | bellard | EXTRACT_HELPER(NB, 11, 5); |
232 | 79aceca5 | bellard | /* Shift count */
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233 | 79aceca5 | bellard | EXTRACT_HELPER(SH, 11, 5); |
234 | 79aceca5 | bellard | /* Mask start */
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235 | 79aceca5 | bellard | EXTRACT_HELPER(MB, 6, 5); |
236 | 79aceca5 | bellard | /* Mask end */
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237 | 79aceca5 | bellard | EXTRACT_HELPER(ME, 1, 5); |
238 | fb0eaffc | bellard | /* Trap operand */
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239 | fb0eaffc | bellard | EXTRACT_HELPER(TO, 21, 5); |
240 | 79aceca5 | bellard | |
241 | 79aceca5 | bellard | EXTRACT_HELPER(CRM, 12, 8); |
242 | 79aceca5 | bellard | EXTRACT_HELPER(FM, 17, 8); |
243 | 79aceca5 | bellard | EXTRACT_HELPER(SR, 16, 4); |
244 | fb0eaffc | bellard | EXTRACT_HELPER(FPIMM, 20, 4); |
245 | fb0eaffc | bellard | |
246 | 79aceca5 | bellard | /*** Jump target decoding ***/
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247 | 79aceca5 | bellard | /* Displacement */
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248 | 79aceca5 | bellard | EXTRACT_SHELPER(d, 0, 16); |
249 | 79aceca5 | bellard | /* Immediate address */
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250 | 79aceca5 | bellard | static inline uint32_t LI (uint32_t opcode) |
251 | 79aceca5 | bellard | { |
252 | 79aceca5 | bellard | return (opcode >> 0) & 0x03FFFFFC; |
253 | 79aceca5 | bellard | } |
254 | 79aceca5 | bellard | |
255 | 79aceca5 | bellard | static inline uint32_t BD (uint32_t opcode) |
256 | 79aceca5 | bellard | { |
257 | 79aceca5 | bellard | return (opcode >> 0) & 0xFFFC; |
258 | 79aceca5 | bellard | } |
259 | 79aceca5 | bellard | |
260 | 79aceca5 | bellard | EXTRACT_HELPER(BO, 21, 5); |
261 | 79aceca5 | bellard | EXTRACT_HELPER(BI, 16, 5); |
262 | 79aceca5 | bellard | /* Absolute/relative address */
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263 | 79aceca5 | bellard | EXTRACT_HELPER(AA, 1, 1); |
264 | 79aceca5 | bellard | /* Link */
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265 | 79aceca5 | bellard | EXTRACT_HELPER(LK, 0, 1); |
266 | 79aceca5 | bellard | |
267 | 79aceca5 | bellard | /* Create a mask between <start> and <end> bits */
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268 | 79aceca5 | bellard | static inline uint32_t MASK (uint32_t start, uint32_t end) |
269 | 79aceca5 | bellard | { |
270 | 79aceca5 | bellard | uint32_t ret; |
271 | 79aceca5 | bellard | |
272 | 79aceca5 | bellard | ret = (((uint32_t)(-1)) >> (start)) ^ (((uint32_t)(-1) >> (end)) >> 1); |
273 | 79aceca5 | bellard | if (start > end)
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274 | 79aceca5 | bellard | return ~ret;
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275 | 79aceca5 | bellard | |
276 | 79aceca5 | bellard | return ret;
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277 | 79aceca5 | bellard | } |
278 | 79aceca5 | bellard | |
279 | 1b039c09 | bellard | #if defined(__APPLE__)
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280 | 933dc6eb | bellard | #define OPCODES_SECTION \
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281 | 1b039c09 | bellard | __attribute__ ((section("__TEXT,__opcodes"), unused, aligned (8) )) |
282 | 933dc6eb | bellard | #else
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283 | 1b039c09 | bellard | #define OPCODES_SECTION \
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284 | 1b039c09 | bellard | __attribute__ ((section(".opcodes"), unused, aligned (8) )) |
285 | 933dc6eb | bellard | #endif
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286 | 933dc6eb | bellard | |
287 | 79aceca5 | bellard | #define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
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288 | 933dc6eb | bellard | OPCODES_SECTION static opcode_t opc_##name = { \ |
289 | 79aceca5 | bellard | .opc1 = op1, \ |
290 | 79aceca5 | bellard | .opc2 = op2, \ |
291 | 79aceca5 | bellard | .opc3 = op3, \ |
292 | 79aceca5 | bellard | .handler = { \ |
293 | 79aceca5 | bellard | .inval = invl, \ |
294 | 9a64fbe4 | bellard | .type = _typ, \ |
295 | 79aceca5 | bellard | .handler = &gen_##name, \ |
296 | 79aceca5 | bellard | }, \ |
297 | 79aceca5 | bellard | } |
298 | 79aceca5 | bellard | |
299 | 79aceca5 | bellard | #define GEN_OPCODE_MARK(name) \
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300 | 933dc6eb | bellard | OPCODES_SECTION static opcode_t opc_##name = { \ |
301 | 79aceca5 | bellard | .opc1 = 0xFF, \
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302 | 79aceca5 | bellard | .opc2 = 0xFF, \
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303 | 79aceca5 | bellard | .opc3 = 0xFF, \
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304 | 79aceca5 | bellard | .handler = { \ |
305 | 79aceca5 | bellard | .inval = 0x00000000, \
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306 | 9a64fbe4 | bellard | .type = 0x00, \
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307 | 79aceca5 | bellard | .handler = NULL, \
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308 | 79aceca5 | bellard | }, \ |
309 | 79aceca5 | bellard | } |
310 | 79aceca5 | bellard | |
311 | 79aceca5 | bellard | /* Start opcode list */
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312 | 79aceca5 | bellard | GEN_OPCODE_MARK(start); |
313 | 79aceca5 | bellard | |
314 | 79aceca5 | bellard | /* Invalid instruction */
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315 | 9a64fbe4 | bellard | GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE) |
316 | 9a64fbe4 | bellard | { |
317 | 9fddaa0c | bellard | RET_INVAL(ctx); |
318 | 9a64fbe4 | bellard | } |
319 | 9a64fbe4 | bellard | |
320 | 9a64fbe4 | bellard | /* Special opcode to stop emulation */
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321 | 9a64fbe4 | bellard | GEN_HANDLER(stop, 0x06, 0x00, 0xFF, 0x03FFFFC1, PPC_COMMON) |
322 | 79aceca5 | bellard | { |
323 | 9fddaa0c | bellard | RET_EXCP(ctx, EXCP_HLT, 0);
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324 | 9a64fbe4 | bellard | } |
325 | 9a64fbe4 | bellard | |
326 | 9a64fbe4 | bellard | /* Special opcode to call open-firmware */
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327 | 9a64fbe4 | bellard | GEN_HANDLER(of_enter, 0x06, 0x01, 0xFF, 0x03FFFFC1, PPC_COMMON) |
328 | 9a64fbe4 | bellard | { |
329 | 9fddaa0c | bellard | RET_EXCP(ctx, EXCP_OFCALL, 0);
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330 | 9a64fbe4 | bellard | } |
331 | 9a64fbe4 | bellard | |
332 | 9a64fbe4 | bellard | /* Special opcode to call RTAS */
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333 | 9a64fbe4 | bellard | GEN_HANDLER(rtas_enter, 0x06, 0x02, 0xFF, 0x03FFFFC1, PPC_COMMON) |
334 | 9a64fbe4 | bellard | { |
335 | 9a64fbe4 | bellard | printf("RTAS entry point !\n");
|
336 | 9fddaa0c | bellard | RET_EXCP(ctx, EXCP_RTASCALL, 0);
|
337 | 79aceca5 | bellard | } |
338 | 79aceca5 | bellard | |
339 | 79aceca5 | bellard | static opc_handler_t invalid_handler = {
|
340 | 79aceca5 | bellard | .inval = 0xFFFFFFFF,
|
341 | 9a64fbe4 | bellard | .type = PPC_NONE, |
342 | 79aceca5 | bellard | .handler = gen_invalid, |
343 | 79aceca5 | bellard | }; |
344 | 79aceca5 | bellard | |
345 | 79aceca5 | bellard | /*** Integer arithmetic ***/
|
346 | 79aceca5 | bellard | #define __GEN_INT_ARITH2(name, opc1, opc2, opc3, inval) \
|
347 | 79aceca5 | bellard | GEN_HANDLER(name, opc1, opc2, opc3, inval, PPC_INTEGER) \ |
348 | 79aceca5 | bellard | { \ |
349 | 79aceca5 | bellard | gen_op_load_gpr_T0(rA(ctx->opcode)); \ |
350 | 79aceca5 | bellard | gen_op_load_gpr_T1(rB(ctx->opcode)); \ |
351 | 79aceca5 | bellard | gen_op_##name(); \ |
352 | 79aceca5 | bellard | if (Rc(ctx->opcode) != 0) \ |
353 | 79aceca5 | bellard | gen_op_set_Rc0(); \ |
354 | 79aceca5 | bellard | gen_op_store_T0_gpr(rD(ctx->opcode)); \ |
355 | 79aceca5 | bellard | } |
356 | 79aceca5 | bellard | |
357 | 79aceca5 | bellard | #define __GEN_INT_ARITH2_O(name, opc1, opc2, opc3, inval) \
|
358 | 79aceca5 | bellard | GEN_HANDLER(name, opc1, opc2, opc3, inval, PPC_INTEGER) \ |
359 | 79aceca5 | bellard | { \ |
360 | 79aceca5 | bellard | gen_op_load_gpr_T0(rA(ctx->opcode)); \ |
361 | 79aceca5 | bellard | gen_op_load_gpr_T1(rB(ctx->opcode)); \ |
362 | 79aceca5 | bellard | gen_op_##name(); \ |
363 | 79aceca5 | bellard | if (Rc(ctx->opcode) != 0) \ |
364 | 79aceca5 | bellard | gen_op_set_Rc0_ov(); \ |
365 | 79aceca5 | bellard | gen_op_store_T0_gpr(rD(ctx->opcode)); \ |
366 | 79aceca5 | bellard | } |
367 | 79aceca5 | bellard | |
368 | 79aceca5 | bellard | #define __GEN_INT_ARITH1(name, opc1, opc2, opc3) \
|
369 | 79aceca5 | bellard | GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, PPC_INTEGER) \
|
370 | 79aceca5 | bellard | { \ |
371 | 79aceca5 | bellard | gen_op_load_gpr_T0(rA(ctx->opcode)); \ |
372 | 79aceca5 | bellard | gen_op_##name(); \ |
373 | 79aceca5 | bellard | if (Rc(ctx->opcode) != 0) \ |
374 | 79aceca5 | bellard | gen_op_set_Rc0(); \ |
375 | 79aceca5 | bellard | gen_op_store_T0_gpr(rD(ctx->opcode)); \ |
376 | 79aceca5 | bellard | } |
377 | 79aceca5 | bellard | #define __GEN_INT_ARITH1_O(name, opc1, opc2, opc3) \
|
378 | 79aceca5 | bellard | GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, PPC_INTEGER) \
|
379 | 79aceca5 | bellard | { \ |
380 | 79aceca5 | bellard | gen_op_load_gpr_T0(rA(ctx->opcode)); \ |
381 | 79aceca5 | bellard | gen_op_##name(); \ |
382 | 79aceca5 | bellard | if (Rc(ctx->opcode) != 0) \ |
383 | 79aceca5 | bellard | gen_op_set_Rc0_ov(); \ |
384 | 79aceca5 | bellard | gen_op_store_T0_gpr(rD(ctx->opcode)); \ |
385 | 79aceca5 | bellard | } |
386 | 79aceca5 | bellard | |
387 | 79aceca5 | bellard | /* Two operands arithmetic functions */
|
388 | 79aceca5 | bellard | #define GEN_INT_ARITH2(name, opc1, opc2, opc3) \
|
389 | 79aceca5 | bellard | __GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000000) \
|
390 | 79aceca5 | bellard | __GEN_INT_ARITH2_O(name##o, opc1, opc2, opc3 | 0x10, 0x00000000) |
391 | 79aceca5 | bellard | |
392 | 79aceca5 | bellard | /* Two operands arithmetic functions with no overflow allowed */
|
393 | 79aceca5 | bellard | #define GEN_INT_ARITHN(name, opc1, opc2, opc3) \
|
394 | 79aceca5 | bellard | __GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000400)
|
395 | 79aceca5 | bellard | |
396 | 79aceca5 | bellard | /* One operand arithmetic functions */
|
397 | 79aceca5 | bellard | #define GEN_INT_ARITH1(name, opc1, opc2, opc3) \
|
398 | 79aceca5 | bellard | __GEN_INT_ARITH1(name, opc1, opc2, opc3) \ |
399 | 79aceca5 | bellard | __GEN_INT_ARITH1_O(name##o, opc1, opc2, opc3 | 0x10) |
400 | 79aceca5 | bellard | |
401 | 79aceca5 | bellard | /* add add. addo addo. */
|
402 | 79aceca5 | bellard | GEN_INT_ARITH2 (add, 0x1F, 0x0A, 0x08); |
403 | 79aceca5 | bellard | /* addc addc. addco addco. */
|
404 | 79aceca5 | bellard | GEN_INT_ARITH2 (addc, 0x1F, 0x0A, 0x00); |
405 | 79aceca5 | bellard | /* adde adde. addeo addeo. */
|
406 | 79aceca5 | bellard | GEN_INT_ARITH2 (adde, 0x1F, 0x0A, 0x04); |
407 | 79aceca5 | bellard | /* addme addme. addmeo addmeo. */
|
408 | 79aceca5 | bellard | GEN_INT_ARITH1 (addme, 0x1F, 0x0A, 0x07); |
409 | 79aceca5 | bellard | /* addze addze. addzeo addzeo. */
|
410 | 79aceca5 | bellard | GEN_INT_ARITH1 (addze, 0x1F, 0x0A, 0x06); |
411 | 79aceca5 | bellard | /* divw divw. divwo divwo. */
|
412 | 79aceca5 | bellard | GEN_INT_ARITH2 (divw, 0x1F, 0x0B, 0x0F); |
413 | 79aceca5 | bellard | /* divwu divwu. divwuo divwuo. */
|
414 | 79aceca5 | bellard | GEN_INT_ARITH2 (divwu, 0x1F, 0x0B, 0x0E); |
415 | 79aceca5 | bellard | /* mulhw mulhw. */
|
416 | 79aceca5 | bellard | GEN_INT_ARITHN (mulhw, 0x1F, 0x0B, 0x02); |
417 | 79aceca5 | bellard | /* mulhwu mulhwu. */
|
418 | 79aceca5 | bellard | GEN_INT_ARITHN (mulhwu, 0x1F, 0x0B, 0x00); |
419 | 79aceca5 | bellard | /* mullw mullw. mullwo mullwo. */
|
420 | 79aceca5 | bellard | GEN_INT_ARITH2 (mullw, 0x1F, 0x0B, 0x07); |
421 | 79aceca5 | bellard | /* neg neg. nego nego. */
|
422 | 79aceca5 | bellard | GEN_INT_ARITH1 (neg, 0x1F, 0x08, 0x03); |
423 | 79aceca5 | bellard | /* subf subf. subfo subfo. */
|
424 | 79aceca5 | bellard | GEN_INT_ARITH2 (subf, 0x1F, 0x08, 0x01); |
425 | 79aceca5 | bellard | /* subfc subfc. subfco subfco. */
|
426 | 79aceca5 | bellard | GEN_INT_ARITH2 (subfc, 0x1F, 0x08, 0x00); |
427 | 79aceca5 | bellard | /* subfe subfe. subfeo subfeo. */
|
428 | 79aceca5 | bellard | GEN_INT_ARITH2 (subfe, 0x1F, 0x08, 0x04); |
429 | 79aceca5 | bellard | /* subfme subfme. subfmeo subfmeo. */
|
430 | 79aceca5 | bellard | GEN_INT_ARITH1 (subfme, 0x1F, 0x08, 0x07); |
431 | 79aceca5 | bellard | /* subfze subfze. subfzeo subfzeo. */
|
432 | 79aceca5 | bellard | GEN_INT_ARITH1 (subfze, 0x1F, 0x08, 0x06); |
433 | 79aceca5 | bellard | /* addi */
|
434 | 79aceca5 | bellard | GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
435 | 79aceca5 | bellard | { |
436 | 79aceca5 | bellard | int32_t simm = SIMM(ctx->opcode); |
437 | 79aceca5 | bellard | |
438 | 79aceca5 | bellard | if (rA(ctx->opcode) == 0) { |
439 | 79aceca5 | bellard | gen_op_set_T0(simm); |
440 | 79aceca5 | bellard | } else {
|
441 | 79aceca5 | bellard | gen_op_load_gpr_T0(rA(ctx->opcode)); |
442 | 79aceca5 | bellard | gen_op_addi(simm); |
443 | 79aceca5 | bellard | } |
444 | 79aceca5 | bellard | gen_op_store_T0_gpr(rD(ctx->opcode)); |
445 | 79aceca5 | bellard | } |
446 | 79aceca5 | bellard | /* addic */
|
447 | 79aceca5 | bellard | GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
448 | 79aceca5 | bellard | { |
449 | 79aceca5 | bellard | gen_op_load_gpr_T0(rA(ctx->opcode)); |
450 | 79aceca5 | bellard | gen_op_addic(SIMM(ctx->opcode)); |
451 | 79aceca5 | bellard | gen_op_store_T0_gpr(rD(ctx->opcode)); |
452 | 79aceca5 | bellard | } |
453 | 79aceca5 | bellard | /* addic. */
|
454 | 79aceca5 | bellard | GEN_HANDLER(addic_, 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
455 | 79aceca5 | bellard | { |
456 | 79aceca5 | bellard | gen_op_load_gpr_T0(rA(ctx->opcode)); |
457 | 79aceca5 | bellard | gen_op_addic(SIMM(ctx->opcode)); |
458 | 79aceca5 | bellard | gen_op_set_Rc0(); |
459 | 79aceca5 | bellard | gen_op_store_T0_gpr(rD(ctx->opcode)); |
460 | 79aceca5 | bellard | } |
461 | 79aceca5 | bellard | /* addis */
|
462 | 79aceca5 | bellard | GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
463 | 79aceca5 | bellard | { |
464 | 79aceca5 | bellard | int32_t simm = SIMM(ctx->opcode); |
465 | 79aceca5 | bellard | |
466 | 79aceca5 | bellard | if (rA(ctx->opcode) == 0) { |
467 | 79aceca5 | bellard | gen_op_set_T0(simm << 16);
|
468 | 79aceca5 | bellard | } else {
|
469 | 79aceca5 | bellard | gen_op_load_gpr_T0(rA(ctx->opcode)); |
470 | 79aceca5 | bellard | gen_op_addi(simm << 16);
|
471 | 79aceca5 | bellard | } |
472 | 79aceca5 | bellard | gen_op_store_T0_gpr(rD(ctx->opcode)); |
473 | 79aceca5 | bellard | } |
474 | 79aceca5 | bellard | /* mulli */
|
475 | 79aceca5 | bellard | GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
476 | 79aceca5 | bellard | { |
477 | 79aceca5 | bellard | gen_op_load_gpr_T0(rA(ctx->opcode)); |
478 | 79aceca5 | bellard | gen_op_mulli(SIMM(ctx->opcode)); |
479 | 79aceca5 | bellard | gen_op_store_T0_gpr(rD(ctx->opcode)); |
480 | 79aceca5 | bellard | } |
481 | 79aceca5 | bellard | /* subfic */
|
482 | 79aceca5 | bellard | GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
483 | 79aceca5 | bellard | { |
484 | 79aceca5 | bellard | gen_op_load_gpr_T0(rA(ctx->opcode)); |
485 | 79aceca5 | bellard | gen_op_subfic(SIMM(ctx->opcode)); |
486 | 79aceca5 | bellard | gen_op_store_T0_gpr(rD(ctx->opcode)); |
487 | 79aceca5 | bellard | } |
488 | 79aceca5 | bellard | |
489 | 79aceca5 | bellard | /*** Integer comparison ***/
|
490 | 79aceca5 | bellard | #define GEN_CMP(name, opc) \
|
491 | 79aceca5 | bellard | GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, PPC_INTEGER) \ |
492 | 79aceca5 | bellard | { \ |
493 | 79aceca5 | bellard | gen_op_load_gpr_T0(rA(ctx->opcode)); \ |
494 | 79aceca5 | bellard | gen_op_load_gpr_T1(rB(ctx->opcode)); \ |
495 | 79aceca5 | bellard | gen_op_##name(); \ |
496 | 79aceca5 | bellard | gen_op_store_T0_crf(crfD(ctx->opcode)); \ |
497 | 79aceca5 | bellard | } |
498 | 79aceca5 | bellard | |
499 | 79aceca5 | bellard | /* cmp */
|
500 | 79aceca5 | bellard | GEN_CMP(cmp, 0x00);
|
501 | 79aceca5 | bellard | /* cmpi */
|
502 | 79aceca5 | bellard | GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER) |
503 | 79aceca5 | bellard | { |
504 | 79aceca5 | bellard | gen_op_load_gpr_T0(rA(ctx->opcode)); |
505 | 79aceca5 | bellard | gen_op_cmpi(SIMM(ctx->opcode)); |
506 | 79aceca5 | bellard | gen_op_store_T0_crf(crfD(ctx->opcode)); |
507 | 79aceca5 | bellard | } |
508 | 79aceca5 | bellard | /* cmpl */
|
509 | 79aceca5 | bellard | GEN_CMP(cmpl, 0x01);
|
510 | 79aceca5 | bellard | /* cmpli */
|
511 | 79aceca5 | bellard | GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER) |
512 | 79aceca5 | bellard | { |
513 | 79aceca5 | bellard | gen_op_load_gpr_T0(rA(ctx->opcode)); |
514 | 79aceca5 | bellard | gen_op_cmpli(UIMM(ctx->opcode)); |
515 | 79aceca5 | bellard | gen_op_store_T0_crf(crfD(ctx->opcode)); |
516 | 79aceca5 | bellard | } |
517 | 79aceca5 | bellard | |
518 | 79aceca5 | bellard | /*** Integer logical ***/
|
519 | 79aceca5 | bellard | #define __GEN_LOGICAL2(name, opc2, opc3) \
|
520 | 79aceca5 | bellard | GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000000, PPC_INTEGER) \ |
521 | 79aceca5 | bellard | { \ |
522 | 79aceca5 | bellard | gen_op_load_gpr_T0(rS(ctx->opcode)); \ |
523 | 79aceca5 | bellard | gen_op_load_gpr_T1(rB(ctx->opcode)); \ |
524 | 79aceca5 | bellard | gen_op_##name(); \ |
525 | 79aceca5 | bellard | if (Rc(ctx->opcode) != 0) \ |
526 | 79aceca5 | bellard | gen_op_set_Rc0(); \ |
527 | 79aceca5 | bellard | gen_op_store_T0_gpr(rA(ctx->opcode)); \ |
528 | 79aceca5 | bellard | } |
529 | 79aceca5 | bellard | #define GEN_LOGICAL2(name, opc) \
|
530 | 79aceca5 | bellard | __GEN_LOGICAL2(name, 0x1C, opc)
|
531 | 79aceca5 | bellard | |
532 | 79aceca5 | bellard | #define GEN_LOGICAL1(name, opc) \
|
533 | 79aceca5 | bellard | GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, PPC_INTEGER) \ |
534 | 79aceca5 | bellard | { \ |
535 | 79aceca5 | bellard | gen_op_load_gpr_T0(rS(ctx->opcode)); \ |
536 | 79aceca5 | bellard | gen_op_##name(); \ |
537 | 79aceca5 | bellard | if (Rc(ctx->opcode) != 0) \ |
538 | 79aceca5 | bellard | gen_op_set_Rc0(); \ |
539 | 79aceca5 | bellard | gen_op_store_T0_gpr(rA(ctx->opcode)); \ |
540 | 79aceca5 | bellard | } |
541 | 79aceca5 | bellard | |
542 | 79aceca5 | bellard | /* and & and. */
|
543 | 79aceca5 | bellard | GEN_LOGICAL2(and, 0x00);
|
544 | 79aceca5 | bellard | /* andc & andc. */
|
545 | 79aceca5 | bellard | GEN_LOGICAL2(andc, 0x01);
|
546 | 79aceca5 | bellard | /* andi. */
|
547 | 79aceca5 | bellard | GEN_HANDLER(andi_, 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
548 | 79aceca5 | bellard | { |
549 | 79aceca5 | bellard | gen_op_load_gpr_T0(rS(ctx->opcode)); |
550 | 79aceca5 | bellard | gen_op_andi_(UIMM(ctx->opcode)); |
551 | 79aceca5 | bellard | gen_op_set_Rc0(); |
552 | 79aceca5 | bellard | gen_op_store_T0_gpr(rA(ctx->opcode)); |
553 | 79aceca5 | bellard | } |
554 | 79aceca5 | bellard | /* andis. */
|
555 | 79aceca5 | bellard | GEN_HANDLER(andis_, 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
556 | 79aceca5 | bellard | { |
557 | 79aceca5 | bellard | gen_op_load_gpr_T0(rS(ctx->opcode)); |
558 | 79aceca5 | bellard | gen_op_andi_(UIMM(ctx->opcode) << 16);
|
559 | 79aceca5 | bellard | gen_op_set_Rc0(); |
560 | 79aceca5 | bellard | gen_op_store_T0_gpr(rA(ctx->opcode)); |
561 | 79aceca5 | bellard | } |
562 | 79aceca5 | bellard | |
563 | 79aceca5 | bellard | /* cntlzw */
|
564 | 79aceca5 | bellard | GEN_LOGICAL1(cntlzw, 0x00);
|
565 | 79aceca5 | bellard | /* eqv & eqv. */
|
566 | 79aceca5 | bellard | GEN_LOGICAL2(eqv, 0x08);
|
567 | 79aceca5 | bellard | /* extsb & extsb. */
|
568 | 79aceca5 | bellard | GEN_LOGICAL1(extsb, 0x1D);
|
569 | 79aceca5 | bellard | /* extsh & extsh. */
|
570 | 79aceca5 | bellard | GEN_LOGICAL1(extsh, 0x1C);
|
571 | 79aceca5 | bellard | /* nand & nand. */
|
572 | 79aceca5 | bellard | GEN_LOGICAL2(nand, 0x0E);
|
573 | 79aceca5 | bellard | /* nor & nor. */
|
574 | 79aceca5 | bellard | GEN_LOGICAL2(nor, 0x03);
|
575 | 9a64fbe4 | bellard | |
576 | 79aceca5 | bellard | /* or & or. */
|
577 | 9a64fbe4 | bellard | GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER) |
578 | 9a64fbe4 | bellard | { |
579 | 9a64fbe4 | bellard | gen_op_load_gpr_T0(rS(ctx->opcode)); |
580 | 9a64fbe4 | bellard | /* Optimisation for mr case */
|
581 | 9a64fbe4 | bellard | if (rS(ctx->opcode) != rB(ctx->opcode)) {
|
582 | 9a64fbe4 | bellard | gen_op_load_gpr_T1(rB(ctx->opcode)); |
583 | 9a64fbe4 | bellard | gen_op_or(); |
584 | 9a64fbe4 | bellard | } |
585 | 9a64fbe4 | bellard | if (Rc(ctx->opcode) != 0) |
586 | 9a64fbe4 | bellard | gen_op_set_Rc0(); |
587 | 9a64fbe4 | bellard | gen_op_store_T0_gpr(rA(ctx->opcode)); |
588 | 9a64fbe4 | bellard | } |
589 | 9a64fbe4 | bellard | |
590 | 79aceca5 | bellard | /* orc & orc. */
|
591 | 79aceca5 | bellard | GEN_LOGICAL2(orc, 0x0C);
|
592 | 79aceca5 | bellard | /* xor & xor. */
|
593 | 9a64fbe4 | bellard | GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER) |
594 | 9a64fbe4 | bellard | { |
595 | 9a64fbe4 | bellard | gen_op_load_gpr_T0(rS(ctx->opcode)); |
596 | 9a64fbe4 | bellard | /* Optimisation for "set to zero" case */
|
597 | 9a64fbe4 | bellard | if (rS(ctx->opcode) != rB(ctx->opcode)) {
|
598 | 9a64fbe4 | bellard | gen_op_load_gpr_T1(rB(ctx->opcode)); |
599 | 9a64fbe4 | bellard | gen_op_xor(); |
600 | 9a64fbe4 | bellard | } else {
|
601 | 9a64fbe4 | bellard | gen_op_set_T0(0);
|
602 | 9a64fbe4 | bellard | } |
603 | 9a64fbe4 | bellard | if (Rc(ctx->opcode) != 0) |
604 | 9a64fbe4 | bellard | gen_op_set_Rc0(); |
605 | 9a64fbe4 | bellard | gen_op_store_T0_gpr(rA(ctx->opcode)); |
606 | 9a64fbe4 | bellard | } |
607 | 79aceca5 | bellard | /* ori */
|
608 | 79aceca5 | bellard | GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
609 | 79aceca5 | bellard | { |
610 | 79aceca5 | bellard | uint32_t uimm = UIMM(ctx->opcode); |
611 | 79aceca5 | bellard | |
612 | 9a64fbe4 | bellard | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { |
613 | 9a64fbe4 | bellard | /* NOP */
|
614 | 9a64fbe4 | bellard | return;
|
615 | 79aceca5 | bellard | } |
616 | 79aceca5 | bellard | gen_op_load_gpr_T0(rS(ctx->opcode)); |
617 | 9a64fbe4 | bellard | if (uimm != 0) |
618 | 79aceca5 | bellard | gen_op_ori(uimm); |
619 | 79aceca5 | bellard | gen_op_store_T0_gpr(rA(ctx->opcode)); |
620 | 79aceca5 | bellard | } |
621 | 79aceca5 | bellard | /* oris */
|
622 | 79aceca5 | bellard | GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
623 | 79aceca5 | bellard | { |
624 | 79aceca5 | bellard | uint32_t uimm = UIMM(ctx->opcode); |
625 | 79aceca5 | bellard | |
626 | 9a64fbe4 | bellard | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { |
627 | 9a64fbe4 | bellard | /* NOP */
|
628 | 9a64fbe4 | bellard | return;
|
629 | 79aceca5 | bellard | } |
630 | 79aceca5 | bellard | gen_op_load_gpr_T0(rS(ctx->opcode)); |
631 | 9a64fbe4 | bellard | if (uimm != 0) |
632 | 79aceca5 | bellard | gen_op_ori(uimm << 16);
|
633 | 79aceca5 | bellard | gen_op_store_T0_gpr(rA(ctx->opcode)); |
634 | 79aceca5 | bellard | } |
635 | 79aceca5 | bellard | /* xori */
|
636 | 79aceca5 | bellard | GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
637 | 79aceca5 | bellard | { |
638 | 9a64fbe4 | bellard | uint32_t uimm = UIMM(ctx->opcode); |
639 | 9a64fbe4 | bellard | |
640 | 9a64fbe4 | bellard | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { |
641 | 9a64fbe4 | bellard | /* NOP */
|
642 | 9a64fbe4 | bellard | return;
|
643 | 9a64fbe4 | bellard | } |
644 | 79aceca5 | bellard | gen_op_load_gpr_T0(rS(ctx->opcode)); |
645 | 9a64fbe4 | bellard | if (uimm != 0) |
646 | 4b3686fa | bellard | gen_op_xori(uimm); |
647 | 79aceca5 | bellard | gen_op_store_T0_gpr(rA(ctx->opcode)); |
648 | 79aceca5 | bellard | } |
649 | 79aceca5 | bellard | |
650 | 79aceca5 | bellard | /* xoris */
|
651 | 79aceca5 | bellard | GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
652 | 79aceca5 | bellard | { |
653 | 9a64fbe4 | bellard | uint32_t uimm = UIMM(ctx->opcode); |
654 | 9a64fbe4 | bellard | |
655 | 9a64fbe4 | bellard | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { |
656 | 9a64fbe4 | bellard | /* NOP */
|
657 | 9a64fbe4 | bellard | return;
|
658 | 9a64fbe4 | bellard | } |
659 | 79aceca5 | bellard | gen_op_load_gpr_T0(rS(ctx->opcode)); |
660 | 9a64fbe4 | bellard | if (uimm != 0) |
661 | 4b3686fa | bellard | gen_op_xori(uimm << 16);
|
662 | 79aceca5 | bellard | gen_op_store_T0_gpr(rA(ctx->opcode)); |
663 | 79aceca5 | bellard | } |
664 | 79aceca5 | bellard | |
665 | 79aceca5 | bellard | /*** Integer rotate ***/
|
666 | 79aceca5 | bellard | /* rlwimi & rlwimi. */
|
667 | 79aceca5 | bellard | GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
668 | 79aceca5 | bellard | { |
669 | 79aceca5 | bellard | uint32_t mb, me; |
670 | 79aceca5 | bellard | |
671 | 79aceca5 | bellard | mb = MB(ctx->opcode); |
672 | 79aceca5 | bellard | me = ME(ctx->opcode); |
673 | 79aceca5 | bellard | gen_op_load_gpr_T0(rS(ctx->opcode)); |
674 | fb0eaffc | bellard | gen_op_load_gpr_T1(rA(ctx->opcode)); |
675 | 79aceca5 | bellard | gen_op_rlwimi(SH(ctx->opcode), MASK(mb, me), ~MASK(mb, me)); |
676 | 79aceca5 | bellard | if (Rc(ctx->opcode) != 0) |
677 | 79aceca5 | bellard | gen_op_set_Rc0(); |
678 | 79aceca5 | bellard | gen_op_store_T0_gpr(rA(ctx->opcode)); |
679 | 79aceca5 | bellard | } |
680 | 79aceca5 | bellard | /* rlwinm & rlwinm. */
|
681 | 79aceca5 | bellard | GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
682 | 79aceca5 | bellard | { |
683 | 79aceca5 | bellard | uint32_t mb, me, sh; |
684 | 79aceca5 | bellard | |
685 | 79aceca5 | bellard | sh = SH(ctx->opcode); |
686 | 79aceca5 | bellard | mb = MB(ctx->opcode); |
687 | 79aceca5 | bellard | me = ME(ctx->opcode); |
688 | 79aceca5 | bellard | gen_op_load_gpr_T0(rS(ctx->opcode)); |
689 | 4b3686fa | bellard | #if 1 // TRY |
690 | 4b3686fa | bellard | if (sh == 0) { |
691 | 4b3686fa | bellard | gen_op_andi_(MASK(mb, me)); |
692 | 4b3686fa | bellard | goto store;
|
693 | 4b3686fa | bellard | } |
694 | 4b3686fa | bellard | #endif
|
695 | 79aceca5 | bellard | if (mb == 0) { |
696 | 79aceca5 | bellard | if (me == 31) { |
697 | 79aceca5 | bellard | gen_op_rotlwi(sh); |
698 | 79aceca5 | bellard | goto store;
|
699 | 4b3686fa | bellard | #if 0
|
700 | 79aceca5 | bellard | } else if (me == (31 - sh)) {
|
701 | 79aceca5 | bellard | gen_op_slwi(sh);
|
702 | 79aceca5 | bellard | goto store;
|
703 | 4b3686fa | bellard | #endif
|
704 | 79aceca5 | bellard | } |
705 | 79aceca5 | bellard | } else if (me == 31) { |
706 | 4b3686fa | bellard | #if 0
|
707 | 79aceca5 | bellard | if (sh == (32 - mb)) {
|
708 | 79aceca5 | bellard | gen_op_srwi(mb);
|
709 | 79aceca5 | bellard | goto store;
|
710 | 79aceca5 | bellard | }
|
711 | 4b3686fa | bellard | #endif
|
712 | 79aceca5 | bellard | } |
713 | 79aceca5 | bellard | gen_op_rlwinm(sh, MASK(mb, me)); |
714 | 79aceca5 | bellard | store:
|
715 | 79aceca5 | bellard | if (Rc(ctx->opcode) != 0) |
716 | 79aceca5 | bellard | gen_op_set_Rc0(); |
717 | 79aceca5 | bellard | gen_op_store_T0_gpr(rA(ctx->opcode)); |
718 | 79aceca5 | bellard | } |
719 | 79aceca5 | bellard | /* rlwnm & rlwnm. */
|
720 | 79aceca5 | bellard | GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
721 | 79aceca5 | bellard | { |
722 | 79aceca5 | bellard | uint32_t mb, me; |
723 | 79aceca5 | bellard | |
724 | 79aceca5 | bellard | mb = MB(ctx->opcode); |
725 | 79aceca5 | bellard | me = ME(ctx->opcode); |
726 | 79aceca5 | bellard | gen_op_load_gpr_T0(rS(ctx->opcode)); |
727 | 79aceca5 | bellard | gen_op_load_gpr_T1(rB(ctx->opcode)); |
728 | 79aceca5 | bellard | if (mb == 0 && me == 31) { |
729 | 79aceca5 | bellard | gen_op_rotl(); |
730 | 79aceca5 | bellard | } else
|
731 | 79aceca5 | bellard | { |
732 | 79aceca5 | bellard | gen_op_rlwnm(MASK(mb, me)); |
733 | 79aceca5 | bellard | } |
734 | 79aceca5 | bellard | if (Rc(ctx->opcode) != 0) |
735 | 79aceca5 | bellard | gen_op_set_Rc0(); |
736 | 79aceca5 | bellard | gen_op_store_T0_gpr(rA(ctx->opcode)); |
737 | 79aceca5 | bellard | } |
738 | 79aceca5 | bellard | |
739 | 79aceca5 | bellard | /*** Integer shift ***/
|
740 | 79aceca5 | bellard | /* slw & slw. */
|
741 | 79aceca5 | bellard | __GEN_LOGICAL2(slw, 0x18, 0x00); |
742 | 79aceca5 | bellard | /* sraw & sraw. */
|
743 | 79aceca5 | bellard | __GEN_LOGICAL2(sraw, 0x18, 0x18); |
744 | 79aceca5 | bellard | /* srawi & srawi. */
|
745 | 79aceca5 | bellard | GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER) |
746 | 79aceca5 | bellard | { |
747 | 79aceca5 | bellard | gen_op_load_gpr_T0(rS(ctx->opcode)); |
748 | 79aceca5 | bellard | gen_op_srawi(SH(ctx->opcode), MASK(32 - SH(ctx->opcode), 31)); |
749 | 79aceca5 | bellard | if (Rc(ctx->opcode) != 0) |
750 | 79aceca5 | bellard | gen_op_set_Rc0(); |
751 | 79aceca5 | bellard | gen_op_store_T0_gpr(rA(ctx->opcode)); |
752 | 79aceca5 | bellard | } |
753 | 79aceca5 | bellard | /* srw & srw. */
|
754 | 79aceca5 | bellard | __GEN_LOGICAL2(srw, 0x18, 0x10); |
755 | 79aceca5 | bellard | |
756 | 79aceca5 | bellard | /*** Floating-Point arithmetic ***/
|
757 | 9a64fbe4 | bellard | #define _GEN_FLOAT_ACB(name, op1, op2) \
|
758 | 9a64fbe4 | bellard | GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, PPC_FLOAT) \ |
759 | 9a64fbe4 | bellard | { \ |
760 | 9a64fbe4 | bellard | gen_op_reset_scrfx(); \ |
761 | 9a64fbe4 | bellard | gen_op_load_fpr_FT0(rA(ctx->opcode)); \ |
762 | 9a64fbe4 | bellard | gen_op_load_fpr_FT1(rC(ctx->opcode)); \ |
763 | 9a64fbe4 | bellard | gen_op_load_fpr_FT2(rB(ctx->opcode)); \ |
764 | 9a64fbe4 | bellard | gen_op_f##name(); \ |
765 | 9a64fbe4 | bellard | gen_op_store_FT0_fpr(rD(ctx->opcode)); \ |
766 | 9a64fbe4 | bellard | if (Rc(ctx->opcode)) \
|
767 | 9a64fbe4 | bellard | gen_op_set_Rc1(); \ |
768 | 9a64fbe4 | bellard | } |
769 | 9a64fbe4 | bellard | |
770 | 9a64fbe4 | bellard | #define GEN_FLOAT_ACB(name, op2) \
|
771 | 9a64fbe4 | bellard | _GEN_FLOAT_ACB(name, 0x3F, op2); \
|
772 | 9a64fbe4 | bellard | _GEN_FLOAT_ACB(name##s, 0x3B, op2); |
773 | 9a64fbe4 | bellard | |
774 | 9a64fbe4 | bellard | #define _GEN_FLOAT_AB(name, op1, op2, inval) \
|
775 | 9a64fbe4 | bellard | GEN_HANDLER(f##name, op1, op2, 0xFF, inval, PPC_FLOAT) \ |
776 | 9a64fbe4 | bellard | { \ |
777 | 9a64fbe4 | bellard | gen_op_reset_scrfx(); \ |
778 | 9a64fbe4 | bellard | gen_op_load_fpr_FT0(rA(ctx->opcode)); \ |
779 | 9a64fbe4 | bellard | gen_op_load_fpr_FT1(rB(ctx->opcode)); \ |
780 | 9a64fbe4 | bellard | gen_op_f##name(); \ |
781 | 9a64fbe4 | bellard | gen_op_store_FT0_fpr(rD(ctx->opcode)); \ |
782 | 9a64fbe4 | bellard | if (Rc(ctx->opcode)) \
|
783 | 9a64fbe4 | bellard | gen_op_set_Rc1(); \ |
784 | 9a64fbe4 | bellard | } |
785 | 9a64fbe4 | bellard | #define GEN_FLOAT_AB(name, op2, inval) \
|
786 | 9a64fbe4 | bellard | _GEN_FLOAT_AB(name, 0x3F, op2, inval); \
|
787 | 9a64fbe4 | bellard | _GEN_FLOAT_AB(name##s, 0x3B, op2, inval); |
788 | 9a64fbe4 | bellard | |
789 | 9a64fbe4 | bellard | #define _GEN_FLOAT_AC(name, op1, op2, inval) \
|
790 | 9a64fbe4 | bellard | GEN_HANDLER(f##name, op1, op2, 0xFF, inval, PPC_FLOAT) \ |
791 | 9a64fbe4 | bellard | { \ |
792 | 9a64fbe4 | bellard | gen_op_reset_scrfx(); \ |
793 | 9a64fbe4 | bellard | gen_op_load_fpr_FT0(rA(ctx->opcode)); \ |
794 | 9a64fbe4 | bellard | gen_op_load_fpr_FT1(rC(ctx->opcode)); \ |
795 | 9a64fbe4 | bellard | gen_op_f##name(); \ |
796 | 9a64fbe4 | bellard | gen_op_store_FT0_fpr(rD(ctx->opcode)); \ |
797 | 9a64fbe4 | bellard | if (Rc(ctx->opcode)) \
|
798 | 9a64fbe4 | bellard | gen_op_set_Rc1(); \ |
799 | 9a64fbe4 | bellard | } |
800 | 9a64fbe4 | bellard | #define GEN_FLOAT_AC(name, op2, inval) \
|
801 | 9a64fbe4 | bellard | _GEN_FLOAT_AC(name, 0x3F, op2, inval); \
|
802 | 9a64fbe4 | bellard | _GEN_FLOAT_AC(name##s, 0x3B, op2, inval); |
803 | 9a64fbe4 | bellard | |
804 | 9a64fbe4 | bellard | #define GEN_FLOAT_B(name, op2, op3) \
|
805 | 9a64fbe4 | bellard | GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, PPC_FLOAT) \ |
806 | 9a64fbe4 | bellard | { \ |
807 | 9a64fbe4 | bellard | gen_op_reset_scrfx(); \ |
808 | 9a64fbe4 | bellard | gen_op_load_fpr_FT0(rB(ctx->opcode)); \ |
809 | 9a64fbe4 | bellard | gen_op_f##name(); \ |
810 | 9a64fbe4 | bellard | gen_op_store_FT0_fpr(rD(ctx->opcode)); \ |
811 | 9a64fbe4 | bellard | if (Rc(ctx->opcode)) \
|
812 | 9a64fbe4 | bellard | gen_op_set_Rc1(); \ |
813 | 79aceca5 | bellard | } |
814 | 79aceca5 | bellard | |
815 | 9a64fbe4 | bellard | #define GEN_FLOAT_BS(name, op2) \
|
816 | 9a64fbe4 | bellard | GEN_HANDLER(f##name, 0x3F, op2, 0xFF, 0x001F07C0, PPC_FLOAT) \ |
817 | 9a64fbe4 | bellard | { \ |
818 | 9a64fbe4 | bellard | gen_op_reset_scrfx(); \ |
819 | 9a64fbe4 | bellard | gen_op_load_fpr_FT0(rB(ctx->opcode)); \ |
820 | 9a64fbe4 | bellard | gen_op_f##name(); \ |
821 | 9a64fbe4 | bellard | gen_op_store_FT0_fpr(rD(ctx->opcode)); \ |
822 | 9a64fbe4 | bellard | if (Rc(ctx->opcode)) \
|
823 | 9a64fbe4 | bellard | gen_op_set_Rc1(); \ |
824 | 79aceca5 | bellard | } |
825 | 79aceca5 | bellard | |
826 | 9a64fbe4 | bellard | /* fadd - fadds */
|
827 | 9a64fbe4 | bellard | GEN_FLOAT_AB(add, 0x15, 0x000007C0); |
828 | 79aceca5 | bellard | /* fdiv */
|
829 | 9a64fbe4 | bellard | GEN_FLOAT_AB(div, 0x12, 0x000007C0); |
830 | 79aceca5 | bellard | /* fmul */
|
831 | 9a64fbe4 | bellard | GEN_FLOAT_AC(mul, 0x19, 0x0000F800); |
832 | 79aceca5 | bellard | |
833 | 79aceca5 | bellard | /* fres */
|
834 | 9a64fbe4 | bellard | GEN_FLOAT_BS(res, 0x18);
|
835 | 79aceca5 | bellard | |
836 | 79aceca5 | bellard | /* frsqrte */
|
837 | 9a64fbe4 | bellard | GEN_FLOAT_BS(rsqrte, 0x1A);
|
838 | 79aceca5 | bellard | |
839 | 79aceca5 | bellard | /* fsel */
|
840 | 9a64fbe4 | bellard | _GEN_FLOAT_ACB(sel, 0x3F, 0x17); |
841 | 79aceca5 | bellard | /* fsub */
|
842 | 9a64fbe4 | bellard | GEN_FLOAT_AB(sub, 0x14, 0x000007C0); |
843 | 79aceca5 | bellard | /* Optional: */
|
844 | 79aceca5 | bellard | /* fsqrt */
|
845 | 9a64fbe4 | bellard | GEN_FLOAT_BS(sqrt, 0x16);
|
846 | 79aceca5 | bellard | |
847 | 9a64fbe4 | bellard | GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_OPT) |
848 | 79aceca5 | bellard | { |
849 | 9a64fbe4 | bellard | gen_op_reset_scrfx(); |
850 | 9a64fbe4 | bellard | gen_op_load_fpr_FT0(rB(ctx->opcode)); |
851 | 9a64fbe4 | bellard | gen_op_fsqrts(); |
852 | 9a64fbe4 | bellard | gen_op_store_FT0_fpr(rD(ctx->opcode)); |
853 | 9a64fbe4 | bellard | if (Rc(ctx->opcode))
|
854 | 9a64fbe4 | bellard | gen_op_set_Rc1(); |
855 | 79aceca5 | bellard | } |
856 | 79aceca5 | bellard | |
857 | 79aceca5 | bellard | /*** Floating-Point multiply-and-add ***/
|
858 | 79aceca5 | bellard | /* fmadd */
|
859 | 9a64fbe4 | bellard | GEN_FLOAT_ACB(madd, 0x1D);
|
860 | 79aceca5 | bellard | /* fmsub */
|
861 | 9a64fbe4 | bellard | GEN_FLOAT_ACB(msub, 0x1C);
|
862 | 79aceca5 | bellard | /* fnmadd */
|
863 | 9a64fbe4 | bellard | GEN_FLOAT_ACB(nmadd, 0x1F);
|
864 | 79aceca5 | bellard | /* fnmsub */
|
865 | 9a64fbe4 | bellard | GEN_FLOAT_ACB(nmsub, 0x1E);
|
866 | 79aceca5 | bellard | |
867 | 79aceca5 | bellard | /*** Floating-Point round & convert ***/
|
868 | 79aceca5 | bellard | /* fctiw */
|
869 | 9a64fbe4 | bellard | GEN_FLOAT_B(ctiw, 0x0E, 0x00); |
870 | 79aceca5 | bellard | /* fctiwz */
|
871 | 9a64fbe4 | bellard | GEN_FLOAT_B(ctiwz, 0x0F, 0x00); |
872 | 79aceca5 | bellard | /* frsp */
|
873 | 9a64fbe4 | bellard | GEN_FLOAT_B(rsp, 0x0C, 0x00); |
874 | 79aceca5 | bellard | |
875 | 79aceca5 | bellard | /*** Floating-Point compare ***/
|
876 | 79aceca5 | bellard | /* fcmpo */
|
877 | 79aceca5 | bellard | GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT) |
878 | 79aceca5 | bellard | { |
879 | 9a64fbe4 | bellard | gen_op_reset_scrfx(); |
880 | 9a64fbe4 | bellard | gen_op_load_fpr_FT0(rA(ctx->opcode)); |
881 | 9a64fbe4 | bellard | gen_op_load_fpr_FT1(rB(ctx->opcode)); |
882 | 9a64fbe4 | bellard | gen_op_fcmpo(); |
883 | 9a64fbe4 | bellard | gen_op_store_T0_crf(crfD(ctx->opcode)); |
884 | 79aceca5 | bellard | } |
885 | 79aceca5 | bellard | |
886 | 79aceca5 | bellard | /* fcmpu */
|
887 | 79aceca5 | bellard | GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT) |
888 | 79aceca5 | bellard | { |
889 | 9a64fbe4 | bellard | gen_op_reset_scrfx(); |
890 | 9a64fbe4 | bellard | gen_op_load_fpr_FT0(rA(ctx->opcode)); |
891 | 9a64fbe4 | bellard | gen_op_load_fpr_FT1(rB(ctx->opcode)); |
892 | 9a64fbe4 | bellard | gen_op_fcmpu(); |
893 | 9a64fbe4 | bellard | gen_op_store_T0_crf(crfD(ctx->opcode)); |
894 | 79aceca5 | bellard | } |
895 | 79aceca5 | bellard | |
896 | 9a64fbe4 | bellard | /*** Floating-point move ***/
|
897 | 9a64fbe4 | bellard | /* fabs */
|
898 | 9a64fbe4 | bellard | GEN_FLOAT_B(abs, 0x08, 0x08); |
899 | 9a64fbe4 | bellard | |
900 | 9a64fbe4 | bellard | /* fmr - fmr. */
|
901 | 9a64fbe4 | bellard | GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT) |
902 | 9a64fbe4 | bellard | { |
903 | 9a64fbe4 | bellard | gen_op_reset_scrfx(); |
904 | 9a64fbe4 | bellard | gen_op_load_fpr_FT0(rB(ctx->opcode)); |
905 | 9a64fbe4 | bellard | gen_op_store_FT0_fpr(rD(ctx->opcode)); |
906 | 9a64fbe4 | bellard | if (Rc(ctx->opcode))
|
907 | 9a64fbe4 | bellard | gen_op_set_Rc1(); |
908 | 9a64fbe4 | bellard | } |
909 | 9a64fbe4 | bellard | |
910 | 9a64fbe4 | bellard | /* fnabs */
|
911 | 9a64fbe4 | bellard | GEN_FLOAT_B(nabs, 0x08, 0x04); |
912 | 9a64fbe4 | bellard | /* fneg */
|
913 | 9a64fbe4 | bellard | GEN_FLOAT_B(neg, 0x08, 0x01); |
914 | 9a64fbe4 | bellard | |
915 | 79aceca5 | bellard | /*** Floating-Point status & ctrl register ***/
|
916 | 79aceca5 | bellard | /* mcrfs */
|
917 | 79aceca5 | bellard | GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT) |
918 | 79aceca5 | bellard | { |
919 | fb0eaffc | bellard | gen_op_load_fpscr_T0(crfS(ctx->opcode)); |
920 | fb0eaffc | bellard | gen_op_store_T0_crf(crfD(ctx->opcode)); |
921 | fb0eaffc | bellard | gen_op_clear_fpscr(crfS(ctx->opcode)); |
922 | 79aceca5 | bellard | } |
923 | 79aceca5 | bellard | |
924 | 79aceca5 | bellard | /* mffs */
|
925 | 79aceca5 | bellard | GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT) |
926 | 79aceca5 | bellard | { |
927 | 28b6751f | bellard | gen_op_load_fpscr(); |
928 | fb0eaffc | bellard | gen_op_store_FT0_fpr(rD(ctx->opcode)); |
929 | fb0eaffc | bellard | if (Rc(ctx->opcode))
|
930 | fb0eaffc | bellard | gen_op_set_Rc1(); |
931 | 79aceca5 | bellard | } |
932 | 79aceca5 | bellard | |
933 | 79aceca5 | bellard | /* mtfsb0 */
|
934 | 79aceca5 | bellard | GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT) |
935 | 79aceca5 | bellard | { |
936 | fb0eaffc | bellard | uint8_t crb; |
937 | fb0eaffc | bellard | |
938 | fb0eaffc | bellard | crb = crbD(ctx->opcode) >> 2;
|
939 | fb0eaffc | bellard | gen_op_load_fpscr_T0(crb); |
940 | fb0eaffc | bellard | gen_op_andi_(~(1 << (crbD(ctx->opcode) & 0x03))); |
941 | fb0eaffc | bellard | gen_op_store_T0_fpscr(crb); |
942 | fb0eaffc | bellard | if (Rc(ctx->opcode))
|
943 | fb0eaffc | bellard | gen_op_set_Rc1(); |
944 | 79aceca5 | bellard | } |
945 | 79aceca5 | bellard | |
946 | 79aceca5 | bellard | /* mtfsb1 */
|
947 | 79aceca5 | bellard | GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT) |
948 | 79aceca5 | bellard | { |
949 | fb0eaffc | bellard | uint8_t crb; |
950 | fb0eaffc | bellard | |
951 | fb0eaffc | bellard | crb = crbD(ctx->opcode) >> 2;
|
952 | fb0eaffc | bellard | gen_op_load_fpscr_T0(crb); |
953 | fb0eaffc | bellard | gen_op_ori(1 << (crbD(ctx->opcode) & 0x03)); |
954 | fb0eaffc | bellard | gen_op_store_T0_fpscr(crb); |
955 | fb0eaffc | bellard | if (Rc(ctx->opcode))
|
956 | fb0eaffc | bellard | gen_op_set_Rc1(); |
957 | 79aceca5 | bellard | } |
958 | 79aceca5 | bellard | |
959 | 79aceca5 | bellard | /* mtfsf */
|
960 | 79aceca5 | bellard | GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT) |
961 | 79aceca5 | bellard | { |
962 | fb0eaffc | bellard | gen_op_load_fpr_FT0(rB(ctx->opcode)); |
963 | 28b6751f | bellard | gen_op_store_fpscr(FM(ctx->opcode)); |
964 | fb0eaffc | bellard | if (Rc(ctx->opcode))
|
965 | fb0eaffc | bellard | gen_op_set_Rc1(); |
966 | 79aceca5 | bellard | } |
967 | 79aceca5 | bellard | |
968 | 79aceca5 | bellard | /* mtfsfi */
|
969 | 79aceca5 | bellard | GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT) |
970 | 79aceca5 | bellard | { |
971 | fb0eaffc | bellard | gen_op_store_T0_fpscri(crbD(ctx->opcode) >> 2, FPIMM(ctx->opcode));
|
972 | fb0eaffc | bellard | if (Rc(ctx->opcode))
|
973 | fb0eaffc | bellard | gen_op_set_Rc1(); |
974 | 79aceca5 | bellard | } |
975 | 79aceca5 | bellard | |
976 | 79aceca5 | bellard | /*** Integer load ***/
|
977 | 9a64fbe4 | bellard | #if defined(CONFIG_USER_ONLY)
|
978 | 9a64fbe4 | bellard | #define op_ldst(name) gen_op_##name##_raw() |
979 | 9a64fbe4 | bellard | #define OP_LD_TABLE(width)
|
980 | 9a64fbe4 | bellard | #define OP_ST_TABLE(width)
|
981 | 9a64fbe4 | bellard | #else
|
982 | 9a64fbe4 | bellard | #define op_ldst(name) (*gen_op_##name[ctx->mem_idx])() |
983 | 9a64fbe4 | bellard | #define OP_LD_TABLE(width) \
|
984 | 9a64fbe4 | bellard | static GenOpFunc *gen_op_l##width[] = { \ |
985 | 9a64fbe4 | bellard | &gen_op_l##width##_user, \ |
986 | 9a64fbe4 | bellard | &gen_op_l##width##_kernel, \ |
987 | 9a64fbe4 | bellard | } |
988 | 9a64fbe4 | bellard | #define OP_ST_TABLE(width) \
|
989 | 9a64fbe4 | bellard | static GenOpFunc *gen_op_st##width[] = { \ |
990 | 9a64fbe4 | bellard | &gen_op_st##width##_user, \ |
991 | 9a64fbe4 | bellard | &gen_op_st##width##_kernel, \ |
992 | 9a64fbe4 | bellard | } |
993 | 9a64fbe4 | bellard | #endif
|
994 | 9a64fbe4 | bellard | |
995 | 9a64fbe4 | bellard | #define GEN_LD(width, opc) \
|
996 | 79aceca5 | bellard | GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \ |
997 | 79aceca5 | bellard | { \ |
998 | 79aceca5 | bellard | uint32_t simm = SIMM(ctx->opcode); \ |
999 | 79aceca5 | bellard | if (rA(ctx->opcode) == 0) { \ |
1000 | 9a64fbe4 | bellard | gen_op_set_T0(simm); \ |
1001 | 79aceca5 | bellard | } else { \
|
1002 | 79aceca5 | bellard | gen_op_load_gpr_T0(rA(ctx->opcode)); \ |
1003 | 9a64fbe4 | bellard | if (simm != 0) \ |
1004 | 9a64fbe4 | bellard | gen_op_addi(simm); \ |
1005 | 79aceca5 | bellard | } \ |
1006 | 9a64fbe4 | bellard | op_ldst(l##width); \ |
1007 | 79aceca5 | bellard | gen_op_store_T1_gpr(rD(ctx->opcode)); \ |
1008 | 79aceca5 | bellard | } |
1009 | 79aceca5 | bellard | |
1010 | 9a64fbe4 | bellard | #define GEN_LDU(width, opc) \
|
1011 | 79aceca5 | bellard | GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \ |
1012 | 79aceca5 | bellard | { \ |
1013 | 9a64fbe4 | bellard | uint32_t simm = SIMM(ctx->opcode); \ |
1014 | 79aceca5 | bellard | if (rA(ctx->opcode) == 0 || \ |
1015 | 9a64fbe4 | bellard | rA(ctx->opcode) == rD(ctx->opcode)) { \ |
1016 | 9fddaa0c | bellard | RET_INVAL(ctx); \ |
1017 | 9fddaa0c | bellard | return; \
|
1018 | 9a64fbe4 | bellard | } \ |
1019 | 79aceca5 | bellard | gen_op_load_gpr_T0(rA(ctx->opcode)); \ |
1020 | 9a64fbe4 | bellard | if (simm != 0) \ |
1021 | 9a64fbe4 | bellard | gen_op_addi(simm); \ |
1022 | 9a64fbe4 | bellard | op_ldst(l##width); \ |
1023 | 79aceca5 | bellard | gen_op_store_T1_gpr(rD(ctx->opcode)); \ |
1024 | 79aceca5 | bellard | gen_op_store_T0_gpr(rA(ctx->opcode)); \ |
1025 | 79aceca5 | bellard | } |
1026 | 79aceca5 | bellard | |
1027 | 9a64fbe4 | bellard | #define GEN_LDUX(width, opc) \
|
1028 | 79aceca5 | bellard | GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_INTEGER) \ |
1029 | 79aceca5 | bellard | { \ |
1030 | 79aceca5 | bellard | if (rA(ctx->opcode) == 0 || \ |
1031 | 9a64fbe4 | bellard | rA(ctx->opcode) == rD(ctx->opcode)) { \ |
1032 | 9fddaa0c | bellard | RET_INVAL(ctx); \ |
1033 | 9fddaa0c | bellard | return; \
|
1034 | 9a64fbe4 | bellard | } \ |
1035 | 79aceca5 | bellard | gen_op_load_gpr_T0(rA(ctx->opcode)); \ |
1036 | 79aceca5 | bellard | gen_op_load_gpr_T1(rB(ctx->opcode)); \ |
1037 | 9a64fbe4 | bellard | gen_op_add(); \ |
1038 | 9a64fbe4 | bellard | op_ldst(l##width); \ |
1039 | 79aceca5 | bellard | gen_op_store_T1_gpr(rD(ctx->opcode)); \ |
1040 | 79aceca5 | bellard | gen_op_store_T0_gpr(rA(ctx->opcode)); \ |
1041 | 79aceca5 | bellard | } |
1042 | 79aceca5 | bellard | |
1043 | 9a64fbe4 | bellard | #define GEN_LDX(width, opc2, opc3) \
|
1044 | 79aceca5 | bellard | GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_INTEGER) \ |
1045 | 79aceca5 | bellard | { \ |
1046 | 79aceca5 | bellard | if (rA(ctx->opcode) == 0) { \ |
1047 | 79aceca5 | bellard | gen_op_load_gpr_T0(rB(ctx->opcode)); \ |
1048 | 79aceca5 | bellard | } else { \
|
1049 | 79aceca5 | bellard | gen_op_load_gpr_T0(rA(ctx->opcode)); \ |
1050 | 79aceca5 | bellard | gen_op_load_gpr_T1(rB(ctx->opcode)); \ |
1051 | 9a64fbe4 | bellard | gen_op_add(); \ |
1052 | 79aceca5 | bellard | } \ |
1053 | 9a64fbe4 | bellard | op_ldst(l##width); \ |
1054 | 79aceca5 | bellard | gen_op_store_T1_gpr(rD(ctx->opcode)); \ |
1055 | 79aceca5 | bellard | } |
1056 | 79aceca5 | bellard | |
1057 | 9a64fbe4 | bellard | #define GEN_LDS(width, op) \
|
1058 | 9a64fbe4 | bellard | OP_LD_TABLE(width); \ |
1059 | 9a64fbe4 | bellard | GEN_LD(width, op | 0x20); \
|
1060 | 9a64fbe4 | bellard | GEN_LDU(width, op | 0x21); \
|
1061 | 9a64fbe4 | bellard | GEN_LDUX(width, op | 0x01); \
|
1062 | 9a64fbe4 | bellard | GEN_LDX(width, 0x17, op | 0x00) |
1063 | 79aceca5 | bellard | |
1064 | 79aceca5 | bellard | /* lbz lbzu lbzux lbzx */
|
1065 | 9a64fbe4 | bellard | GEN_LDS(bz, 0x02);
|
1066 | 79aceca5 | bellard | /* lha lhau lhaux lhax */
|
1067 | 9a64fbe4 | bellard | GEN_LDS(ha, 0x0A);
|
1068 | 79aceca5 | bellard | /* lhz lhzu lhzux lhzx */
|
1069 | 9a64fbe4 | bellard | GEN_LDS(hz, 0x08);
|
1070 | 79aceca5 | bellard | /* lwz lwzu lwzux lwzx */
|
1071 | 9a64fbe4 | bellard | GEN_LDS(wz, 0x00);
|
1072 | 79aceca5 | bellard | |
1073 | 79aceca5 | bellard | /*** Integer store ***/
|
1074 | 9a64fbe4 | bellard | #define GEN_ST(width, opc) \
|
1075 | 79aceca5 | bellard | GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \ |
1076 | 79aceca5 | bellard | { \ |
1077 | 79aceca5 | bellard | uint32_t simm = SIMM(ctx->opcode); \ |
1078 | 79aceca5 | bellard | if (rA(ctx->opcode) == 0) { \ |
1079 | 9a64fbe4 | bellard | gen_op_set_T0(simm); \ |
1080 | 79aceca5 | bellard | } else { \
|
1081 | 79aceca5 | bellard | gen_op_load_gpr_T0(rA(ctx->opcode)); \ |
1082 | 9a64fbe4 | bellard | if (simm != 0) \ |
1083 | 9a64fbe4 | bellard | gen_op_addi(simm); \ |
1084 | 79aceca5 | bellard | } \ |
1085 | 9a64fbe4 | bellard | gen_op_load_gpr_T1(rS(ctx->opcode)); \ |
1086 | 9a64fbe4 | bellard | op_ldst(st##width); \ |
1087 | 79aceca5 | bellard | } |
1088 | 79aceca5 | bellard | |
1089 | 9a64fbe4 | bellard | #define GEN_STU(width, opc) \
|
1090 | 79aceca5 | bellard | GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \ |
1091 | 79aceca5 | bellard | { \ |
1092 | 9a64fbe4 | bellard | uint32_t simm = SIMM(ctx->opcode); \ |
1093 | 9a64fbe4 | bellard | if (rA(ctx->opcode) == 0) { \ |
1094 | 9fddaa0c | bellard | RET_INVAL(ctx); \ |
1095 | 9fddaa0c | bellard | return; \
|
1096 | 9a64fbe4 | bellard | } \ |
1097 | 79aceca5 | bellard | gen_op_load_gpr_T0(rA(ctx->opcode)); \ |
1098 | 9a64fbe4 | bellard | if (simm != 0) \ |
1099 | 9a64fbe4 | bellard | gen_op_addi(simm); \ |
1100 | 79aceca5 | bellard | gen_op_load_gpr_T1(rS(ctx->opcode)); \ |
1101 | 9a64fbe4 | bellard | op_ldst(st##width); \ |
1102 | 79aceca5 | bellard | gen_op_store_T0_gpr(rA(ctx->opcode)); \ |
1103 | 79aceca5 | bellard | } |
1104 | 79aceca5 | bellard | |
1105 | 9a64fbe4 | bellard | #define GEN_STUX(width, opc) \
|
1106 | 79aceca5 | bellard | GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_INTEGER) \ |
1107 | 79aceca5 | bellard | { \ |
1108 | 9a64fbe4 | bellard | if (rA(ctx->opcode) == 0) { \ |
1109 | 9fddaa0c | bellard | RET_INVAL(ctx); \ |
1110 | 9fddaa0c | bellard | return; \
|
1111 | 9a64fbe4 | bellard | } \ |
1112 | 79aceca5 | bellard | gen_op_load_gpr_T0(rA(ctx->opcode)); \ |
1113 | 79aceca5 | bellard | gen_op_load_gpr_T1(rB(ctx->opcode)); \ |
1114 | 9a64fbe4 | bellard | gen_op_add(); \ |
1115 | 9a64fbe4 | bellard | gen_op_load_gpr_T1(rS(ctx->opcode)); \ |
1116 | 9a64fbe4 | bellard | op_ldst(st##width); \ |
1117 | 79aceca5 | bellard | gen_op_store_T0_gpr(rA(ctx->opcode)); \ |
1118 | 79aceca5 | bellard | } |
1119 | 79aceca5 | bellard | |
1120 | 9a64fbe4 | bellard | #define GEN_STX(width, opc2, opc3) \
|
1121 | 79aceca5 | bellard | GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_INTEGER) \ |
1122 | 79aceca5 | bellard | { \ |
1123 | 79aceca5 | bellard | if (rA(ctx->opcode) == 0) { \ |
1124 | 79aceca5 | bellard | gen_op_load_gpr_T0(rB(ctx->opcode)); \ |
1125 | 79aceca5 | bellard | } else { \
|
1126 | 79aceca5 | bellard | gen_op_load_gpr_T0(rA(ctx->opcode)); \ |
1127 | 79aceca5 | bellard | gen_op_load_gpr_T1(rB(ctx->opcode)); \ |
1128 | 9a64fbe4 | bellard | gen_op_add(); \ |
1129 | 79aceca5 | bellard | } \ |
1130 | 9a64fbe4 | bellard | gen_op_load_gpr_T1(rS(ctx->opcode)); \ |
1131 | 9a64fbe4 | bellard | op_ldst(st##width); \ |
1132 | 79aceca5 | bellard | } |
1133 | 79aceca5 | bellard | |
1134 | 9a64fbe4 | bellard | #define GEN_STS(width, op) \
|
1135 | 9a64fbe4 | bellard | OP_ST_TABLE(width); \ |
1136 | 9a64fbe4 | bellard | GEN_ST(width, op | 0x20); \
|
1137 | 9a64fbe4 | bellard | GEN_STU(width, op | 0x21); \
|
1138 | 9a64fbe4 | bellard | GEN_STUX(width, op | 0x01); \
|
1139 | 9a64fbe4 | bellard | GEN_STX(width, 0x17, op | 0x00) |
1140 | 79aceca5 | bellard | |
1141 | 79aceca5 | bellard | /* stb stbu stbux stbx */
|
1142 | 9a64fbe4 | bellard | GEN_STS(b, 0x06);
|
1143 | 79aceca5 | bellard | /* sth sthu sthux sthx */
|
1144 | 9a64fbe4 | bellard | GEN_STS(h, 0x0C);
|
1145 | 79aceca5 | bellard | /* stw stwu stwux stwx */
|
1146 | 9a64fbe4 | bellard | GEN_STS(w, 0x04);
|
1147 | 79aceca5 | bellard | |
1148 | 79aceca5 | bellard | /*** Integer load and store with byte reverse ***/
|
1149 | 79aceca5 | bellard | /* lhbrx */
|
1150 | 9a64fbe4 | bellard | OP_LD_TABLE(hbr); |
1151 | 9a64fbe4 | bellard | GEN_LDX(hbr, 0x16, 0x18); |
1152 | 79aceca5 | bellard | /* lwbrx */
|
1153 | 9a64fbe4 | bellard | OP_LD_TABLE(wbr); |
1154 | 9a64fbe4 | bellard | GEN_LDX(wbr, 0x16, 0x10); |
1155 | 79aceca5 | bellard | /* sthbrx */
|
1156 | 9a64fbe4 | bellard | OP_ST_TABLE(hbr); |
1157 | 9a64fbe4 | bellard | GEN_STX(hbr, 0x16, 0x1C); |
1158 | 79aceca5 | bellard | /* stwbrx */
|
1159 | 9a64fbe4 | bellard | OP_ST_TABLE(wbr); |
1160 | 9a64fbe4 | bellard | GEN_STX(wbr, 0x16, 0x14); |
1161 | 79aceca5 | bellard | |
1162 | 79aceca5 | bellard | /*** Integer load and store multiple ***/
|
1163 | 9a64fbe4 | bellard | #if defined(CONFIG_USER_ONLY)
|
1164 | 9a64fbe4 | bellard | #define op_ldstm(name, reg) gen_op_##name##_raw(reg) |
1165 | 9a64fbe4 | bellard | #else
|
1166 | 9a64fbe4 | bellard | #define op_ldstm(name, reg) (*gen_op_##name[ctx->mem_idx])(reg) |
1167 | 9a64fbe4 | bellard | static GenOpFunc1 *gen_op_lmw[] = {
|
1168 | 9a64fbe4 | bellard | &gen_op_lmw_user, |
1169 | 9a64fbe4 | bellard | &gen_op_lmw_kernel, |
1170 | 9a64fbe4 | bellard | }; |
1171 | 9a64fbe4 | bellard | static GenOpFunc1 *gen_op_stmw[] = {
|
1172 | 9a64fbe4 | bellard | &gen_op_stmw_user, |
1173 | 9a64fbe4 | bellard | &gen_op_stmw_kernel, |
1174 | 9a64fbe4 | bellard | }; |
1175 | 9a64fbe4 | bellard | #endif
|
1176 | 9a64fbe4 | bellard | |
1177 | 79aceca5 | bellard | /* lmw */
|
1178 | 79aceca5 | bellard | GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
1179 | 79aceca5 | bellard | { |
1180 | 9a64fbe4 | bellard | int simm = SIMM(ctx->opcode);
|
1181 | 9a64fbe4 | bellard | |
1182 | 79aceca5 | bellard | if (rA(ctx->opcode) == 0) { |
1183 | 9a64fbe4 | bellard | gen_op_set_T0(simm); |
1184 | 79aceca5 | bellard | } else {
|
1185 | 79aceca5 | bellard | gen_op_load_gpr_T0(rA(ctx->opcode)); |
1186 | 9a64fbe4 | bellard | if (simm != 0) |
1187 | 9a64fbe4 | bellard | gen_op_addi(simm); |
1188 | 79aceca5 | bellard | } |
1189 | 9a64fbe4 | bellard | op_ldstm(lmw, rD(ctx->opcode)); |
1190 | 79aceca5 | bellard | } |
1191 | 79aceca5 | bellard | |
1192 | 79aceca5 | bellard | /* stmw */
|
1193 | 79aceca5 | bellard | GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
1194 | 79aceca5 | bellard | { |
1195 | 9a64fbe4 | bellard | int simm = SIMM(ctx->opcode);
|
1196 | 9a64fbe4 | bellard | |
1197 | 79aceca5 | bellard | if (rA(ctx->opcode) == 0) { |
1198 | 9a64fbe4 | bellard | gen_op_set_T0(simm); |
1199 | 79aceca5 | bellard | } else {
|
1200 | 79aceca5 | bellard | gen_op_load_gpr_T0(rA(ctx->opcode)); |
1201 | 9a64fbe4 | bellard | if (simm != 0) |
1202 | 9a64fbe4 | bellard | gen_op_addi(simm); |
1203 | 79aceca5 | bellard | } |
1204 | 9a64fbe4 | bellard | op_ldstm(stmw, rS(ctx->opcode)); |
1205 | 79aceca5 | bellard | } |
1206 | 79aceca5 | bellard | |
1207 | 79aceca5 | bellard | /*** Integer load and store strings ***/
|
1208 | 9a64fbe4 | bellard | #if defined(CONFIG_USER_ONLY)
|
1209 | 9a64fbe4 | bellard | #define op_ldsts(name, start) gen_op_##name##_raw(start) |
1210 | 9a64fbe4 | bellard | #define op_ldstsx(name, rd, ra, rb) gen_op_##name##_raw(rd, ra, rb) |
1211 | 9a64fbe4 | bellard | #else
|
1212 | 9a64fbe4 | bellard | #define op_ldsts(name, start) (*gen_op_##name[ctx->mem_idx])(start) |
1213 | 9a64fbe4 | bellard | #define op_ldstsx(name, rd, ra, rb) (*gen_op_##name[ctx->mem_idx])(rd, ra, rb) |
1214 | 9a64fbe4 | bellard | static GenOpFunc1 *gen_op_lswi[] = {
|
1215 | 9a64fbe4 | bellard | &gen_op_lswi_user, |
1216 | 9a64fbe4 | bellard | &gen_op_lswi_kernel, |
1217 | 9a64fbe4 | bellard | }; |
1218 | 9a64fbe4 | bellard | static GenOpFunc3 *gen_op_lswx[] = {
|
1219 | 9a64fbe4 | bellard | &gen_op_lswx_user, |
1220 | 9a64fbe4 | bellard | &gen_op_lswx_kernel, |
1221 | 9a64fbe4 | bellard | }; |
1222 | 9a64fbe4 | bellard | static GenOpFunc1 *gen_op_stsw[] = {
|
1223 | 9a64fbe4 | bellard | &gen_op_stsw_user, |
1224 | 9a64fbe4 | bellard | &gen_op_stsw_kernel, |
1225 | 9a64fbe4 | bellard | }; |
1226 | 9a64fbe4 | bellard | #endif
|
1227 | 9a64fbe4 | bellard | |
1228 | 79aceca5 | bellard | /* lswi */
|
1229 | 9a64fbe4 | bellard | /* PPC32 specification says we must generate an exception if
|
1230 | 9a64fbe4 | bellard | * rA is in the range of registers to be loaded.
|
1231 | 9a64fbe4 | bellard | * In an other hand, IBM says this is valid, but rA won't be loaded.
|
1232 | 9a64fbe4 | bellard | * For now, I'll follow the spec...
|
1233 | 9a64fbe4 | bellard | */
|
1234 | 79aceca5 | bellard | GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_INTEGER) |
1235 | 79aceca5 | bellard | { |
1236 | 79aceca5 | bellard | int nb = NB(ctx->opcode);
|
1237 | 79aceca5 | bellard | int start = rD(ctx->opcode);
|
1238 | 9a64fbe4 | bellard | int ra = rA(ctx->opcode);
|
1239 | 79aceca5 | bellard | int nr;
|
1240 | 79aceca5 | bellard | |
1241 | 79aceca5 | bellard | if (nb == 0) |
1242 | 79aceca5 | bellard | nb = 32;
|
1243 | 79aceca5 | bellard | nr = nb / 4;
|
1244 | 297d8e62 | bellard | if (((start + nr) > 32 && start <= ra && (start + nr - 32) > ra) || |
1245 | 297d8e62 | bellard | ((start + nr) <= 32 && start <= ra && (start + nr) > ra)) {
|
1246 | 9fddaa0c | bellard | RET_EXCP(ctx, EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_LSWX); |
1247 | 9fddaa0c | bellard | return;
|
1248 | 297d8e62 | bellard | } |
1249 | 9a64fbe4 | bellard | if (ra == 0) { |
1250 | 79aceca5 | bellard | gen_op_set_T0(0);
|
1251 | 79aceca5 | bellard | } else {
|
1252 | 9a64fbe4 | bellard | gen_op_load_gpr_T0(ra); |
1253 | 79aceca5 | bellard | } |
1254 | 9a64fbe4 | bellard | gen_op_set_T1(nb); |
1255 | 9a64fbe4 | bellard | op_ldsts(lswi, start); |
1256 | 79aceca5 | bellard | } |
1257 | 79aceca5 | bellard | |
1258 | 79aceca5 | bellard | /* lswx */
|
1259 | 79aceca5 | bellard | GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_INTEGER) |
1260 | 79aceca5 | bellard | { |
1261 | 9a64fbe4 | bellard | int ra = rA(ctx->opcode);
|
1262 | 9a64fbe4 | bellard | int rb = rB(ctx->opcode);
|
1263 | 9a64fbe4 | bellard | |
1264 | 9a64fbe4 | bellard | if (ra == 0) { |
1265 | 9a64fbe4 | bellard | gen_op_load_gpr_T0(rb); |
1266 | 9a64fbe4 | bellard | ra = rb; |
1267 | 79aceca5 | bellard | } else {
|
1268 | 9a64fbe4 | bellard | gen_op_load_gpr_T0(ra); |
1269 | 9a64fbe4 | bellard | gen_op_load_gpr_T1(rb); |
1270 | 9a64fbe4 | bellard | gen_op_add(); |
1271 | 79aceca5 | bellard | } |
1272 | 9a64fbe4 | bellard | gen_op_load_xer_bc(); |
1273 | 9a64fbe4 | bellard | op_ldstsx(lswx, rD(ctx->opcode), ra, rb); |
1274 | 79aceca5 | bellard | } |
1275 | 79aceca5 | bellard | |
1276 | 79aceca5 | bellard | /* stswi */
|
1277 | 79aceca5 | bellard | GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_INTEGER) |
1278 | 79aceca5 | bellard | { |
1279 | 4b3686fa | bellard | int nb = NB(ctx->opcode);
|
1280 | 4b3686fa | bellard | |
1281 | 79aceca5 | bellard | if (rA(ctx->opcode) == 0) { |
1282 | 79aceca5 | bellard | gen_op_set_T0(0);
|
1283 | 79aceca5 | bellard | } else {
|
1284 | 79aceca5 | bellard | gen_op_load_gpr_T0(rA(ctx->opcode)); |
1285 | 79aceca5 | bellard | } |
1286 | 4b3686fa | bellard | if (nb == 0) |
1287 | 4b3686fa | bellard | nb = 32;
|
1288 | 4b3686fa | bellard | gen_op_set_T1(nb); |
1289 | 9a64fbe4 | bellard | op_ldsts(stsw, rS(ctx->opcode)); |
1290 | 79aceca5 | bellard | } |
1291 | 79aceca5 | bellard | |
1292 | 79aceca5 | bellard | /* stswx */
|
1293 | 79aceca5 | bellard | GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_INTEGER) |
1294 | 79aceca5 | bellard | { |
1295 | 9a64fbe4 | bellard | int ra = rA(ctx->opcode);
|
1296 | 9a64fbe4 | bellard | |
1297 | 9a64fbe4 | bellard | if (ra == 0) { |
1298 | 9a64fbe4 | bellard | gen_op_load_gpr_T0(rB(ctx->opcode)); |
1299 | 9a64fbe4 | bellard | ra = rB(ctx->opcode); |
1300 | 79aceca5 | bellard | } else {
|
1301 | 9a64fbe4 | bellard | gen_op_load_gpr_T0(ra); |
1302 | 9a64fbe4 | bellard | gen_op_load_gpr_T1(rB(ctx->opcode)); |
1303 | 9a64fbe4 | bellard | gen_op_add(); |
1304 | 79aceca5 | bellard | } |
1305 | 9a64fbe4 | bellard | gen_op_load_xer_bc(); |
1306 | 9a64fbe4 | bellard | op_ldsts(stsw, rS(ctx->opcode)); |
1307 | 79aceca5 | bellard | } |
1308 | 79aceca5 | bellard | |
1309 | 79aceca5 | bellard | /*** Memory synchronisation ***/
|
1310 | 79aceca5 | bellard | /* eieio */
|
1311 | 79aceca5 | bellard | GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FF0801, PPC_MEM) |
1312 | 79aceca5 | bellard | { |
1313 | 79aceca5 | bellard | } |
1314 | 79aceca5 | bellard | |
1315 | 79aceca5 | bellard | /* isync */
|
1316 | 79aceca5 | bellard | GEN_HANDLER(isync, 0x13, 0x16, 0xFF, 0x03FF0801, PPC_MEM) |
1317 | 79aceca5 | bellard | { |
1318 | 79aceca5 | bellard | } |
1319 | 79aceca5 | bellard | |
1320 | 79aceca5 | bellard | /* lwarx */
|
1321 | 9a64fbe4 | bellard | #if defined(CONFIG_USER_ONLY)
|
1322 | 985a19d6 | bellard | #define op_lwarx() gen_op_lwarx_raw()
|
1323 | 9a64fbe4 | bellard | #define op_stwcx() gen_op_stwcx_raw()
|
1324 | 9a64fbe4 | bellard | #else
|
1325 | 985a19d6 | bellard | #define op_lwarx() (*gen_op_lwarx[ctx->mem_idx])()
|
1326 | 985a19d6 | bellard | static GenOpFunc *gen_op_lwarx[] = {
|
1327 | 985a19d6 | bellard | &gen_op_lwarx_user, |
1328 | 985a19d6 | bellard | &gen_op_lwarx_kernel, |
1329 | 985a19d6 | bellard | }; |
1330 | 9a64fbe4 | bellard | #define op_stwcx() (*gen_op_stwcx[ctx->mem_idx])()
|
1331 | 9a64fbe4 | bellard | static GenOpFunc *gen_op_stwcx[] = {
|
1332 | 9a64fbe4 | bellard | &gen_op_stwcx_user, |
1333 | 9a64fbe4 | bellard | &gen_op_stwcx_kernel, |
1334 | 9a64fbe4 | bellard | }; |
1335 | 9a64fbe4 | bellard | #endif
|
1336 | 9a64fbe4 | bellard | |
1337 | 9a64fbe4 | bellard | GEN_HANDLER(lwarx, 0x1F, 0x14, 0xFF, 0x00000001, PPC_RES) |
1338 | 79aceca5 | bellard | { |
1339 | 79aceca5 | bellard | if (rA(ctx->opcode) == 0) { |
1340 | 79aceca5 | bellard | gen_op_load_gpr_T0(rB(ctx->opcode)); |
1341 | 79aceca5 | bellard | } else {
|
1342 | 79aceca5 | bellard | gen_op_load_gpr_T0(rA(ctx->opcode)); |
1343 | 79aceca5 | bellard | gen_op_load_gpr_T1(rB(ctx->opcode)); |
1344 | 9a64fbe4 | bellard | gen_op_add(); |
1345 | 79aceca5 | bellard | } |
1346 | 985a19d6 | bellard | op_lwarx(); |
1347 | 79aceca5 | bellard | gen_op_store_T1_gpr(rD(ctx->opcode)); |
1348 | 79aceca5 | bellard | } |
1349 | 79aceca5 | bellard | |
1350 | 79aceca5 | bellard | /* stwcx. */
|
1351 | 9a64fbe4 | bellard | GEN_HANDLER(stwcx_, 0x1F, 0x16, 0x04, 0x00000000, PPC_RES) |
1352 | 79aceca5 | bellard | { |
1353 | 79aceca5 | bellard | if (rA(ctx->opcode) == 0) { |
1354 | 79aceca5 | bellard | gen_op_load_gpr_T0(rB(ctx->opcode)); |
1355 | 79aceca5 | bellard | } else {
|
1356 | 79aceca5 | bellard | gen_op_load_gpr_T0(rA(ctx->opcode)); |
1357 | 79aceca5 | bellard | gen_op_load_gpr_T1(rB(ctx->opcode)); |
1358 | 9a64fbe4 | bellard | gen_op_add(); |
1359 | 79aceca5 | bellard | } |
1360 | 9a64fbe4 | bellard | gen_op_load_gpr_T1(rS(ctx->opcode)); |
1361 | 9a64fbe4 | bellard | op_stwcx(); |
1362 | 79aceca5 | bellard | } |
1363 | 79aceca5 | bellard | |
1364 | 79aceca5 | bellard | /* sync */
|
1365 | 79aceca5 | bellard | GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x03FF0801, PPC_MEM) |
1366 | 79aceca5 | bellard | { |
1367 | 79aceca5 | bellard | } |
1368 | 79aceca5 | bellard | |
1369 | 79aceca5 | bellard | /*** Floating-point load ***/
|
1370 | 9a64fbe4 | bellard | #define GEN_LDF(width, opc) \
|
1371 | 9a64fbe4 | bellard | GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \ |
1372 | 79aceca5 | bellard | { \ |
1373 | 79aceca5 | bellard | uint32_t simm = SIMM(ctx->opcode); \ |
1374 | 79aceca5 | bellard | if (rA(ctx->opcode) == 0) { \ |
1375 | 9a64fbe4 | bellard | gen_op_set_T0(simm); \ |
1376 | 79aceca5 | bellard | } else { \
|
1377 | 79aceca5 | bellard | gen_op_load_gpr_T0(rA(ctx->opcode)); \ |
1378 | 9a64fbe4 | bellard | if (simm != 0) \ |
1379 | 9a64fbe4 | bellard | gen_op_addi(simm); \ |
1380 | 79aceca5 | bellard | } \ |
1381 | 9a64fbe4 | bellard | op_ldst(l##width); \ |
1382 | 9a64fbe4 | bellard | gen_op_store_FT1_fpr(rD(ctx->opcode)); \ |
1383 | 79aceca5 | bellard | } |
1384 | 79aceca5 | bellard | |
1385 | 9a64fbe4 | bellard | #define GEN_LDUF(width, opc) \
|
1386 | 9a64fbe4 | bellard | GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \ |
1387 | 79aceca5 | bellard | { \ |
1388 | 9a64fbe4 | bellard | uint32_t simm = SIMM(ctx->opcode); \ |
1389 | 79aceca5 | bellard | if (rA(ctx->opcode) == 0 || \ |
1390 | 9a64fbe4 | bellard | rA(ctx->opcode) == rD(ctx->opcode)) { \ |
1391 | 9fddaa0c | bellard | RET_INVAL(ctx); \ |
1392 | 9fddaa0c | bellard | return; \
|
1393 | 9a64fbe4 | bellard | } \ |
1394 | 79aceca5 | bellard | gen_op_load_gpr_T0(rA(ctx->opcode)); \ |
1395 | 9a64fbe4 | bellard | if (simm != 0) \ |
1396 | 9a64fbe4 | bellard | gen_op_addi(simm); \ |
1397 | 9a64fbe4 | bellard | op_ldst(l##width); \ |
1398 | 9a64fbe4 | bellard | gen_op_store_FT1_fpr(rD(ctx->opcode)); \ |
1399 | 79aceca5 | bellard | gen_op_store_T0_gpr(rA(ctx->opcode)); \ |
1400 | 79aceca5 | bellard | } |
1401 | 79aceca5 | bellard | |
1402 | 9a64fbe4 | bellard | #define GEN_LDUXF(width, opc) \
|
1403 | 9a64fbe4 | bellard | GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_INTEGER) \ |
1404 | 79aceca5 | bellard | { \ |
1405 | 79aceca5 | bellard | if (rA(ctx->opcode) == 0 || \ |
1406 | 9a64fbe4 | bellard | rA(ctx->opcode) == rD(ctx->opcode)) { \ |
1407 | 9fddaa0c | bellard | RET_INVAL(ctx); \ |
1408 | 9fddaa0c | bellard | return; \
|
1409 | 9a64fbe4 | bellard | } \ |
1410 | 79aceca5 | bellard | gen_op_load_gpr_T0(rA(ctx->opcode)); \ |
1411 | 79aceca5 | bellard | gen_op_load_gpr_T1(rB(ctx->opcode)); \ |
1412 | 9a64fbe4 | bellard | gen_op_add(); \ |
1413 | 9a64fbe4 | bellard | op_ldst(l##width); \ |
1414 | 9a64fbe4 | bellard | gen_op_store_FT1_fpr(rD(ctx->opcode)); \ |
1415 | 79aceca5 | bellard | gen_op_store_T0_gpr(rA(ctx->opcode)); \ |
1416 | 79aceca5 | bellard | } |
1417 | 79aceca5 | bellard | |
1418 | 9a64fbe4 | bellard | #define GEN_LDXF(width, opc2, opc3) \
|
1419 | 9a64fbe4 | bellard | GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_INTEGER) \ |
1420 | 79aceca5 | bellard | { \ |
1421 | 79aceca5 | bellard | if (rA(ctx->opcode) == 0) { \ |
1422 | 79aceca5 | bellard | gen_op_load_gpr_T0(rB(ctx->opcode)); \ |
1423 | 79aceca5 | bellard | } else { \
|
1424 | 79aceca5 | bellard | gen_op_load_gpr_T0(rA(ctx->opcode)); \ |
1425 | 79aceca5 | bellard | gen_op_load_gpr_T1(rB(ctx->opcode)); \ |
1426 | 9a64fbe4 | bellard | gen_op_add(); \ |
1427 | 79aceca5 | bellard | } \ |
1428 | 9a64fbe4 | bellard | op_ldst(l##width); \ |
1429 | 9a64fbe4 | bellard | gen_op_store_FT1_fpr(rD(ctx->opcode)); \ |
1430 | 79aceca5 | bellard | } |
1431 | 79aceca5 | bellard | |
1432 | 9a64fbe4 | bellard | #define GEN_LDFS(width, op) \
|
1433 | 9a64fbe4 | bellard | OP_LD_TABLE(width); \ |
1434 | 9a64fbe4 | bellard | GEN_LDF(width, op | 0x20); \
|
1435 | 9a64fbe4 | bellard | GEN_LDUF(width, op | 0x21); \
|
1436 | 9a64fbe4 | bellard | GEN_LDUXF(width, op | 0x01); \
|
1437 | 9a64fbe4 | bellard | GEN_LDXF(width, 0x17, op | 0x00) |
1438 | 79aceca5 | bellard | |
1439 | 79aceca5 | bellard | /* lfd lfdu lfdux lfdx */
|
1440 | 9a64fbe4 | bellard | GEN_LDFS(fd, 0x12);
|
1441 | 79aceca5 | bellard | /* lfs lfsu lfsux lfsx */
|
1442 | 9a64fbe4 | bellard | GEN_LDFS(fs, 0x10);
|
1443 | 79aceca5 | bellard | |
1444 | 79aceca5 | bellard | /*** Floating-point store ***/
|
1445 | 79aceca5 | bellard | #define GEN_STF(width, opc) \
|
1446 | 9a64fbe4 | bellard | GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \ |
1447 | 79aceca5 | bellard | { \ |
1448 | 79aceca5 | bellard | uint32_t simm = SIMM(ctx->opcode); \ |
1449 | 79aceca5 | bellard | if (rA(ctx->opcode) == 0) { \ |
1450 | 9a64fbe4 | bellard | gen_op_set_T0(simm); \ |
1451 | 79aceca5 | bellard | } else { \
|
1452 | 79aceca5 | bellard | gen_op_load_gpr_T0(rA(ctx->opcode)); \ |
1453 | 9a64fbe4 | bellard | if (simm != 0) \ |
1454 | 9a64fbe4 | bellard | gen_op_addi(simm); \ |
1455 | 79aceca5 | bellard | } \ |
1456 | 9a64fbe4 | bellard | gen_op_load_fpr_FT1(rS(ctx->opcode)); \ |
1457 | 9a64fbe4 | bellard | op_ldst(st##width); \ |
1458 | 79aceca5 | bellard | } |
1459 | 79aceca5 | bellard | |
1460 | 9a64fbe4 | bellard | #define GEN_STUF(width, opc) \
|
1461 | 9a64fbe4 | bellard | GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \ |
1462 | 79aceca5 | bellard | { \ |
1463 | 9a64fbe4 | bellard | uint32_t simm = SIMM(ctx->opcode); \ |
1464 | 9a64fbe4 | bellard | if (rA(ctx->opcode) == 0) { \ |
1465 | 9fddaa0c | bellard | RET_INVAL(ctx); \ |
1466 | 9fddaa0c | bellard | return; \
|
1467 | 9a64fbe4 | bellard | } \ |
1468 | 79aceca5 | bellard | gen_op_load_gpr_T0(rA(ctx->opcode)); \ |
1469 | 9a64fbe4 | bellard | if (simm != 0) \ |
1470 | 9a64fbe4 | bellard | gen_op_addi(simm); \ |
1471 | 9a64fbe4 | bellard | gen_op_load_fpr_FT1(rS(ctx->opcode)); \ |
1472 | 9a64fbe4 | bellard | op_ldst(st##width); \ |
1473 | 79aceca5 | bellard | gen_op_store_T0_gpr(rA(ctx->opcode)); \ |
1474 | 79aceca5 | bellard | } |
1475 | 79aceca5 | bellard | |
1476 | 9a64fbe4 | bellard | #define GEN_STUXF(width, opc) \
|
1477 | 9a64fbe4 | bellard | GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_INTEGER) \ |
1478 | 79aceca5 | bellard | { \ |
1479 | 9a64fbe4 | bellard | if (rA(ctx->opcode) == 0) { \ |
1480 | 9fddaa0c | bellard | RET_INVAL(ctx); \ |
1481 | 9fddaa0c | bellard | return; \
|
1482 | 9a64fbe4 | bellard | } \ |
1483 | 79aceca5 | bellard | gen_op_load_gpr_T0(rA(ctx->opcode)); \ |
1484 | 79aceca5 | bellard | gen_op_load_gpr_T1(rB(ctx->opcode)); \ |
1485 | 9a64fbe4 | bellard | gen_op_add(); \ |
1486 | 9a64fbe4 | bellard | gen_op_load_fpr_FT1(rS(ctx->opcode)); \ |
1487 | 9a64fbe4 | bellard | op_ldst(st##width); \ |
1488 | 79aceca5 | bellard | gen_op_store_T0_gpr(rA(ctx->opcode)); \ |
1489 | 79aceca5 | bellard | } |
1490 | 79aceca5 | bellard | |
1491 | 9a64fbe4 | bellard | #define GEN_STXF(width, opc2, opc3) \
|
1492 | 9a64fbe4 | bellard | GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_INTEGER) \ |
1493 | 79aceca5 | bellard | { \ |
1494 | 79aceca5 | bellard | if (rA(ctx->opcode) == 0) { \ |
1495 | 79aceca5 | bellard | gen_op_load_gpr_T0(rB(ctx->opcode)); \ |
1496 | 79aceca5 | bellard | } else { \
|
1497 | 79aceca5 | bellard | gen_op_load_gpr_T0(rA(ctx->opcode)); \ |
1498 | 79aceca5 | bellard | gen_op_load_gpr_T1(rB(ctx->opcode)); \ |
1499 | 9a64fbe4 | bellard | gen_op_add(); \ |
1500 | 79aceca5 | bellard | } \ |
1501 | 9a64fbe4 | bellard | gen_op_load_fpr_FT1(rS(ctx->opcode)); \ |
1502 | 9a64fbe4 | bellard | op_ldst(st##width); \ |
1503 | 79aceca5 | bellard | } |
1504 | 79aceca5 | bellard | |
1505 | 9a64fbe4 | bellard | #define GEN_STFS(width, op) \
|
1506 | 9a64fbe4 | bellard | OP_ST_TABLE(width); \ |
1507 | 9a64fbe4 | bellard | GEN_STF(width, op | 0x20); \
|
1508 | 9a64fbe4 | bellard | GEN_STUF(width, op | 0x21); \
|
1509 | 9a64fbe4 | bellard | GEN_STUXF(width, op | 0x01); \
|
1510 | 9a64fbe4 | bellard | GEN_STXF(width, 0x17, op | 0x00) |
1511 | 79aceca5 | bellard | |
1512 | 79aceca5 | bellard | /* stfd stfdu stfdux stfdx */
|
1513 | 9a64fbe4 | bellard | GEN_STFS(fd, 0x16);
|
1514 | 79aceca5 | bellard | /* stfs stfsu stfsux stfsx */
|
1515 | 9a64fbe4 | bellard | GEN_STFS(fs, 0x14);
|
1516 | 79aceca5 | bellard | |
1517 | 79aceca5 | bellard | /* Optional: */
|
1518 | 79aceca5 | bellard | /* stfiwx */
|
1519 | 79aceca5 | bellard | GEN_HANDLER(stfiwx, 0x1F, 0x17, 0x1E, 0x00000001, PPC_FLOAT) |
1520 | 79aceca5 | bellard | { |
1521 | 9fddaa0c | bellard | RET_INVAL(ctx); |
1522 | 79aceca5 | bellard | } |
1523 | 79aceca5 | bellard | |
1524 | 79aceca5 | bellard | /*** Branch ***/
|
1525 | 79aceca5 | bellard | |
1526 | 79aceca5 | bellard | /* b ba bl bla */
|
1527 | 79aceca5 | bellard | GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW) |
1528 | 79aceca5 | bellard | { |
1529 | 38a64f9d | bellard | uint32_t li, target; |
1530 | 38a64f9d | bellard | |
1531 | 38a64f9d | bellard | /* sign extend LI */
|
1532 | 38a64f9d | bellard | li = ((int32_t)LI(ctx->opcode) << 6) >> 6; |
1533 | 79aceca5 | bellard | |
1534 | 79aceca5 | bellard | if (AA(ctx->opcode) == 0) |
1535 | 046d6672 | bellard | target = ctx->nip + li - 4;
|
1536 | 79aceca5 | bellard | else
|
1537 | 9a64fbe4 | bellard | target = li; |
1538 | 9a64fbe4 | bellard | if (LK(ctx->opcode)) {
|
1539 | 046d6672 | bellard | gen_op_setlr(ctx->nip); |
1540 | 9a64fbe4 | bellard | } |
1541 | e98a6e40 | bellard | gen_op_b((long)ctx->tb, target);
|
1542 | 9a64fbe4 | bellard | ctx->exception = EXCP_BRANCH; |
1543 | 79aceca5 | bellard | } |
1544 | 79aceca5 | bellard | |
1545 | e98a6e40 | bellard | #define BCOND_IM 0 |
1546 | e98a6e40 | bellard | #define BCOND_LR 1 |
1547 | e98a6e40 | bellard | #define BCOND_CTR 2 |
1548 | e98a6e40 | bellard | |
1549 | e98a6e40 | bellard | static inline void gen_bcond(DisasContext *ctx, int type) |
1550 | e98a6e40 | bellard | { |
1551 | e98a6e40 | bellard | uint32_t target = 0;
|
1552 | e98a6e40 | bellard | uint32_t bo = BO(ctx->opcode); |
1553 | e98a6e40 | bellard | uint32_t bi = BI(ctx->opcode); |
1554 | e98a6e40 | bellard | uint32_t mask; |
1555 | e98a6e40 | bellard | uint32_t li; |
1556 | e98a6e40 | bellard | |
1557 | e98a6e40 | bellard | if ((bo & 0x4) == 0) |
1558 | e98a6e40 | bellard | gen_op_dec_ctr(); |
1559 | e98a6e40 | bellard | switch(type) {
|
1560 | e98a6e40 | bellard | case BCOND_IM:
|
1561 | e98a6e40 | bellard | li = s_ext16(BD(ctx->opcode)); |
1562 | e98a6e40 | bellard | if (AA(ctx->opcode) == 0) { |
1563 | 046d6672 | bellard | target = ctx->nip + li - 4;
|
1564 | e98a6e40 | bellard | } else {
|
1565 | e98a6e40 | bellard | target = li; |
1566 | e98a6e40 | bellard | } |
1567 | e98a6e40 | bellard | break;
|
1568 | e98a6e40 | bellard | case BCOND_CTR:
|
1569 | e98a6e40 | bellard | gen_op_movl_T1_ctr(); |
1570 | e98a6e40 | bellard | break;
|
1571 | e98a6e40 | bellard | default:
|
1572 | e98a6e40 | bellard | case BCOND_LR:
|
1573 | e98a6e40 | bellard | gen_op_movl_T1_lr(); |
1574 | e98a6e40 | bellard | break;
|
1575 | e98a6e40 | bellard | } |
1576 | e98a6e40 | bellard | if (LK(ctx->opcode)) {
|
1577 | 046d6672 | bellard | gen_op_setlr(ctx->nip); |
1578 | e98a6e40 | bellard | } |
1579 | e98a6e40 | bellard | if (bo & 0x10) { |
1580 | e98a6e40 | bellard | /* No CR condition */
|
1581 | e98a6e40 | bellard | switch (bo & 0x6) { |
1582 | e98a6e40 | bellard | case 0: |
1583 | e98a6e40 | bellard | gen_op_test_ctr(); |
1584 | e98a6e40 | bellard | break;
|
1585 | e98a6e40 | bellard | case 2: |
1586 | e98a6e40 | bellard | gen_op_test_ctrz(); |
1587 | e98a6e40 | bellard | break;
|
1588 | e98a6e40 | bellard | default:
|
1589 | e98a6e40 | bellard | case 4: |
1590 | e98a6e40 | bellard | case 6: |
1591 | e98a6e40 | bellard | if (type == BCOND_IM) {
|
1592 | e98a6e40 | bellard | gen_op_b((long)ctx->tb, target);
|
1593 | e98a6e40 | bellard | } else {
|
1594 | e98a6e40 | bellard | gen_op_b_T1(); |
1595 | e98a6e40 | bellard | } |
1596 | e98a6e40 | bellard | goto no_test;
|
1597 | e98a6e40 | bellard | } |
1598 | e98a6e40 | bellard | } else {
|
1599 | e98a6e40 | bellard | mask = 1 << (3 - (bi & 0x03)); |
1600 | e98a6e40 | bellard | gen_op_load_crf_T0(bi >> 2);
|
1601 | e98a6e40 | bellard | if (bo & 0x8) { |
1602 | e98a6e40 | bellard | switch (bo & 0x6) { |
1603 | e98a6e40 | bellard | case 0: |
1604 | e98a6e40 | bellard | gen_op_test_ctr_true(mask); |
1605 | e98a6e40 | bellard | break;
|
1606 | e98a6e40 | bellard | case 2: |
1607 | e98a6e40 | bellard | gen_op_test_ctrz_true(mask); |
1608 | e98a6e40 | bellard | break;
|
1609 | e98a6e40 | bellard | default:
|
1610 | e98a6e40 | bellard | case 4: |
1611 | e98a6e40 | bellard | case 6: |
1612 | e98a6e40 | bellard | gen_op_test_true(mask); |
1613 | e98a6e40 | bellard | break;
|
1614 | e98a6e40 | bellard | } |
1615 | e98a6e40 | bellard | } else {
|
1616 | e98a6e40 | bellard | switch (bo & 0x6) { |
1617 | e98a6e40 | bellard | case 0: |
1618 | e98a6e40 | bellard | gen_op_test_ctr_false(mask); |
1619 | e98a6e40 | bellard | break;
|
1620 | e98a6e40 | bellard | case 2: |
1621 | e98a6e40 | bellard | gen_op_test_ctrz_false(mask); |
1622 | e98a6e40 | bellard | break;
|
1623 | e98a6e40 | bellard | default:
|
1624 | e98a6e40 | bellard | case 4: |
1625 | e98a6e40 | bellard | case 6: |
1626 | e98a6e40 | bellard | gen_op_test_false(mask); |
1627 | e98a6e40 | bellard | break;
|
1628 | e98a6e40 | bellard | } |
1629 | e98a6e40 | bellard | } |
1630 | e98a6e40 | bellard | } |
1631 | e98a6e40 | bellard | if (type == BCOND_IM) {
|
1632 | 046d6672 | bellard | gen_op_btest((long)ctx->tb, target, ctx->nip);
|
1633 | e98a6e40 | bellard | } else {
|
1634 | 046d6672 | bellard | gen_op_btest_T1(ctx->nip); |
1635 | e98a6e40 | bellard | } |
1636 | e98a6e40 | bellard | no_test:
|
1637 | e98a6e40 | bellard | ctx->exception = EXCP_BRANCH; |
1638 | e98a6e40 | bellard | } |
1639 | e98a6e40 | bellard | |
1640 | e98a6e40 | bellard | GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW) |
1641 | e98a6e40 | bellard | { |
1642 | e98a6e40 | bellard | gen_bcond(ctx, BCOND_IM); |
1643 | e98a6e40 | bellard | } |
1644 | e98a6e40 | bellard | |
1645 | e98a6e40 | bellard | GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW) |
1646 | e98a6e40 | bellard | { |
1647 | e98a6e40 | bellard | gen_bcond(ctx, BCOND_CTR); |
1648 | e98a6e40 | bellard | } |
1649 | e98a6e40 | bellard | |
1650 | e98a6e40 | bellard | GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW) |
1651 | e98a6e40 | bellard | { |
1652 | e98a6e40 | bellard | gen_bcond(ctx, BCOND_LR); |
1653 | e98a6e40 | bellard | } |
1654 | 79aceca5 | bellard | |
1655 | 79aceca5 | bellard | /*** Condition register logical ***/
|
1656 | 79aceca5 | bellard | #define GEN_CRLOGIC(op, opc) \
|
1657 | 79aceca5 | bellard | GEN_HANDLER(cr##op, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) \ |
1658 | 79aceca5 | bellard | { \ |
1659 | 79aceca5 | bellard | gen_op_load_crf_T0(crbA(ctx->opcode) >> 2); \
|
1660 | 79aceca5 | bellard | gen_op_getbit_T0(3 - (crbA(ctx->opcode) & 0x03)); \ |
1661 | 79aceca5 | bellard | gen_op_load_crf_T1(crbB(ctx->opcode) >> 2); \
|
1662 | 79aceca5 | bellard | gen_op_getbit_T1(3 - (crbB(ctx->opcode) & 0x03)); \ |
1663 | 79aceca5 | bellard | gen_op_##op(); \ |
1664 | 79aceca5 | bellard | gen_op_load_crf_T1(crbD(ctx->opcode) >> 2); \
|
1665 | 79aceca5 | bellard | gen_op_setcrfbit(~(1 << (3 - (crbD(ctx->opcode) & 0x03))), \ |
1666 | 79aceca5 | bellard | 3 - (crbD(ctx->opcode) & 0x03)); \ |
1667 | 79aceca5 | bellard | gen_op_store_T1_crf(crbD(ctx->opcode) >> 2); \
|
1668 | 79aceca5 | bellard | } |
1669 | 79aceca5 | bellard | |
1670 | 79aceca5 | bellard | /* crand */
|
1671 | 79aceca5 | bellard | GEN_CRLOGIC(and, 0x08)
|
1672 | 79aceca5 | bellard | /* crandc */
|
1673 | 79aceca5 | bellard | GEN_CRLOGIC(andc, 0x04)
|
1674 | 79aceca5 | bellard | /* creqv */
|
1675 | 79aceca5 | bellard | GEN_CRLOGIC(eqv, 0x09)
|
1676 | 79aceca5 | bellard | /* crnand */
|
1677 | 79aceca5 | bellard | GEN_CRLOGIC(nand, 0x07)
|
1678 | 79aceca5 | bellard | /* crnor */
|
1679 | 79aceca5 | bellard | GEN_CRLOGIC(nor, 0x01)
|
1680 | 79aceca5 | bellard | /* cror */
|
1681 | 79aceca5 | bellard | GEN_CRLOGIC(or, 0x0E)
|
1682 | 79aceca5 | bellard | /* crorc */
|
1683 | 79aceca5 | bellard | GEN_CRLOGIC(orc, 0x0D)
|
1684 | 79aceca5 | bellard | /* crxor */
|
1685 | 79aceca5 | bellard | GEN_CRLOGIC(xor, 0x06)
|
1686 | 79aceca5 | bellard | /* mcrf */
|
1687 | 79aceca5 | bellard | GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER) |
1688 | 79aceca5 | bellard | { |
1689 | 79aceca5 | bellard | gen_op_load_crf_T0(crfS(ctx->opcode)); |
1690 | 79aceca5 | bellard | gen_op_store_T0_crf(crfD(ctx->opcode)); |
1691 | 79aceca5 | bellard | } |
1692 | 79aceca5 | bellard | |
1693 | 79aceca5 | bellard | /*** System linkage ***/
|
1694 | 79aceca5 | bellard | /* rfi (supervisor only) */
|
1695 | 79aceca5 | bellard | GEN_HANDLER(rfi, 0x13, 0x12, 0xFF, 0x03FF8001, PPC_FLOW) |
1696 | 79aceca5 | bellard | { |
1697 | 9a64fbe4 | bellard | #if defined(CONFIG_USER_ONLY)
|
1698 | 9fddaa0c | bellard | RET_PRIVOPC(ctx); |
1699 | 9a64fbe4 | bellard | #else
|
1700 | 9a64fbe4 | bellard | /* Restore CPU state */
|
1701 | 9a64fbe4 | bellard | if (!ctx->supervisor) {
|
1702 | 9fddaa0c | bellard | RET_PRIVOPC(ctx); |
1703 | 9fddaa0c | bellard | return;
|
1704 | 9a64fbe4 | bellard | } |
1705 | 9a64fbe4 | bellard | gen_op_rfi(); |
1706 | 9fddaa0c | bellard | RET_EXCP(ctx, EXCP_RFI, 0);
|
1707 | 9a64fbe4 | bellard | #endif
|
1708 | 79aceca5 | bellard | } |
1709 | 79aceca5 | bellard | |
1710 | 79aceca5 | bellard | /* sc */
|
1711 | 79aceca5 | bellard | GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFFFFD, PPC_FLOW) |
1712 | 79aceca5 | bellard | { |
1713 | 9a64fbe4 | bellard | #if defined(CONFIG_USER_ONLY)
|
1714 | 9fddaa0c | bellard | RET_EXCP(ctx, EXCP_SYSCALL_USER, 0);
|
1715 | 9a64fbe4 | bellard | #else
|
1716 | 9fddaa0c | bellard | RET_EXCP(ctx, EXCP_SYSCALL, 0);
|
1717 | 9a64fbe4 | bellard | #endif
|
1718 | 79aceca5 | bellard | } |
1719 | 79aceca5 | bellard | |
1720 | 79aceca5 | bellard | /*** Trap ***/
|
1721 | 79aceca5 | bellard | /* tw */
|
1722 | 79aceca5 | bellard | GEN_HANDLER(tw, 0x1F, 0x04, 0xFF, 0x00000001, PPC_FLOW) |
1723 | 79aceca5 | bellard | { |
1724 | 9a64fbe4 | bellard | gen_op_load_gpr_T0(rA(ctx->opcode)); |
1725 | 9a64fbe4 | bellard | gen_op_load_gpr_T1(rB(ctx->opcode)); |
1726 | 9a64fbe4 | bellard | gen_op_tw(TO(ctx->opcode)); |
1727 | 79aceca5 | bellard | } |
1728 | 79aceca5 | bellard | |
1729 | 79aceca5 | bellard | /* twi */
|
1730 | 79aceca5 | bellard | GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW) |
1731 | 79aceca5 | bellard | { |
1732 | 9a64fbe4 | bellard | gen_op_load_gpr_T0(rA(ctx->opcode)); |
1733 | 9a64fbe4 | bellard | #if 0
|
1734 | 9a64fbe4 | bellard | printf("%s: param=0x%04x T0=0x%04x\n", __func__,
|
1735 | 9a64fbe4 | bellard | SIMM(ctx->opcode), TO(ctx->opcode));
|
1736 | 9a64fbe4 | bellard | #endif
|
1737 | 9a64fbe4 | bellard | gen_op_twi(SIMM(ctx->opcode), TO(ctx->opcode)); |
1738 | 79aceca5 | bellard | } |
1739 | 79aceca5 | bellard | |
1740 | 79aceca5 | bellard | /*** Processor control ***/
|
1741 | 79aceca5 | bellard | static inline int check_spr_access (int spr, int rw, int supervisor) |
1742 | 79aceca5 | bellard | { |
1743 | 79aceca5 | bellard | uint32_t rights = spr_access[spr >> 1] >> (4 * (spr & 1)); |
1744 | 79aceca5 | bellard | |
1745 | 9a64fbe4 | bellard | #if 0
|
1746 | 9a64fbe4 | bellard | if (spr != LR && spr != CTR) {
|
1747 | 9a64fbe4 | bellard | if (loglevel > 0) {
|
1748 | 9a64fbe4 | bellard | fprintf(logfile, "%s reg=%d s=%d rw=%d r=0x%02x 0x%02x\n", __func__,
|
1749 | 9a64fbe4 | bellard | SPR_ENCODE(spr), supervisor, rw, rights,
|
1750 | 9a64fbe4 | bellard | (rights >> ((2 * supervisor) + rw)) & 1);
|
1751 | 9a64fbe4 | bellard | } else {
|
1752 | 9a64fbe4 | bellard | printf("%s reg=%d s=%d rw=%d r=0x%02x 0x%02x\n", __func__,
|
1753 | 9a64fbe4 | bellard | SPR_ENCODE(spr), supervisor, rw, rights,
|
1754 | 9a64fbe4 | bellard | (rights >> ((2 * supervisor) + rw)) & 1);
|
1755 | 9a64fbe4 | bellard | }
|
1756 | 9a64fbe4 | bellard | }
|
1757 | 9a64fbe4 | bellard | #endif
|
1758 | 9a64fbe4 | bellard | if (rights == 0) |
1759 | 9a64fbe4 | bellard | return -1; |
1760 | 79aceca5 | bellard | rights = rights >> (2 * supervisor);
|
1761 | 79aceca5 | bellard | rights = rights >> rw; |
1762 | 79aceca5 | bellard | |
1763 | 79aceca5 | bellard | return rights & 1; |
1764 | 79aceca5 | bellard | } |
1765 | 79aceca5 | bellard | |
1766 | 79aceca5 | bellard | /* mcrxr */
|
1767 | 79aceca5 | bellard | GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC) |
1768 | 79aceca5 | bellard | { |
1769 | 79aceca5 | bellard | gen_op_load_xer_cr(); |
1770 | 79aceca5 | bellard | gen_op_store_T0_crf(crfD(ctx->opcode)); |
1771 | 79aceca5 | bellard | gen_op_clear_xer_cr(); |
1772 | 79aceca5 | bellard | } |
1773 | 79aceca5 | bellard | |
1774 | 79aceca5 | bellard | /* mfcr */
|
1775 | 79aceca5 | bellard | GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x001FF801, PPC_MISC) |
1776 | 79aceca5 | bellard | { |
1777 | 79aceca5 | bellard | gen_op_load_cr(); |
1778 | 79aceca5 | bellard | gen_op_store_T0_gpr(rD(ctx->opcode)); |
1779 | 79aceca5 | bellard | } |
1780 | 79aceca5 | bellard | |
1781 | 79aceca5 | bellard | /* mfmsr */
|
1782 | 79aceca5 | bellard | GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC) |
1783 | 79aceca5 | bellard | { |
1784 | 9a64fbe4 | bellard | #if defined(CONFIG_USER_ONLY)
|
1785 | 9fddaa0c | bellard | RET_PRIVREG(ctx); |
1786 | 9a64fbe4 | bellard | #else
|
1787 | 9a64fbe4 | bellard | if (!ctx->supervisor) {
|
1788 | 9fddaa0c | bellard | RET_PRIVREG(ctx); |
1789 | 9fddaa0c | bellard | return;
|
1790 | 9a64fbe4 | bellard | } |
1791 | 79aceca5 | bellard | gen_op_load_msr(); |
1792 | 79aceca5 | bellard | gen_op_store_T0_gpr(rD(ctx->opcode)); |
1793 | 9a64fbe4 | bellard | #endif
|
1794 | 79aceca5 | bellard | } |
1795 | 79aceca5 | bellard | |
1796 | 79aceca5 | bellard | /* mfspr */
|
1797 | 79aceca5 | bellard | GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC) |
1798 | 79aceca5 | bellard | { |
1799 | 79aceca5 | bellard | uint32_t sprn = SPR(ctx->opcode); |
1800 | 79aceca5 | bellard | |
1801 | 9a64fbe4 | bellard | #if defined(CONFIG_USER_ONLY)
|
1802 | 9a64fbe4 | bellard | switch (check_spr_access(sprn, 0, 0)) |
1803 | 9a64fbe4 | bellard | #else
|
1804 | 9a64fbe4 | bellard | switch (check_spr_access(sprn, 0, ctx->supervisor)) |
1805 | 9a64fbe4 | bellard | #endif
|
1806 | 9a64fbe4 | bellard | { |
1807 | 9a64fbe4 | bellard | case -1: |
1808 | 9fddaa0c | bellard | RET_EXCP(ctx, EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_SPR); |
1809 | 9fddaa0c | bellard | return;
|
1810 | 9a64fbe4 | bellard | case 0: |
1811 | 9fddaa0c | bellard | RET_PRIVREG(ctx); |
1812 | 9fddaa0c | bellard | return;
|
1813 | 9a64fbe4 | bellard | default:
|
1814 | 9a64fbe4 | bellard | break;
|
1815 | 79aceca5 | bellard | } |
1816 | 9a64fbe4 | bellard | switch (sprn) {
|
1817 | 9a64fbe4 | bellard | case XER:
|
1818 | 79aceca5 | bellard | gen_op_load_xer(); |
1819 | 79aceca5 | bellard | break;
|
1820 | 9a64fbe4 | bellard | case LR:
|
1821 | 9a64fbe4 | bellard | gen_op_load_lr(); |
1822 | 9a64fbe4 | bellard | break;
|
1823 | 9a64fbe4 | bellard | case CTR:
|
1824 | 9a64fbe4 | bellard | gen_op_load_ctr(); |
1825 | 9a64fbe4 | bellard | break;
|
1826 | 9a64fbe4 | bellard | case IBAT0U:
|
1827 | 9a64fbe4 | bellard | gen_op_load_ibat(0, 0); |
1828 | 9a64fbe4 | bellard | break;
|
1829 | 9a64fbe4 | bellard | case IBAT1U:
|
1830 | 9a64fbe4 | bellard | gen_op_load_ibat(0, 1); |
1831 | 9a64fbe4 | bellard | break;
|
1832 | 9a64fbe4 | bellard | case IBAT2U:
|
1833 | 9a64fbe4 | bellard | gen_op_load_ibat(0, 2); |
1834 | 9a64fbe4 | bellard | break;
|
1835 | 9a64fbe4 | bellard | case IBAT3U:
|
1836 | 9a64fbe4 | bellard | gen_op_load_ibat(0, 3); |
1837 | 9a64fbe4 | bellard | break;
|
1838 | 9a64fbe4 | bellard | case IBAT4U:
|
1839 | 9a64fbe4 | bellard | gen_op_load_ibat(0, 4); |
1840 | 9a64fbe4 | bellard | break;
|
1841 | 9a64fbe4 | bellard | case IBAT5U:
|
1842 | 9a64fbe4 | bellard | gen_op_load_ibat(0, 5); |
1843 | 9a64fbe4 | bellard | break;
|
1844 | 9a64fbe4 | bellard | case IBAT6U:
|
1845 | 9a64fbe4 | bellard | gen_op_load_ibat(0, 6); |
1846 | 9a64fbe4 | bellard | break;
|
1847 | 9a64fbe4 | bellard | case IBAT7U:
|
1848 | 9a64fbe4 | bellard | gen_op_load_ibat(0, 7); |
1849 | 9a64fbe4 | bellard | break;
|
1850 | 9a64fbe4 | bellard | case IBAT0L:
|
1851 | 9a64fbe4 | bellard | gen_op_load_ibat(1, 0); |
1852 | 9a64fbe4 | bellard | break;
|
1853 | 9a64fbe4 | bellard | case IBAT1L:
|
1854 | 9a64fbe4 | bellard | gen_op_load_ibat(1, 1); |
1855 | 9a64fbe4 | bellard | break;
|
1856 | 9a64fbe4 | bellard | case IBAT2L:
|
1857 | 9a64fbe4 | bellard | gen_op_load_ibat(1, 2); |
1858 | 9a64fbe4 | bellard | break;
|
1859 | 9a64fbe4 | bellard | case IBAT3L:
|
1860 | 9a64fbe4 | bellard | gen_op_load_ibat(1, 3); |
1861 | 9a64fbe4 | bellard | break;
|
1862 | 9a64fbe4 | bellard | case IBAT4L:
|
1863 | 9a64fbe4 | bellard | gen_op_load_ibat(1, 4); |
1864 | 9a64fbe4 | bellard | break;
|
1865 | 9a64fbe4 | bellard | case IBAT5L:
|
1866 | 9a64fbe4 | bellard | gen_op_load_ibat(1, 5); |
1867 | 9a64fbe4 | bellard | break;
|
1868 | 9a64fbe4 | bellard | case IBAT6L:
|
1869 | 9a64fbe4 | bellard | gen_op_load_ibat(1, 6); |
1870 | 9a64fbe4 | bellard | break;
|
1871 | 9a64fbe4 | bellard | case IBAT7L:
|
1872 | 9a64fbe4 | bellard | gen_op_load_ibat(1, 7); |
1873 | 9a64fbe4 | bellard | break;
|
1874 | 9a64fbe4 | bellard | case DBAT0U:
|
1875 | 9a64fbe4 | bellard | gen_op_load_dbat(0, 0); |
1876 | 9a64fbe4 | bellard | break;
|
1877 | 9a64fbe4 | bellard | case DBAT1U:
|
1878 | 9a64fbe4 | bellard | gen_op_load_dbat(0, 1); |
1879 | 9a64fbe4 | bellard | break;
|
1880 | 9a64fbe4 | bellard | case DBAT2U:
|
1881 | 9a64fbe4 | bellard | gen_op_load_dbat(0, 2); |
1882 | 9a64fbe4 | bellard | break;
|
1883 | 9a64fbe4 | bellard | case DBAT3U:
|
1884 | 9a64fbe4 | bellard | gen_op_load_dbat(0, 3); |
1885 | 9a64fbe4 | bellard | break;
|
1886 | 9a64fbe4 | bellard | case DBAT4U:
|
1887 | 9a64fbe4 | bellard | gen_op_load_dbat(0, 4); |
1888 | 9a64fbe4 | bellard | break;
|
1889 | 9a64fbe4 | bellard | case DBAT5U:
|
1890 | 9a64fbe4 | bellard | gen_op_load_dbat(0, 5); |
1891 | 9a64fbe4 | bellard | break;
|
1892 | 9a64fbe4 | bellard | case DBAT6U:
|
1893 | 9a64fbe4 | bellard | gen_op_load_dbat(0, 6); |
1894 | 9a64fbe4 | bellard | break;
|
1895 | 9a64fbe4 | bellard | case DBAT7U:
|
1896 | 9a64fbe4 | bellard | gen_op_load_dbat(0, 7); |
1897 | 9a64fbe4 | bellard | break;
|
1898 | 9a64fbe4 | bellard | case DBAT0L:
|
1899 | 9a64fbe4 | bellard | gen_op_load_dbat(1, 0); |
1900 | 9a64fbe4 | bellard | break;
|
1901 | 9a64fbe4 | bellard | case DBAT1L:
|
1902 | 9a64fbe4 | bellard | gen_op_load_dbat(1, 1); |
1903 | 9a64fbe4 | bellard | break;
|
1904 | 9a64fbe4 | bellard | case DBAT2L:
|
1905 | 9a64fbe4 | bellard | gen_op_load_dbat(1, 2); |
1906 | 9a64fbe4 | bellard | break;
|
1907 | 9a64fbe4 | bellard | case DBAT3L:
|
1908 | 9a64fbe4 | bellard | gen_op_load_dbat(1, 3); |
1909 | 9a64fbe4 | bellard | break;
|
1910 | 9a64fbe4 | bellard | case DBAT4L:
|
1911 | 9a64fbe4 | bellard | gen_op_load_dbat(1, 4); |
1912 | 9a64fbe4 | bellard | break;
|
1913 | 9a64fbe4 | bellard | case DBAT5L:
|
1914 | 9a64fbe4 | bellard | gen_op_load_dbat(1, 5); |
1915 | 9a64fbe4 | bellard | break;
|
1916 | 9a64fbe4 | bellard | case DBAT6L:
|
1917 | 9a64fbe4 | bellard | gen_op_load_dbat(1, 6); |
1918 | 9a64fbe4 | bellard | break;
|
1919 | 9a64fbe4 | bellard | case DBAT7L:
|
1920 | 9a64fbe4 | bellard | gen_op_load_dbat(1, 7); |
1921 | 9a64fbe4 | bellard | break;
|
1922 | 9a64fbe4 | bellard | case SDR1:
|
1923 | 9a64fbe4 | bellard | gen_op_load_sdr1(); |
1924 | 9a64fbe4 | bellard | break;
|
1925 | 9a64fbe4 | bellard | case V_TBL:
|
1926 | 9fddaa0c | bellard | gen_op_load_tbl(); |
1927 | 79aceca5 | bellard | break;
|
1928 | 9a64fbe4 | bellard | case V_TBU:
|
1929 | 9fddaa0c | bellard | gen_op_load_tbu(); |
1930 | 9a64fbe4 | bellard | break;
|
1931 | 9a64fbe4 | bellard | case DECR:
|
1932 | 9fddaa0c | bellard | gen_op_load_decr(); |
1933 | 79aceca5 | bellard | break;
|
1934 | 79aceca5 | bellard | default:
|
1935 | 79aceca5 | bellard | gen_op_load_spr(sprn); |
1936 | 79aceca5 | bellard | break;
|
1937 | 79aceca5 | bellard | } |
1938 | 9a64fbe4 | bellard | gen_op_store_T0_gpr(rD(ctx->opcode)); |
1939 | 79aceca5 | bellard | } |
1940 | 79aceca5 | bellard | |
1941 | 79aceca5 | bellard | /* mftb */
|
1942 | 79aceca5 | bellard | GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MISC) |
1943 | 79aceca5 | bellard | { |
1944 | 79aceca5 | bellard | uint32_t sprn = SPR(ctx->opcode); |
1945 | 79aceca5 | bellard | |
1946 | 79aceca5 | bellard | /* We need to update the time base before reading it */
|
1947 | 9a64fbe4 | bellard | switch (sprn) {
|
1948 | 9a64fbe4 | bellard | case V_TBL:
|
1949 | 9fddaa0c | bellard | gen_op_load_tbl(); |
1950 | 79aceca5 | bellard | break;
|
1951 | 9a64fbe4 | bellard | case V_TBU:
|
1952 | 9fddaa0c | bellard | gen_op_load_tbu(); |
1953 | 79aceca5 | bellard | break;
|
1954 | 79aceca5 | bellard | default:
|
1955 | 9fddaa0c | bellard | RET_INVAL(ctx); |
1956 | 9fddaa0c | bellard | return;
|
1957 | 79aceca5 | bellard | } |
1958 | 9a64fbe4 | bellard | gen_op_store_T0_gpr(rD(ctx->opcode)); |
1959 | 79aceca5 | bellard | } |
1960 | 79aceca5 | bellard | |
1961 | 79aceca5 | bellard | /* mtcrf */
|
1962 | 79aceca5 | bellard | GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00100801, PPC_MISC) |
1963 | 79aceca5 | bellard | { |
1964 | 79aceca5 | bellard | gen_op_load_gpr_T0(rS(ctx->opcode)); |
1965 | 79aceca5 | bellard | gen_op_store_cr(CRM(ctx->opcode)); |
1966 | 79aceca5 | bellard | } |
1967 | 79aceca5 | bellard | |
1968 | 79aceca5 | bellard | /* mtmsr */
|
1969 | 79aceca5 | bellard | GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC) |
1970 | 79aceca5 | bellard | { |
1971 | 9a64fbe4 | bellard | #if defined(CONFIG_USER_ONLY)
|
1972 | 9fddaa0c | bellard | RET_PRIVREG(ctx); |
1973 | 9a64fbe4 | bellard | #else
|
1974 | 9a64fbe4 | bellard | if (!ctx->supervisor) {
|
1975 | 9fddaa0c | bellard | RET_PRIVREG(ctx); |
1976 | 9fddaa0c | bellard | return;
|
1977 | 9a64fbe4 | bellard | } |
1978 | 79aceca5 | bellard | gen_op_load_gpr_T0(rS(ctx->opcode)); |
1979 | 79aceca5 | bellard | gen_op_store_msr(); |
1980 | 79aceca5 | bellard | /* Must stop the translation as machine state (may have) changed */
|
1981 | 9fddaa0c | bellard | RET_MTMSR(ctx); |
1982 | 9a64fbe4 | bellard | #endif
|
1983 | 79aceca5 | bellard | } |
1984 | 79aceca5 | bellard | |
1985 | 79aceca5 | bellard | /* mtspr */
|
1986 | 79aceca5 | bellard | GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC) |
1987 | 79aceca5 | bellard | { |
1988 | 79aceca5 | bellard | uint32_t sprn = SPR(ctx->opcode); |
1989 | 79aceca5 | bellard | |
1990 | 9a64fbe4 | bellard | #if 0
|
1991 | 9a64fbe4 | bellard | if (loglevel > 0) {
|
1992 | 9a64fbe4 | bellard | fprintf(logfile, "MTSPR %d src=%d (%d)\n", SPR_ENCODE(sprn),
|
1993 | 9a64fbe4 | bellard | rS(ctx->opcode), sprn);
|
1994 | 9a64fbe4 | bellard | }
|
1995 | 9a64fbe4 | bellard | #endif
|
1996 | 9a64fbe4 | bellard | #if defined(CONFIG_USER_ONLY)
|
1997 | 9a64fbe4 | bellard | switch (check_spr_access(sprn, 1, 0)) |
1998 | 9a64fbe4 | bellard | #else
|
1999 | 9a64fbe4 | bellard | switch (check_spr_access(sprn, 1, ctx->supervisor)) |
2000 | 9a64fbe4 | bellard | #endif
|
2001 | 9a64fbe4 | bellard | { |
2002 | 9a64fbe4 | bellard | case -1: |
2003 | 9fddaa0c | bellard | RET_EXCP(ctx, EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_SPR); |
2004 | 9a64fbe4 | bellard | break;
|
2005 | 9a64fbe4 | bellard | case 0: |
2006 | 9fddaa0c | bellard | RET_PRIVREG(ctx); |
2007 | 9a64fbe4 | bellard | break;
|
2008 | 9a64fbe4 | bellard | default:
|
2009 | 9a64fbe4 | bellard | break;
|
2010 | 9a64fbe4 | bellard | } |
2011 | 79aceca5 | bellard | gen_op_load_gpr_T0(rS(ctx->opcode)); |
2012 | 9a64fbe4 | bellard | switch (sprn) {
|
2013 | 9a64fbe4 | bellard | case XER:
|
2014 | 79aceca5 | bellard | gen_op_store_xer(); |
2015 | 9a64fbe4 | bellard | break;
|
2016 | 9a64fbe4 | bellard | case LR:
|
2017 | 9a64fbe4 | bellard | gen_op_store_lr(); |
2018 | 9a64fbe4 | bellard | break;
|
2019 | 9a64fbe4 | bellard | case CTR:
|
2020 | 9a64fbe4 | bellard | gen_op_store_ctr(); |
2021 | 9a64fbe4 | bellard | break;
|
2022 | 9a64fbe4 | bellard | case IBAT0U:
|
2023 | 9a64fbe4 | bellard | gen_op_store_ibat(0, 0); |
2024 | 4b3686fa | bellard | RET_MTMSR(ctx); |
2025 | 9a64fbe4 | bellard | break;
|
2026 | 9a64fbe4 | bellard | case IBAT1U:
|
2027 | 9a64fbe4 | bellard | gen_op_store_ibat(0, 1); |
2028 | 4b3686fa | bellard | RET_MTMSR(ctx); |
2029 | 9a64fbe4 | bellard | break;
|
2030 | 9a64fbe4 | bellard | case IBAT2U:
|
2031 | 9a64fbe4 | bellard | gen_op_store_ibat(0, 2); |
2032 | 4b3686fa | bellard | RET_MTMSR(ctx); |
2033 | 9a64fbe4 | bellard | break;
|
2034 | 9a64fbe4 | bellard | case IBAT3U:
|
2035 | 9a64fbe4 | bellard | gen_op_store_ibat(0, 3); |
2036 | 4b3686fa | bellard | RET_MTMSR(ctx); |
2037 | 9a64fbe4 | bellard | break;
|
2038 | 9a64fbe4 | bellard | case IBAT4U:
|
2039 | 9a64fbe4 | bellard | gen_op_store_ibat(0, 4); |
2040 | 4b3686fa | bellard | RET_MTMSR(ctx); |
2041 | 9a64fbe4 | bellard | break;
|
2042 | 9a64fbe4 | bellard | case IBAT5U:
|
2043 | 9a64fbe4 | bellard | gen_op_store_ibat(0, 5); |
2044 | 4b3686fa | bellard | RET_MTMSR(ctx); |
2045 | 9a64fbe4 | bellard | break;
|
2046 | 9a64fbe4 | bellard | case IBAT6U:
|
2047 | 9a64fbe4 | bellard | gen_op_store_ibat(0, 6); |
2048 | 4b3686fa | bellard | RET_MTMSR(ctx); |
2049 | 9a64fbe4 | bellard | break;
|
2050 | 9a64fbe4 | bellard | case IBAT7U:
|
2051 | 9a64fbe4 | bellard | gen_op_store_ibat(0, 7); |
2052 | 4b3686fa | bellard | RET_MTMSR(ctx); |
2053 | 9a64fbe4 | bellard | break;
|
2054 | 9a64fbe4 | bellard | case IBAT0L:
|
2055 | 9a64fbe4 | bellard | gen_op_store_ibat(1, 0); |
2056 | 4b3686fa | bellard | RET_MTMSR(ctx); |
2057 | 9a64fbe4 | bellard | break;
|
2058 | 9a64fbe4 | bellard | case IBAT1L:
|
2059 | 9a64fbe4 | bellard | gen_op_store_ibat(1, 1); |
2060 | 4b3686fa | bellard | RET_MTMSR(ctx); |
2061 | 9a64fbe4 | bellard | break;
|
2062 | 9a64fbe4 | bellard | case IBAT2L:
|
2063 | 9a64fbe4 | bellard | gen_op_store_ibat(1, 2); |
2064 | 4b3686fa | bellard | RET_MTMSR(ctx); |
2065 | 9a64fbe4 | bellard | break;
|
2066 | 9a64fbe4 | bellard | case IBAT3L:
|
2067 | 9a64fbe4 | bellard | gen_op_store_ibat(1, 3); |
2068 | 4b3686fa | bellard | RET_MTMSR(ctx); |
2069 | 9a64fbe4 | bellard | break;
|
2070 | 9a64fbe4 | bellard | case IBAT4L:
|
2071 | 9a64fbe4 | bellard | gen_op_store_ibat(1, 4); |
2072 | 4b3686fa | bellard | RET_MTMSR(ctx); |
2073 | 9a64fbe4 | bellard | break;
|
2074 | 9a64fbe4 | bellard | case IBAT5L:
|
2075 | 9a64fbe4 | bellard | gen_op_store_ibat(1, 5); |
2076 | 4b3686fa | bellard | RET_MTMSR(ctx); |
2077 | 9a64fbe4 | bellard | break;
|
2078 | 9a64fbe4 | bellard | case IBAT6L:
|
2079 | 9a64fbe4 | bellard | gen_op_store_ibat(1, 6); |
2080 | 4b3686fa | bellard | RET_MTMSR(ctx); |
2081 | 9a64fbe4 | bellard | break;
|
2082 | 9a64fbe4 | bellard | case IBAT7L:
|
2083 | 9a64fbe4 | bellard | gen_op_store_ibat(1, 7); |
2084 | 4b3686fa | bellard | RET_MTMSR(ctx); |
2085 | 9a64fbe4 | bellard | break;
|
2086 | 9a64fbe4 | bellard | case DBAT0U:
|
2087 | 9a64fbe4 | bellard | gen_op_store_dbat(0, 0); |
2088 | 4b3686fa | bellard | RET_MTMSR(ctx); |
2089 | 9a64fbe4 | bellard | break;
|
2090 | 9a64fbe4 | bellard | case DBAT1U:
|
2091 | 9a64fbe4 | bellard | gen_op_store_dbat(0, 1); |
2092 | 4b3686fa | bellard | RET_MTMSR(ctx); |
2093 | 9a64fbe4 | bellard | break;
|
2094 | 9a64fbe4 | bellard | case DBAT2U:
|
2095 | 9a64fbe4 | bellard | gen_op_store_dbat(0, 2); |
2096 | 4b3686fa | bellard | RET_MTMSR(ctx); |
2097 | 9a64fbe4 | bellard | break;
|
2098 | 9a64fbe4 | bellard | case DBAT3U:
|
2099 | 9a64fbe4 | bellard | gen_op_store_dbat(0, 3); |
2100 | 4b3686fa | bellard | RET_MTMSR(ctx); |
2101 | 9a64fbe4 | bellard | break;
|
2102 | 9a64fbe4 | bellard | case DBAT4U:
|
2103 | 9a64fbe4 | bellard | gen_op_store_dbat(0, 4); |
2104 | 4b3686fa | bellard | RET_MTMSR(ctx); |
2105 | 9a64fbe4 | bellard | break;
|
2106 | 9a64fbe4 | bellard | case DBAT5U:
|
2107 | 9a64fbe4 | bellard | gen_op_store_dbat(0, 5); |
2108 | 4b3686fa | bellard | RET_MTMSR(ctx); |
2109 | 9a64fbe4 | bellard | break;
|
2110 | 9a64fbe4 | bellard | case DBAT6U:
|
2111 | 9a64fbe4 | bellard | gen_op_store_dbat(0, 6); |
2112 | 4b3686fa | bellard | RET_MTMSR(ctx); |
2113 | 9a64fbe4 | bellard | break;
|
2114 | 9a64fbe4 | bellard | case DBAT7U:
|
2115 | 9a64fbe4 | bellard | gen_op_store_dbat(0, 7); |
2116 | 4b3686fa | bellard | RET_MTMSR(ctx); |
2117 | 9a64fbe4 | bellard | break;
|
2118 | 9a64fbe4 | bellard | case DBAT0L:
|
2119 | 9a64fbe4 | bellard | gen_op_store_dbat(1, 0); |
2120 | 4b3686fa | bellard | RET_MTMSR(ctx); |
2121 | 9a64fbe4 | bellard | break;
|
2122 | 9a64fbe4 | bellard | case DBAT1L:
|
2123 | 9a64fbe4 | bellard | gen_op_store_dbat(1, 1); |
2124 | 4b3686fa | bellard | RET_MTMSR(ctx); |
2125 | 9a64fbe4 | bellard | break;
|
2126 | 9a64fbe4 | bellard | case DBAT2L:
|
2127 | 9a64fbe4 | bellard | gen_op_store_dbat(1, 2); |
2128 | 4b3686fa | bellard | RET_MTMSR(ctx); |
2129 | 9a64fbe4 | bellard | break;
|
2130 | 9a64fbe4 | bellard | case DBAT3L:
|
2131 | 9a64fbe4 | bellard | gen_op_store_dbat(1, 3); |
2132 | 4b3686fa | bellard | RET_MTMSR(ctx); |
2133 | 9a64fbe4 | bellard | break;
|
2134 | 9a64fbe4 | bellard | case DBAT4L:
|
2135 | 9a64fbe4 | bellard | gen_op_store_dbat(1, 4); |
2136 | 4b3686fa | bellard | RET_MTMSR(ctx); |
2137 | 9a64fbe4 | bellard | break;
|
2138 | 9a64fbe4 | bellard | case DBAT5L:
|
2139 | 9a64fbe4 | bellard | gen_op_store_dbat(1, 5); |
2140 | 4b3686fa | bellard | RET_MTMSR(ctx); |
2141 | 9a64fbe4 | bellard | break;
|
2142 | 9a64fbe4 | bellard | case DBAT6L:
|
2143 | 9a64fbe4 | bellard | gen_op_store_dbat(1, 6); |
2144 | 4b3686fa | bellard | RET_MTMSR(ctx); |
2145 | 9a64fbe4 | bellard | break;
|
2146 | 9a64fbe4 | bellard | case DBAT7L:
|
2147 | 9a64fbe4 | bellard | gen_op_store_dbat(1, 7); |
2148 | 4b3686fa | bellard | RET_MTMSR(ctx); |
2149 | 9a64fbe4 | bellard | break;
|
2150 | 9a64fbe4 | bellard | case SDR1:
|
2151 | 9a64fbe4 | bellard | gen_op_store_sdr1(); |
2152 | 4b3686fa | bellard | RET_MTMSR(ctx); |
2153 | 9a64fbe4 | bellard | break;
|
2154 | 9a64fbe4 | bellard | case O_TBL:
|
2155 | 9fddaa0c | bellard | gen_op_store_tbl(); |
2156 | 9a64fbe4 | bellard | break;
|
2157 | 9a64fbe4 | bellard | case O_TBU:
|
2158 | 9fddaa0c | bellard | gen_op_store_tbu(); |
2159 | 9a64fbe4 | bellard | break;
|
2160 | 9a64fbe4 | bellard | case DECR:
|
2161 | 9a64fbe4 | bellard | gen_op_store_decr(); |
2162 | 9a64fbe4 | bellard | break;
|
2163 | 4b3686fa | bellard | #if 0
|
2164 | 4b3686fa | bellard | case HID0:
|
2165 | 4b3686fa | bellard | gen_op_store_hid0();
|
2166 | 4b3686fa | bellard | break;
|
2167 | 4b3686fa | bellard | #endif
|
2168 | 9a64fbe4 | bellard | default:
|
2169 | 79aceca5 | bellard | gen_op_store_spr(sprn); |
2170 | 9a64fbe4 | bellard | break;
|
2171 | 79aceca5 | bellard | } |
2172 | 79aceca5 | bellard | } |
2173 | 79aceca5 | bellard | |
2174 | 79aceca5 | bellard | /*** Cache management ***/
|
2175 | 79aceca5 | bellard | /* For now, all those will be implemented as nop:
|
2176 | 79aceca5 | bellard | * this is valid, regarding the PowerPC specs...
|
2177 | 9a64fbe4 | bellard | * We just have to flush tb while invalidating instruction cache lines...
|
2178 | 79aceca5 | bellard | */
|
2179 | 79aceca5 | bellard | /* dcbf */
|
2180 | 9a64fbe4 | bellard | GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03E00001, PPC_CACHE) |
2181 | 79aceca5 | bellard | { |
2182 | a541f297 | bellard | if (rA(ctx->opcode) == 0) { |
2183 | a541f297 | bellard | gen_op_load_gpr_T0(rB(ctx->opcode)); |
2184 | a541f297 | bellard | } else {
|
2185 | a541f297 | bellard | gen_op_load_gpr_T0(rA(ctx->opcode)); |
2186 | a541f297 | bellard | gen_op_load_gpr_T1(rB(ctx->opcode)); |
2187 | a541f297 | bellard | gen_op_add(); |
2188 | a541f297 | bellard | } |
2189 | a541f297 | bellard | op_ldst(lbz); |
2190 | 79aceca5 | bellard | } |
2191 | 79aceca5 | bellard | |
2192 | 79aceca5 | bellard | /* dcbi (Supervisor only) */
|
2193 | 9a64fbe4 | bellard | GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE) |
2194 | 79aceca5 | bellard | { |
2195 | a541f297 | bellard | #if defined(CONFIG_USER_ONLY)
|
2196 | 9fddaa0c | bellard | RET_PRIVOPC(ctx); |
2197 | a541f297 | bellard | #else
|
2198 | a541f297 | bellard | if (!ctx->supervisor) {
|
2199 | 9fddaa0c | bellard | RET_PRIVOPC(ctx); |
2200 | 9fddaa0c | bellard | return;
|
2201 | 9a64fbe4 | bellard | } |
2202 | a541f297 | bellard | if (rA(ctx->opcode) == 0) { |
2203 | a541f297 | bellard | gen_op_load_gpr_T0(rB(ctx->opcode)); |
2204 | a541f297 | bellard | } else {
|
2205 | a541f297 | bellard | gen_op_load_gpr_T0(rA(ctx->opcode)); |
2206 | a541f297 | bellard | gen_op_load_gpr_T1(rB(ctx->opcode)); |
2207 | a541f297 | bellard | gen_op_add(); |
2208 | a541f297 | bellard | } |
2209 | a541f297 | bellard | op_ldst(lbz); |
2210 | a541f297 | bellard | op_ldst(stb); |
2211 | a541f297 | bellard | #endif
|
2212 | 79aceca5 | bellard | } |
2213 | 79aceca5 | bellard | |
2214 | 79aceca5 | bellard | /* dcdst */
|
2215 | 9a64fbe4 | bellard | GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE) |
2216 | 79aceca5 | bellard | { |
2217 | a541f297 | bellard | if (rA(ctx->opcode) == 0) { |
2218 | a541f297 | bellard | gen_op_load_gpr_T0(rB(ctx->opcode)); |
2219 | a541f297 | bellard | } else {
|
2220 | a541f297 | bellard | gen_op_load_gpr_T0(rA(ctx->opcode)); |
2221 | a541f297 | bellard | gen_op_load_gpr_T1(rB(ctx->opcode)); |
2222 | a541f297 | bellard | gen_op_add(); |
2223 | a541f297 | bellard | } |
2224 | a541f297 | bellard | op_ldst(lbz); |
2225 | 79aceca5 | bellard | } |
2226 | 79aceca5 | bellard | |
2227 | 79aceca5 | bellard | /* dcbt */
|
2228 | 9a64fbe4 | bellard | GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x03E00001, PPC_CACHE) |
2229 | 79aceca5 | bellard | { |
2230 | 79aceca5 | bellard | } |
2231 | 79aceca5 | bellard | |
2232 | 79aceca5 | bellard | /* dcbtst */
|
2233 | 9a64fbe4 | bellard | GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x03E00001, PPC_CACHE) |
2234 | 79aceca5 | bellard | { |
2235 | 79aceca5 | bellard | } |
2236 | 79aceca5 | bellard | |
2237 | 79aceca5 | bellard | /* dcbz */
|
2238 | 9a64fbe4 | bellard | #if defined(CONFIG_USER_ONLY)
|
2239 | 9a64fbe4 | bellard | #define op_dcbz() gen_op_dcbz_raw()
|
2240 | 9a64fbe4 | bellard | #else
|
2241 | 9a64fbe4 | bellard | #define op_dcbz() (*gen_op_dcbz[ctx->mem_idx])()
|
2242 | 9a64fbe4 | bellard | static GenOpFunc *gen_op_dcbz[] = {
|
2243 | 9a64fbe4 | bellard | &gen_op_dcbz_user, |
2244 | 9a64fbe4 | bellard | &gen_op_dcbz_kernel, |
2245 | 9a64fbe4 | bellard | }; |
2246 | 9a64fbe4 | bellard | #endif
|
2247 | 9a64fbe4 | bellard | |
2248 | 9a64fbe4 | bellard | GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE) |
2249 | 79aceca5 | bellard | { |
2250 | fb0eaffc | bellard | if (rA(ctx->opcode) == 0) { |
2251 | fb0eaffc | bellard | gen_op_load_gpr_T0(rB(ctx->opcode)); |
2252 | fb0eaffc | bellard | } else {
|
2253 | fb0eaffc | bellard | gen_op_load_gpr_T0(rA(ctx->opcode)); |
2254 | fb0eaffc | bellard | gen_op_load_gpr_T1(rB(ctx->opcode)); |
2255 | 9a64fbe4 | bellard | gen_op_add(); |
2256 | fb0eaffc | bellard | } |
2257 | 9a64fbe4 | bellard | op_dcbz(); |
2258 | 4b3686fa | bellard | gen_op_check_reservation(); |
2259 | 79aceca5 | bellard | } |
2260 | 79aceca5 | bellard | |
2261 | 79aceca5 | bellard | /* icbi */
|
2262 | 9a64fbe4 | bellard | GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE) |
2263 | 79aceca5 | bellard | { |
2264 | fb0eaffc | bellard | if (rA(ctx->opcode) == 0) { |
2265 | fb0eaffc | bellard | gen_op_load_gpr_T0(rB(ctx->opcode)); |
2266 | fb0eaffc | bellard | } else {
|
2267 | fb0eaffc | bellard | gen_op_load_gpr_T0(rA(ctx->opcode)); |
2268 | fb0eaffc | bellard | gen_op_load_gpr_T1(rB(ctx->opcode)); |
2269 | 9a64fbe4 | bellard | gen_op_add(); |
2270 | fb0eaffc | bellard | } |
2271 | 9a64fbe4 | bellard | gen_op_icbi(); |
2272 | 79aceca5 | bellard | } |
2273 | 79aceca5 | bellard | |
2274 | 79aceca5 | bellard | /* Optional: */
|
2275 | 79aceca5 | bellard | /* dcba */
|
2276 | 9a64fbe4 | bellard | GEN_HANDLER(dcba, 0x1F, 0x16, 0x07, 0x03E00001, PPC_CACHE_OPT) |
2277 | 79aceca5 | bellard | { |
2278 | 79aceca5 | bellard | } |
2279 | 79aceca5 | bellard | |
2280 | 79aceca5 | bellard | /*** Segment register manipulation ***/
|
2281 | 79aceca5 | bellard | /* Supervisor only: */
|
2282 | 79aceca5 | bellard | /* mfsr */
|
2283 | 79aceca5 | bellard | GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT) |
2284 | 79aceca5 | bellard | { |
2285 | 9a64fbe4 | bellard | #if defined(CONFIG_USER_ONLY)
|
2286 | 9fddaa0c | bellard | RET_PRIVREG(ctx); |
2287 | 9a64fbe4 | bellard | #else
|
2288 | 9a64fbe4 | bellard | if (!ctx->supervisor) {
|
2289 | 9fddaa0c | bellard | RET_PRIVREG(ctx); |
2290 | 9fddaa0c | bellard | return;
|
2291 | 9a64fbe4 | bellard | } |
2292 | 9a64fbe4 | bellard | gen_op_load_sr(SR(ctx->opcode)); |
2293 | 9a64fbe4 | bellard | gen_op_store_T0_gpr(rD(ctx->opcode)); |
2294 | 9a64fbe4 | bellard | #endif
|
2295 | 79aceca5 | bellard | } |
2296 | 79aceca5 | bellard | |
2297 | 79aceca5 | bellard | /* mfsrin */
|
2298 | 9a64fbe4 | bellard | GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT) |
2299 | 79aceca5 | bellard | { |
2300 | 9a64fbe4 | bellard | #if defined(CONFIG_USER_ONLY)
|
2301 | 9fddaa0c | bellard | RET_PRIVREG(ctx); |
2302 | 9a64fbe4 | bellard | #else
|
2303 | 9a64fbe4 | bellard | if (!ctx->supervisor) {
|
2304 | 9fddaa0c | bellard | RET_PRIVREG(ctx); |
2305 | 9fddaa0c | bellard | return;
|
2306 | 9a64fbe4 | bellard | } |
2307 | 9a64fbe4 | bellard | gen_op_load_gpr_T1(rB(ctx->opcode)); |
2308 | 9a64fbe4 | bellard | gen_op_load_srin(); |
2309 | 9a64fbe4 | bellard | gen_op_store_T0_gpr(rD(ctx->opcode)); |
2310 | 9a64fbe4 | bellard | #endif
|
2311 | 79aceca5 | bellard | } |
2312 | 79aceca5 | bellard | |
2313 | 79aceca5 | bellard | /* mtsr */
|
2314 | e63c59cb | bellard | GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT) |
2315 | 79aceca5 | bellard | { |
2316 | 9a64fbe4 | bellard | #if defined(CONFIG_USER_ONLY)
|
2317 | 9fddaa0c | bellard | RET_PRIVREG(ctx); |
2318 | 9a64fbe4 | bellard | #else
|
2319 | 9a64fbe4 | bellard | if (!ctx->supervisor) {
|
2320 | 9fddaa0c | bellard | RET_PRIVREG(ctx); |
2321 | 9fddaa0c | bellard | return;
|
2322 | 9a64fbe4 | bellard | } |
2323 | 9a64fbe4 | bellard | gen_op_load_gpr_T0(rS(ctx->opcode)); |
2324 | 9a64fbe4 | bellard | gen_op_store_sr(SR(ctx->opcode)); |
2325 | 9a64fbe4 | bellard | #endif
|
2326 | 79aceca5 | bellard | } |
2327 | 79aceca5 | bellard | |
2328 | 79aceca5 | bellard | /* mtsrin */
|
2329 | 9a64fbe4 | bellard | GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT) |
2330 | 79aceca5 | bellard | { |
2331 | 9a64fbe4 | bellard | #if defined(CONFIG_USER_ONLY)
|
2332 | 9fddaa0c | bellard | RET_PRIVREG(ctx); |
2333 | 9a64fbe4 | bellard | #else
|
2334 | 9a64fbe4 | bellard | if (!ctx->supervisor) {
|
2335 | 9fddaa0c | bellard | RET_PRIVREG(ctx); |
2336 | 9fddaa0c | bellard | return;
|
2337 | 9a64fbe4 | bellard | } |
2338 | 9a64fbe4 | bellard | gen_op_load_gpr_T0(rS(ctx->opcode)); |
2339 | 9a64fbe4 | bellard | gen_op_load_gpr_T1(rB(ctx->opcode)); |
2340 | 9a64fbe4 | bellard | gen_op_store_srin(); |
2341 | 9a64fbe4 | bellard | #endif
|
2342 | 79aceca5 | bellard | } |
2343 | 79aceca5 | bellard | |
2344 | 79aceca5 | bellard | /*** Lookaside buffer management ***/
|
2345 | 79aceca5 | bellard | /* Optional & supervisor only: */
|
2346 | 79aceca5 | bellard | /* tlbia */
|
2347 | 9a64fbe4 | bellard | GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_OPT) |
2348 | 79aceca5 | bellard | { |
2349 | 9a64fbe4 | bellard | #if defined(CONFIG_USER_ONLY)
|
2350 | 9fddaa0c | bellard | RET_PRIVOPC(ctx); |
2351 | 9a64fbe4 | bellard | #else
|
2352 | 9a64fbe4 | bellard | if (!ctx->supervisor) {
|
2353 | 9fddaa0c | bellard | if (loglevel)
|
2354 | 9fddaa0c | bellard | fprintf(logfile, "%s: ! supervisor\n", __func__);
|
2355 | 9fddaa0c | bellard | RET_PRIVOPC(ctx); |
2356 | 9fddaa0c | bellard | return;
|
2357 | 9a64fbe4 | bellard | } |
2358 | 9a64fbe4 | bellard | gen_op_tlbia(); |
2359 | 4b3686fa | bellard | RET_MTMSR(ctx); |
2360 | 9a64fbe4 | bellard | #endif
|
2361 | 79aceca5 | bellard | } |
2362 | 79aceca5 | bellard | |
2363 | 79aceca5 | bellard | /* tlbie */
|
2364 | 9a64fbe4 | bellard | GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM) |
2365 | 79aceca5 | bellard | { |
2366 | 9a64fbe4 | bellard | #if defined(CONFIG_USER_ONLY)
|
2367 | 9fddaa0c | bellard | RET_PRIVOPC(ctx); |
2368 | 9a64fbe4 | bellard | #else
|
2369 | 9a64fbe4 | bellard | if (!ctx->supervisor) {
|
2370 | 9fddaa0c | bellard | RET_PRIVOPC(ctx); |
2371 | 9fddaa0c | bellard | return;
|
2372 | 9a64fbe4 | bellard | } |
2373 | 9a64fbe4 | bellard | gen_op_load_gpr_T0(rB(ctx->opcode)); |
2374 | 9a64fbe4 | bellard | gen_op_tlbie(); |
2375 | 4b3686fa | bellard | RET_MTMSR(ctx); |
2376 | 9a64fbe4 | bellard | #endif
|
2377 | 79aceca5 | bellard | } |
2378 | 79aceca5 | bellard | |
2379 | 79aceca5 | bellard | /* tlbsync */
|
2380 | e63c59cb | bellard | GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM) |
2381 | 79aceca5 | bellard | { |
2382 | 9a64fbe4 | bellard | #if defined(CONFIG_USER_ONLY)
|
2383 | 9fddaa0c | bellard | RET_PRIVOPC(ctx); |
2384 | 9a64fbe4 | bellard | #else
|
2385 | 9a64fbe4 | bellard | if (!ctx->supervisor) {
|
2386 | 9fddaa0c | bellard | RET_PRIVOPC(ctx); |
2387 | 9fddaa0c | bellard | return;
|
2388 | 9a64fbe4 | bellard | } |
2389 | 9a64fbe4 | bellard | /* This has no effect: it should ensure that all previous
|
2390 | 9a64fbe4 | bellard | * tlbie have completed
|
2391 | 9a64fbe4 | bellard | */
|
2392 | 4b3686fa | bellard | RET_MTMSR(ctx); |
2393 | 9a64fbe4 | bellard | #endif
|
2394 | 79aceca5 | bellard | } |
2395 | 79aceca5 | bellard | |
2396 | 79aceca5 | bellard | /*** External control ***/
|
2397 | 79aceca5 | bellard | /* Optional: */
|
2398 | 79aceca5 | bellard | /* eciwx */
|
2399 | 9a64fbe4 | bellard | #if defined(CONFIG_USER_ONLY)
|
2400 | 9a64fbe4 | bellard | #define op_eciwx() gen_op_eciwx_raw()
|
2401 | 9a64fbe4 | bellard | #define op_ecowx() gen_op_ecowx_raw()
|
2402 | 9a64fbe4 | bellard | #else
|
2403 | 9a64fbe4 | bellard | #define op_eciwx() (*gen_op_eciwx[ctx->mem_idx])()
|
2404 | 9a64fbe4 | bellard | #define op_ecowx() (*gen_op_ecowx[ctx->mem_idx])()
|
2405 | 9a64fbe4 | bellard | static GenOpFunc *gen_op_eciwx[] = {
|
2406 | 9a64fbe4 | bellard | &gen_op_eciwx_user, |
2407 | 9a64fbe4 | bellard | &gen_op_eciwx_kernel, |
2408 | 9a64fbe4 | bellard | }; |
2409 | 9a64fbe4 | bellard | static GenOpFunc *gen_op_ecowx[] = {
|
2410 | 9a64fbe4 | bellard | &gen_op_ecowx_user, |
2411 | 9a64fbe4 | bellard | &gen_op_ecowx_kernel, |
2412 | 9a64fbe4 | bellard | }; |
2413 | 9a64fbe4 | bellard | #endif
|
2414 | 9a64fbe4 | bellard | |
2415 | 79aceca5 | bellard | GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN) |
2416 | 79aceca5 | bellard | { |
2417 | 9a64fbe4 | bellard | /* Should check EAR[E] & alignment ! */
|
2418 | 9a64fbe4 | bellard | if (rA(ctx->opcode) == 0) { |
2419 | 9a64fbe4 | bellard | gen_op_load_gpr_T0(rB(ctx->opcode)); |
2420 | 9a64fbe4 | bellard | } else {
|
2421 | 9a64fbe4 | bellard | gen_op_load_gpr_T0(rA(ctx->opcode)); |
2422 | 9a64fbe4 | bellard | gen_op_load_gpr_T1(rB(ctx->opcode)); |
2423 | 9a64fbe4 | bellard | gen_op_add(); |
2424 | 9a64fbe4 | bellard | } |
2425 | 9a64fbe4 | bellard | op_eciwx(); |
2426 | 9a64fbe4 | bellard | gen_op_store_T0_gpr(rD(ctx->opcode)); |
2427 | 79aceca5 | bellard | } |
2428 | 79aceca5 | bellard | |
2429 | 79aceca5 | bellard | /* ecowx */
|
2430 | 79aceca5 | bellard | GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN) |
2431 | 79aceca5 | bellard | { |
2432 | 9a64fbe4 | bellard | /* Should check EAR[E] & alignment ! */
|
2433 | 9a64fbe4 | bellard | if (rA(ctx->opcode) == 0) { |
2434 | 9a64fbe4 | bellard | gen_op_load_gpr_T0(rB(ctx->opcode)); |
2435 | 9a64fbe4 | bellard | } else {
|
2436 | 9a64fbe4 | bellard | gen_op_load_gpr_T0(rA(ctx->opcode)); |
2437 | 9a64fbe4 | bellard | gen_op_load_gpr_T1(rB(ctx->opcode)); |
2438 | 9a64fbe4 | bellard | gen_op_add(); |
2439 | 9a64fbe4 | bellard | } |
2440 | 9a64fbe4 | bellard | gen_op_load_gpr_T2(rS(ctx->opcode)); |
2441 | 9a64fbe4 | bellard | op_ecowx(); |
2442 | 79aceca5 | bellard | } |
2443 | 79aceca5 | bellard | |
2444 | 79aceca5 | bellard | /* End opcode list */
|
2445 | 79aceca5 | bellard | GEN_OPCODE_MARK(end); |
2446 | 79aceca5 | bellard | |
2447 | 79aceca5 | bellard | /*****************************************************************************/
|
2448 | 9a64fbe4 | bellard | #include <stdlib.h> |
2449 | 79aceca5 | bellard | #include <string.h> |
2450 | 9a64fbe4 | bellard | |
2451 | 9a64fbe4 | bellard | int fflush (FILE *stream);
|
2452 | 79aceca5 | bellard | |
2453 | 79aceca5 | bellard | /* Main ppc opcodes table:
|
2454 | 79aceca5 | bellard | * at init, all opcodes are invalids
|
2455 | 79aceca5 | bellard | */
|
2456 | 79aceca5 | bellard | static opc_handler_t *ppc_opcodes[0x40]; |
2457 | 79aceca5 | bellard | |
2458 | 79aceca5 | bellard | /* Opcode types */
|
2459 | 79aceca5 | bellard | enum {
|
2460 | 79aceca5 | bellard | PPC_DIRECT = 0, /* Opcode routine */ |
2461 | 79aceca5 | bellard | PPC_INDIRECT = 1, /* Indirect opcode table */ |
2462 | 79aceca5 | bellard | }; |
2463 | 79aceca5 | bellard | |
2464 | 79aceca5 | bellard | static inline int is_indirect_opcode (void *handler) |
2465 | 79aceca5 | bellard | { |
2466 | 79aceca5 | bellard | return ((unsigned long)handler & 0x03) == PPC_INDIRECT; |
2467 | 79aceca5 | bellard | } |
2468 | 79aceca5 | bellard | |
2469 | 79aceca5 | bellard | static inline opc_handler_t **ind_table(void *handler) |
2470 | 79aceca5 | bellard | { |
2471 | 79aceca5 | bellard | return (opc_handler_t **)((unsigned long)handler & ~3); |
2472 | 79aceca5 | bellard | } |
2473 | 79aceca5 | bellard | |
2474 | 9a64fbe4 | bellard | /* Instruction table creation */
|
2475 | 79aceca5 | bellard | /* Opcodes tables creation */
|
2476 | 79aceca5 | bellard | static void fill_new_table (opc_handler_t **table, int len) |
2477 | 79aceca5 | bellard | { |
2478 | 79aceca5 | bellard | int i;
|
2479 | 79aceca5 | bellard | |
2480 | 79aceca5 | bellard | for (i = 0; i < len; i++) |
2481 | 79aceca5 | bellard | table[i] = &invalid_handler; |
2482 | 79aceca5 | bellard | } |
2483 | 79aceca5 | bellard | |
2484 | 79aceca5 | bellard | static int create_new_table (opc_handler_t **table, unsigned char idx) |
2485 | 79aceca5 | bellard | { |
2486 | 79aceca5 | bellard | opc_handler_t **tmp; |
2487 | 79aceca5 | bellard | |
2488 | 79aceca5 | bellard | tmp = malloc(0x20 * sizeof(opc_handler_t)); |
2489 | 79aceca5 | bellard | if (tmp == NULL) |
2490 | 79aceca5 | bellard | return -1; |
2491 | 79aceca5 | bellard | fill_new_table(tmp, 0x20);
|
2492 | 79aceca5 | bellard | table[idx] = (opc_handler_t *)((unsigned long)tmp | PPC_INDIRECT); |
2493 | 79aceca5 | bellard | |
2494 | 79aceca5 | bellard | return 0; |
2495 | 79aceca5 | bellard | } |
2496 | 79aceca5 | bellard | |
2497 | 79aceca5 | bellard | static int insert_in_table (opc_handler_t **table, unsigned char idx, |
2498 | 79aceca5 | bellard | opc_handler_t *handler) |
2499 | 79aceca5 | bellard | { |
2500 | 79aceca5 | bellard | if (table[idx] != &invalid_handler)
|
2501 | 79aceca5 | bellard | return -1; |
2502 | 79aceca5 | bellard | table[idx] = handler; |
2503 | 79aceca5 | bellard | |
2504 | 79aceca5 | bellard | return 0; |
2505 | 79aceca5 | bellard | } |
2506 | 79aceca5 | bellard | |
2507 | 9a64fbe4 | bellard | static int register_direct_insn (opc_handler_t **ppc_opcodes, |
2508 | 9a64fbe4 | bellard | unsigned char idx, opc_handler_t *handler) |
2509 | 79aceca5 | bellard | { |
2510 | 79aceca5 | bellard | if (insert_in_table(ppc_opcodes, idx, handler) < 0) { |
2511 | 9a64fbe4 | bellard | printf("*** ERROR: opcode %02x already assigned in main "
|
2512 | 79aceca5 | bellard | "opcode table\n", idx);
|
2513 | 79aceca5 | bellard | return -1; |
2514 | 79aceca5 | bellard | } |
2515 | 79aceca5 | bellard | |
2516 | 79aceca5 | bellard | return 0; |
2517 | 79aceca5 | bellard | } |
2518 | 79aceca5 | bellard | |
2519 | 79aceca5 | bellard | static int register_ind_in_table (opc_handler_t **table, |
2520 | 79aceca5 | bellard | unsigned char idx1, unsigned char idx2, |
2521 | 79aceca5 | bellard | opc_handler_t *handler) |
2522 | 79aceca5 | bellard | { |
2523 | 79aceca5 | bellard | if (table[idx1] == &invalid_handler) {
|
2524 | 79aceca5 | bellard | if (create_new_table(table, idx1) < 0) { |
2525 | 9a64fbe4 | bellard | printf("*** ERROR: unable to create indirect table "
|
2526 | 79aceca5 | bellard | "idx=%02x\n", idx1);
|
2527 | 79aceca5 | bellard | return -1; |
2528 | 79aceca5 | bellard | } |
2529 | 79aceca5 | bellard | } else {
|
2530 | 79aceca5 | bellard | if (!is_indirect_opcode(table[idx1])) {
|
2531 | 9a64fbe4 | bellard | printf("*** ERROR: idx %02x already assigned to a direct "
|
2532 | 79aceca5 | bellard | "opcode\n", idx1);
|
2533 | 79aceca5 | bellard | return -1; |
2534 | 79aceca5 | bellard | } |
2535 | 79aceca5 | bellard | } |
2536 | 79aceca5 | bellard | if (handler != NULL && |
2537 | 79aceca5 | bellard | insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
|
2538 | 9a64fbe4 | bellard | printf("*** ERROR: opcode %02x already assigned in "
|
2539 | 79aceca5 | bellard | "opcode table %02x\n", idx2, idx1);
|
2540 | 79aceca5 | bellard | return -1; |
2541 | 79aceca5 | bellard | } |
2542 | 79aceca5 | bellard | |
2543 | 79aceca5 | bellard | return 0; |
2544 | 79aceca5 | bellard | } |
2545 | 79aceca5 | bellard | |
2546 | 9a64fbe4 | bellard | static int register_ind_insn (opc_handler_t **ppc_opcodes, |
2547 | 9a64fbe4 | bellard | unsigned char idx1, unsigned char idx2, |
2548 | 79aceca5 | bellard | opc_handler_t *handler) |
2549 | 79aceca5 | bellard | { |
2550 | 79aceca5 | bellard | int ret;
|
2551 | 79aceca5 | bellard | |
2552 | 79aceca5 | bellard | ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler); |
2553 | 79aceca5 | bellard | |
2554 | 79aceca5 | bellard | return ret;
|
2555 | 79aceca5 | bellard | } |
2556 | 79aceca5 | bellard | |
2557 | 9a64fbe4 | bellard | static int register_dblind_insn (opc_handler_t **ppc_opcodes, |
2558 | 9a64fbe4 | bellard | unsigned char idx1, unsigned char idx2, |
2559 | 79aceca5 | bellard | unsigned char idx3, opc_handler_t *handler) |
2560 | 79aceca5 | bellard | { |
2561 | 79aceca5 | bellard | if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { |
2562 | 9a64fbe4 | bellard | printf("*** ERROR: unable to join indirect table idx "
|
2563 | 79aceca5 | bellard | "[%02x-%02x]\n", idx1, idx2);
|
2564 | 79aceca5 | bellard | return -1; |
2565 | 79aceca5 | bellard | } |
2566 | 79aceca5 | bellard | if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
|
2567 | 79aceca5 | bellard | handler) < 0) {
|
2568 | 9a64fbe4 | bellard | printf("*** ERROR: unable to insert opcode "
|
2569 | 79aceca5 | bellard | "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
|
2570 | 79aceca5 | bellard | return -1; |
2571 | 79aceca5 | bellard | } |
2572 | 79aceca5 | bellard | |
2573 | 79aceca5 | bellard | return 0; |
2574 | 79aceca5 | bellard | } |
2575 | 79aceca5 | bellard | |
2576 | 9a64fbe4 | bellard | static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn) |
2577 | 79aceca5 | bellard | { |
2578 | 79aceca5 | bellard | if (insn->opc2 != 0xFF) { |
2579 | 79aceca5 | bellard | if (insn->opc3 != 0xFF) { |
2580 | 9a64fbe4 | bellard | if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
|
2581 | 9a64fbe4 | bellard | insn->opc3, &insn->handler) < 0)
|
2582 | 79aceca5 | bellard | return -1; |
2583 | 79aceca5 | bellard | } else {
|
2584 | 9a64fbe4 | bellard | if (register_ind_insn(ppc_opcodes, insn->opc1,
|
2585 | 9a64fbe4 | bellard | insn->opc2, &insn->handler) < 0)
|
2586 | 79aceca5 | bellard | return -1; |
2587 | 79aceca5 | bellard | } |
2588 | 79aceca5 | bellard | } else {
|
2589 | 9a64fbe4 | bellard | if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0) |
2590 | 79aceca5 | bellard | return -1; |
2591 | 79aceca5 | bellard | } |
2592 | 79aceca5 | bellard | |
2593 | 79aceca5 | bellard | return 0; |
2594 | 79aceca5 | bellard | } |
2595 | 79aceca5 | bellard | |
2596 | 79aceca5 | bellard | static int test_opcode_table (opc_handler_t **table, int len) |
2597 | 79aceca5 | bellard | { |
2598 | 79aceca5 | bellard | int i, count, tmp;
|
2599 | 79aceca5 | bellard | |
2600 | 79aceca5 | bellard | for (i = 0, count = 0; i < len; i++) { |
2601 | 79aceca5 | bellard | /* Consistency fixup */
|
2602 | 79aceca5 | bellard | if (table[i] == NULL) |
2603 | 79aceca5 | bellard | table[i] = &invalid_handler; |
2604 | 79aceca5 | bellard | if (table[i] != &invalid_handler) {
|
2605 | 79aceca5 | bellard | if (is_indirect_opcode(table[i])) {
|
2606 | 79aceca5 | bellard | tmp = test_opcode_table(ind_table(table[i]), 0x20);
|
2607 | 79aceca5 | bellard | if (tmp == 0) { |
2608 | 79aceca5 | bellard | free(table[i]); |
2609 | 79aceca5 | bellard | table[i] = &invalid_handler; |
2610 | 79aceca5 | bellard | } else {
|
2611 | 79aceca5 | bellard | count++; |
2612 | 79aceca5 | bellard | } |
2613 | 79aceca5 | bellard | } else {
|
2614 | 79aceca5 | bellard | count++; |
2615 | 79aceca5 | bellard | } |
2616 | 79aceca5 | bellard | } |
2617 | 79aceca5 | bellard | } |
2618 | 79aceca5 | bellard | |
2619 | 79aceca5 | bellard | return count;
|
2620 | 79aceca5 | bellard | } |
2621 | 79aceca5 | bellard | |
2622 | 9a64fbe4 | bellard | static void fix_opcode_tables (opc_handler_t **ppc_opcodes) |
2623 | 79aceca5 | bellard | { |
2624 | 79aceca5 | bellard | if (test_opcode_table(ppc_opcodes, 0x40) == 0) |
2625 | 9a64fbe4 | bellard | printf("*** WARNING: no opcode defined !\n");
|
2626 | 79aceca5 | bellard | } |
2627 | 79aceca5 | bellard | |
2628 | 9a64fbe4 | bellard | #define SPR_RIGHTS(rw, priv) (1 << ((2 * (priv)) + (rw))) |
2629 | 79aceca5 | bellard | #define SPR_UR SPR_RIGHTS(0, 0) |
2630 | 79aceca5 | bellard | #define SPR_UW SPR_RIGHTS(1, 0) |
2631 | 79aceca5 | bellard | #define SPR_SR SPR_RIGHTS(0, 1) |
2632 | 79aceca5 | bellard | #define SPR_SW SPR_RIGHTS(1, 1) |
2633 | 79aceca5 | bellard | |
2634 | 79aceca5 | bellard | #define spr_set_rights(spr, rights) \
|
2635 | 79aceca5 | bellard | do { \
|
2636 | 79aceca5 | bellard | spr_access[(spr) >> 1] |= ((rights) << (4 * ((spr) & 1))); \ |
2637 | 79aceca5 | bellard | } while (0) |
2638 | 79aceca5 | bellard | |
2639 | 9a64fbe4 | bellard | static void init_spr_rights (uint32_t pvr) |
2640 | 79aceca5 | bellard | { |
2641 | 79aceca5 | bellard | /* XER (SPR 1) */
|
2642 | 9a64fbe4 | bellard | spr_set_rights(XER, SPR_UR | SPR_UW | SPR_SR | SPR_SW); |
2643 | 79aceca5 | bellard | /* LR (SPR 8) */
|
2644 | 9a64fbe4 | bellard | spr_set_rights(LR, SPR_UR | SPR_UW | SPR_SR | SPR_SW); |
2645 | 79aceca5 | bellard | /* CTR (SPR 9) */
|
2646 | 9a64fbe4 | bellard | spr_set_rights(CTR, SPR_UR | SPR_UW | SPR_SR | SPR_SW); |
2647 | 79aceca5 | bellard | /* TBL (SPR 268) */
|
2648 | 9a64fbe4 | bellard | spr_set_rights(V_TBL, SPR_UR | SPR_SR); |
2649 | 79aceca5 | bellard | /* TBU (SPR 269) */
|
2650 | 9a64fbe4 | bellard | spr_set_rights(V_TBU, SPR_UR | SPR_SR); |
2651 | 79aceca5 | bellard | /* DSISR (SPR 18) */
|
2652 | 9a64fbe4 | bellard | spr_set_rights(DSISR, SPR_SR | SPR_SW); |
2653 | 79aceca5 | bellard | /* DAR (SPR 19) */
|
2654 | 9a64fbe4 | bellard | spr_set_rights(DAR, SPR_SR | SPR_SW); |
2655 | 79aceca5 | bellard | /* DEC (SPR 22) */
|
2656 | 9a64fbe4 | bellard | spr_set_rights(DECR, SPR_SR | SPR_SW); |
2657 | 79aceca5 | bellard | /* SDR1 (SPR 25) */
|
2658 | 9a64fbe4 | bellard | spr_set_rights(SDR1, SPR_SR | SPR_SW); |
2659 | 9a64fbe4 | bellard | /* SRR0 (SPR 26) */
|
2660 | 9a64fbe4 | bellard | spr_set_rights(SRR0, SPR_SR | SPR_SW); |
2661 | 9a64fbe4 | bellard | /* SRR1 (SPR 27) */
|
2662 | 9a64fbe4 | bellard | spr_set_rights(SRR1, SPR_SR | SPR_SW); |
2663 | 79aceca5 | bellard | /* SPRG0 (SPR 272) */
|
2664 | 9a64fbe4 | bellard | spr_set_rights(SPRG0, SPR_SR | SPR_SW); |
2665 | 79aceca5 | bellard | /* SPRG1 (SPR 273) */
|
2666 | 9a64fbe4 | bellard | spr_set_rights(SPRG1, SPR_SR | SPR_SW); |
2667 | 79aceca5 | bellard | /* SPRG2 (SPR 274) */
|
2668 | 9a64fbe4 | bellard | spr_set_rights(SPRG2, SPR_SR | SPR_SW); |
2669 | 79aceca5 | bellard | /* SPRG3 (SPR 275) */
|
2670 | 9a64fbe4 | bellard | spr_set_rights(SPRG3, SPR_SR | SPR_SW); |
2671 | 79aceca5 | bellard | /* ASR (SPR 280) */
|
2672 | 9a64fbe4 | bellard | spr_set_rights(ASR, SPR_SR | SPR_SW); |
2673 | 79aceca5 | bellard | /* EAR (SPR 282) */
|
2674 | 9a64fbe4 | bellard | spr_set_rights(EAR, SPR_SR | SPR_SW); |
2675 | 9a64fbe4 | bellard | /* TBL (SPR 284) */
|
2676 | 9a64fbe4 | bellard | spr_set_rights(O_TBL, SPR_SW); |
2677 | 9a64fbe4 | bellard | /* TBU (SPR 285) */
|
2678 | 9a64fbe4 | bellard | spr_set_rights(O_TBU, SPR_SW); |
2679 | 9a64fbe4 | bellard | /* PVR (SPR 287) */
|
2680 | 9a64fbe4 | bellard | spr_set_rights(PVR, SPR_SR); |
2681 | 79aceca5 | bellard | /* IBAT0U (SPR 528) */
|
2682 | 9a64fbe4 | bellard | spr_set_rights(IBAT0U, SPR_SR | SPR_SW); |
2683 | 79aceca5 | bellard | /* IBAT0L (SPR 529) */
|
2684 | 9a64fbe4 | bellard | spr_set_rights(IBAT0L, SPR_SR | SPR_SW); |
2685 | 79aceca5 | bellard | /* IBAT1U (SPR 530) */
|
2686 | 9a64fbe4 | bellard | spr_set_rights(IBAT1U, SPR_SR | SPR_SW); |
2687 | 79aceca5 | bellard | /* IBAT1L (SPR 531) */
|
2688 | 9a64fbe4 | bellard | spr_set_rights(IBAT1L, SPR_SR | SPR_SW); |
2689 | 79aceca5 | bellard | /* IBAT2U (SPR 532) */
|
2690 | 9a64fbe4 | bellard | spr_set_rights(IBAT2U, SPR_SR | SPR_SW); |
2691 | 79aceca5 | bellard | /* IBAT2L (SPR 533) */
|
2692 | 9a64fbe4 | bellard | spr_set_rights(IBAT2L, SPR_SR | SPR_SW); |
2693 | 79aceca5 | bellard | /* IBAT3U (SPR 534) */
|
2694 | 9a64fbe4 | bellard | spr_set_rights(IBAT3U, SPR_SR | SPR_SW); |
2695 | 79aceca5 | bellard | /* IBAT3L (SPR 535) */
|
2696 | 9a64fbe4 | bellard | spr_set_rights(IBAT3L, SPR_SR | SPR_SW); |
2697 | 79aceca5 | bellard | /* DBAT0U (SPR 536) */
|
2698 | 9a64fbe4 | bellard | spr_set_rights(DBAT0U, SPR_SR | SPR_SW); |
2699 | 79aceca5 | bellard | /* DBAT0L (SPR 537) */
|
2700 | 9a64fbe4 | bellard | spr_set_rights(DBAT0L, SPR_SR | SPR_SW); |
2701 | 79aceca5 | bellard | /* DBAT1U (SPR 538) */
|
2702 | 9a64fbe4 | bellard | spr_set_rights(DBAT1U, SPR_SR | SPR_SW); |
2703 | 79aceca5 | bellard | /* DBAT1L (SPR 539) */
|
2704 | 9a64fbe4 | bellard | spr_set_rights(DBAT1L, SPR_SR | SPR_SW); |
2705 | 79aceca5 | bellard | /* DBAT2U (SPR 540) */
|
2706 | 9a64fbe4 | bellard | spr_set_rights(DBAT2U, SPR_SR | SPR_SW); |
2707 | 79aceca5 | bellard | /* DBAT2L (SPR 541) */
|
2708 | 9a64fbe4 | bellard | spr_set_rights(DBAT2L, SPR_SR | SPR_SW); |
2709 | 79aceca5 | bellard | /* DBAT3U (SPR 542) */
|
2710 | 9a64fbe4 | bellard | spr_set_rights(DBAT3U, SPR_SR | SPR_SW); |
2711 | 79aceca5 | bellard | /* DBAT3L (SPR 543) */
|
2712 | 9a64fbe4 | bellard | spr_set_rights(DBAT3L, SPR_SR | SPR_SW); |
2713 | 79aceca5 | bellard | /* FPECR (SPR 1022) */
|
2714 | 9a64fbe4 | bellard | spr_set_rights(FPECR, SPR_SR | SPR_SW); |
2715 | 4b3686fa | bellard | /* Special registers for PPC 604 */
|
2716 | 4b3686fa | bellard | if ((pvr & 0xFFFF0000) == 0x00040000) { |
2717 | 4b3686fa | bellard | /* IABR */
|
2718 | 4b3686fa | bellard | spr_set_rights(IABR , SPR_SR | SPR_SW); |
2719 | 4b3686fa | bellard | /* DABR (SPR 1013) */
|
2720 | 4b3686fa | bellard | spr_set_rights(DABR, SPR_SR | SPR_SW); |
2721 | 4b3686fa | bellard | /* HID0 */
|
2722 | 4b3686fa | bellard | spr_set_rights(HID0, SPR_SR | SPR_SW); |
2723 | 4b3686fa | bellard | /* PIR */
|
2724 | 9a64fbe4 | bellard | spr_set_rights(PIR, SPR_SR | SPR_SW); |
2725 | 4b3686fa | bellard | /* PMC1 */
|
2726 | 4b3686fa | bellard | spr_set_rights(PMC1, SPR_SR | SPR_SW); |
2727 | 4b3686fa | bellard | /* PMC2 */
|
2728 | 4b3686fa | bellard | spr_set_rights(PMC2, SPR_SR | SPR_SW); |
2729 | 4b3686fa | bellard | /* MMCR0 */
|
2730 | 4b3686fa | bellard | spr_set_rights(MMCR0, SPR_SR | SPR_SW); |
2731 | 4b3686fa | bellard | /* SIA */
|
2732 | 4b3686fa | bellard | spr_set_rights(SIA, SPR_SR | SPR_SW); |
2733 | 4b3686fa | bellard | /* SDA */
|
2734 | 4b3686fa | bellard | spr_set_rights(SDA, SPR_SR | SPR_SW); |
2735 | 4b3686fa | bellard | } |
2736 | 9a64fbe4 | bellard | /* Special registers for MPC740/745/750/755 (aka G3) & IBM 750 */
|
2737 | 9a64fbe4 | bellard | if ((pvr & 0xFFFF0000) == 0x00080000 || |
2738 | 9a64fbe4 | bellard | (pvr & 0xFFFF0000) == 0x70000000) { |
2739 | 9a64fbe4 | bellard | /* HID0 */
|
2740 | 4b3686fa | bellard | spr_set_rights(HID0, SPR_SR | SPR_SW); |
2741 | 9a64fbe4 | bellard | /* HID1 */
|
2742 | 4b3686fa | bellard | spr_set_rights(HID1, SPR_SR | SPR_SW); |
2743 | 9a64fbe4 | bellard | /* IABR */
|
2744 | 4b3686fa | bellard | spr_set_rights(IABR, SPR_SR | SPR_SW); |
2745 | 9a64fbe4 | bellard | /* ICTC */
|
2746 | 4b3686fa | bellard | spr_set_rights(ICTC, SPR_SR | SPR_SW); |
2747 | 9a64fbe4 | bellard | /* L2CR */
|
2748 | 4b3686fa | bellard | spr_set_rights(L2CR, SPR_SR | SPR_SW); |
2749 | 9a64fbe4 | bellard | /* MMCR0 */
|
2750 | 4b3686fa | bellard | spr_set_rights(MMCR0, SPR_SR | SPR_SW); |
2751 | 9a64fbe4 | bellard | /* MMCR1 */
|
2752 | 4b3686fa | bellard | spr_set_rights(MMCR1, SPR_SR | SPR_SW); |
2753 | 9a64fbe4 | bellard | /* PMC1 */
|
2754 | 4b3686fa | bellard | spr_set_rights(PMC1, SPR_SR | SPR_SW); |
2755 | 9a64fbe4 | bellard | /* PMC2 */
|
2756 | 4b3686fa | bellard | spr_set_rights(PMC2, SPR_SR | SPR_SW); |
2757 | 9a64fbe4 | bellard | /* PMC3 */
|
2758 | 4b3686fa | bellard | spr_set_rights(PMC3, SPR_SR | SPR_SW); |
2759 | 9a64fbe4 | bellard | /* PMC4 */
|
2760 | 4b3686fa | bellard | spr_set_rights(PMC4, SPR_SR | SPR_SW); |
2761 | 9a64fbe4 | bellard | /* SIA */
|
2762 | 4b3686fa | bellard | spr_set_rights(SIA, SPR_SR | SPR_SW); |
2763 | 4b3686fa | bellard | /* SDA */
|
2764 | 4b3686fa | bellard | spr_set_rights(SDA, SPR_SR | SPR_SW); |
2765 | 9a64fbe4 | bellard | /* THRM1 */
|
2766 | 4b3686fa | bellard | spr_set_rights(THRM1, SPR_SR | SPR_SW); |
2767 | 9a64fbe4 | bellard | /* THRM2 */
|
2768 | 4b3686fa | bellard | spr_set_rights(THRM2, SPR_SR | SPR_SW); |
2769 | 9a64fbe4 | bellard | /* THRM3 */
|
2770 | 4b3686fa | bellard | spr_set_rights(THRM3, SPR_SR | SPR_SW); |
2771 | 9a64fbe4 | bellard | /* UMMCR0 */
|
2772 | 4b3686fa | bellard | spr_set_rights(UMMCR0, SPR_UR | SPR_UW); |
2773 | 9a64fbe4 | bellard | /* UMMCR1 */
|
2774 | 4b3686fa | bellard | spr_set_rights(UMMCR1, SPR_UR | SPR_UW); |
2775 | 9a64fbe4 | bellard | /* UPMC1 */
|
2776 | 4b3686fa | bellard | spr_set_rights(UPMC1, SPR_UR | SPR_UW); |
2777 | 9a64fbe4 | bellard | /* UPMC2 */
|
2778 | 4b3686fa | bellard | spr_set_rights(UPMC2, SPR_UR | SPR_UW); |
2779 | 9a64fbe4 | bellard | /* UPMC3 */
|
2780 | 4b3686fa | bellard | spr_set_rights(UPMC3, SPR_UR | SPR_UW); |
2781 | 9a64fbe4 | bellard | /* UPMC4 */
|
2782 | 4b3686fa | bellard | spr_set_rights(UPMC4, SPR_UR | SPR_UW); |
2783 | 9a64fbe4 | bellard | /* USIA */
|
2784 | 4b3686fa | bellard | spr_set_rights(USIA, SPR_UR | SPR_UW); |
2785 | 9a64fbe4 | bellard | } |
2786 | 9a64fbe4 | bellard | /* MPC755 has special registers */
|
2787 | 9a64fbe4 | bellard | if (pvr == 0x00083100) { |
2788 | 9a64fbe4 | bellard | /* SPRG4 */
|
2789 | 9a64fbe4 | bellard | spr_set_rights(SPRG4, SPR_SR | SPR_SW); |
2790 | 9a64fbe4 | bellard | /* SPRG5 */
|
2791 | 9a64fbe4 | bellard | spr_set_rights(SPRG5, SPR_SR | SPR_SW); |
2792 | 9a64fbe4 | bellard | /* SPRG6 */
|
2793 | 9a64fbe4 | bellard | spr_set_rights(SPRG6, SPR_SR | SPR_SW); |
2794 | 9a64fbe4 | bellard | /* SPRG7 */
|
2795 | 9a64fbe4 | bellard | spr_set_rights(SPRG7, SPR_SR | SPR_SW); |
2796 | 9a64fbe4 | bellard | /* IBAT4U */
|
2797 | 9a64fbe4 | bellard | spr_set_rights(IBAT4U, SPR_SR | SPR_SW); |
2798 | 9a64fbe4 | bellard | /* IBAT4L */
|
2799 | 9a64fbe4 | bellard | spr_set_rights(IBAT4L, SPR_SR | SPR_SW); |
2800 | 9a64fbe4 | bellard | /* IBAT5U */
|
2801 | 9a64fbe4 | bellard | spr_set_rights(IBAT5U, SPR_SR | SPR_SW); |
2802 | 9a64fbe4 | bellard | /* IBAT5L */
|
2803 | 9a64fbe4 | bellard | spr_set_rights(IBAT5L, SPR_SR | SPR_SW); |
2804 | 9a64fbe4 | bellard | /* IBAT6U */
|
2805 | 9a64fbe4 | bellard | spr_set_rights(IBAT6U, SPR_SR | SPR_SW); |
2806 | 9a64fbe4 | bellard | /* IBAT6L */
|
2807 | 9a64fbe4 | bellard | spr_set_rights(IBAT6L, SPR_SR | SPR_SW); |
2808 | 9a64fbe4 | bellard | /* IBAT7U */
|
2809 | 9a64fbe4 | bellard | spr_set_rights(IBAT7U, SPR_SR | SPR_SW); |
2810 | 9a64fbe4 | bellard | /* IBAT7L */
|
2811 | 9a64fbe4 | bellard | spr_set_rights(IBAT7L, SPR_SR | SPR_SW); |
2812 | 9a64fbe4 | bellard | /* DBAT4U */
|
2813 | 9a64fbe4 | bellard | spr_set_rights(DBAT4U, SPR_SR | SPR_SW); |
2814 | 9a64fbe4 | bellard | /* DBAT4L */
|
2815 | 9a64fbe4 | bellard | spr_set_rights(DBAT4L, SPR_SR | SPR_SW); |
2816 | 9a64fbe4 | bellard | /* DBAT5U */
|
2817 | 9a64fbe4 | bellard | spr_set_rights(DBAT5U, SPR_SR | SPR_SW); |
2818 | 9a64fbe4 | bellard | /* DBAT5L */
|
2819 | 9a64fbe4 | bellard | spr_set_rights(DBAT5L, SPR_SR | SPR_SW); |
2820 | 9a64fbe4 | bellard | /* DBAT6U */
|
2821 | 9a64fbe4 | bellard | spr_set_rights(DBAT6U, SPR_SR | SPR_SW); |
2822 | 9a64fbe4 | bellard | /* DBAT6L */
|
2823 | 9a64fbe4 | bellard | spr_set_rights(DBAT6L, SPR_SR | SPR_SW); |
2824 | 9a64fbe4 | bellard | /* DBAT7U */
|
2825 | 9a64fbe4 | bellard | spr_set_rights(DBAT7U, SPR_SR | SPR_SW); |
2826 | 9a64fbe4 | bellard | /* DBAT7L */
|
2827 | 9a64fbe4 | bellard | spr_set_rights(DBAT7L, SPR_SR | SPR_SW); |
2828 | 9a64fbe4 | bellard | /* DMISS */
|
2829 | 4b3686fa | bellard | spr_set_rights(DMISS, SPR_SR | SPR_SW); |
2830 | 9a64fbe4 | bellard | /* DCMP */
|
2831 | 4b3686fa | bellard | spr_set_rights(DCMP, SPR_SR | SPR_SW); |
2832 | 9a64fbe4 | bellard | /* DHASH1 */
|
2833 | 4b3686fa | bellard | spr_set_rights(DHASH1, SPR_SR | SPR_SW); |
2834 | 9a64fbe4 | bellard | /* DHASH2 */
|
2835 | 4b3686fa | bellard | spr_set_rights(DHASH2, SPR_SR | SPR_SW); |
2836 | 9a64fbe4 | bellard | /* IMISS */
|
2837 | 4b3686fa | bellard | spr_set_rights(IMISS, SPR_SR | SPR_SW); |
2838 | 9a64fbe4 | bellard | /* ICMP */
|
2839 | 4b3686fa | bellard | spr_set_rights(ICMP, SPR_SR | SPR_SW); |
2840 | 9a64fbe4 | bellard | /* RPA */
|
2841 | 4b3686fa | bellard | spr_set_rights(RPA, SPR_SR | SPR_SW); |
2842 | 9a64fbe4 | bellard | /* HID2 */
|
2843 | 4b3686fa | bellard | spr_set_rights(HID2, SPR_SR | SPR_SW); |
2844 | 9a64fbe4 | bellard | /* L2PM */
|
2845 | 4b3686fa | bellard | spr_set_rights(L2PM, SPR_SR | SPR_SW); |
2846 | 9a64fbe4 | bellard | } |
2847 | 79aceca5 | bellard | } |
2848 | 79aceca5 | bellard | |
2849 | 9a64fbe4 | bellard | /*****************************************************************************/
|
2850 | 9a64fbe4 | bellard | /* PPC "main stream" common instructions (no optional ones) */
|
2851 | 79aceca5 | bellard | |
2852 | 79aceca5 | bellard | typedef struct ppc_proc_t { |
2853 | 79aceca5 | bellard | int flags;
|
2854 | 79aceca5 | bellard | void *specific;
|
2855 | 79aceca5 | bellard | } ppc_proc_t; |
2856 | 79aceca5 | bellard | |
2857 | 79aceca5 | bellard | typedef struct ppc_def_t { |
2858 | 79aceca5 | bellard | unsigned long pvr; |
2859 | 79aceca5 | bellard | unsigned long pvr_mask; |
2860 | 79aceca5 | bellard | ppc_proc_t *proc; |
2861 | 79aceca5 | bellard | } ppc_def_t; |
2862 | 79aceca5 | bellard | |
2863 | 79aceca5 | bellard | static ppc_proc_t ppc_proc_common = {
|
2864 | 79aceca5 | bellard | .flags = PPC_COMMON, |
2865 | 79aceca5 | bellard | .specific = NULL,
|
2866 | 79aceca5 | bellard | }; |
2867 | 79aceca5 | bellard | |
2868 | 9a64fbe4 | bellard | static ppc_proc_t ppc_proc_G3 = {
|
2869 | 9a64fbe4 | bellard | .flags = PPC_750, |
2870 | 9a64fbe4 | bellard | .specific = NULL,
|
2871 | 9a64fbe4 | bellard | }; |
2872 | 9a64fbe4 | bellard | |
2873 | 79aceca5 | bellard | static ppc_def_t ppc_defs[] =
|
2874 | 79aceca5 | bellard | { |
2875 | 9a64fbe4 | bellard | /* MPC740/745/750/755 (G3) */
|
2876 | 9a64fbe4 | bellard | { |
2877 | 9a64fbe4 | bellard | .pvr = 0x00080000,
|
2878 | 9a64fbe4 | bellard | .pvr_mask = 0xFFFF0000,
|
2879 | 9a64fbe4 | bellard | .proc = &ppc_proc_G3, |
2880 | 9a64fbe4 | bellard | }, |
2881 | 9a64fbe4 | bellard | /* IBM 750FX (G3 embedded) */
|
2882 | 9a64fbe4 | bellard | { |
2883 | 9a64fbe4 | bellard | .pvr = 0x70000000,
|
2884 | 9a64fbe4 | bellard | .pvr_mask = 0xFFFF0000,
|
2885 | 9a64fbe4 | bellard | .proc = &ppc_proc_G3, |
2886 | 9a64fbe4 | bellard | }, |
2887 | 9a64fbe4 | bellard | /* Fallback (generic PPC) */
|
2888 | 79aceca5 | bellard | { |
2889 | 79aceca5 | bellard | .pvr = 0x00000000,
|
2890 | 79aceca5 | bellard | .pvr_mask = 0x00000000,
|
2891 | 79aceca5 | bellard | .proc = &ppc_proc_common, |
2892 | 79aceca5 | bellard | }, |
2893 | 79aceca5 | bellard | }; |
2894 | 79aceca5 | bellard | |
2895 | 9a64fbe4 | bellard | static int create_ppc_proc (opc_handler_t **ppc_opcodes, unsigned long pvr) |
2896 | 79aceca5 | bellard | { |
2897 | 79aceca5 | bellard | opcode_t *opc; |
2898 | 79aceca5 | bellard | int i, flags;
|
2899 | 79aceca5 | bellard | |
2900 | 79aceca5 | bellard | fill_new_table(ppc_opcodes, 0x40);
|
2901 | 79aceca5 | bellard | for (i = 0; ; i++) { |
2902 | 79aceca5 | bellard | if ((ppc_defs[i].pvr & ppc_defs[i].pvr_mask) ==
|
2903 | 79aceca5 | bellard | (pvr & ppc_defs[i].pvr_mask)) { |
2904 | 79aceca5 | bellard | flags = ppc_defs[i].proc->flags; |
2905 | 79aceca5 | bellard | break;
|
2906 | 79aceca5 | bellard | } |
2907 | 79aceca5 | bellard | } |
2908 | 79aceca5 | bellard | |
2909 | 79aceca5 | bellard | for (opc = &opc_start + 1; opc != &opc_end; opc++) { |
2910 | 9a64fbe4 | bellard | if ((opc->handler.type & flags) != 0) |
2911 | 9a64fbe4 | bellard | if (register_insn(ppc_opcodes, opc) < 0) { |
2912 | 9a64fbe4 | bellard | printf("*** ERROR initializing PPC instruction "
|
2913 | 79aceca5 | bellard | "0x%02x 0x%02x 0x%02x\n", opc->opc1, opc->opc2,
|
2914 | 79aceca5 | bellard | opc->opc3); |
2915 | 79aceca5 | bellard | return -1; |
2916 | 79aceca5 | bellard | } |
2917 | 79aceca5 | bellard | } |
2918 | 9a64fbe4 | bellard | fix_opcode_tables(ppc_opcodes); |
2919 | 79aceca5 | bellard | |
2920 | 79aceca5 | bellard | return 0; |
2921 | 79aceca5 | bellard | } |
2922 | 79aceca5 | bellard | |
2923 | 9a64fbe4 | bellard | |
2924 | 79aceca5 | bellard | /*****************************************************************************/
|
2925 | 9a64fbe4 | bellard | /* Misc PPC helpers */
|
2926 | 79aceca5 | bellard | |
2927 | 7fe48483 | bellard | void cpu_dump_state(CPUState *env, FILE *f,
|
2928 | 7fe48483 | bellard | int (*cpu_fprintf)(FILE *f, const char *fmt, ...), |
2929 | 7fe48483 | bellard | int flags)
|
2930 | 79aceca5 | bellard | { |
2931 | 79aceca5 | bellard | int i;
|
2932 | 79aceca5 | bellard | |
2933 | 7fe48483 | bellard | cpu_fprintf(f, "nip=0x%08x LR=0x%08x CTR=0x%08x XER=0x%08x "
|
2934 | 9a64fbe4 | bellard | "MSR=0x%08x\n", env->nip, env->lr, env->ctr,
|
2935 | a541f297 | bellard | _load_xer(env), _load_msr(env)); |
2936 | 79aceca5 | bellard | for (i = 0; i < 32; i++) { |
2937 | 79aceca5 | bellard | if ((i & 7) == 0) |
2938 | 7fe48483 | bellard | cpu_fprintf(f, "GPR%02d:", i);
|
2939 | 7fe48483 | bellard | cpu_fprintf(f, " %08x", env->gpr[i]);
|
2940 | 79aceca5 | bellard | if ((i & 7) == 7) |
2941 | 7fe48483 | bellard | cpu_fprintf(f, "\n");
|
2942 | 79aceca5 | bellard | } |
2943 | 7fe48483 | bellard | cpu_fprintf(f, "CR: 0x");
|
2944 | 79aceca5 | bellard | for (i = 0; i < 8; i++) |
2945 | 7fe48483 | bellard | cpu_fprintf(f, "%01x", env->crf[i]);
|
2946 | 7fe48483 | bellard | cpu_fprintf(f, " [");
|
2947 | 79aceca5 | bellard | for (i = 0; i < 8; i++) { |
2948 | 79aceca5 | bellard | char a = '-'; |
2949 | 79aceca5 | bellard | if (env->crf[i] & 0x08) |
2950 | 79aceca5 | bellard | a = 'L';
|
2951 | 79aceca5 | bellard | else if (env->crf[i] & 0x04) |
2952 | 79aceca5 | bellard | a = 'G';
|
2953 | 79aceca5 | bellard | else if (env->crf[i] & 0x02) |
2954 | 79aceca5 | bellard | a = 'E';
|
2955 | 7fe48483 | bellard | cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' '); |
2956 | 79aceca5 | bellard | } |
2957 | 7fe48483 | bellard | cpu_fprintf(f, " ] ");
|
2958 | 7fe48483 | bellard | cpu_fprintf(f, "TB: 0x%08x %08x\n", cpu_ppc_load_tbu(env),
|
2959 | 9fddaa0c | bellard | cpu_ppc_load_tbl(env)); |
2960 | 79aceca5 | bellard | for (i = 0; i < 16; i++) { |
2961 | 79aceca5 | bellard | if ((i & 3) == 0) |
2962 | 7fe48483 | bellard | cpu_fprintf(f, "FPR%02d:", i);
|
2963 | 7fe48483 | bellard | cpu_fprintf(f, " %016llx", *((uint64_t *)&env->fpr[i]));
|
2964 | 79aceca5 | bellard | if ((i & 3) == 3) |
2965 | 7fe48483 | bellard | cpu_fprintf(f, "\n");
|
2966 | 79aceca5 | bellard | } |
2967 | 7fe48483 | bellard | cpu_fprintf(f, "SRR0 0x%08x SRR1 0x%08x DECR=0x%08x\n",
|
2968 | 9fddaa0c | bellard | env->spr[SRR0], env->spr[SRR1], cpu_ppc_load_decr(env)); |
2969 | 7fe48483 | bellard | cpu_fprintf(f, "reservation 0x%08x\n", env->reserve);
|
2970 | 79aceca5 | bellard | } |
2971 | 79aceca5 | bellard | |
2972 | 9a64fbe4 | bellard | #if !defined(CONFIG_USER_ONLY) && defined (USE_OPENFIRMWARE)
|
2973 | 9a64fbe4 | bellard | int setup_machine (CPUPPCState *env, uint32_t mid);
|
2974 | 9a64fbe4 | bellard | #endif
|
2975 | 9a64fbe4 | bellard | |
2976 | 79aceca5 | bellard | CPUPPCState *cpu_ppc_init(void)
|
2977 | 79aceca5 | bellard | { |
2978 | 79aceca5 | bellard | CPUPPCState *env; |
2979 | 79aceca5 | bellard | |
2980 | 79aceca5 | bellard | cpu_exec_init(); |
2981 | 79aceca5 | bellard | |
2982 | 4b3686fa | bellard | env = qemu_mallocz(sizeof(CPUPPCState));
|
2983 | 79aceca5 | bellard | if (!env)
|
2984 | 79aceca5 | bellard | return NULL; |
2985 | 9a64fbe4 | bellard | #if !defined(CONFIG_USER_ONLY) && defined (USE_OPEN_FIRMWARE)
|
2986 | 9a64fbe4 | bellard | setup_machine(env, 0);
|
2987 | 9a64fbe4 | bellard | #else
|
2988 | 9a64fbe4 | bellard | // env->spr[PVR] = 0; /* Basic PPC */
|
2989 | 9a64fbe4 | bellard | env->spr[PVR] = 0x00080100; /* G3 CPU */ |
2990 | 9a64fbe4 | bellard | // env->spr[PVR] = 0x00083100; /* MPC755 (G3 embedded) */
|
2991 | 9a64fbe4 | bellard | // env->spr[PVR] = 0x00070100; /* IBM 750FX */
|
2992 | 9a64fbe4 | bellard | #endif
|
2993 | ad081323 | bellard | tlb_flush(env, 1);
|
2994 | 9a64fbe4 | bellard | #if defined (DO_SINGLE_STEP)
|
2995 | 9a64fbe4 | bellard | /* Single step trace mode */
|
2996 | 9a64fbe4 | bellard | msr_se = 1;
|
2997 | 9a64fbe4 | bellard | #endif
|
2998 | 4b3686fa | bellard | msr_fp = 1; /* Allow floating point exceptions */ |
2999 | 4b3686fa | bellard | msr_me = 1; /* Allow machine check exceptions */ |
3000 | 9a64fbe4 | bellard | #if defined(CONFIG_USER_ONLY)
|
3001 | 9a64fbe4 | bellard | msr_pr = 1;
|
3002 | 4b3686fa | bellard | cpu_ppc_register(env, 0x00080000);
|
3003 | 4b3686fa | bellard | #else
|
3004 | 4b3686fa | bellard | env->nip = 0xFFFFFFFC;
|
3005 | 9a64fbe4 | bellard | #endif
|
3006 | 7496f526 | bellard | cpu_single_env = env; |
3007 | 79aceca5 | bellard | return env;
|
3008 | 79aceca5 | bellard | } |
3009 | 79aceca5 | bellard | |
3010 | 4b3686fa | bellard | int cpu_ppc_register (CPUPPCState *env, uint32_t pvr)
|
3011 | 4b3686fa | bellard | { |
3012 | 4b3686fa | bellard | env->spr[PVR] = pvr; |
3013 | 4b3686fa | bellard | if (create_ppc_proc(ppc_opcodes, env->spr[PVR]) < 0) |
3014 | 4b3686fa | bellard | return -1; |
3015 | 4b3686fa | bellard | init_spr_rights(env->spr[PVR]); |
3016 | 4b3686fa | bellard | |
3017 | 4b3686fa | bellard | return 0; |
3018 | 4b3686fa | bellard | } |
3019 | 4b3686fa | bellard | |
3020 | 79aceca5 | bellard | void cpu_ppc_close(CPUPPCState *env)
|
3021 | 79aceca5 | bellard | { |
3022 | 79aceca5 | bellard | /* Should also remove all opcode tables... */
|
3023 | 79aceca5 | bellard | free(env); |
3024 | 79aceca5 | bellard | } |
3025 | 79aceca5 | bellard | |
3026 | 9a64fbe4 | bellard | /*****************************************************************************/
|
3027 | 79aceca5 | bellard | int gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
|
3028 | 79aceca5 | bellard | int search_pc)
|
3029 | 79aceca5 | bellard | { |
3030 | 9fddaa0c | bellard | DisasContext ctx, *ctxp = &ctx; |
3031 | 79aceca5 | bellard | opc_handler_t **table, *handler; |
3032 | 0fa85d43 | bellard | target_ulong pc_start; |
3033 | 79aceca5 | bellard | uint16_t *gen_opc_end; |
3034 | 79aceca5 | bellard | int j, lj = -1; |
3035 | 79aceca5 | bellard | |
3036 | 79aceca5 | bellard | pc_start = tb->pc; |
3037 | 79aceca5 | bellard | gen_opc_ptr = gen_opc_buf; |
3038 | 79aceca5 | bellard | gen_opc_end = gen_opc_buf + OPC_MAX_SIZE; |
3039 | 79aceca5 | bellard | gen_opparam_ptr = gen_opparam_buf; |
3040 | 046d6672 | bellard | ctx.nip = pc_start; |
3041 | 79aceca5 | bellard | ctx.tb = tb; |
3042 | 9a64fbe4 | bellard | ctx.exception = EXCP_NONE; |
3043 | 9a64fbe4 | bellard | #if defined(CONFIG_USER_ONLY)
|
3044 | 9a64fbe4 | bellard | ctx.mem_idx = 0;
|
3045 | 9a64fbe4 | bellard | #else
|
3046 | 9a64fbe4 | bellard | ctx.supervisor = 1 - msr_pr;
|
3047 | 9a64fbe4 | bellard | ctx.mem_idx = (1 - msr_pr);
|
3048 | 9a64fbe4 | bellard | #endif
|
3049 | 9a64fbe4 | bellard | #if defined (DO_SINGLE_STEP)
|
3050 | 9a64fbe4 | bellard | /* Single step trace mode */
|
3051 | 9a64fbe4 | bellard | msr_se = 1;
|
3052 | 9a64fbe4 | bellard | #endif
|
3053 | 9a64fbe4 | bellard | /* Set env in case of segfault during code fetch */
|
3054 | 9a64fbe4 | bellard | while (ctx.exception == EXCP_NONE && gen_opc_ptr < gen_opc_end) {
|
3055 | 79aceca5 | bellard | if (search_pc) {
|
3056 | 79aceca5 | bellard | j = gen_opc_ptr - gen_opc_buf; |
3057 | 79aceca5 | bellard | if (lj < j) {
|
3058 | 79aceca5 | bellard | lj++; |
3059 | 79aceca5 | bellard | while (lj < j)
|
3060 | 79aceca5 | bellard | gen_opc_instr_start[lj++] = 0;
|
3061 | 046d6672 | bellard | gen_opc_pc[lj] = ctx.nip; |
3062 | 79aceca5 | bellard | gen_opc_instr_start[lj] = 1;
|
3063 | 79aceca5 | bellard | } |
3064 | 79aceca5 | bellard | } |
3065 | 9fddaa0c | bellard | #if defined PPC_DEBUG_DISAS
|
3066 | 9fddaa0c | bellard | if (loglevel & CPU_LOG_TB_IN_ASM) {
|
3067 | 79aceca5 | bellard | fprintf(logfile, "----------------\n");
|
3068 | 046d6672 | bellard | fprintf(logfile, "nip=%08x super=%d ir=%d\n",
|
3069 | 9a64fbe4 | bellard | ctx.nip, 1 - msr_pr, msr_ir);
|
3070 | 9a64fbe4 | bellard | } |
3071 | 9a64fbe4 | bellard | #endif
|
3072 | 0fa85d43 | bellard | ctx.opcode = ldl_code(ctx.nip); |
3073 | 9fddaa0c | bellard | #if defined PPC_DEBUG_DISAS
|
3074 | 9fddaa0c | bellard | if (loglevel & CPU_LOG_TB_IN_ASM) {
|
3075 | 9a64fbe4 | bellard | fprintf(logfile, "translate opcode %08x (%02x %02x %02x)\n",
|
3076 | 9a64fbe4 | bellard | ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode), |
3077 | 9a64fbe4 | bellard | opc3(ctx.opcode)); |
3078 | 79aceca5 | bellard | } |
3079 | 79aceca5 | bellard | #endif
|
3080 | 046d6672 | bellard | ctx.nip += 4;
|
3081 | 79aceca5 | bellard | table = ppc_opcodes; |
3082 | 79aceca5 | bellard | handler = table[opc1(ctx.opcode)]; |
3083 | 79aceca5 | bellard | if (is_indirect_opcode(handler)) {
|
3084 | 79aceca5 | bellard | table = ind_table(handler); |
3085 | 79aceca5 | bellard | handler = table[opc2(ctx.opcode)]; |
3086 | 79aceca5 | bellard | if (is_indirect_opcode(handler)) {
|
3087 | 79aceca5 | bellard | table = ind_table(handler); |
3088 | 79aceca5 | bellard | handler = table[opc3(ctx.opcode)]; |
3089 | 79aceca5 | bellard | } |
3090 | 79aceca5 | bellard | } |
3091 | 79aceca5 | bellard | /* Is opcode *REALLY* valid ? */
|
3092 | 79aceca5 | bellard | if (handler->handler == &gen_invalid) {
|
3093 | 4b3686fa | bellard | if (loglevel > 0) { |
3094 | 79aceca5 | bellard | fprintf(logfile, "invalid/unsupported opcode: "
|
3095 | 4b3686fa | bellard | "%02x - %02x - %02x (%08x) 0x%08x %d\n",
|
3096 | 9a64fbe4 | bellard | opc1(ctx.opcode), opc2(ctx.opcode), |
3097 | 4b3686fa | bellard | opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, msr_ir);
|
3098 | 4b3686fa | bellard | } else {
|
3099 | 4b3686fa | bellard | printf("invalid/unsupported opcode: "
|
3100 | 4b3686fa | bellard | "%02x - %02x - %02x (%08x) 0x%08x %d\n",
|
3101 | 4b3686fa | bellard | opc1(ctx.opcode), opc2(ctx.opcode), |
3102 | 4b3686fa | bellard | opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, msr_ir);
|
3103 | 4b3686fa | bellard | } |
3104 | 79aceca5 | bellard | } else {
|
3105 | 4b3686fa | bellard | if ((ctx.opcode & handler->inval) != 0) { |
3106 | 4b3686fa | bellard | if (loglevel > 0) { |
3107 | 79aceca5 | bellard | fprintf(logfile, "invalid bits: %08x for opcode: "
|
3108 | 046d6672 | bellard | "%02x -%02x - %02x (0x%08x) (0x%08x)\n",
|
3109 | 79aceca5 | bellard | ctx.opcode & handler->inval, opc1(ctx.opcode), |
3110 | 79aceca5 | bellard | opc2(ctx.opcode), opc3(ctx.opcode), |
3111 | 046d6672 | bellard | ctx.opcode, ctx.nip - 4);
|
3112 | 9a64fbe4 | bellard | } else {
|
3113 | 9a64fbe4 | bellard | printf("invalid bits: %08x for opcode: "
|
3114 | 046d6672 | bellard | "%02x -%02x - %02x (0x%08x) (0x%08x)\n",
|
3115 | 9a64fbe4 | bellard | ctx.opcode & handler->inval, opc1(ctx.opcode), |
3116 | 9a64fbe4 | bellard | opc2(ctx.opcode), opc3(ctx.opcode), |
3117 | 046d6672 | bellard | ctx.opcode, ctx.nip - 4);
|
3118 | 9a64fbe4 | bellard | } |
3119 | 4b3686fa | bellard | RET_INVAL(ctxp); |
3120 | 4b3686fa | bellard | break;
|
3121 | 79aceca5 | bellard | } |
3122 | 79aceca5 | bellard | } |
3123 | 4b3686fa | bellard | (*(handler->handler))(&ctx); |
3124 | 9a64fbe4 | bellard | /* Check trace mode exceptions */
|
3125 | 9a64fbe4 | bellard | if ((msr_be && ctx.exception == EXCP_BRANCH) ||
|
3126 | 9a64fbe4 | bellard | /* Check in single step trace mode
|
3127 | 9a64fbe4 | bellard | * we need to stop except if:
|
3128 | 9a64fbe4 | bellard | * - rfi, trap or syscall
|
3129 | 9a64fbe4 | bellard | * - first instruction of an exception handler
|
3130 | 9a64fbe4 | bellard | */
|
3131 | 046d6672 | bellard | (msr_se && (ctx.nip < 0x100 ||
|
3132 | 046d6672 | bellard | ctx.nip > 0xF00 ||
|
3133 | 046d6672 | bellard | (ctx.nip & 0xFC) != 0x04) && |
3134 | 9a64fbe4 | bellard | ctx.exception != EXCP_SYSCALL && ctx.exception != EXCP_RFI && |
3135 | 9a64fbe4 | bellard | ctx.exception != EXCP_TRAP)) { |
3136 | 9fddaa0c | bellard | RET_EXCP(ctxp, EXCP_TRACE, 0);
|
3137 | 9a64fbe4 | bellard | } |
3138 | a541f297 | bellard | /* if we reach a page boundary, stop generation */
|
3139 | 046d6672 | bellard | if ((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) { |
3140 | 9fddaa0c | bellard | RET_EXCP(ctxp, EXCP_BRANCH, 0);
|
3141 | 79aceca5 | bellard | } |
3142 | 9a64fbe4 | bellard | } |
3143 | 9fddaa0c | bellard | if (ctx.exception == EXCP_NONE) {
|
3144 | 9fddaa0c | bellard | gen_op_b((unsigned long)ctx.tb, ctx.nip); |
3145 | 9fddaa0c | bellard | } else if (ctx.exception != EXCP_BRANCH) { |
3146 | 9fddaa0c | bellard | gen_op_set_T0(0);
|
3147 | 9a64fbe4 | bellard | } |
3148 | 9a64fbe4 | bellard | #if 1 |
3149 | 79aceca5 | bellard | /* TO BE FIXED: T0 hasn't got a proper value, which makes tb_add_jump
|
3150 | 79aceca5 | bellard | * do bad business and then qemu crashes !
|
3151 | 79aceca5 | bellard | */
|
3152 | 79aceca5 | bellard | gen_op_set_T0(0);
|
3153 | 9a64fbe4 | bellard | #endif
|
3154 | 79aceca5 | bellard | /* Generate the return instruction */
|
3155 | 79aceca5 | bellard | gen_op_exit_tb(); |
3156 | 79aceca5 | bellard | *gen_opc_ptr = INDEX_op_end; |
3157 | 9a64fbe4 | bellard | if (search_pc) {
|
3158 | 9a64fbe4 | bellard | j = gen_opc_ptr - gen_opc_buf; |
3159 | 9a64fbe4 | bellard | lj++; |
3160 | 9a64fbe4 | bellard | while (lj <= j)
|
3161 | 9a64fbe4 | bellard | gen_opc_instr_start[lj++] = 0;
|
3162 | 79aceca5 | bellard | tb->size = 0;
|
3163 | 985a19d6 | bellard | #if 0
|
3164 | 9a64fbe4 | bellard | if (loglevel > 0) {
|
3165 | 9a64fbe4 | bellard | page_dump(logfile);
|
3166 | 9a64fbe4 | bellard | }
|
3167 | 985a19d6 | bellard | #endif
|
3168 | 9a64fbe4 | bellard | } else {
|
3169 | 046d6672 | bellard | tb->size = ctx.nip - pc_start; |
3170 | 9a64fbe4 | bellard | } |
3171 | 79aceca5 | bellard | #ifdef DEBUG_DISAS
|
3172 | 9fddaa0c | bellard | if (loglevel & CPU_LOG_TB_CPU) {
|
3173 | 9a64fbe4 | bellard | fprintf(logfile, "---------------- excp: %04x\n", ctx.exception);
|
3174 | 7fe48483 | bellard | cpu_dump_state(env, logfile, fprintf, 0);
|
3175 | 9fddaa0c | bellard | } |
3176 | 9fddaa0c | bellard | if (loglevel & CPU_LOG_TB_IN_ASM) {
|
3177 | 0fa85d43 | bellard | fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
|
3178 | 0fa85d43 | bellard | target_disas(logfile, pc_start, ctx.nip - pc_start, 0);
|
3179 | 79aceca5 | bellard | fprintf(logfile, "\n");
|
3180 | 9fddaa0c | bellard | } |
3181 | 9fddaa0c | bellard | if (loglevel & CPU_LOG_TB_OP) {
|
3182 | 79aceca5 | bellard | fprintf(logfile, "OP:\n");
|
3183 | 79aceca5 | bellard | dump_ops(gen_opc_buf, gen_opparam_buf); |
3184 | 79aceca5 | bellard | fprintf(logfile, "\n");
|
3185 | 79aceca5 | bellard | } |
3186 | 79aceca5 | bellard | #endif
|
3187 | 79aceca5 | bellard | return 0; |
3188 | 79aceca5 | bellard | } |
3189 | 79aceca5 | bellard | |
3190 | 9a64fbe4 | bellard | int gen_intermediate_code (CPUState *env, struct TranslationBlock *tb) |
3191 | 79aceca5 | bellard | { |
3192 | 79aceca5 | bellard | return gen_intermediate_code_internal(env, tb, 0); |
3193 | 79aceca5 | bellard | } |
3194 | 79aceca5 | bellard | |
3195 | 9a64fbe4 | bellard | int gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb) |
3196 | 79aceca5 | bellard | { |
3197 | 79aceca5 | bellard | return gen_intermediate_code_internal(env, tb, 1); |
3198 | 79aceca5 | bellard | } |