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/* alpha-dis.c -- Disassemble Alpha AXP instructions

   Copyright 1996, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.

   Contributed by Richard Henderson <rth@tamu.edu>,

   patterned after the PPC opcode handling written by Ian Lance Taylor.

This file is part of GDB, GAS, and the GNU binutils.

GDB, GAS, and the GNU binutils are free software; you can redistribute

them and/or modify them under the terms of the GNU General Public

License as published by the Free Software Foundation; either version

2, or (at your option) any later version.

GDB, GAS, and the GNU binutils are distributed in the hope that they

will be useful, but WITHOUT ANY WARRANTY; without even the implied

warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See

the GNU General Public License for more details.

You should have received a copy of the GNU General Public License

along with this file; see the file COPYING.  If not, see

<http://www.gnu.org/licenses/>. */

#include <stdio.h>

#include "dis-asm.h"

/* MAX is redefined below, so remove any previous definition. */

#undef MAX

/* The opcode table is an array of struct alpha_opcode.  */

struct alpha_opcode

{

  /* The opcode name.  */

  const char *name;

  /* The opcode itself.  Those bits which will be filled in with

     operands are zeroes.  */

  unsigned opcode;

  /* The opcode mask.  This is used by the disassembler.  This is a

     mask containing ones indicating those bits which must match the

     opcode field, and zeroes indicating those bits which need not

     match (and are presumably filled in by operands).  */

  unsigned mask;

  /* One bit flags for the opcode.  These are primarily used to

     indicate specific processors and environments support the

     instructions.  The defined values are listed below. */

  unsigned flags;

  /* An array of operand codes.  Each code is an index into the

     operand table.  They appear in the order which the operands must

     appear in assembly code, and are terminated by a zero.  */

  unsigned char operands[4];

};

/* The table itself is sorted by major opcode number, and is otherwise

   in the order in which the disassembler should consider

   instructions.  */

extern const struct alpha_opcode alpha_opcodes[];

extern const unsigned alpha_num_opcodes;

/* Values defined for the flags field of a struct alpha_opcode.  */

/* CPU Availability */

#define AXP_OPCODE_BASE  0x0001  /* Base architecture -- all cpus.  */

#define AXP_OPCODE_EV4   0x0002  /* EV4 specific PALcode insns.  */

#define AXP_OPCODE_EV5   0x0004  /* EV5 specific PALcode insns.  */

#define AXP_OPCODE_EV6   0x0008  /* EV6 specific PALcode insns.  */

#define AXP_OPCODE_BWX   0x0100  /* Byte/word extension (amask bit 0).  */

#define AXP_OPCODE_CIX   0x0200  /* "Count" extension (amask bit 1).  */

#define AXP_OPCODE_MAX   0x0400  /* Multimedia extension (amask bit 8).  */

#define AXP_OPCODE_NOPAL (~(AXP_OPCODE_EV4|AXP_OPCODE_EV5|AXP_OPCODE_EV6))

/* A macro to extract the major opcode from an instruction.  */

#define AXP_OP(i)        (((i) >> 26) & 0x3F)

/* The total number of major opcodes. */

#define AXP_NOPS        0x40

/* The operands table is an array of struct alpha_operand.  */

struct alpha_operand

{

  /* The number of bits in the operand.  */

  unsigned int bits : 5;

  /* How far the operand is left shifted in the instruction.  */

  unsigned int shift : 5;

  /* The default relocation type for this operand.  */

  signed int default_reloc : 16;

  /* One bit syntax flags.  */

  unsigned int flags : 16;

  /* Insertion function.  This is used by the assembler.  To insert an

     operand value into an instruction, check this field.

     If it is NULL, execute

         i |= (op & ((1 << o->bits) - 1)) << o->shift;

     (i is the instruction which we are filling in, o is a pointer to

     this structure, and op is the opcode value; this assumes twos

     complement arithmetic).

     If this field is not NULL, then simply call it with the

     instruction and the operand value.  It will return the new value

     of the instruction.  If the ERRMSG argument is not NULL, then if

     the operand value is illegal, *ERRMSG will be set to a warning

     string (the operand will be inserted in any case).  If the

     operand value is legal, *ERRMSG will be unchanged (most operands

     can accept any value).  */

  unsigned (*insert) (unsigned instruction, int op,

                      const char **errmsg);

  /* Extraction function.  This is used by the disassembler.  To

     extract this operand type from an instruction, check this field.

     If it is NULL, compute

         op = ((i) >> o->shift) & ((1 << o->bits) - 1);

         if ((o->flags & AXP_OPERAND_SIGNED) != 0

             && (op & (1 << (o->bits - 1))) != 0)

           op -= 1 << o->bits;

     (i is the instruction, o is a pointer to this structure, and op

     is the result; this assumes twos complement arithmetic).

     If this field is not NULL, then simply call it with the

     instruction value.  It will return the value of the operand.  If

     the INVALID argument is not NULL, *INVALID will be set to

     non-zero if this operand type can not actually be extracted from

     this operand (i.e., the instruction does not match).  If the

     operand is valid, *INVALID will not be changed.  */

  int (*extract) (unsigned instruction, int *invalid);

};

/* Elements in the table are retrieved by indexing with values from

   the operands field of the alpha_opcodes table.  */

extern const struct alpha_operand alpha_operands[];

extern const unsigned alpha_num_operands;

/* Values defined for the flags field of a struct alpha_operand.  */

/* Mask for selecting the type for typecheck purposes */

#define AXP_OPERAND_TYPECHECK_MASK                                        \

  (AXP_OPERAND_PARENS | AXP_OPERAND_COMMA | AXP_OPERAND_IR |                \

   AXP_OPERAND_FPR | AXP_OPERAND_RELATIVE | AXP_OPERAND_SIGNED |         \

   AXP_OPERAND_UNSIGNED)

/* This operand does not actually exist in the assembler input.  This

   is used to support extended mnemonics, for which two operands fields

   are identical.  The assembler should call the insert function with

   any op value.  The disassembler should call the extract function,

   ignore the return value, and check the value placed in the invalid

   argument.  */

#define AXP_OPERAND_FAKE        01

/* The operand should be wrapped in parentheses rather than separated

   from the previous by a comma.  This is used for the load and store

   instructions which want their operands to look like "Ra,disp(Rb)".  */

#define AXP_OPERAND_PARENS        02

/* Used in combination with PARENS, this suppresses the suppression of

   the comma.  This is used for "jmp Ra,(Rb),hint".  */

#define AXP_OPERAND_COMMA        04

/* This operand names an integer register.  */

#define AXP_OPERAND_IR                010

/* This operand names a floating point register.  */

#define AXP_OPERAND_FPR                020

/* This operand is a relative branch displacement.  The disassembler

   prints these symbolically if possible.  */

#define AXP_OPERAND_RELATIVE        040

/* This operand takes signed values.  */

#define AXP_OPERAND_SIGNED        0100

/* This operand takes unsigned values.  This exists primarily so that

   a flags value of 0 can be treated as end-of-arguments.  */

#define AXP_OPERAND_UNSIGNED        0200

/* Suppress overflow detection on this field.  This is used for hints. */

#define AXP_OPERAND_NOOVERFLOW        0400

/* Mask for optional argument default value.  */

#define AXP_OPERAND_OPTIONAL_MASK 07000

/* This operand defaults to zero.  This is used for jump hints.  */

#define AXP_OPERAND_DEFAULT_ZERO 01000

/* This operand should default to the first (real) operand and is used

   in conjunction with AXP_OPERAND_OPTIONAL.  This allows

   "and $0,3,$0" to be written as "and $0,3", etc.  I don't like

   it, but it's what DEC does.  */

#define AXP_OPERAND_DEFAULT_FIRST 02000

/* Similarly, this operand should default to the second (real) operand.

   This allows "negl $0" instead of "negl $0,$0".  */

#define AXP_OPERAND_DEFAULT_SECOND 04000

/* Register common names */

#define AXP_REG_V0        0

#define AXP_REG_T0        1

#define AXP_REG_T1        2

#define AXP_REG_T2        3

#define AXP_REG_T3        4

#define AXP_REG_T4        5

#define AXP_REG_T5        6

#define AXP_REG_T6        7

#define AXP_REG_T7        8

#define AXP_REG_S0        9

#define AXP_REG_S1        10

#define AXP_REG_S2        11

#define AXP_REG_S3        12

#define AXP_REG_S4        13

#define AXP_REG_S5        14

#define AXP_REG_FP        15

#define AXP_REG_A0        16

#define AXP_REG_A1        17

#define AXP_REG_A2        18

#define AXP_REG_A3        19

#define AXP_REG_A4        20

#define AXP_REG_A5        21

#define AXP_REG_T8        22

#define AXP_REG_T9        23

#define AXP_REG_T10        24

#define AXP_REG_T11        25

#define AXP_REG_RA        26

#define AXP_REG_PV        27

#define AXP_REG_T12        27

#define AXP_REG_AT        28

#define AXP_REG_GP        29

#define AXP_REG_SP        30

#define AXP_REG_ZERO        31

#define bfd_mach_alpha_ev4  0x10

#define bfd_mach_alpha_ev5  0x20

#define bfd_mach_alpha_ev6  0x30

enum bfd_reloc_code_real {

    BFD_RELOC_23_PCREL_S2,

    BFD_RELOC_ALPHA_HINT

};

/* This file holds the Alpha AXP opcode table.  The opcode table includes

   almost all of the extended instruction mnemonics.  This permits the

   disassembler to use them, and simplifies the assembler logic, at the

   cost of increasing the table size.  The table is strictly constant

   data, so the compiler should be able to put it in the text segment.

   This file also holds the operand table.  All knowledge about inserting

   and extracting operands from instructions is kept in this file.

   The information for the base instruction set was compiled from the

   _Alpha Architecture Handbook_, Digital Order Number EC-QD2KB-TE,

   version 2.

   The information for the post-ev5 architecture extensions BWX, CIX and

   MAX came from version 3 of this same document, which is also available

   on-line at http://ftp.digital.com/pub/Digital/info/semiconductor

   /literature/alphahb2.pdf

   The information for the EV4 PALcode instructions was compiled from

   _DECchip 21064 and DECchip 21064A Alpha AXP Microprocessors Hardware

   Reference Manual_, Digital Order Number EC-Q9ZUA-TE, preliminary

   revision dated June 1994.

   The information for the EV5 PALcode instructions was compiled from

   _Alpha 21164 Microprocessor Hardware Reference Manual_, Digital

   Order Number EC-QAEQB-TE, preliminary revision dated April 1995.  */

/* Local insertion and extraction functions */

static unsigned insert_rba (unsigned, int, const char **);

static unsigned insert_rca (unsigned, int, const char **);

static unsigned insert_za (unsigned, int, const char **);

static unsigned insert_zb (unsigned, int, const char **);

static unsigned insert_zc (unsigned, int, const char **);

static unsigned insert_bdisp (unsigned, int, const char **);

static unsigned insert_jhint (unsigned, int, const char **);

static unsigned insert_ev6hwjhint (unsigned, int, const char **);

static int extract_rba (unsigned, int *);

static int extract_rca (unsigned, int *);

static int extract_za (unsigned, int *);

static int extract_zb (unsigned, int *);

static int extract_zc (unsigned, int *);

static int extract_bdisp (unsigned, int *);

static int extract_jhint (unsigned, int *);

static int extract_ev6hwjhint (unsigned, int *);

/* The operands table  */

const struct alpha_operand alpha_operands[] =

{

  /* The fields are bits, shift, insert, extract, flags */

  /* The zero index is used to indicate end-of-list */

#define UNUSED                0

  { 0, 0, 0, 0, 0, 0 },

  /* The plain integer register fields */

#define RA                (UNUSED + 1)

  { 5, 21, 0, AXP_OPERAND_IR, 0, 0 },

#define RB                (RA + 1)

  { 5, 16, 0, AXP_OPERAND_IR, 0, 0 },

#define RC                (RB + 1)

  { 5, 0, 0, AXP_OPERAND_IR, 0, 0 },

  /* The plain fp register fields */

#define FA                (RC + 1)

  { 5, 21, 0, AXP_OPERAND_FPR, 0, 0 },

#define FB                (FA + 1)

  { 5, 16, 0, AXP_OPERAND_FPR, 0, 0 },

#define FC                (FB + 1)

  { 5, 0, 0, AXP_OPERAND_FPR, 0, 0 },

  /* The integer registers when they are ZERO */

#define ZA                (FC + 1)

  { 5, 21, 0, AXP_OPERAND_FAKE, insert_za, extract_za },

#define ZB                (ZA + 1)

  { 5, 16, 0, AXP_OPERAND_FAKE, insert_zb, extract_zb },

#define ZC                (ZB + 1)

  { 5, 0, 0, AXP_OPERAND_FAKE, insert_zc, extract_zc },

  /* The RB field when it needs parentheses */

#define PRB                (ZC + 1)

  { 5, 16, 0, AXP_OPERAND_IR|AXP_OPERAND_PARENS, 0, 0 },

  /* The RB field when it needs parentheses _and_ a preceding comma */

#define CPRB                (PRB + 1)

  { 5, 16, 0,

    AXP_OPERAND_IR|AXP_OPERAND_PARENS|AXP_OPERAND_COMMA, 0, 0 },

  /* The RB field when it must be the same as the RA field */

#define RBA                (CPRB + 1)

  { 5, 16, 0, AXP_OPERAND_FAKE, insert_rba, extract_rba },

  /* The RC field when it must be the same as the RB field */

#define RCA                (RBA + 1)

  { 5, 0, 0, AXP_OPERAND_FAKE, insert_rca, extract_rca },

  /* The RC field when it can *default* to RA */

#define DRC1                (RCA + 1)

  { 5, 0, 0,

    AXP_OPERAND_IR|AXP_OPERAND_DEFAULT_FIRST, 0, 0 },

  /* The RC field when it can *default* to RB */

#define DRC2                (DRC1 + 1)

  { 5, 0, 0,

    AXP_OPERAND_IR|AXP_OPERAND_DEFAULT_SECOND, 0, 0 },

  /* The FC field when it can *default* to RA */

#define DFC1                (DRC2 + 1)

  { 5, 0, 0,

    AXP_OPERAND_FPR|AXP_OPERAND_DEFAULT_FIRST, 0, 0 },

  /* The FC field when it can *default* to RB */

#define DFC2                (DFC1 + 1)

  { 5, 0, 0,

    AXP_OPERAND_FPR|AXP_OPERAND_DEFAULT_SECOND, 0, 0 },

  /* The unsigned 8-bit literal of Operate format insns */

#define LIT                (DFC2 + 1)

  { 8, 13, -LIT, AXP_OPERAND_UNSIGNED, 0, 0 },

  /* The signed 16-bit displacement of Memory format insns.  From here

     we can't tell what relocation should be used, so don't use a default. */

#define MDISP                (LIT + 1)

  { 16, 0, -MDISP, AXP_OPERAND_SIGNED, 0, 0 },

  /* The signed "23-bit" aligned displacement of Branch format insns */

#define BDISP                (MDISP + 1)

  { 21, 0, BFD_RELOC_23_PCREL_S2,

    AXP_OPERAND_RELATIVE, insert_bdisp, extract_bdisp },

  /* The 26-bit PALcode function */

#define PALFN                (BDISP + 1)

  { 26, 0, -PALFN, AXP_OPERAND_UNSIGNED, 0, 0 },

  /* The optional signed "16-bit" aligned displacement of the JMP/JSR hint */

#define JMPHINT                (PALFN + 1)

  { 14, 0, BFD_RELOC_ALPHA_HINT,

    AXP_OPERAND_RELATIVE|AXP_OPERAND_DEFAULT_ZERO|AXP_OPERAND_NOOVERFLOW,

    insert_jhint, extract_jhint },

  /* The optional hint to RET/JSR_COROUTINE */

#define RETHINT                (JMPHINT + 1)

  { 14, 0, -RETHINT,

    AXP_OPERAND_UNSIGNED|AXP_OPERAND_DEFAULT_ZERO, 0, 0 },

  /* The 12-bit displacement for the ev[46] hw_{ld,st} (pal1b/pal1f) insns */

#define EV4HWDISP        (RETHINT + 1)

#define EV6HWDISP        (EV4HWDISP)

  { 12, 0, -EV4HWDISP, AXP_OPERAND_SIGNED, 0, 0 },

  /* The 5-bit index for the ev4 hw_m[ft]pr (pal19/pal1d) insns */

#define EV4HWINDEX        (EV4HWDISP + 1)

  { 5, 0, -EV4HWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 },

  /* The 8-bit index for the oddly unqualified hw_m[tf]pr insns

     that occur in DEC PALcode.  */

#define EV4EXTHWINDEX        (EV4HWINDEX + 1)

  { 8, 0, -EV4EXTHWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 },

  /* The 10-bit displacement for the ev5 hw_{ld,st} (pal1b/pal1f) insns */

#define EV5HWDISP        (EV4EXTHWINDEX + 1)

  { 10, 0, -EV5HWDISP, AXP_OPERAND_SIGNED, 0, 0 },

  /* The 16-bit index for the ev5 hw_m[ft]pr (pal19/pal1d) insns */

#define EV5HWINDEX        (EV5HWDISP + 1)

  { 16, 0, -EV5HWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 },

  /* The 16-bit combined index/scoreboard mask for the ev6

     hw_m[ft]pr (pal19/pal1d) insns */

#define EV6HWINDEX        (EV5HWINDEX + 1)

  { 16, 0, -EV6HWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 },

  /* The 13-bit branch hint for the ev6 hw_jmp/jsr (pal1e) insn */

#define EV6HWJMPHINT        (EV6HWINDEX+ 1)

  { 8, 0, -EV6HWJMPHINT,

    AXP_OPERAND_RELATIVE|AXP_OPERAND_DEFAULT_ZERO|AXP_OPERAND_NOOVERFLOW,

    insert_ev6hwjhint, extract_ev6hwjhint }

};

const unsigned alpha_num_operands = sizeof(alpha_operands)/sizeof(*alpha_operands);

/* The RB field when it is the same as the RA field in the same insn.

   This operand is marked fake.  The insertion function just copies

   the RA field into the RB field, and the extraction function just

   checks that the fields are the same. */

/*ARGSUSED*/

static unsigned

insert_rba(unsigned insn, int value ATTRIBUTE_UNUSED, const char **errmsg ATTRIBUTE_UNUSED)

{

  return insn | (((insn >> 21) & 0x1f) << 16);

}

static int

extract_rba(unsigned insn, int *invalid)

{

  if (invalid != (int *) NULL

      && ((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))

    *invalid = 1;

  return 0;

}

/* The same for the RC field */

/*ARGSUSED*/

static unsigned

insert_rca(unsigned insn, int value ATTRIBUTE_UNUSED, const char **errmsg ATTRIBUTE_UNUSED)

{

  return insn | ((insn >> 21) & 0x1f);

}

static int

extract_rca(unsigned insn, int *invalid)

{

  if (invalid != (int *) NULL

      && ((insn >> 21) & 0x1f) != (insn & 0x1f))

    *invalid = 1;

  return 0;

}

/* Fake arguments in which the registers must be set to ZERO */

/*ARGSUSED*/

static unsigned

insert_za(unsigned insn, int value ATTRIBUTE_UNUSED, const char **errmsg ATTRIBUTE_UNUSED)

{

  return insn | (31 << 21);

}

static int

extract_za(unsigned insn, int *invalid)

{

  if (invalid != (int *) NULL && ((insn >> 21) & 0x1f) != 31)

    *invalid = 1;

  return 0;

}

/*ARGSUSED*/

static unsigned

insert_zb(unsigned insn, int value ATTRIBUTE_UNUSED, const char **errmsg ATTRIBUTE_UNUSED)

{

  return insn | (31 << 16);

}

static int

extract_zb(unsigned insn, int *invalid)

{

  if (invalid != (int *) NULL && ((insn >> 16) & 0x1f) != 31)

    *invalid = 1;

  return 0;

}

/*ARGSUSED*/

static unsigned

insert_zc(unsigned insn, int value ATTRIBUTE_UNUSED, const char **errmsg ATTRIBUTE_UNUSED)

{

  return insn | 31;

}

static int

extract_zc(unsigned insn, int *invalid)

{

  if (invalid != (int *) NULL && (insn & 0x1f) != 31)

    *invalid = 1;

  return 0;

}

/* The displacement field of a Branch format insn.  */

static unsigned

insert_bdisp(unsigned insn, int value, const char **errmsg)

{

  if (errmsg != (const char **)NULL && (value & 3))

    *errmsg = _("branch operand unaligned");

  return insn | ((value / 4) & 0x1FFFFF);

}

/*ARGSUSED*/

static int

extract_bdisp(unsigned insn, int *invalid ATTRIBUTE_UNUSED)

{

  return 4 * (((insn & 0x1FFFFF) ^ 0x100000) - 0x100000);

}

/* The hint field of a JMP/JSR insn.  */

static unsigned

insert_jhint(unsigned insn, int value, const char **errmsg)

{

  if (errmsg != (const char **)NULL && (value & 3))

    *errmsg = _("jump hint unaligned");

  return insn | ((value / 4) & 0x3FFF);

}

/*ARGSUSED*/

static int

extract_jhint(unsigned insn, int *invalid ATTRIBUTE_UNUSED)

{

  return 4 * (((insn & 0x3FFF) ^ 0x2000) - 0x2000);

}

/* The hint field of an EV6 HW_JMP/JSR insn.  */

static unsigned

insert_ev6hwjhint(unsigned insn, int value, const char **errmsg)

{

  if (errmsg != (const char **)NULL && (value & 3))

    *errmsg = _("jump hint unaligned");

  return insn | ((value / 4) & 0x1FFF);

}

/*ARGSUSED*/

static int

extract_ev6hwjhint(unsigned insn, int *invalid ATTRIBUTE_UNUSED)

{

  return 4 * (((insn & 0x1FFF) ^ 0x1000) - 0x1000);

}

/* Macros used to form opcodes */

/* The main opcode */

#define OP(x)                (((x) & 0x3F) << 26)

#define OP_MASK                0xFC000000

/* Branch format instructions */

#define BRA_(oo)        OP(oo)

#define BRA_MASK        OP_MASK

#define BRA(oo)                BRA_(oo), BRA_MASK

/* Floating point format instructions */

#define FP_(oo,fff)        (OP(oo) | (((fff) & 0x7FF) << 5))

#define FP_MASK                (OP_MASK | 0xFFE0)

#define FP(oo,fff)        FP_(oo,fff), FP_MASK

/* Memory format instructions */

#define MEM_(oo)        OP(oo)

#define MEM_MASK        OP_MASK

#define MEM(oo)                MEM_(oo), MEM_MASK

/* Memory/Func Code format instructions */

#define MFC_(oo,ffff)        (OP(oo) | ((ffff) & 0xFFFF))

#define MFC_MASK        (OP_MASK | 0xFFFF)

#define MFC(oo,ffff)        MFC_(oo,ffff), MFC_MASK

/* Memory/Branch format instructions */

#define MBR_(oo,h)        (OP(oo) | (((h) & 3) << 14))

#define MBR_MASK        (OP_MASK | 0xC000)

#define MBR(oo,h)        MBR_(oo,h), MBR_MASK

/* Operate format instructions.  The OPRL variant specifies a

   literal second argument. */

#define OPR_(oo,ff)        (OP(oo) | (((ff) & 0x7F) << 5))

#define OPRL_(oo,ff)        (OPR_((oo),(ff)) | 0x1000)

#define OPR_MASK        (OP_MASK | 0x1FE0)

#define OPR(oo,ff)        OPR_(oo,ff), OPR_MASK

#define OPRL(oo,ff)        OPRL_(oo,ff), OPR_MASK

/* Generic PALcode format instructions */

#define PCD_(oo)        OP(oo)

#define PCD_MASK        OP_MASK

#define PCD(oo)                PCD_(oo), PCD_MASK

/* Specific PALcode instructions */

#define SPCD_(oo,ffff)        (OP(oo) | ((ffff) & 0x3FFFFFF))

#define SPCD_MASK        0xFFFFFFFF

#define SPCD(oo,ffff)        SPCD_(oo,ffff), SPCD_MASK

/* Hardware memory (hw_{ld,st}) instructions */

#define EV4HWMEM_(oo,f)        (OP(oo) | (((f) & 0xF) << 12))

#define EV4HWMEM_MASK        (OP_MASK | 0xF000)

#define EV4HWMEM(oo,f)        EV4HWMEM_(oo,f), EV4HWMEM_MASK

#define EV5HWMEM_(oo,f)        (OP(oo) | (((f) & 0x3F) << 10))

#define EV5HWMEM_MASK        (OP_MASK | 0xF800)

#define EV5HWMEM(oo,f)        EV5HWMEM_(oo,f), EV5HWMEM_MASK

#define EV6HWMEM_(oo,f)        (OP(oo) | (((f) & 0xF) << 12))

#define EV6HWMEM_MASK        (OP_MASK | 0xF000)

#define EV6HWMEM(oo,f)        EV6HWMEM_(oo,f), EV6HWMEM_MASK

#define EV6HWMBR_(oo,h)        (OP(oo) | (((h) & 7) << 13))

#define EV6HWMBR_MASK        (OP_MASK | 0xE000)

#define EV6HWMBR(oo,h)        EV6HWMBR_(oo,h), EV6HWMBR_MASK

/* Abbreviations for instruction subsets.  */

#define BASE                        AXP_OPCODE_BASE

#define EV4                        AXP_OPCODE_EV4

#define EV5                        AXP_OPCODE_EV5

#define EV6                        AXP_OPCODE_EV6

#define BWX                        AXP_OPCODE_BWX

#define CIX                        AXP_OPCODE_CIX

#define MAX                        AXP_OPCODE_MAX

/* Common combinations of arguments */

#define ARG_NONE                { 0 }

#define ARG_BRA                        { RA, BDISP }

#define ARG_FBRA                { FA, BDISP }

#define ARG_FP                        { FA, FB, DFC1 }

#define ARG_FPZ1                { ZA, FB, DFC1 }

#define ARG_MEM                        { RA, MDISP, PRB }

#define ARG_FMEM                { FA, MDISP, PRB }

#define ARG_OPR                        { RA, RB, DRC1 }

#define ARG_OPRL                { RA, LIT, DRC1 }

#define ARG_OPRZ1                { ZA, RB, DRC1 }

#define ARG_OPRLZ1                { ZA, LIT, RC }

#define ARG_PCD                        { PALFN }

#define ARG_EV4HWMEM                { RA, EV4HWDISP, PRB }

#define ARG_EV4HWMPR                { RA, RBA, EV4HWINDEX }

#define ARG_EV5HWMEM                { RA, EV5HWDISP, PRB }

#define ARG_EV6HWMEM                { RA, EV6HWDISP, PRB }

/* The opcode table.

   The format of the opcode table is:

   NAME OPCODE MASK { OPERANDS }

   NAME                is the name of the instruction.

   OPCODE        is the instruction opcode.

   MASK                is the opcode mask; this is used to tell the disassembler

                    which bits in the actual opcode must match OPCODE.

   OPERANDS        is the list of operands.

   The preceding macros merge the text of the OPCODE and MASK fields.

   The disassembler reads the table in order and prints the first

   instruction which matches, so this table is sorted to put more

   specific instructions before more general instructions.

   Otherwise, it is sorted by major opcode and minor function code.

   There are three classes of not-really-instructions in this table:

   ALIAS        is another name for another instruction.  Some of

                these come from the Architecture Handbook, some

                come from the original gas opcode tables.  In all

                cases, the functionality of the opcode is unchanged.

   PSEUDO        a stylized code form endorsed by Chapter A.4 of the

                Architecture Handbook.

   EXTRA        a stylized code form found in the original gas tables.

   And two annotations:

   EV56 BUT        opcodes that are officially introduced as of the ev56,

                   but with defined results on previous implementations.

   EV56 UNA        opcodes that were introduced as of the ev56 with

                   presumably undefined results on previous implementations

                that were not assigned to a particular extension.

*/

const struct alpha_opcode alpha_opcodes[] = {

  { "halt",                SPCD(0x00,0x0000), BASE, ARG_NONE },

  { "draina",                SPCD(0x00,0x0002), BASE, ARG_NONE },

  { "bpt",                SPCD(0x00,0x0080), BASE, ARG_NONE },

  { "bugchk",                SPCD(0x00,0x0081), BASE, ARG_NONE },

  { "callsys",                SPCD(0x00,0x0083), BASE, ARG_NONE },

  { "chmk",                 SPCD(0x00,0x0083), BASE, ARG_NONE },

  { "imb",                SPCD(0x00,0x0086), BASE, ARG_NONE },

  { "rduniq",                SPCD(0x00,0x009e), BASE, ARG_NONE },

  { "wruniq",                SPCD(0x00,0x009f), BASE, ARG_NONE },

  { "gentrap",                SPCD(0x00,0x00aa), BASE, ARG_NONE },

  { "call_pal",                PCD(0x00), BASE, ARG_PCD },

  { "pal",                PCD(0x00), BASE, ARG_PCD },                /* alias */

  { "lda",                MEM(0x08), BASE, { RA, MDISP, ZB } },        /* pseudo */

  { "lda",                MEM(0x08), BASE, ARG_MEM },

  { "ldah",                MEM(0x09), BASE, { RA, MDISP, ZB } },        /* pseudo */

  { "ldah",                MEM(0x09), BASE, ARG_MEM },

  { "ldbu",                MEM(0x0A), BWX, ARG_MEM },

  { "unop",                MEM_(0x0B) | (30 << 16),

                        MEM_MASK, BASE, { ZA } },                /* pseudo */

  { "ldq_u",                MEM(0x0B), BASE, ARG_MEM },

  { "ldwu",                MEM(0x0C), BWX, ARG_MEM },

  { "stw",                MEM(0x0D), BWX, ARG_MEM },

  { "stb",                MEM(0x0E), BWX, ARG_MEM },

  { "stq_u",                MEM(0x0F), BASE, ARG_MEM },

  { "sextl",                OPR(0x10,0x00), BASE, ARG_OPRZ1 },        /* pseudo */

  { "sextl",                OPRL(0x10,0x00), BASE, ARG_OPRLZ1 },        /* pseudo */

  { "addl",                OPR(0x10,0x00), BASE, ARG_OPR },

  { "addl",                OPRL(0x10,0x00), BASE, ARG_OPRL },

  { "s4addl",                OPR(0x10,0x02), BASE, ARG_OPR },

  { "s4addl",                OPRL(0x10,0x02), BASE, ARG_OPRL },

  { "negl",                OPR(0x10,0x09), BASE, ARG_OPRZ1 },        /* pseudo */

  { "negl",                OPRL(0x10,0x09), BASE, ARG_OPRLZ1 },        /* pseudo */

  { "subl",                OPR(0x10,0x09), BASE, ARG_OPR },

  { "subl",                OPRL(0x10,0x09), BASE, ARG_OPRL },

  { "s4subl",                OPR(0x10,0x0B), BASE, ARG_OPR },

  { "s4subl",                OPRL(0x10,0x0B), BASE, ARG_OPRL },

  { "cmpbge",                OPR(0x10,0x0F), BASE, ARG_OPR },

  { "cmpbge",                OPRL(0x10,0x0F), BASE, ARG_OPRL },

  { "s8addl",                OPR(0x10,0x12), BASE, ARG_OPR },

  { "s8addl",                OPRL(0x10,0x12), BASE, ARG_OPRL },

  { "s8subl",                OPR(0x10,0x1B), BASE, ARG_OPR },

  { "s8subl",                OPRL(0x10,0x1B), BASE, ARG_OPRL },

  { "cmpult",                OPR(0x10,0x1D), BASE, ARG_OPR },

  { "cmpult",                OPRL(0x10,0x1D), BASE, ARG_OPRL },

  { "addq",                OPR(0x10,0x20), BASE, ARG_OPR },

  { "addq",                OPRL(0x10,0x20), BASE, ARG_OPRL },

  { "s4addq",                OPR(0x10,0x22), BASE, ARG_OPR },

  { "s4addq",                OPRL(0x10,0x22), BASE, ARG_OPRL },

  { "negq",                 OPR(0x10,0x29), BASE, ARG_OPRZ1 },        /* pseudo */

  { "negq",                 OPRL(0x10,0x29), BASE, ARG_OPRLZ1 },        /* pseudo */

  { "subq",                OPR(0x10,0x29), BASE, ARG_OPR },

  { "subq",                OPRL(0x10,0x29), BASE, ARG_OPRL },

  { "s4subq",                OPR(0x10,0x2B), BASE, ARG_OPR },

  { "s4subq",                OPRL(0x10,0x2B), BASE, ARG_OPRL },

  { "cmpeq",                OPR(0x10,0x2D), BASE, ARG_OPR },

  { "cmpeq",                OPRL(0x10,0x2D), BASE, ARG_OPRL },

  { "s8addq",                OPR(0x10,0x32), BASE, ARG_OPR },

  { "s8addq",                OPRL(0x10,0x32), BASE, ARG_OPRL },

  { "s8subq",                OPR(0x10,0x3B), BASE, ARG_OPR },

  { "s8subq",                OPRL(0x10,0x3B), BASE, ARG_OPRL },

  { "cmpule",                OPR(0x10,0x3D), BASE, ARG_OPR },

  { "cmpule",                OPRL(0x10,0x3D), BASE, ARG_OPRL },

  { "addl/v",                OPR(0x10,0x40), BASE, ARG_OPR },

  { "addl/v",                OPRL(0x10,0x40), BASE, ARG_OPRL },

  { "negl/v",                OPR(0x10,0x49), BASE, ARG_OPRZ1 },        /* pseudo */

  { "negl/v",                OPRL(0x10,0x49), BASE, ARG_OPRLZ1 },        /* pseudo */

  { "subl/v",                OPR(0x10,0x49), BASE, ARG_OPR },

  { "subl/v",                OPRL(0x10,0x49), BASE, ARG_OPRL },

  { "cmplt",                OPR(0x10,0x4D), BASE, ARG_OPR },

  { "cmplt",                OPRL(0x10,0x4D), BASE, ARG_OPRL },

  { "addq/v",                OPR(0x10,0x60), BASE, ARG_OPR },

  { "addq/v",                OPRL(0x10,0x60), BASE, ARG_OPRL },

  { "negq/v",                OPR(0x10,0x69), BASE, ARG_OPRZ1 },        /* pseudo */

  { "negq/v",                OPRL(0x10,0x69), BASE, ARG_OPRLZ1 },        /* pseudo */

  { "subq/v",                OPR(0x10,0x69), BASE, ARG_OPR },

  { "subq/v",                OPRL(0x10,0x69), BASE, ARG_OPRL },

  { "cmple",                OPR(0x10,0x6D), BASE, ARG_OPR },

  { "cmple",                OPRL(0x10,0x6D), BASE, ARG_OPRL },

  { "and",                OPR(0x11,0x00), BASE, ARG_OPR },

  { "and",                OPRL(0x11,0x00), BASE, ARG_OPRL },

  { "andnot",                OPR(0x11,0x08), BASE, ARG_OPR },        /* alias */

  { "andnot",                OPRL(0x11,0x08), BASE, ARG_OPRL },        /* alias */

  { "bic",                OPR(0x11,0x08), BASE, ARG_OPR },

  { "bic",                OPRL(0x11,0x08), BASE, ARG_OPRL },

  { "cmovlbs",                OPR(0x11,0x14), BASE, ARG_OPR },

  { "cmovlbs",                OPRL(0x11,0x14), BASE, ARG_OPRL },

  { "cmovlbc",                OPR(0x11,0x16), BASE, ARG_OPR },

  { "cmovlbc",                OPRL(0x11,0x16), BASE, ARG_OPRL },

  { "nop",                OPR(0x11,0x20), BASE, { ZA, ZB, ZC } }, /* pseudo */

  { "clr",                OPR(0x11,0x20), BASE, { ZA, ZB, RC } }, /* pseudo */

  { "mov",                OPR(0x11,0x20), BASE, { ZA, RB, RC } }, /* pseudo */

  { "mov",                OPR(0x11,0x20), BASE, { RA, RBA, RC } }, /* pseudo */

  { "mov",                OPRL(0x11,0x20), BASE, { ZA, LIT, RC } }, /* pseudo */

  { "or",                OPR(0x11,0x20), BASE, ARG_OPR },        /* alias */

  { "or",                OPRL(0x11,0x20), BASE, ARG_OPRL },        /* alias */

  { "bis",                OPR(0x11,0x20), BASE, ARG_OPR },

  { "bis",                OPRL(0x11,0x20), BASE, ARG_OPRL },

  { "cmoveq",                OPR(0x11,0x24), BASE, ARG_OPR },

  { "cmoveq",                OPRL(0x11,0x24), BASE, ARG_OPRL },

  { "cmovne",                OPR(0x11,0x26), BASE, ARG_OPR },

  { "cmovne",                OPRL(0x11,0x26), BASE, ARG_OPRL },

  { "not",                OPR(0x11,0x28), BASE, ARG_OPRZ1 },        /* pseudo */

  { "not",                OPRL(0x11,0x28), BASE, ARG_OPRLZ1 },        /* pseudo */

  { "ornot",                OPR(0x11,0x28), BASE, ARG_OPR },

  { "ornot",                OPRL(0x11,0x28), BASE, ARG_OPRL },

  { "xor",                OPR(0x11,0x40), BASE, ARG_OPR },

  { "xor",                OPRL(0x11,0x40), BASE, ARG_OPRL },

  { "cmovlt",                OPR(0x11,0x44), BASE, ARG_OPR },

  { "cmovlt",                OPRL(0x11,0x44), BASE, ARG_OPRL },

  { "cmovge",                OPR(0x11,0x46), BASE, ARG_OPR },

  { "cmovge",                OPRL(0x11,0x46), BASE, ARG_OPRL },

  { "eqv",                OPR(0x11,0x48), BASE, ARG_OPR },

  { "eqv",                OPRL(0x11,0x48), BASE, ARG_OPRL },

  { "xornot",                OPR(0x11,0x48), BASE, ARG_OPR },        /* alias */

  { "xornot",                OPRL(0x11,0x48), BASE, ARG_OPRL },        /* alias */

  { "amask",                OPR(0x11,0x61), BASE, ARG_OPRZ1 },        /* ev56 but */

  { "amask",                OPRL(0x11,0x61), BASE, ARG_OPRLZ1 },        /* ev56 but */

  { "cmovle",                OPR(0x11,0x64), BASE, ARG_OPR },

  { "cmovle",                OPRL(0x11,0x64), BASE, ARG_OPRL },

  { "cmovgt",                OPR(0x11,0x66), BASE, ARG_OPR },

  { "cmovgt",                OPRL(0x11,0x66), BASE, ARG_OPRL },

  { "implver",                OPRL_(0x11,0x6C)|(31<<21)|(1<<13),

                            0xFFFFFFE0, BASE, { RC } },                /* ev56 but */

  { "mskbl",                OPR(0x12,0x02), BASE, ARG_OPR },

  { "mskbl",                OPRL(0x12,0x02), BASE, ARG_OPRL },

  { "extbl",                OPR(0x12,0x06), BASE, ARG_OPR },

  { "extbl",                OPRL(0x12,0x06), BASE, ARG_OPRL },

  { "insbl",                OPR(0x12,0x0B), BASE, ARG_OPR },

  { "insbl",                OPRL(0x12,0x0B), BASE, ARG_OPRL },

  { "mskwl",                OPR(0x12,0x12), BASE, ARG_OPR },

  { "mskwl",                OPRL(0x12,0x12), BASE, ARG_OPRL },

  { "extwl",                OPR(0x12,0x16), BASE, ARG_OPR },

  { "extwl",                OPRL(0x12,0x16), BASE, ARG_OPRL },

  { "inswl",                OPR(0x12,0x1B), BASE, ARG_OPR },

  { "inswl",                OPRL(0x12,0x1B), BASE, ARG_OPRL },

  { "mskll",                OPR(0x12,0x22), BASE, ARG_OPR },

  { "mskll",                OPRL(0x12,0x22), BASE, ARG_OPRL },

  { "extll",                OPR(0x12,0x26), BASE, ARG_OPR },

  { "extll",                OPRL(0x12,0x26), BASE, ARG_OPRL },

  { "insll",                OPR(0x12,0x2B), BASE, ARG_OPR },

  { "insll",                OPRL(0x12,0x2B), BASE, ARG_OPRL },

  { "zap",                OPR(0x12,0x30), BASE, ARG_OPR },

  { "zap",                OPRL(0x12,0x30), BASE, ARG_OPRL },

  { "zapnot",                OPR(0x12,0x31), BASE, ARG_OPR },

  { "zapnot",                OPRL(0x12,0x31), BASE, ARG_OPRL },

  { "mskql",                OPR(0x12,0x32), BASE, ARG_OPR },

  { "mskql",                OPRL(0x12,0x32), BASE, ARG_OPRL },

  { "srl",                OPR(0x12,0x34), BASE, ARG_OPR },

  { "srl",                OPRL(0x12,0x34), BASE, ARG_OPRL },

  { "extql",                OPR(0x12,0x36), BASE, ARG_OPR },

  { "extql",                OPRL(0x12,0x36), BASE, ARG_OPRL },

  { "sll",                OPR(0x12,0x39), BASE, ARG_OPR },

  { "sll",                OPRL(0x12,0x39), BASE, ARG_OPRL },

  { "insql",                OPR(0x12,0x3B), BASE, ARG_OPR },

  { "insql",                OPRL(0x12,0x3B), BASE, ARG_OPRL },

  { "sra",                OPR(0x12,0x3C), BASE, ARG_OPR },

  { "sra",                OPRL(0x12,0x3C), BASE, ARG_OPRL },

  { "mskwh",                OPR(0x12,0x52), BASE, ARG_OPR },

  { "mskwh",                OPRL(0x12,0x52), BASE, ARG_OPRL },

  { "inswh",                OPR(0x12,0x57), BASE, ARG_OPR },

  { "inswh",                OPRL(0x12,0x57), BASE, ARG_OPRL },

  { "extwh",                OPR(0x12,0x5A), BASE, ARG_OPR },

  { "extwh",                OPRL(0x12,0x5A), BASE, ARG_OPRL },

  { "msklh",                OPR(0x12,0x62), BASE, ARG_OPR },

  { "msklh",                OPRL(0x12,0x62), BASE, ARG_OPRL },

  { "inslh",                OPR(0x12,0x67), BASE, ARG_OPR },

  { "inslh",                OPRL(0x12,0x67), BASE, ARG_OPRL },

  { "extlh",                OPR(0x12,0x6A), BASE, ARG_OPR },

  { "extlh",                OPRL(0x12,0x6A), BASE, ARG_OPRL },

  { "mskqh",                OPR(0x12,0x72), BASE, ARG_OPR },

  { "mskqh",                OPRL(0x12,0x72), BASE, ARG_OPRL },

  { "insqh",                OPR(0x12,0x77), BASE, ARG_OPR },

  { "insqh",                OPRL(0x12,0x77), BASE, ARG_OPRL },

  { "extqh",                OPR(0x12,0x7A), BASE, ARG_OPR },

  { "extqh",                OPRL(0x12,0x7A), BASE, ARG_OPRL },

  { "mull",                OPR(0x13,0x00), BASE, ARG_OPR },

  { "mull",                OPRL(0x13,0x00), BASE, ARG_OPRL },

  { "mulq",                OPR(0x13,0x20), BASE, ARG_OPR },

  { "mulq",                OPRL(0x13,0x20), BASE, ARG_OPRL },

  { "umulh",                OPR(0x13,0x30), BASE, ARG_OPR },

  { "umulh",                OPRL(0x13,0x30), BASE, ARG_OPRL },

  { "mull/v",                OPR(0x13,0x40), BASE, ARG_OPR },

  { "mull/v",                OPRL(0x13,0x40), BASE, ARG_OPRL },

  { "mulq/v",                OPR(0x13,0x60), BASE, ARG_OPR },

  { "mulq/v",                OPRL(0x13,0x60), BASE, ARG_OPRL },

  { "itofs",                FP(0x14,0x004), CIX, { RA, ZB, FC } },

  { "sqrtf/c",                FP(0x14,0x00A), CIX, ARG_FPZ1 },

  { "sqrts/c",                FP(0x14,0x00B), CIX, ARG_FPZ1 },

  { "itoff",                FP(0x14,0x014), CIX, { RA, ZB, FC } },

  { "itoft",                FP(0x14,0x024), CIX, { RA, ZB, FC } },

  { "sqrtg/c",                FP(0x14,0x02A), CIX, ARG_FPZ1 },

  { "sqrtt/c",                FP(0x14,0x02B), CIX, ARG_FPZ1 },

  { "sqrts/m",                FP(0x14,0x04B), CIX, ARG_FPZ1 },

  { "sqrtt/m",                FP(0x14,0x06B), CIX, ARG_FPZ1 },

  { "sqrtf",                FP(0x14,0x08A), CIX, ARG_FPZ1 },

  { "sqrts",                FP(0x14,0x08B), CIX, ARG_FPZ1 },

  { "sqrtg",                FP(0x14,0x0AA), CIX, ARG_FPZ1 },

  { "sqrtt",                FP(0x14,0x0AB), CIX, ARG_FPZ1 },

  { "sqrts/d",                FP(0x14,0x0CB), CIX, ARG_FPZ1 },

  { "sqrtt/d",                FP(0x14,0x0EB), CIX, ARG_FPZ1 },

  { "sqrtf/uc",                FP(0x14,0x10A), CIX, ARG_FPZ1 },

  { "sqrts/uc",                FP(0x14,0x10B), CIX, ARG_FPZ1 },

  { "sqrtg/uc",                FP(0x14,0x12A), CIX, ARG_FPZ1 },

  { "sqrtt/uc",                FP(0x14,0x12B), CIX, ARG_FPZ1 },

  { "sqrts/um",                FP(0x14,0x14B), CIX, ARG_FPZ1 },

  { "sqrtt/um",                FP(0x14,0x16B), CIX, ARG_FPZ1 },

  { "sqrtf/u",                FP(0x14,0x18A), CIX, ARG_FPZ1 },

  { "sqrts/u",                FP(0x14,0x18B), CIX, ARG_FPZ1 },

  { "sqrtg/u",                FP(0x14,0x1AA), CIX, ARG_FPZ1 },

  { "sqrtt/u",                FP(0x14,0x1AB), CIX, ARG_FPZ1 },

  { "sqrts/ud",                FP(0x14,0x1CB), CIX, ARG_FPZ1 },

  { "sqrtt/ud",                FP(0x14,0x1EB), CIX, ARG_FPZ1 },

  { "sqrtf/sc",                FP(0x14,0x40A), CIX, ARG_FPZ1 },

  { "sqrtg/sc",                FP(0x14,0x42A), CIX, ARG_FPZ1 },

  { "sqrtf/s",                FP(0x14,0x48A), CIX, ARG_FPZ1 },

  { "sqrtg/s",                FP(0x14,0x4AA), CIX, ARG_FPZ1 },

  { "sqrtf/suc",        FP(0x14,0x50A), CIX, ARG_FPZ1 },

  { "sqrts/suc",        FP(0x14,0x50B), CIX, ARG_FPZ1 },

  { "sqrtg/suc",        FP(0x14,0x52A), CIX, ARG_FPZ1 },

  { "sqrtt/suc",        FP(0x14,0x52B), CIX, ARG_FPZ1 },

  { "sqrts/sum",        FP(0x14,0x54B), CIX, ARG_FPZ1 },

  { "sqrtt/sum",        FP(0x14,0x56B), CIX, ARG_FPZ1 },

  { "sqrtf/su",                FP(0x14,0x58A), CIX, ARG_FPZ1 },

  { "sqrts/su",                FP(0x14,0x58B), CIX, ARG_FPZ1 },

  { "sqrtg/su",                FP(0x14,0x5AA), CIX, ARG_FPZ1 },

  { "sqrtt/su",                FP(0x14,0x5AB), CIX, ARG_FPZ1 },

  { "sqrts/sud",        FP(0x14,0x5CB), CIX, ARG_FPZ1 },

  { "sqrtt/sud",        FP(0x14,0x5EB), CIX, ARG_FPZ1 },

  { "sqrts/suic",        FP(0x14,0x70B), CIX, ARG_FPZ1 },

  { "sqrtt/suic",        FP(0x14,0x72B), CIX, ARG_FPZ1 },

  { "sqrts/suim",        FP(0x14,0x74B), CIX, ARG_FPZ1 },

  { "sqrtt/suim",        FP(0x14,0x76B), CIX, ARG_FPZ1 },

  { "sqrts/sui",        FP(0x14,0x78B), CIX, ARG_FPZ1 },

  { "sqrtt/sui",        FP(0x14,0x7AB), CIX, ARG_FPZ1 },

  { "sqrts/suid",        FP(0x14,0x7CB), CIX, ARG_FPZ1 },

  { "sqrtt/suid",        FP(0x14,0x7EB), CIX, ARG_FPZ1 },

  { "addf/c",                FP(0x15,0x000), BASE, ARG_FP },

  { "subf/c",                FP(0x15,0x001), BASE, ARG_FP },

  { "mulf/c",                FP(0x15,0x002), BASE, ARG_FP },

  { "divf/c",                FP(0x15,0x003), BASE, ARG_FP },

  { "cvtdg/c",                FP(0x15,0x01E), BASE, ARG_FPZ1 },

  { "addg/c",                FP(0x15,0x020), BASE, ARG_FP },

  { "subg/c",                FP(0x15,0x021), BASE, ARG_FP },

  { "mulg/c",                FP(0x15,0x022), BASE, ARG_FP },

  { "divg/c",                FP(0x15,0x023), BASE, ARG_FP },

  { "cvtgf/c",                FP(0x15,0x02C), BASE, ARG_FPZ1 },

  { "cvtgd/c",                FP(0x15,0x02D), BASE, ARG_FPZ1 },

  { "cvtgq/c",                FP(0x15,0x02F), BASE, ARG_FPZ1 },

  { "cvtqf/c",                FP(0x15,0x03C), BASE, ARG_FPZ1 },

  { "cvtqg/c",                FP(0x15,0x03E), BASE, ARG_FPZ1 },

  { "addf",                FP(0x15,0x080), BASE, ARG_FP },

  { "negf",                FP(0x15,0x081), BASE, ARG_FPZ1 },        /* pseudo */

  { "subf",                FP(0x15,0x081), BASE, ARG_FP },

  { "mulf",                FP(0x15,0x082), BASE, ARG_FP },

  { "divf",                FP(0x15,0x083), BASE, ARG_FP },

  { "cvtdg",                FP(0x15,0x09E), BASE, ARG_FPZ1 },

  { "addg",                FP(0x15,0x0A0), BASE, ARG_FP },

  { "negg",                FP(0x15,0x0A1), BASE, ARG_FPZ1 },        /* pseudo */

  { "subg",                FP(0x15,0x0A1), BASE, ARG_FP },

  { "mulg",                FP(0x15,0x0A2), BASE, ARG_FP },

  { "divg",                FP(0x15,0x0A3), BASE, ARG_FP },

  { "cmpgeq",                FP(0x15,0x0A5), BASE, ARG_FP },

  { "cmpglt",                FP(0x15,0x0A6), BASE, ARG_FP },

  { "cmpgle",                FP(0x15,0x0A7), BASE, ARG_FP },

  { "cvtgf",                FP(0x15,0x0AC), BASE, ARG_FPZ1 },

  { "cvtgd",                FP(0x15,0x0AD), BASE, ARG_FPZ1 },

  { "cvtgq",                FP(0x15,0x0AF), BASE, ARG_FPZ1 },

  { "cvtqf",                FP(0x15,0x0BC), BASE, ARG_FPZ1 },

  { "cvtqg",                FP(0x15,0x0BE), BASE, ARG_FPZ1 },

  { "addf/uc",                FP(0x15,0x100), BASE, ARG_FP },

  { "subf/uc",                FP(0x15,0x101), BASE, ARG_FP },

  { "mulf/uc",                FP(0x15,0x102), BASE, ARG_FP },

  { "divf/uc",                FP(0x15,0x103), BASE, ARG_FP },

  { "cvtdg/uc",                FP(0x15,0x11E), BASE, ARG_FPZ1 },

  { "addg/uc",                FP(0x15,0x120), BASE, ARG_FP },

  { "subg/uc",                FP(0x15,0x121), BASE, ARG_FP },

  { "mulg/uc",                FP(0x15,0x122), BASE, ARG_FP },

  { "divg/uc",                FP(0x15,0x123), BASE, ARG_FP },

  { "cvtgf/uc",                FP(0x15,0x12C), BASE, ARG_FPZ1 },

  { "cvtgd/uc",                FP(0x15,0x12D), BASE, ARG_FPZ1 },

  { "cvtgq/vc",                FP(0x15,0x12F), BASE, ARG_FPZ1 },

  { "addf/u",                FP(0x15,0x180), BASE, ARG_FP },

  { "subf/u",                FP(0x15,0x181), BASE, ARG_FP },

  { "mulf/u",                FP(0x15,0x182), BASE, ARG_FP },

  { "divf/u",                FP(0x15,0x183), BASE, ARG_FP },

  { "cvtdg/u",                FP(0x15,0x19E), BASE, ARG_FPZ1 },

  { "addg/u",                FP(0x15,0x1A0), BASE, ARG_FP },

  { "subg/u",                FP(0x15,0x1A1), BASE, ARG_FP },

  { "mulg/u",                FP(0x15,0x1A2), BASE, ARG_FP },

  { "divg/u",                FP(0x15,0x1A3), BASE, ARG_FP },

  { "cvtgf/u",                FP(0x15,0x1AC), BASE, ARG_FPZ1 },

  { "cvtgd/u",                FP(0x15,0x1AD), BASE, ARG_FPZ1 },

  { "cvtgq/v",                FP(0x15,0x1AF), BASE, ARG_FPZ1 },

  { "addf/sc",                FP(0x15,0x400), BASE, ARG_FP },

  { "subf/sc",                FP(0x15,0x401), BASE, ARG_FP },

  { "mulf/sc",                FP(0x15,0x402), BASE, ARG_FP },

  { "divf/sc",                FP(0x15,0x403), BASE, ARG_FP },

  { "cvtdg/sc",                FP(0x15,0x41E), BASE, ARG_FPZ1 },

  { "addg/sc",                FP(0x15,0x420), BASE, ARG_FP },

  { "subg/sc",                FP(0x15,0x421), BASE, ARG_FP },

  { "mulg/sc",                FP(0x15,0x422), BASE, ARG_FP },

  { "divg/sc",                FP(0x15,0x423), BASE, ARG_FP },

  { "cvtgf/sc",                FP(0x15,0x42C), BASE, ARG_FPZ1 },