root / hw / cs4231.c @ 979ba184
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/*
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* QEMU Crystal CS4231 audio chip emulation
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*
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* Copyright (c) 2006 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "sun4m.h" |
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#include "sysbus.h" |
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/* debug CS4231 */
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//#define DEBUG_CS
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/*
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* In addition to Crystal CS4231 there is a DMA controller on Sparc.
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*/
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#define CS_SIZE 0x40 |
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#define CS_REGS 16 |
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#define CS_DREGS 32 |
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#define CS_MAXDREG (CS_DREGS - 1) |
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typedef struct CSState { |
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SysBusDevice busdev; |
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qemu_irq irq; |
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uint32_t regs[CS_REGS]; |
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uint8_t dregs[CS_DREGS]; |
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} CSState; |
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#define CS_RAP(s) ((s)->regs[0] & CS_MAXDREG) |
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#define CS_VER 0xa0 |
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#define CS_CDC_VER 0x8a |
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#ifdef DEBUG_CS
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#define DPRINTF(fmt, ...) \
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do { printf("CS: " fmt , ## __VA_ARGS__); } while (0) |
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#else
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#define DPRINTF(fmt, ...)
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#endif
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static void cs_reset(void *opaque) |
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{ |
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CSState *s = opaque; |
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memset(s->regs, 0, CS_REGS * 4); |
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memset(s->dregs, 0, CS_DREGS);
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s->dregs[12] = CS_CDC_VER;
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s->dregs[25] = CS_VER;
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} |
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static uint32_t cs_mem_readl(void *opaque, target_phys_addr_t addr) |
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{ |
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CSState *s = opaque; |
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uint32_t saddr, ret; |
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saddr = addr >> 2;
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switch (saddr) {
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case 1: |
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switch (CS_RAP(s)) {
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case 3: // Write only |
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ret = 0;
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break;
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default:
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ret = s->dregs[CS_RAP(s)]; |
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break;
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} |
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DPRINTF("read dreg[%d]: 0x%8.8x\n", CS_RAP(s), ret);
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break;
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default:
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ret = s->regs[saddr]; |
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DPRINTF("read reg[%d]: 0x%8.8x\n", saddr, ret);
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break;
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} |
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return ret;
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} |
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static void cs_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
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{ |
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CSState *s = opaque; |
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uint32_t saddr; |
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saddr = addr >> 2;
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DPRINTF("write reg[%d]: 0x%8.8x -> 0x%8.8x\n", saddr, s->regs[saddr], val);
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switch (saddr) {
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case 1: |
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DPRINTF("write dreg[%d]: 0x%2.2x -> 0x%2.2x\n", CS_RAP(s),
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s->dregs[CS_RAP(s)], val); |
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switch(CS_RAP(s)) {
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case 11: |
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case 25: // Read only |
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break;
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case 12: |
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val &= 0x40;
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val |= CS_CDC_VER; // Codec version
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s->dregs[CS_RAP(s)] = val; |
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break;
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default:
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s->dregs[CS_RAP(s)] = val; |
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break;
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} |
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break;
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case 2: // Read only |
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break;
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case 4: |
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if (val & 1) |
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cs_reset(s); |
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val &= 0x7f;
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s->regs[saddr] = val; |
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break;
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default:
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s->regs[saddr] = val; |
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break;
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} |
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} |
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static CPUReadMemoryFunc * const cs_mem_read[3] = { |
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cs_mem_readl, |
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cs_mem_readl, |
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cs_mem_readl, |
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}; |
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static CPUWriteMemoryFunc * const cs_mem_write[3] = { |
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cs_mem_writel, |
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cs_mem_writel, |
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cs_mem_writel, |
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}; |
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static void cs_save(QEMUFile *f, void *opaque) |
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{ |
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CSState *s = opaque; |
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unsigned int i; |
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for (i = 0; i < CS_REGS; i++) |
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qemu_put_be32s(f, &s->regs[i]); |
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qemu_put_buffer(f, s->dregs, CS_DREGS); |
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} |
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static int cs_load(QEMUFile *f, void *opaque, int version_id) |
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{ |
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CSState *s = opaque; |
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unsigned int i; |
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if (version_id > 1) |
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return -EINVAL;
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for (i = 0; i < CS_REGS; i++) |
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qemu_get_be32s(f, &s->regs[i]); |
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qemu_get_buffer(f, s->dregs, CS_DREGS); |
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return 0; |
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} |
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static int cs4231_init1(SysBusDevice *dev) |
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{ |
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int io;
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CSState *s = FROM_SYSBUS(CSState, dev); |
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io = cpu_register_io_memory(cs_mem_read, cs_mem_write, s); |
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sysbus_init_mmio(dev, CS_SIZE, io); |
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sysbus_init_irq(dev, &s->irq); |
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register_savevm("cs4231", -1, 1, cs_save, cs_load, s); |
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qemu_register_reset(cs_reset, s); |
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cs_reset(s); |
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return 0; |
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} |
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static SysBusDeviceInfo cs4231_info = {
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.init = cs4231_init1, |
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.qdev.name = "SUNW,CS4231",
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.qdev.size = sizeof(CSState),
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.qdev.props = (Property[]) { |
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{.name = NULL}
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} |
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}; |
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static void cs4231_register_devices(void) |
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{ |
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sysbus_register_withprop(&cs4231_info); |
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} |
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device_init(cs4231_register_devices) |