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1 | 7d13299d | bellard | /*
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2 | 7d13299d | bellard | * i386 emulator main execution loop
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3 | 7d13299d | bellard | *
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4 | 7d13299d | bellard | * Copyright (c) 2003 Fabrice Bellard
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5 | 7d13299d | bellard | *
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6 | 3ef693a0 | bellard | * This library is free software; you can redistribute it and/or
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7 | 3ef693a0 | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 3ef693a0 | bellard | * License as published by the Free Software Foundation; either
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9 | 3ef693a0 | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 7d13299d | bellard | *
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11 | 3ef693a0 | bellard | * This library is distributed in the hope that it will be useful,
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12 | 3ef693a0 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 3ef693a0 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 3ef693a0 | bellard | * Lesser General Public License for more details.
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15 | 7d13299d | bellard | *
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16 | 3ef693a0 | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 3ef693a0 | bellard | * License along with this library; if not, write to the Free Software
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18 | 3ef693a0 | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | 7d13299d | bellard | */
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20 | e4533c7a | bellard | #include "config.h" |
21 | 93ac68bc | bellard | #include "exec.h" |
22 | 956034d7 | bellard | #include "disas.h" |
23 | 7d13299d | bellard | |
24 | 36bdbe54 | bellard | int tb_invalidated_flag;
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25 | 36bdbe54 | bellard | |
26 | dc99065b | bellard | //#define DEBUG_EXEC
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27 | 9de5e440 | bellard | //#define DEBUG_SIGNAL
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28 | 7d13299d | bellard | |
29 | 93ac68bc | bellard | #if defined(TARGET_ARM) || defined(TARGET_SPARC)
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30 | e4533c7a | bellard | /* XXX: unify with i386 target */
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31 | e4533c7a | bellard | void cpu_loop_exit(void) |
32 | e4533c7a | bellard | { |
33 | e4533c7a | bellard | longjmp(env->jmp_env, 1);
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34 | e4533c7a | bellard | } |
35 | e4533c7a | bellard | #endif
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36 | e4533c7a | bellard | |
37 | 7d13299d | bellard | /* main execution loop */
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38 | 7d13299d | bellard | |
39 | e4533c7a | bellard | int cpu_exec(CPUState *env1)
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40 | 7d13299d | bellard | { |
41 | e4533c7a | bellard | int saved_T0, saved_T1, saved_T2;
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42 | e4533c7a | bellard | CPUState *saved_env; |
43 | 04369ff2 | bellard | #ifdef reg_EAX
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44 | 04369ff2 | bellard | int saved_EAX;
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45 | 04369ff2 | bellard | #endif
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46 | 04369ff2 | bellard | #ifdef reg_ECX
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47 | 04369ff2 | bellard | int saved_ECX;
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48 | 04369ff2 | bellard | #endif
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49 | 04369ff2 | bellard | #ifdef reg_EDX
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50 | 04369ff2 | bellard | int saved_EDX;
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51 | 04369ff2 | bellard | #endif
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52 | 04369ff2 | bellard | #ifdef reg_EBX
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53 | 04369ff2 | bellard | int saved_EBX;
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54 | 04369ff2 | bellard | #endif
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55 | 04369ff2 | bellard | #ifdef reg_ESP
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56 | 04369ff2 | bellard | int saved_ESP;
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57 | 04369ff2 | bellard | #endif
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58 | 04369ff2 | bellard | #ifdef reg_EBP
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59 | 04369ff2 | bellard | int saved_EBP;
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60 | 04369ff2 | bellard | #endif
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61 | 04369ff2 | bellard | #ifdef reg_ESI
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62 | 04369ff2 | bellard | int saved_ESI;
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63 | 04369ff2 | bellard | #endif
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64 | 04369ff2 | bellard | #ifdef reg_EDI
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65 | 04369ff2 | bellard | int saved_EDI;
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66 | 04369ff2 | bellard | #endif
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67 | 8c6939c0 | bellard | #ifdef __sparc__
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68 | 8c6939c0 | bellard | int saved_i7, tmp_T0;
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69 | 8c6939c0 | bellard | #endif
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70 | 68a79315 | bellard | int code_gen_size, ret, interrupt_request;
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71 | 7d13299d | bellard | void (*gen_func)(void); |
72 | 9de5e440 | bellard | TranslationBlock *tb, **ptb; |
73 | dab2ed99 | bellard | uint8_t *tc_ptr, *cs_base, *pc; |
74 | 6dbad63e | bellard | unsigned int flags; |
75 | 8c6939c0 | bellard | |
76 | 7d13299d | bellard | /* first we save global registers */
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77 | 7d13299d | bellard | saved_T0 = T0; |
78 | 7d13299d | bellard | saved_T1 = T1; |
79 | e4533c7a | bellard | saved_T2 = T2; |
80 | 7d13299d | bellard | saved_env = env; |
81 | 7d13299d | bellard | env = env1; |
82 | e4533c7a | bellard | #ifdef __sparc__
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83 | e4533c7a | bellard | /* we also save i7 because longjmp may not restore it */
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84 | e4533c7a | bellard | asm volatile ("mov %%i7, %0" : "=r" (saved_i7)); |
85 | e4533c7a | bellard | #endif
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86 | e4533c7a | bellard | |
87 | e4533c7a | bellard | #if defined(TARGET_I386)
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88 | 04369ff2 | bellard | #ifdef reg_EAX
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89 | 04369ff2 | bellard | saved_EAX = EAX; |
90 | 04369ff2 | bellard | EAX = env->regs[R_EAX]; |
91 | 04369ff2 | bellard | #endif
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92 | 04369ff2 | bellard | #ifdef reg_ECX
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93 | 04369ff2 | bellard | saved_ECX = ECX; |
94 | 04369ff2 | bellard | ECX = env->regs[R_ECX]; |
95 | 04369ff2 | bellard | #endif
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96 | 04369ff2 | bellard | #ifdef reg_EDX
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97 | 04369ff2 | bellard | saved_EDX = EDX; |
98 | 04369ff2 | bellard | EDX = env->regs[R_EDX]; |
99 | 04369ff2 | bellard | #endif
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100 | 04369ff2 | bellard | #ifdef reg_EBX
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101 | 04369ff2 | bellard | saved_EBX = EBX; |
102 | 04369ff2 | bellard | EBX = env->regs[R_EBX]; |
103 | 04369ff2 | bellard | #endif
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104 | 04369ff2 | bellard | #ifdef reg_ESP
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105 | 04369ff2 | bellard | saved_ESP = ESP; |
106 | 04369ff2 | bellard | ESP = env->regs[R_ESP]; |
107 | 04369ff2 | bellard | #endif
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108 | 04369ff2 | bellard | #ifdef reg_EBP
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109 | 04369ff2 | bellard | saved_EBP = EBP; |
110 | 04369ff2 | bellard | EBP = env->regs[R_EBP]; |
111 | 04369ff2 | bellard | #endif
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112 | 04369ff2 | bellard | #ifdef reg_ESI
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113 | 04369ff2 | bellard | saved_ESI = ESI; |
114 | 04369ff2 | bellard | ESI = env->regs[R_ESI]; |
115 | 04369ff2 | bellard | #endif
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116 | 04369ff2 | bellard | #ifdef reg_EDI
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117 | 04369ff2 | bellard | saved_EDI = EDI; |
118 | 04369ff2 | bellard | EDI = env->regs[R_EDI]; |
119 | 04369ff2 | bellard | #endif
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120 | 7d13299d | bellard | |
121 | 9de5e440 | bellard | /* put eflags in CPU temporary format */
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122 | fc2b4c48 | bellard | CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
123 | fc2b4c48 | bellard | DF = 1 - (2 * ((env->eflags >> 10) & 1)); |
124 | 9de5e440 | bellard | CC_OP = CC_OP_EFLAGS; |
125 | fc2b4c48 | bellard | env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
126 | e4533c7a | bellard | #elif defined(TARGET_ARM)
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127 | e4533c7a | bellard | { |
128 | e4533c7a | bellard | unsigned int psr; |
129 | e4533c7a | bellard | psr = env->cpsr; |
130 | e4533c7a | bellard | env->CF = (psr >> 29) & 1; |
131 | e4533c7a | bellard | env->NZF = (psr & 0xc0000000) ^ 0x40000000; |
132 | e4533c7a | bellard | env->VF = (psr << 3) & 0x80000000; |
133 | e4533c7a | bellard | env->cpsr = psr & ~0xf0000000;
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134 | e4533c7a | bellard | } |
135 | 93ac68bc | bellard | #elif defined(TARGET_SPARC)
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136 | 67867308 | bellard | #elif defined(TARGET_PPC)
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137 | e4533c7a | bellard | #else
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138 | e4533c7a | bellard | #error unsupported target CPU
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139 | e4533c7a | bellard | #endif
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140 | 3fb2ded1 | bellard | env->exception_index = -1;
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141 | 9d27abd9 | bellard | |
142 | 7d13299d | bellard | /* prepare setjmp context for exception handling */
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143 | 3fb2ded1 | bellard | for(;;) {
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144 | 3fb2ded1 | bellard | if (setjmp(env->jmp_env) == 0) { |
145 | ee8b7021 | bellard | env->current_tb = NULL;
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146 | 3fb2ded1 | bellard | /* if an exception is pending, we execute it here */
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147 | 3fb2ded1 | bellard | if (env->exception_index >= 0) { |
148 | 3fb2ded1 | bellard | if (env->exception_index >= EXCP_INTERRUPT) {
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149 | 3fb2ded1 | bellard | /* exit request from the cpu execution loop */
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150 | 3fb2ded1 | bellard | ret = env->exception_index; |
151 | 3fb2ded1 | bellard | break;
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152 | 3fb2ded1 | bellard | } else if (env->user_mode_only) { |
153 | 3fb2ded1 | bellard | /* if user mode only, we simulate a fake exception
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154 | 3fb2ded1 | bellard | which will be hanlded outside the cpu execution
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155 | 3fb2ded1 | bellard | loop */
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156 | 83479e77 | bellard | #if defined(TARGET_I386)
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157 | 3fb2ded1 | bellard | do_interrupt_user(env->exception_index, |
158 | 3fb2ded1 | bellard | env->exception_is_int, |
159 | 3fb2ded1 | bellard | env->error_code, |
160 | 3fb2ded1 | bellard | env->exception_next_eip); |
161 | 83479e77 | bellard | #endif
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162 | 3fb2ded1 | bellard | ret = env->exception_index; |
163 | 3fb2ded1 | bellard | break;
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164 | 3fb2ded1 | bellard | } else {
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165 | 83479e77 | bellard | #if defined(TARGET_I386)
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166 | 3fb2ded1 | bellard | /* simulate a real cpu exception. On i386, it can
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167 | 3fb2ded1 | bellard | trigger new exceptions, but we do not handle
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168 | 3fb2ded1 | bellard | double or triple faults yet. */
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169 | 3fb2ded1 | bellard | do_interrupt(env->exception_index, |
170 | 3fb2ded1 | bellard | env->exception_is_int, |
171 | 3fb2ded1 | bellard | env->error_code, |
172 | d05e66d2 | bellard | env->exception_next_eip, 0);
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173 | ce09776b | bellard | #elif defined(TARGET_PPC)
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174 | ce09776b | bellard | do_interrupt(env); |
175 | 83479e77 | bellard | #endif
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176 | 3fb2ded1 | bellard | } |
177 | 3fb2ded1 | bellard | env->exception_index = -1;
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178 | 3fb2ded1 | bellard | } |
179 | 3fb2ded1 | bellard | T0 = 0; /* force lookup of first TB */ |
180 | 3fb2ded1 | bellard | for(;;) {
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181 | 8c6939c0 | bellard | #ifdef __sparc__
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182 | 3fb2ded1 | bellard | /* g1 can be modified by some libc? functions */
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183 | 3fb2ded1 | bellard | tmp_T0 = T0; |
184 | 8c6939c0 | bellard | #endif
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185 | 68a79315 | bellard | interrupt_request = env->interrupt_request; |
186 | 2e255c6b | bellard | if (__builtin_expect(interrupt_request, 0)) { |
187 | 68a79315 | bellard | #if defined(TARGET_I386)
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188 | 68a79315 | bellard | /* if hardware interrupt pending, we execute it */
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189 | 68a79315 | bellard | if ((interrupt_request & CPU_INTERRUPT_HARD) &&
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190 | 3f337316 | bellard | (env->eflags & IF_MASK) && |
191 | 3f337316 | bellard | !(env->hflags & HF_INHIBIT_IRQ_MASK)) { |
192 | 68a79315 | bellard | int intno;
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193 | 68a79315 | bellard | intno = cpu_x86_get_pic_interrupt(env); |
194 | 68a79315 | bellard | if (loglevel) {
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195 | 68a79315 | bellard | fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno);
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196 | 68a79315 | bellard | } |
197 | d05e66d2 | bellard | do_interrupt(intno, 0, 0, 0, 1); |
198 | 68a79315 | bellard | env->interrupt_request &= ~CPU_INTERRUPT_HARD; |
199 | 907a5b26 | bellard | /* ensure that no TB jump will be modified as
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200 | 907a5b26 | bellard | the program flow was changed */
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201 | 907a5b26 | bellard | #ifdef __sparc__
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202 | 907a5b26 | bellard | tmp_T0 = 0;
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203 | 907a5b26 | bellard | #else
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204 | 907a5b26 | bellard | T0 = 0;
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205 | 907a5b26 | bellard | #endif
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206 | 68a79315 | bellard | } |
207 | ce09776b | bellard | #elif defined(TARGET_PPC)
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208 | ce09776b | bellard | if ((interrupt_request & CPU_INTERRUPT_HARD)) {
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209 | ce09776b | bellard | do_queue_exception(EXCP_EXTERNAL); |
210 | ce09776b | bellard | if (check_exception_state(env))
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211 | ce09776b | bellard | do_interrupt(env); |
212 | ce09776b | bellard | env->interrupt_request &= ~CPU_INTERRUPT_HARD; |
213 | ce09776b | bellard | } |
214 | 68a79315 | bellard | #endif
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215 | bf3e8bf1 | bellard | if (interrupt_request & CPU_INTERRUPT_EXITTB) {
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216 | bf3e8bf1 | bellard | env->interrupt_request &= ~CPU_INTERRUPT_EXITTB; |
217 | bf3e8bf1 | bellard | /* ensure that no TB jump will be modified as
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218 | bf3e8bf1 | bellard | the program flow was changed */
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219 | bf3e8bf1 | bellard | #ifdef __sparc__
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220 | bf3e8bf1 | bellard | tmp_T0 = 0;
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221 | bf3e8bf1 | bellard | #else
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222 | bf3e8bf1 | bellard | T0 = 0;
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223 | bf3e8bf1 | bellard | #endif
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224 | bf3e8bf1 | bellard | } |
225 | 68a79315 | bellard | if (interrupt_request & CPU_INTERRUPT_EXIT) {
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226 | 68a79315 | bellard | env->interrupt_request &= ~CPU_INTERRUPT_EXIT; |
227 | 68a79315 | bellard | env->exception_index = EXCP_INTERRUPT; |
228 | 68a79315 | bellard | cpu_loop_exit(); |
229 | 68a79315 | bellard | } |
230 | 3fb2ded1 | bellard | } |
231 | 7d13299d | bellard | #ifdef DEBUG_EXEC
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232 | 3fb2ded1 | bellard | if (loglevel) {
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233 | e4533c7a | bellard | #if defined(TARGET_I386)
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234 | 3fb2ded1 | bellard | /* restore flags in standard format */
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235 | 3fb2ded1 | bellard | env->regs[R_EAX] = EAX; |
236 | 3fb2ded1 | bellard | env->regs[R_EBX] = EBX; |
237 | 3fb2ded1 | bellard | env->regs[R_ECX] = ECX; |
238 | 3fb2ded1 | bellard | env->regs[R_EDX] = EDX; |
239 | 3fb2ded1 | bellard | env->regs[R_ESI] = ESI; |
240 | 3fb2ded1 | bellard | env->regs[R_EDI] = EDI; |
241 | 3fb2ded1 | bellard | env->regs[R_EBP] = EBP; |
242 | 3fb2ded1 | bellard | env->regs[R_ESP] = ESP; |
243 | 3fb2ded1 | bellard | env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK); |
244 | 68a79315 | bellard | cpu_x86_dump_state(env, logfile, X86_DUMP_CCOP); |
245 | 3fb2ded1 | bellard | env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
246 | e4533c7a | bellard | #elif defined(TARGET_ARM)
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247 | 1b21b62a | bellard | env->cpsr = compute_cpsr(); |
248 | 3fb2ded1 | bellard | cpu_arm_dump_state(env, logfile, 0);
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249 | 1b21b62a | bellard | env->cpsr &= ~0xf0000000;
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250 | 93ac68bc | bellard | #elif defined(TARGET_SPARC)
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251 | 93a40ea9 | bellard | cpu_sparc_dump_state (env, logfile, 0);
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252 | 67867308 | bellard | #elif defined(TARGET_PPC)
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253 | 67867308 | bellard | cpu_ppc_dump_state(env, logfile, 0);
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254 | e4533c7a | bellard | #else
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255 | e4533c7a | bellard | #error unsupported target CPU
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256 | e4533c7a | bellard | #endif
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257 | 3fb2ded1 | bellard | } |
258 | 7d13299d | bellard | #endif
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259 | 3f337316 | bellard | /* we record a subset of the CPU state. It will
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260 | 3f337316 | bellard | always be the same before a given translated block
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261 | 3f337316 | bellard | is executed. */
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262 | e4533c7a | bellard | #if defined(TARGET_I386)
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263 | 2e255c6b | bellard | flags = env->hflags; |
264 | 3f337316 | bellard | flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK)); |
265 | 3fb2ded1 | bellard | cs_base = env->segs[R_CS].base; |
266 | 3fb2ded1 | bellard | pc = cs_base + env->eip; |
267 | e4533c7a | bellard | #elif defined(TARGET_ARM)
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268 | 3fb2ded1 | bellard | flags = 0;
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269 | 3fb2ded1 | bellard | cs_base = 0;
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270 | 3fb2ded1 | bellard | pc = (uint8_t *)env->regs[15];
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271 | 93ac68bc | bellard | #elif defined(TARGET_SPARC)
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272 | 67867308 | bellard | flags = 0;
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273 | ce09776b | bellard | cs_base = (uint8_t *)env->npc; |
274 | 67867308 | bellard | pc = (uint8_t *) env->pc; |
275 | 67867308 | bellard | #elif defined(TARGET_PPC)
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276 | 67867308 | bellard | flags = 0;
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277 | 67867308 | bellard | cs_base = 0;
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278 | 67867308 | bellard | pc = (uint8_t *)env->nip; |
279 | e4533c7a | bellard | #else
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280 | e4533c7a | bellard | #error unsupported CPU
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281 | e4533c7a | bellard | #endif
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282 | 3fb2ded1 | bellard | tb = tb_find(&ptb, (unsigned long)pc, (unsigned long)cs_base, |
283 | 3fb2ded1 | bellard | flags); |
284 | d4e8164f | bellard | if (!tb) {
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285 | 1376847f | bellard | TranslationBlock **ptb1; |
286 | 1376847f | bellard | unsigned int h; |
287 | 1376847f | bellard | target_ulong phys_pc, phys_page1, phys_page2, virt_page2; |
288 | 1376847f | bellard | |
289 | 1376847f | bellard | |
290 | 3fb2ded1 | bellard | spin_lock(&tb_lock); |
291 | 1376847f | bellard | |
292 | 1376847f | bellard | tb_invalidated_flag = 0;
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293 | 1376847f | bellard | |
294 | 1376847f | bellard | /* find translated block using physical mappings */
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295 | 1376847f | bellard | phys_pc = get_phys_addr_code(env, (unsigned long)pc); |
296 | 1376847f | bellard | phys_page1 = phys_pc & TARGET_PAGE_MASK; |
297 | 1376847f | bellard | phys_page2 = -1;
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298 | 1376847f | bellard | h = tb_phys_hash_func(phys_pc); |
299 | 1376847f | bellard | ptb1 = &tb_phys_hash[h]; |
300 | 1376847f | bellard | for(;;) {
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301 | 1376847f | bellard | tb = *ptb1; |
302 | 1376847f | bellard | if (!tb)
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303 | 1376847f | bellard | goto not_found;
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304 | 1376847f | bellard | if (tb->pc == (unsigned long)pc && |
305 | 1376847f | bellard | tb->page_addr[0] == phys_page1 &&
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306 | 1376847f | bellard | tb->cs_base == (unsigned long)cs_base && |
307 | 1376847f | bellard | tb->flags == flags) { |
308 | 1376847f | bellard | /* check next page if needed */
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309 | b516f85c | bellard | if (tb->page_addr[1] != -1) { |
310 | b516f85c | bellard | virt_page2 = ((unsigned long)pc & TARGET_PAGE_MASK) + |
311 | b516f85c | bellard | TARGET_PAGE_SIZE; |
312 | 1376847f | bellard | phys_page2 = get_phys_addr_code(env, virt_page2); |
313 | 1376847f | bellard | if (tb->page_addr[1] == phys_page2) |
314 | 1376847f | bellard | goto found;
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315 | 1376847f | bellard | } else {
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316 | 1376847f | bellard | goto found;
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317 | 1376847f | bellard | } |
318 | 1376847f | bellard | } |
319 | 1376847f | bellard | ptb1 = &tb->phys_hash_next; |
320 | 1376847f | bellard | } |
321 | 1376847f | bellard | not_found:
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322 | 3fb2ded1 | bellard | /* if no translated code available, then translate it now */
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323 | d4e8164f | bellard | tb = tb_alloc((unsigned long)pc); |
324 | 3fb2ded1 | bellard | if (!tb) {
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325 | 3fb2ded1 | bellard | /* flush must be done */
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326 | b453b70b | bellard | tb_flush(env); |
327 | 3fb2ded1 | bellard | /* cannot fail at this point */
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328 | 3fb2ded1 | bellard | tb = tb_alloc((unsigned long)pc); |
329 | 3fb2ded1 | bellard | /* don't forget to invalidate previous TB info */
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330 | 3fb2ded1 | bellard | ptb = &tb_hash[tb_hash_func((unsigned long)pc)]; |
331 | 3fb2ded1 | bellard | T0 = 0;
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332 | 3fb2ded1 | bellard | } |
333 | 3fb2ded1 | bellard | tc_ptr = code_gen_ptr; |
334 | 3fb2ded1 | bellard | tb->tc_ptr = tc_ptr; |
335 | 3fb2ded1 | bellard | tb->cs_base = (unsigned long)cs_base; |
336 | 3fb2ded1 | bellard | tb->flags = flags; |
337 | facc68be | bellard | cpu_gen_code(env, tb, CODE_GEN_MAX_SIZE, &code_gen_size); |
338 | 1376847f | bellard | code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1)); |
339 | 1376847f | bellard | |
340 | 1376847f | bellard | /* check next page if needed */
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341 | 1376847f | bellard | virt_page2 = ((unsigned long)pc + tb->size - 1) & TARGET_PAGE_MASK; |
342 | 1376847f | bellard | phys_page2 = -1;
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343 | 1376847f | bellard | if (((unsigned long)pc & TARGET_PAGE_MASK) != virt_page2) { |
344 | 1376847f | bellard | phys_page2 = get_phys_addr_code(env, virt_page2); |
345 | 1376847f | bellard | } |
346 | 1376847f | bellard | tb_link_phys(tb, phys_pc, phys_page2); |
347 | 1376847f | bellard | |
348 | 1376847f | bellard | found:
|
349 | 36bdbe54 | bellard | if (tb_invalidated_flag) {
|
350 | 36bdbe54 | bellard | /* as some TB could have been invalidated because
|
351 | 36bdbe54 | bellard | of memory exceptions while generating the code, we
|
352 | 36bdbe54 | bellard | must recompute the hash index here */
|
353 | 36bdbe54 | bellard | ptb = &tb_hash[tb_hash_func((unsigned long)pc)]; |
354 | 36bdbe54 | bellard | while (*ptb != NULL) |
355 | 36bdbe54 | bellard | ptb = &(*ptb)->hash_next; |
356 | 36bdbe54 | bellard | T0 = 0;
|
357 | 36bdbe54 | bellard | } |
358 | 1376847f | bellard | /* we add the TB in the virtual pc hash table */
|
359 | 3fb2ded1 | bellard | *ptb = tb; |
360 | 3fb2ded1 | bellard | tb->hash_next = NULL;
|
361 | 3fb2ded1 | bellard | tb_link(tb); |
362 | 25eb4484 | bellard | spin_unlock(&tb_lock); |
363 | 9de5e440 | bellard | } |
364 | 9d27abd9 | bellard | #ifdef DEBUG_EXEC
|
365 | 3fb2ded1 | bellard | if (loglevel) {
|
366 | 3fb2ded1 | bellard | fprintf(logfile, "Trace 0x%08lx [0x%08lx] %s\n",
|
367 | 3fb2ded1 | bellard | (long)tb->tc_ptr, (long)tb->pc, |
368 | 3fb2ded1 | bellard | lookup_symbol((void *)tb->pc));
|
369 | 3fb2ded1 | bellard | } |
370 | 9d27abd9 | bellard | #endif
|
371 | 8c6939c0 | bellard | #ifdef __sparc__
|
372 | 3fb2ded1 | bellard | T0 = tmp_T0; |
373 | 8c6939c0 | bellard | #endif
|
374 | facc68be | bellard | /* see if we can patch the calling TB. */
|
375 | bf3e8bf1 | bellard | if (T0 != 0 |
376 | bf3e8bf1 | bellard | #if defined(TARGET_I386) && defined(USE_CODE_COPY)
|
377 | bf3e8bf1 | bellard | && (tb->cflags & CF_CODE_COPY) == |
378 | bf3e8bf1 | bellard | (((TranslationBlock *)(T0 & ~3))->cflags & CF_CODE_COPY)
|
379 | bf3e8bf1 | bellard | #endif
|
380 | bf3e8bf1 | bellard | ) { |
381 | 3fb2ded1 | bellard | spin_lock(&tb_lock); |
382 | 3fb2ded1 | bellard | tb_add_jump((TranslationBlock *)(T0 & ~3), T0 & 3, tb); |
383 | 97eb5b14 | bellard | #if defined(USE_CODE_COPY)
|
384 | 97eb5b14 | bellard | /* propagates the FP use info */
|
385 | 97eb5b14 | bellard | ((TranslationBlock *)(T0 & ~3))->cflags |=
|
386 | 97eb5b14 | bellard | (tb->cflags & CF_FP_USED); |
387 | 97eb5b14 | bellard | #endif
|
388 | 3fb2ded1 | bellard | spin_unlock(&tb_lock); |
389 | 3fb2ded1 | bellard | } |
390 | 3fb2ded1 | bellard | tc_ptr = tb->tc_ptr; |
391 | 83479e77 | bellard | env->current_tb = tb; |
392 | 3fb2ded1 | bellard | /* execute the generated code */
|
393 | 3fb2ded1 | bellard | gen_func = (void *)tc_ptr;
|
394 | 8c6939c0 | bellard | #if defined(__sparc__)
|
395 | 3fb2ded1 | bellard | __asm__ __volatile__("call %0\n\t"
|
396 | 3fb2ded1 | bellard | "mov %%o7,%%i0"
|
397 | 3fb2ded1 | bellard | : /* no outputs */
|
398 | 3fb2ded1 | bellard | : "r" (gen_func)
|
399 | 3fb2ded1 | bellard | : "i0", "i1", "i2", "i3", "i4", "i5"); |
400 | 8c6939c0 | bellard | #elif defined(__arm__)
|
401 | 3fb2ded1 | bellard | asm volatile ("mov pc, %0\n\t" |
402 | 3fb2ded1 | bellard | ".global exec_loop\n\t"
|
403 | 3fb2ded1 | bellard | "exec_loop:\n\t"
|
404 | 3fb2ded1 | bellard | : /* no outputs */
|
405 | 3fb2ded1 | bellard | : "r" (gen_func)
|
406 | 3fb2ded1 | bellard | : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14"); |
407 | bf3e8bf1 | bellard | #elif defined(TARGET_I386) && defined(USE_CODE_COPY)
|
408 | bf3e8bf1 | bellard | { |
409 | bf3e8bf1 | bellard | if (!(tb->cflags & CF_CODE_COPY)) {
|
410 | 97eb5b14 | bellard | if ((tb->cflags & CF_FP_USED) && env->native_fp_regs) {
|
411 | 97eb5b14 | bellard | save_native_fp_state(env); |
412 | 97eb5b14 | bellard | } |
413 | bf3e8bf1 | bellard | gen_func(); |
414 | bf3e8bf1 | bellard | } else {
|
415 | 97eb5b14 | bellard | if ((tb->cflags & CF_FP_USED) && !env->native_fp_regs) {
|
416 | 97eb5b14 | bellard | restore_native_fp_state(env); |
417 | 97eb5b14 | bellard | } |
418 | bf3e8bf1 | bellard | /* we work with native eflags */
|
419 | bf3e8bf1 | bellard | CC_SRC = cc_table[CC_OP].compute_all(); |
420 | bf3e8bf1 | bellard | CC_OP = CC_OP_EFLAGS; |
421 | bf3e8bf1 | bellard | asm(".globl exec_loop\n" |
422 | bf3e8bf1 | bellard | "\n"
|
423 | bf3e8bf1 | bellard | "debug1:\n"
|
424 | bf3e8bf1 | bellard | " pushl %%ebp\n"
|
425 | bf3e8bf1 | bellard | " fs movl %10, %9\n"
|
426 | bf3e8bf1 | bellard | " fs movl %11, %%eax\n"
|
427 | bf3e8bf1 | bellard | " andl $0x400, %%eax\n"
|
428 | bf3e8bf1 | bellard | " fs orl %8, %%eax\n"
|
429 | bf3e8bf1 | bellard | " pushl %%eax\n"
|
430 | bf3e8bf1 | bellard | " popf\n"
|
431 | bf3e8bf1 | bellard | " fs movl %%esp, %12\n"
|
432 | bf3e8bf1 | bellard | " fs movl %0, %%eax\n"
|
433 | bf3e8bf1 | bellard | " fs movl %1, %%ecx\n"
|
434 | bf3e8bf1 | bellard | " fs movl %2, %%edx\n"
|
435 | bf3e8bf1 | bellard | " fs movl %3, %%ebx\n"
|
436 | bf3e8bf1 | bellard | " fs movl %4, %%esp\n"
|
437 | bf3e8bf1 | bellard | " fs movl %5, %%ebp\n"
|
438 | bf3e8bf1 | bellard | " fs movl %6, %%esi\n"
|
439 | bf3e8bf1 | bellard | " fs movl %7, %%edi\n"
|
440 | bf3e8bf1 | bellard | " fs jmp *%9\n"
|
441 | bf3e8bf1 | bellard | "exec_loop:\n"
|
442 | bf3e8bf1 | bellard | " fs movl %%esp, %4\n"
|
443 | bf3e8bf1 | bellard | " fs movl %12, %%esp\n"
|
444 | bf3e8bf1 | bellard | " fs movl %%eax, %0\n"
|
445 | bf3e8bf1 | bellard | " fs movl %%ecx, %1\n"
|
446 | bf3e8bf1 | bellard | " fs movl %%edx, %2\n"
|
447 | bf3e8bf1 | bellard | " fs movl %%ebx, %3\n"
|
448 | bf3e8bf1 | bellard | " fs movl %%ebp, %5\n"
|
449 | bf3e8bf1 | bellard | " fs movl %%esi, %6\n"
|
450 | bf3e8bf1 | bellard | " fs movl %%edi, %7\n"
|
451 | bf3e8bf1 | bellard | " pushf\n"
|
452 | bf3e8bf1 | bellard | " popl %%eax\n"
|
453 | bf3e8bf1 | bellard | " movl %%eax, %%ecx\n"
|
454 | bf3e8bf1 | bellard | " andl $0x400, %%ecx\n"
|
455 | bf3e8bf1 | bellard | " shrl $9, %%ecx\n"
|
456 | bf3e8bf1 | bellard | " andl $0x8d5, %%eax\n"
|
457 | bf3e8bf1 | bellard | " fs movl %%eax, %8\n"
|
458 | bf3e8bf1 | bellard | " movl $1, %%eax\n"
|
459 | bf3e8bf1 | bellard | " subl %%ecx, %%eax\n"
|
460 | bf3e8bf1 | bellard | " fs movl %%eax, %11\n"
|
461 | bf3e8bf1 | bellard | " fs movl %9, %%ebx\n" /* get T0 value */ |
462 | bf3e8bf1 | bellard | " popl %%ebp\n"
|
463 | bf3e8bf1 | bellard | : |
464 | bf3e8bf1 | bellard | : "m" (*(uint8_t *)offsetof(CPUState, regs[0])), |
465 | bf3e8bf1 | bellard | "m" (*(uint8_t *)offsetof(CPUState, regs[1])), |
466 | bf3e8bf1 | bellard | "m" (*(uint8_t *)offsetof(CPUState, regs[2])), |
467 | bf3e8bf1 | bellard | "m" (*(uint8_t *)offsetof(CPUState, regs[3])), |
468 | bf3e8bf1 | bellard | "m" (*(uint8_t *)offsetof(CPUState, regs[4])), |
469 | bf3e8bf1 | bellard | "m" (*(uint8_t *)offsetof(CPUState, regs[5])), |
470 | bf3e8bf1 | bellard | "m" (*(uint8_t *)offsetof(CPUState, regs[6])), |
471 | bf3e8bf1 | bellard | "m" (*(uint8_t *)offsetof(CPUState, regs[7])), |
472 | bf3e8bf1 | bellard | "m" (*(uint8_t *)offsetof(CPUState, cc_src)),
|
473 | bf3e8bf1 | bellard | "m" (*(uint8_t *)offsetof(CPUState, tmp0)),
|
474 | bf3e8bf1 | bellard | "a" (gen_func),
|
475 | bf3e8bf1 | bellard | "m" (*(uint8_t *)offsetof(CPUState, df)),
|
476 | bf3e8bf1 | bellard | "m" (*(uint8_t *)offsetof(CPUState, saved_esp))
|
477 | bf3e8bf1 | bellard | : "%ecx", "%edx" |
478 | bf3e8bf1 | bellard | ); |
479 | bf3e8bf1 | bellard | } |
480 | bf3e8bf1 | bellard | } |
481 | ae228531 | bellard | #else
|
482 | 3fb2ded1 | bellard | gen_func(); |
483 | ae228531 | bellard | #endif
|
484 | 83479e77 | bellard | env->current_tb = NULL;
|
485 | 4cbf74b6 | bellard | /* reset soft MMU for next block (it can currently
|
486 | 4cbf74b6 | bellard | only be set by a memory fault) */
|
487 | 4cbf74b6 | bellard | #if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU)
|
488 | 3f337316 | bellard | if (env->hflags & HF_SOFTMMU_MASK) {
|
489 | 3f337316 | bellard | env->hflags &= ~HF_SOFTMMU_MASK; |
490 | 4cbf74b6 | bellard | /* do not allow linking to another block */
|
491 | 4cbf74b6 | bellard | T0 = 0;
|
492 | 4cbf74b6 | bellard | } |
493 | 4cbf74b6 | bellard | #endif
|
494 | 3fb2ded1 | bellard | } |
495 | 3fb2ded1 | bellard | } else {
|
496 | 7d13299d | bellard | } |
497 | 3fb2ded1 | bellard | } /* for(;;) */
|
498 | 3fb2ded1 | bellard | |
499 | 7d13299d | bellard | |
500 | e4533c7a | bellard | #if defined(TARGET_I386)
|
501 | 97eb5b14 | bellard | #if defined(USE_CODE_COPY)
|
502 | 97eb5b14 | bellard | if (env->native_fp_regs) {
|
503 | 97eb5b14 | bellard | save_native_fp_state(env); |
504 | 97eb5b14 | bellard | } |
505 | 97eb5b14 | bellard | #endif
|
506 | 9de5e440 | bellard | /* restore flags in standard format */
|
507 | fc2b4c48 | bellard | env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK); |
508 | 9de5e440 | bellard | |
509 | 7d13299d | bellard | /* restore global registers */
|
510 | 04369ff2 | bellard | #ifdef reg_EAX
|
511 | 04369ff2 | bellard | EAX = saved_EAX; |
512 | 04369ff2 | bellard | #endif
|
513 | 04369ff2 | bellard | #ifdef reg_ECX
|
514 | 04369ff2 | bellard | ECX = saved_ECX; |
515 | 04369ff2 | bellard | #endif
|
516 | 04369ff2 | bellard | #ifdef reg_EDX
|
517 | 04369ff2 | bellard | EDX = saved_EDX; |
518 | 04369ff2 | bellard | #endif
|
519 | 04369ff2 | bellard | #ifdef reg_EBX
|
520 | 04369ff2 | bellard | EBX = saved_EBX; |
521 | 04369ff2 | bellard | #endif
|
522 | 04369ff2 | bellard | #ifdef reg_ESP
|
523 | 04369ff2 | bellard | ESP = saved_ESP; |
524 | 04369ff2 | bellard | #endif
|
525 | 04369ff2 | bellard | #ifdef reg_EBP
|
526 | 04369ff2 | bellard | EBP = saved_EBP; |
527 | 04369ff2 | bellard | #endif
|
528 | 04369ff2 | bellard | #ifdef reg_ESI
|
529 | 04369ff2 | bellard | ESI = saved_ESI; |
530 | 04369ff2 | bellard | #endif
|
531 | 04369ff2 | bellard | #ifdef reg_EDI
|
532 | 04369ff2 | bellard | EDI = saved_EDI; |
533 | 04369ff2 | bellard | #endif
|
534 | e4533c7a | bellard | #elif defined(TARGET_ARM)
|
535 | 1b21b62a | bellard | env->cpsr = compute_cpsr(); |
536 | 93ac68bc | bellard | #elif defined(TARGET_SPARC)
|
537 | 67867308 | bellard | #elif defined(TARGET_PPC)
|
538 | e4533c7a | bellard | #else
|
539 | e4533c7a | bellard | #error unsupported target CPU
|
540 | e4533c7a | bellard | #endif
|
541 | 8c6939c0 | bellard | #ifdef __sparc__
|
542 | 8c6939c0 | bellard | asm volatile ("mov %0, %%i7" : : "r" (saved_i7)); |
543 | 8c6939c0 | bellard | #endif
|
544 | 7d13299d | bellard | T0 = saved_T0; |
545 | 7d13299d | bellard | T1 = saved_T1; |
546 | e4533c7a | bellard | T2 = saved_T2; |
547 | 7d13299d | bellard | env = saved_env; |
548 | 7d13299d | bellard | return ret;
|
549 | 7d13299d | bellard | } |
550 | 6dbad63e | bellard | |
551 | 1a18c71b | bellard | #if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
|
552 | e4533c7a | bellard | |
553 | 6dbad63e | bellard | void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector) |
554 | 6dbad63e | bellard | { |
555 | 6dbad63e | bellard | CPUX86State *saved_env; |
556 | 6dbad63e | bellard | |
557 | 6dbad63e | bellard | saved_env = env; |
558 | 6dbad63e | bellard | env = s; |
559 | a412ac57 | bellard | if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) { |
560 | a513fe19 | bellard | selector &= 0xffff;
|
561 | 2e255c6b | bellard | cpu_x86_load_seg_cache(env, seg_reg, selector, |
562 | 2e255c6b | bellard | (uint8_t *)(selector << 4), 0xffff, 0); |
563 | a513fe19 | bellard | } else {
|
564 | b453b70b | bellard | load_seg(seg_reg, selector); |
565 | a513fe19 | bellard | } |
566 | 6dbad63e | bellard | env = saved_env; |
567 | 6dbad63e | bellard | } |
568 | 9de5e440 | bellard | |
569 | d0a1ffc9 | bellard | void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32) |
570 | d0a1ffc9 | bellard | { |
571 | d0a1ffc9 | bellard | CPUX86State *saved_env; |
572 | d0a1ffc9 | bellard | |
573 | d0a1ffc9 | bellard | saved_env = env; |
574 | d0a1ffc9 | bellard | env = s; |
575 | d0a1ffc9 | bellard | |
576 | d0a1ffc9 | bellard | helper_fsave(ptr, data32); |
577 | d0a1ffc9 | bellard | |
578 | d0a1ffc9 | bellard | env = saved_env; |
579 | d0a1ffc9 | bellard | } |
580 | d0a1ffc9 | bellard | |
581 | d0a1ffc9 | bellard | void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32) |
582 | d0a1ffc9 | bellard | { |
583 | d0a1ffc9 | bellard | CPUX86State *saved_env; |
584 | d0a1ffc9 | bellard | |
585 | d0a1ffc9 | bellard | saved_env = env; |
586 | d0a1ffc9 | bellard | env = s; |
587 | d0a1ffc9 | bellard | |
588 | d0a1ffc9 | bellard | helper_frstor(ptr, data32); |
589 | d0a1ffc9 | bellard | |
590 | d0a1ffc9 | bellard | env = saved_env; |
591 | d0a1ffc9 | bellard | } |
592 | d0a1ffc9 | bellard | |
593 | e4533c7a | bellard | #endif /* TARGET_I386 */ |
594 | e4533c7a | bellard | |
595 | 9de5e440 | bellard | #undef EAX
|
596 | 9de5e440 | bellard | #undef ECX
|
597 | 9de5e440 | bellard | #undef EDX
|
598 | 9de5e440 | bellard | #undef EBX
|
599 | 9de5e440 | bellard | #undef ESP
|
600 | 9de5e440 | bellard | #undef EBP
|
601 | 9de5e440 | bellard | #undef ESI
|
602 | 9de5e440 | bellard | #undef EDI
|
603 | 9de5e440 | bellard | #undef EIP
|
604 | 9de5e440 | bellard | #include <signal.h> |
605 | 9de5e440 | bellard | #include <sys/ucontext.h> |
606 | 9de5e440 | bellard | |
607 | 3fb2ded1 | bellard | #if defined(TARGET_I386)
|
608 | 3fb2ded1 | bellard | |
609 | b56dad1c | bellard | /* 'pc' is the host PC at which the exception was raised. 'address' is
|
610 | fd6ce8f6 | bellard | the effective address of the memory exception. 'is_write' is 1 if a
|
611 | fd6ce8f6 | bellard | write caused the exception and otherwise 0'. 'old_set' is the
|
612 | fd6ce8f6 | bellard | signal set which should be restored */
|
613 | 2b413144 | bellard | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
614 | bf3e8bf1 | bellard | int is_write, sigset_t *old_set,
|
615 | bf3e8bf1 | bellard | void *puc)
|
616 | 9de5e440 | bellard | { |
617 | a513fe19 | bellard | TranslationBlock *tb; |
618 | a513fe19 | bellard | int ret;
|
619 | 68a79315 | bellard | |
620 | 83479e77 | bellard | if (cpu_single_env)
|
621 | 83479e77 | bellard | env = cpu_single_env; /* XXX: find a correct solution for multithread */
|
622 | fd6ce8f6 | bellard | #if defined(DEBUG_SIGNAL)
|
623 | bf3e8bf1 | bellard | qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
|
624 | bf3e8bf1 | bellard | pc, address, is_write, *(unsigned long *)old_set); |
625 | 9de5e440 | bellard | #endif
|
626 | 25eb4484 | bellard | /* XXX: locking issue */
|
627 | fd6ce8f6 | bellard | if (is_write && page_unprotect(address)) {
|
628 | fd6ce8f6 | bellard | return 1; |
629 | fd6ce8f6 | bellard | } |
630 | 3fb2ded1 | bellard | /* see if it is an MMU fault */
|
631 | 93a40ea9 | bellard | ret = cpu_x86_handle_mmu_fault(env, address, is_write, |
632 | 93a40ea9 | bellard | ((env->hflags & HF_CPL_MASK) == 3), 0); |
633 | 3fb2ded1 | bellard | if (ret < 0) |
634 | 3fb2ded1 | bellard | return 0; /* not an MMU fault */ |
635 | 3fb2ded1 | bellard | if (ret == 0) |
636 | 3fb2ded1 | bellard | return 1; /* the MMU fault was handled without causing real CPU fault */ |
637 | 3fb2ded1 | bellard | /* now we have a real cpu fault */
|
638 | a513fe19 | bellard | tb = tb_find_pc(pc); |
639 | a513fe19 | bellard | if (tb) {
|
640 | 9de5e440 | bellard | /* the PC is inside the translated code. It means that we have
|
641 | 9de5e440 | bellard | a virtual CPU fault */
|
642 | bf3e8bf1 | bellard | cpu_restore_state(tb, env, pc, puc); |
643 | 3fb2ded1 | bellard | } |
644 | 4cbf74b6 | bellard | if (ret == 1) { |
645 | 3fb2ded1 | bellard | #if 0
|
646 | 4cbf74b6 | bellard | printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
|
647 | 4cbf74b6 | bellard | env->eip, env->cr[2], env->error_code);
|
648 | 3fb2ded1 | bellard | #endif
|
649 | 4cbf74b6 | bellard | /* we restore the process signal mask as the sigreturn should
|
650 | 4cbf74b6 | bellard | do it (XXX: use sigsetjmp) */
|
651 | 4cbf74b6 | bellard | sigprocmask(SIG_SETMASK, old_set, NULL);
|
652 | 4cbf74b6 | bellard | raise_exception_err(EXCP0E_PAGE, env->error_code); |
653 | 4cbf74b6 | bellard | } else {
|
654 | 4cbf74b6 | bellard | /* activate soft MMU for this block */
|
655 | 3f337316 | bellard | env->hflags |= HF_SOFTMMU_MASK; |
656 | 4cbf74b6 | bellard | sigprocmask(SIG_SETMASK, old_set, NULL);
|
657 | 4cbf74b6 | bellard | cpu_loop_exit(); |
658 | 4cbf74b6 | bellard | } |
659 | 3fb2ded1 | bellard | /* never comes here */
|
660 | 3fb2ded1 | bellard | return 1; |
661 | 3fb2ded1 | bellard | } |
662 | 3fb2ded1 | bellard | |
663 | e4533c7a | bellard | #elif defined(TARGET_ARM)
|
664 | 3fb2ded1 | bellard | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
665 | bf3e8bf1 | bellard | int is_write, sigset_t *old_set,
|
666 | bf3e8bf1 | bellard | void *puc)
|
667 | 3fb2ded1 | bellard | { |
668 | 3fb2ded1 | bellard | /* XXX: do more */
|
669 | 3fb2ded1 | bellard | return 0; |
670 | 3fb2ded1 | bellard | } |
671 | 93ac68bc | bellard | #elif defined(TARGET_SPARC)
|
672 | 93ac68bc | bellard | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
673 | bf3e8bf1 | bellard | int is_write, sigset_t *old_set,
|
674 | bf3e8bf1 | bellard | void *puc)
|
675 | 93ac68bc | bellard | { |
676 | b453b70b | bellard | /* XXX: locking issue */
|
677 | b453b70b | bellard | if (is_write && page_unprotect(address)) {
|
678 | b453b70b | bellard | return 1; |
679 | b453b70b | bellard | } |
680 | b453b70b | bellard | return 0; |
681 | 93ac68bc | bellard | } |
682 | 67867308 | bellard | #elif defined (TARGET_PPC)
|
683 | 67867308 | bellard | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
684 | bf3e8bf1 | bellard | int is_write, sigset_t *old_set,
|
685 | bf3e8bf1 | bellard | void *puc)
|
686 | 67867308 | bellard | { |
687 | 67867308 | bellard | TranslationBlock *tb; |
688 | ce09776b | bellard | int ret;
|
689 | 67867308 | bellard | |
690 | ce09776b | bellard | #if 1 |
691 | 67867308 | bellard | if (cpu_single_env)
|
692 | 67867308 | bellard | env = cpu_single_env; /* XXX: find a correct solution for multithread */
|
693 | 67867308 | bellard | #endif
|
694 | 67867308 | bellard | #if defined(DEBUG_SIGNAL)
|
695 | 67867308 | bellard | printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
|
696 | 67867308 | bellard | pc, address, is_write, *(unsigned long *)old_set); |
697 | 67867308 | bellard | #endif
|
698 | 67867308 | bellard | /* XXX: locking issue */
|
699 | 67867308 | bellard | if (is_write && page_unprotect(address)) {
|
700 | 67867308 | bellard | return 1; |
701 | 67867308 | bellard | } |
702 | 67867308 | bellard | |
703 | ce09776b | bellard | /* see if it is an MMU fault */
|
704 | 7f957d28 | bellard | ret = cpu_ppc_handle_mmu_fault(env, address, is_write, msr_pr, 0);
|
705 | ce09776b | bellard | if (ret < 0) |
706 | ce09776b | bellard | return 0; /* not an MMU fault */ |
707 | ce09776b | bellard | if (ret == 0) |
708 | ce09776b | bellard | return 1; /* the MMU fault was handled without causing real CPU fault */ |
709 | ce09776b | bellard | |
710 | 67867308 | bellard | /* now we have a real cpu fault */
|
711 | 67867308 | bellard | tb = tb_find_pc(pc); |
712 | 67867308 | bellard | if (tb) {
|
713 | 67867308 | bellard | /* the PC is inside the translated code. It means that we have
|
714 | 67867308 | bellard | a virtual CPU fault */
|
715 | bf3e8bf1 | bellard | cpu_restore_state(tb, env, pc, puc); |
716 | 67867308 | bellard | } |
717 | ce09776b | bellard | if (ret == 1) { |
718 | 67867308 | bellard | #if 0
|
719 | ce09776b | bellard | printf("PF exception: NIP=0x%08x error=0x%x %p\n",
|
720 | ce09776b | bellard | env->nip, env->error_code, tb);
|
721 | 67867308 | bellard | #endif
|
722 | 67867308 | bellard | /* we restore the process signal mask as the sigreturn should
|
723 | 67867308 | bellard | do it (XXX: use sigsetjmp) */
|
724 | bf3e8bf1 | bellard | sigprocmask(SIG_SETMASK, old_set, NULL);
|
725 | ce09776b | bellard | do_queue_exception_err(env->exception_index, env->error_code); |
726 | ce09776b | bellard | } else {
|
727 | ce09776b | bellard | /* activate soft MMU for this block */
|
728 | ce09776b | bellard | sigprocmask(SIG_SETMASK, old_set, NULL);
|
729 | ce09776b | bellard | cpu_loop_exit(); |
730 | ce09776b | bellard | } |
731 | 67867308 | bellard | /* never comes here */
|
732 | 67867308 | bellard | return 1; |
733 | 67867308 | bellard | } |
734 | e4533c7a | bellard | #else
|
735 | e4533c7a | bellard | #error unsupported target CPU
|
736 | e4533c7a | bellard | #endif
|
737 | 9de5e440 | bellard | |
738 | 2b413144 | bellard | #if defined(__i386__)
|
739 | 2b413144 | bellard | |
740 | bf3e8bf1 | bellard | #if defined(USE_CODE_COPY)
|
741 | bf3e8bf1 | bellard | static void cpu_send_trap(unsigned long pc, int trap, |
742 | bf3e8bf1 | bellard | struct ucontext *uc)
|
743 | bf3e8bf1 | bellard | { |
744 | bf3e8bf1 | bellard | TranslationBlock *tb; |
745 | bf3e8bf1 | bellard | |
746 | bf3e8bf1 | bellard | if (cpu_single_env)
|
747 | bf3e8bf1 | bellard | env = cpu_single_env; /* XXX: find a correct solution for multithread */
|
748 | bf3e8bf1 | bellard | /* now we have a real cpu fault */
|
749 | bf3e8bf1 | bellard | tb = tb_find_pc(pc); |
750 | bf3e8bf1 | bellard | if (tb) {
|
751 | bf3e8bf1 | bellard | /* the PC is inside the translated code. It means that we have
|
752 | bf3e8bf1 | bellard | a virtual CPU fault */
|
753 | bf3e8bf1 | bellard | cpu_restore_state(tb, env, pc, uc); |
754 | bf3e8bf1 | bellard | } |
755 | bf3e8bf1 | bellard | sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
|
756 | bf3e8bf1 | bellard | raise_exception_err(trap, env->error_code); |
757 | bf3e8bf1 | bellard | } |
758 | bf3e8bf1 | bellard | #endif
|
759 | bf3e8bf1 | bellard | |
760 | e4533c7a | bellard | int cpu_signal_handler(int host_signum, struct siginfo *info, |
761 | e4533c7a | bellard | void *puc)
|
762 | 9de5e440 | bellard | { |
763 | 9de5e440 | bellard | struct ucontext *uc = puc;
|
764 | 9de5e440 | bellard | unsigned long pc; |
765 | bf3e8bf1 | bellard | int trapno;
|
766 | 97eb5b14 | bellard | |
767 | d691f669 | bellard | #ifndef REG_EIP
|
768 | d691f669 | bellard | /* for glibc 2.1 */
|
769 | fd6ce8f6 | bellard | #define REG_EIP EIP
|
770 | fd6ce8f6 | bellard | #define REG_ERR ERR
|
771 | fd6ce8f6 | bellard | #define REG_TRAPNO TRAPNO
|
772 | d691f669 | bellard | #endif
|
773 | fc2b4c48 | bellard | pc = uc->uc_mcontext.gregs[REG_EIP]; |
774 | bf3e8bf1 | bellard | trapno = uc->uc_mcontext.gregs[REG_TRAPNO]; |
775 | bf3e8bf1 | bellard | #if defined(TARGET_I386) && defined(USE_CODE_COPY)
|
776 | bf3e8bf1 | bellard | if (trapno == 0x00 || trapno == 0x05) { |
777 | bf3e8bf1 | bellard | /* send division by zero or bound exception */
|
778 | bf3e8bf1 | bellard | cpu_send_trap(pc, trapno, uc); |
779 | bf3e8bf1 | bellard | return 1; |
780 | bf3e8bf1 | bellard | } else
|
781 | bf3e8bf1 | bellard | #endif
|
782 | bf3e8bf1 | bellard | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
783 | bf3e8bf1 | bellard | trapno == 0xe ?
|
784 | bf3e8bf1 | bellard | (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0, |
785 | bf3e8bf1 | bellard | &uc->uc_sigmask, puc); |
786 | 2b413144 | bellard | } |
787 | 2b413144 | bellard | |
788 | 25eb4484 | bellard | #elif defined(__powerpc)
|
789 | 2b413144 | bellard | |
790 | e4533c7a | bellard | int cpu_signal_handler(int host_signum, struct siginfo *info, |
791 | e4533c7a | bellard | void *puc)
|
792 | 2b413144 | bellard | { |
793 | 25eb4484 | bellard | struct ucontext *uc = puc;
|
794 | 25eb4484 | bellard | struct pt_regs *regs = uc->uc_mcontext.regs;
|
795 | 25eb4484 | bellard | unsigned long pc; |
796 | 25eb4484 | bellard | int is_write;
|
797 | 25eb4484 | bellard | |
798 | 25eb4484 | bellard | pc = regs->nip; |
799 | 25eb4484 | bellard | is_write = 0;
|
800 | 25eb4484 | bellard | #if 0
|
801 | 25eb4484 | bellard | /* ppc 4xx case */
|
802 | 25eb4484 | bellard | if (regs->dsisr & 0x00800000)
|
803 | 25eb4484 | bellard | is_write = 1;
|
804 | 25eb4484 | bellard | #else
|
805 | 25eb4484 | bellard | if (regs->trap != 0x400 && (regs->dsisr & 0x02000000)) |
806 | 25eb4484 | bellard | is_write = 1;
|
807 | 25eb4484 | bellard | #endif
|
808 | 25eb4484 | bellard | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
809 | bf3e8bf1 | bellard | is_write, &uc->uc_sigmask, puc); |
810 | 2b413144 | bellard | } |
811 | 2b413144 | bellard | |
812 | 2f87c607 | bellard | #elif defined(__alpha__)
|
813 | 2f87c607 | bellard | |
814 | e4533c7a | bellard | int cpu_signal_handler(int host_signum, struct siginfo *info, |
815 | 2f87c607 | bellard | void *puc)
|
816 | 2f87c607 | bellard | { |
817 | 2f87c607 | bellard | struct ucontext *uc = puc;
|
818 | 2f87c607 | bellard | uint32_t *pc = uc->uc_mcontext.sc_pc; |
819 | 2f87c607 | bellard | uint32_t insn = *pc; |
820 | 2f87c607 | bellard | int is_write = 0; |
821 | 2f87c607 | bellard | |
822 | 8c6939c0 | bellard | /* XXX: need kernel patch to get write flag faster */
|
823 | 2f87c607 | bellard | switch (insn >> 26) { |
824 | 2f87c607 | bellard | case 0x0d: // stw |
825 | 2f87c607 | bellard | case 0x0e: // stb |
826 | 2f87c607 | bellard | case 0x0f: // stq_u |
827 | 2f87c607 | bellard | case 0x24: // stf |
828 | 2f87c607 | bellard | case 0x25: // stg |
829 | 2f87c607 | bellard | case 0x26: // sts |
830 | 2f87c607 | bellard | case 0x27: // stt |
831 | 2f87c607 | bellard | case 0x2c: // stl |
832 | 2f87c607 | bellard | case 0x2d: // stq |
833 | 2f87c607 | bellard | case 0x2e: // stl_c |
834 | 2f87c607 | bellard | case 0x2f: // stq_c |
835 | 2f87c607 | bellard | is_write = 1;
|
836 | 2f87c607 | bellard | } |
837 | 2f87c607 | bellard | |
838 | 2f87c607 | bellard | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
839 | bf3e8bf1 | bellard | is_write, &uc->uc_sigmask, puc); |
840 | 2f87c607 | bellard | } |
841 | 8c6939c0 | bellard | #elif defined(__sparc__)
|
842 | 8c6939c0 | bellard | |
843 | e4533c7a | bellard | int cpu_signal_handler(int host_signum, struct siginfo *info, |
844 | e4533c7a | bellard | void *puc)
|
845 | 8c6939c0 | bellard | { |
846 | 8c6939c0 | bellard | uint32_t *regs = (uint32_t *)(info + 1);
|
847 | 8c6939c0 | bellard | void *sigmask = (regs + 20); |
848 | 8c6939c0 | bellard | unsigned long pc; |
849 | 8c6939c0 | bellard | int is_write;
|
850 | 8c6939c0 | bellard | uint32_t insn; |
851 | 8c6939c0 | bellard | |
852 | 8c6939c0 | bellard | /* XXX: is there a standard glibc define ? */
|
853 | 8c6939c0 | bellard | pc = regs[1];
|
854 | 8c6939c0 | bellard | /* XXX: need kernel patch to get write flag faster */
|
855 | 8c6939c0 | bellard | is_write = 0;
|
856 | 8c6939c0 | bellard | insn = *(uint32_t *)pc; |
857 | 8c6939c0 | bellard | if ((insn >> 30) == 3) { |
858 | 8c6939c0 | bellard | switch((insn >> 19) & 0x3f) { |
859 | 8c6939c0 | bellard | case 0x05: // stb |
860 | 8c6939c0 | bellard | case 0x06: // sth |
861 | 8c6939c0 | bellard | case 0x04: // st |
862 | 8c6939c0 | bellard | case 0x07: // std |
863 | 8c6939c0 | bellard | case 0x24: // stf |
864 | 8c6939c0 | bellard | case 0x27: // stdf |
865 | 8c6939c0 | bellard | case 0x25: // stfsr |
866 | 8c6939c0 | bellard | is_write = 1;
|
867 | 8c6939c0 | bellard | break;
|
868 | 8c6939c0 | bellard | } |
869 | 8c6939c0 | bellard | } |
870 | 8c6939c0 | bellard | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
871 | bf3e8bf1 | bellard | is_write, sigmask, NULL);
|
872 | 8c6939c0 | bellard | } |
873 | 8c6939c0 | bellard | |
874 | 8c6939c0 | bellard | #elif defined(__arm__)
|
875 | 8c6939c0 | bellard | |
876 | e4533c7a | bellard | int cpu_signal_handler(int host_signum, struct siginfo *info, |
877 | e4533c7a | bellard | void *puc)
|
878 | 8c6939c0 | bellard | { |
879 | 8c6939c0 | bellard | struct ucontext *uc = puc;
|
880 | 8c6939c0 | bellard | unsigned long pc; |
881 | 8c6939c0 | bellard | int is_write;
|
882 | 8c6939c0 | bellard | |
883 | 8c6939c0 | bellard | pc = uc->uc_mcontext.gregs[R15]; |
884 | 8c6939c0 | bellard | /* XXX: compute is_write */
|
885 | 8c6939c0 | bellard | is_write = 0;
|
886 | 8c6939c0 | bellard | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
887 | 8c6939c0 | bellard | is_write, |
888 | 8c6939c0 | bellard | &uc->uc_sigmask); |
889 | 8c6939c0 | bellard | } |
890 | 8c6939c0 | bellard | |
891 | 38e584a0 | bellard | #elif defined(__mc68000)
|
892 | 38e584a0 | bellard | |
893 | 38e584a0 | bellard | int cpu_signal_handler(int host_signum, struct siginfo *info, |
894 | 38e584a0 | bellard | void *puc)
|
895 | 38e584a0 | bellard | { |
896 | 38e584a0 | bellard | struct ucontext *uc = puc;
|
897 | 38e584a0 | bellard | unsigned long pc; |
898 | 38e584a0 | bellard | int is_write;
|
899 | 38e584a0 | bellard | |
900 | 38e584a0 | bellard | pc = uc->uc_mcontext.gregs[16];
|
901 | 38e584a0 | bellard | /* XXX: compute is_write */
|
902 | 38e584a0 | bellard | is_write = 0;
|
903 | 38e584a0 | bellard | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
904 | 38e584a0 | bellard | is_write, |
905 | bf3e8bf1 | bellard | &uc->uc_sigmask, puc); |
906 | 38e584a0 | bellard | } |
907 | 38e584a0 | bellard | |
908 | 9de5e440 | bellard | #else
|
909 | 2b413144 | bellard | |
910 | 3fb2ded1 | bellard | #error host CPU specific signal handler needed
|
911 | 2b413144 | bellard | |
912 | 9de5e440 | bellard | #endif |