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/*
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 *  PPC emulation helpers for qemu.
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 * 
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 *  Copyright (c) 2003 Jocelyn Mayer
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 *
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 * This library is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU Lesser General Public
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 * License as published by the Free Software Foundation; either
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 * version 2 of the License, or (at your option) any later version.
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 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, write to the Free Software
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 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
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 */
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#include <sys/mman.h>
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#include "exec.h"
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#if defined (USE_OPEN_FIRMWARE)
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#include "of.h"
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#endif
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//#define DEBUG_MMU
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//#define DEBUG_BATS
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//#define DEBUG_EXCEPTIONS
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extern FILE *logfile, *stderr;
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void exit (int);
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void abort (void);
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void cpu_loop_exit(void)
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{
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    longjmp(env->jmp_env, 1);
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}
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void do_process_exceptions (void)
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{
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    cpu_loop_exit();
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}
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int check_exception_state (CPUState *env)
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{
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    int i;
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    /* Process PPC exceptions */
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    for (i = 1; i  < EXCP_PPC_MAX; i++) {
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        if (env->exceptions & (1 << i)) {
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            switch (i) {
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            case EXCP_EXTERNAL:
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            case EXCP_DECR:
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                if (msr_ee == 0)
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                    return 0;
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                break;
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            case EXCP_PROGRAM:
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                if (env->errors[EXCP_PROGRAM] == EXCP_FP &&
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                    msr_fe0 == 0 && msr_fe1 == 0)
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                    return 0;
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                break;
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            default:
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                break;
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            }
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            env->exception_index = i;
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            env->error_code = env->errors[i];
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            return 1;
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        }
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    }
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    return 0;
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}
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/*****************************************************************************/
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/* PPC MMU emulation */
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/* Perform BAT hit & translation */
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static int get_bat (CPUState *env, uint32_t *real, int *prot,
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                    uint32_t virtual, int rw, int type)
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{
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    uint32_t *BATlt, *BATut, *BATu, *BATl;
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    uint32_t base, BEPIl, BEPIu, bl;
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    int i;
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    int ret = -1;
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#if defined (DEBUG_BATS)
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    if (loglevel > 0) {
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        fprintf(logfile, "%s: %cBAT v 0x%08x\n", __func__,
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               type == ACCESS_CODE ? 'I' : 'D', virtual);
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    }
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    printf("%s: %cBAT v 0x%08x\n", __func__,
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           type == ACCESS_CODE ? 'I' : 'D', virtual);
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#endif
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    switch (type) {
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    case ACCESS_CODE:
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        BATlt = env->IBAT[1];
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        BATut = env->IBAT[0];
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        break;
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    default:
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        BATlt = env->DBAT[1];
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        BATut = env->DBAT[0];
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        break;
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    }
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#if defined (DEBUG_BATS)
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    if (loglevel > 0) {
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        fprintf(logfile, "%s...: %cBAT v 0x%08x\n", __func__,
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               type == ACCESS_CODE ? 'I' : 'D', virtual);
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    }
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    printf("%s...: %cBAT v 0x%08x\n", __func__,
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           type == ACCESS_CODE ? 'I' : 'D', virtual);
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#endif
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    base = virtual & 0xFFFC0000;
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    for (i = 0; i < 4; i++) {
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        BATu = &BATut[i];
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        BATl = &BATlt[i];
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        BEPIu = *BATu & 0xF0000000;
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        BEPIl = *BATu & 0x0FFE0000;
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        bl = (*BATu & 0x00001FFC) << 15;
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#if defined (DEBUG_BATS)
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        if (loglevel > 0) {
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            fprintf(logfile, "%s: %cBAT%d v 0x%08x BATu 0x%08x BATl 0x%08x\n",
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                    __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
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                    *BATu, *BATl);
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        } else {
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            printf("%s: %cBAT%d v 0x%08x BATu 0x%08x BATl 0x%08x\n",
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                   __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
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                   *BATu, *BATl);
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        }
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#endif
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        if ((virtual & 0xF0000000) == BEPIu &&
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            ((virtual & 0x0FFE0000) & ~bl) == BEPIl) {
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            /* BAT matches */
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            if ((msr_pr == 0 && (*BATu & 0x00000002)) ||
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                (msr_pr == 1 && (*BATu & 0x00000001))) {
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                /* Get physical address */
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                *real = (*BATl & 0xF0000000) |
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                    ((virtual & 0x0FFE0000 & bl) | (*BATl & 0x0FFE0000)) |
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                    (virtual & 0x0001FFFF);
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                if (*BATl & 0x00000001)
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                    *prot = PROT_READ;
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                if (*BATl & 0x00000002)
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                    *prot = PROT_WRITE | PROT_READ;
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#if defined (DEBUG_BATS)
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                if (loglevel > 0) {
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                    fprintf(logfile, "BAT %d match: r 0x%08x prot=%c%c\n",
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                            i, *real, *prot & PROT_READ ? 'R' : '-',
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                            *prot & PROT_WRITE ? 'W' : '-');
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                } else {
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                    printf("BAT %d match: 0x%08x => 0x%08x prot=%c%c\n",
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                           i, virtual, *real, *prot & PROT_READ ? 'R' : '-',
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                           *prot & PROT_WRITE ? 'W' : '-');
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                }
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#endif
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                ret = 0;
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                break;
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            }
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        }
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    }
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    if (ret < 0) {
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#if defined (DEBUG_BATS)
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        printf("no BAT match for 0x%08x:\n", virtual);
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        for (i = 0; i < 4; i++) {
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            BATu = &BATut[i];
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            BATl = &BATlt[i];
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            BEPIu = *BATu & 0xF0000000;
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            BEPIl = *BATu & 0x0FFE0000;
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            bl = (*BATu & 0x00001FFC) << 15;
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            printf("%s: %cBAT%d v 0x%08x BATu 0x%08x BATl 0x%08x \n\t"
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                   "0x%08x 0x%08x 0x%08x\n",
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                   __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
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                   *BATu, *BATl, BEPIu, BEPIl, bl);
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        }
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#endif
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        env->spr[DAR] = virtual;
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    }
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    /* No hit */
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    return ret;
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}
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/* PTE table lookup */
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static int find_pte (uint32_t *RPN, int *prot, uint32_t base, uint32_t va,
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                     int h, int key, int rw)
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{
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    uint32_t pte0, pte1, keep = 0;
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    int i, good = -1, store = 0;
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    int ret = -1; /* No entry found */
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    for (i = 0; i < 8; i++) {
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        pte0 = ldl_raw((void *)((uint32_t)phys_ram_base + base + (i * 8)));
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        pte1 =  ldl_raw((void *)((uint32_t)phys_ram_base + base + (i * 8) + 4));
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#if defined (DEBUG_MMU)
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        printf("Load pte from 0x%08x => 0x%08x 0x%08x\n", base + (i * 8),
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               pte0, pte1);
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#endif
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        /* Check validity and table match */
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        if (pte0 & 0x80000000 && (h == ((pte0 >> 6) & 1))) {
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#if defined (DEBUG_MMU)
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            printf("PTE is valid and table matches... compare 0x%08x:%08x\n",
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                   pte0 & 0x7FFFFFBF, va);
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#endif
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            /* Check vsid & api */
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            if ((pte0 & 0x7FFFFFBF) == va) {
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#if defined (DEBUG_MMU)
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                printf("PTE match !\n");
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#endif
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                if (good == -1) {
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                    good = i;
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                    keep = pte1;
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                } else {
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                    /* All matches should have equal RPN, WIMG & PP */
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                    if ((keep & 0xFFFFF07B) != (pte1 & 0xFFFFF07B)) {
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                        printf("Bad RPN/WIMG/PP\n");
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                        return -1;
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                    }
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                }
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                /* Check access rights */
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                if (key == 0) {
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                    *prot = PROT_READ;
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                    if ((pte1 & 0x00000003) != 0x3)
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                        *prot |= PROT_WRITE;
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                } else {
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                    switch (pte1 & 0x00000003) {
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                    case 0x0:
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                        *prot = 0;
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                        break;
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                    case 0x1:
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                    case 0x3:
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                        *prot = PROT_READ;
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                        break;
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                    case 0x2:
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                        *prot = PROT_READ | PROT_WRITE;
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                        break;
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                    }
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                }
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                if ((rw == 0 && *prot != 0) ||
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                    (rw == 1 && (*prot & PROT_WRITE))) {
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#if defined (DEBUG_MMU)
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                    printf("PTE access granted !\n");
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#endif
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                    good = i;
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                    keep = pte1;
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                    ret = 0;
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                } else if (ret == -1) {
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                    ret = -2; /* Access right violation */
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#if defined (DEBUG_MMU)
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                    printf("PTE access rejected\n");
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#endif
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                }
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            }
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        }
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    }
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    if (good != -1) {
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        *RPN = keep & 0xFFFFF000;
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#if defined (DEBUG_MMU)
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        printf("found PTE at addr 0x%08x prot=0x%01x ret=%d\n",
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               *RPN, *prot, ret);
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#endif
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        /* Update page flags */
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        if (!(keep & 0x00000100)) {
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            keep |= 0x00000100;
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            store = 1;
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        }
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        if (rw) {
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            if (!(keep & 0x00000080)) {
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                keep |= 0x00000080;
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                store = 1;
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            }
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        }
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        if (store)
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            stl_raw((void *)(base + (good * 2) + 1), keep);
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    }
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    return ret;
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}
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static inline uint32_t get_pgaddr (uint32_t sdr1, uint32_t hash, uint32_t mask)
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{
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    return (sdr1 & 0xFFFF0000) | (hash & mask);
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}
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/* Perform segment based translation */
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static int get_segment (CPUState *env, uint32_t *real, int *prot,
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                        uint32_t virtual, int rw, int type)
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{
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    uint32_t pg_addr, sdr, ptem, vsid, pgidx;
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    uint32_t hash, mask;
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    uint32_t sr;
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    int key;
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    int ret = -1, ret2;
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    sr = env->sr[virtual >> 28];
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#if defined (DEBUG_MMU)
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    printf("Check segment v=0x%08x %d 0x%08x nip=0x%08x lr=0x%08x ir=%d dr=%d "
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           "pr=%d t=%d\n", virtual, virtual >> 28, sr, env->nip,
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           env->lr, msr_ir, msr_dr, msr_pr, type);
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#endif
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    key = ((sr & 0x20000000) && msr_pr == 1) ||
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        ((sr & 0x40000000) && msr_pr == 0) ? 1 : 0;
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    if ((sr & 0x80000000) == 0) {
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#if defined (DEBUG_MMU)
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        printf("pte segment: key=%d n=0x%08x\n", key, sr & 0x10000000);
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#endif
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        /* Check if instruction fetch is allowed, if needed */
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        if (type != ACCESS_CODE || (sr & 0x10000000) == 0) {
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            /* Page address translation */
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            vsid = sr & 0x00FFFFFF;
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            pgidx = (virtual >> 12) & 0xFFFF;
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            sdr = env->spr[SDR1];
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            hash = ((vsid ^ pgidx) & 0x07FFFF) << 6;
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            mask = ((sdr & 0x000001FF) << 16) | 0xFFC0;
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            pg_addr = get_pgaddr(sdr, hash, mask);
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            ptem = (vsid << 7) | (pgidx >> 10);
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#if defined (DEBUG_MMU)
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            printf("0 sdr1=0x%08x vsid=0x%06x api=0x%04x hash=0x%07x "
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                   "pg_addr=0x%08x\n", sdr, vsid, pgidx, hash, pg_addr);
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#endif
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            /* Primary table lookup */
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            ret = find_pte(real, prot, pg_addr, ptem, 0, key, rw);
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            if (ret < 0) {
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                /* Secondary table lookup */
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                hash = (~hash) & 0x01FFFFC0;
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                pg_addr = get_pgaddr(sdr, hash, mask);
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#if defined (DEBUG_MMU)
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                printf("1 sdr1=0x%08x vsid=0x%06x api=0x%04x hash=0x%05x "
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                       "pg_addr=0x%08x\n", sdr, vsid, pgidx, hash, pg_addr);
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#endif
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                ret2 = find_pte(real, prot, pg_addr, ptem, 1, key, rw);
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                if (ret2 != -1)
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                    ret = ret2;
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            }
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            if (ret != -1)
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                *real |= (virtual & 0x00000FFF);
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            if (ret == -2 && type == ACCESS_CODE && (sr & 0x10000000))
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                ret = -3;
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        } else {
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#if defined (DEBUG_MMU)
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            printf("No access allowed\n");
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#endif
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        }
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    } else {
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#if defined (DEBUG_MMU)
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        printf("direct store...\n");
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#endif
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        /* Direct-store segment : absolutely *BUGGY* for now */
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        switch (type) {
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        case ACCESS_INT:
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            /* Integer load/store : only access allowed */
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            break;
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        case ACCESS_CODE:
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            /* No code fetch is allowed in direct-store areas */
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            return -4;
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        case ACCESS_FLOAT:
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            /* Floating point load/store */
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            return -4;
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        case ACCESS_RES:
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            /* lwarx, ldarx or srwcx. */
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            return -4;
358 9a64fbe4 bellard
        case ACCESS_CACHE:
359 9a64fbe4 bellard
            /* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi */
360 9a64fbe4 bellard
            /* Should make the instruction do no-op.
361 9a64fbe4 bellard
             * As it already do no-op, it's quite easy :-)
362 9a64fbe4 bellard
             */
363 9a64fbe4 bellard
            *real = virtual;
364 9a64fbe4 bellard
            return 0;
365 9a64fbe4 bellard
        case ACCESS_EXT:
366 9a64fbe4 bellard
            /* eciwx or ecowx */
367 9a64fbe4 bellard
            return -4;
368 9a64fbe4 bellard
        default:
369 9a64fbe4 bellard
            if (logfile) {
370 9a64fbe4 bellard
                fprintf(logfile, "ERROR: instruction should not need "
371 9a64fbe4 bellard
                        "address translation\n");
372 9a64fbe4 bellard
            }
373 9a64fbe4 bellard
            printf("ERROR: instruction should not need "
374 9a64fbe4 bellard
                   "address translation\n");
375 9a64fbe4 bellard
            return -4;
376 9a64fbe4 bellard
        }
377 9a64fbe4 bellard
        if ((rw == 1 || key != 1) && (rw == 0 || key != 0)) {
378 9a64fbe4 bellard
            *real = virtual;
379 9a64fbe4 bellard
            ret = 2;
380 9a64fbe4 bellard
        } else {
381 9a64fbe4 bellard
            ret = -2;
382 9a64fbe4 bellard
        }
383 79aceca5 bellard
    }
384 9a64fbe4 bellard
385 9a64fbe4 bellard
    return ret;
386 79aceca5 bellard
}
387 79aceca5 bellard
388 9a64fbe4 bellard
int get_physical_address (CPUState *env, uint32_t *physical, int *prot,
389 9a64fbe4 bellard
                          uint32_t address, int rw, int access_type)
390 9a64fbe4 bellard
{
391 9a64fbe4 bellard
    int ret;
392 9a64fbe4 bellard
393 9a64fbe4 bellard
    if (loglevel > 0) {
394 9a64fbe4 bellard
        fprintf(logfile, "%s\n", __func__);
395 9a64fbe4 bellard
    }
396 9a64fbe4 bellard
    if ((access_type == ACCESS_CODE && msr_ir == 0) || msr_dr == 0) {
397 9a64fbe4 bellard
        /* No address translation */
398 9a64fbe4 bellard
        *physical = address;
399 9a64fbe4 bellard
        *prot = PROT_READ | PROT_WRITE;
400 9a64fbe4 bellard
        ret = 0;
401 9a64fbe4 bellard
    } else {
402 9a64fbe4 bellard
        /* Try to find a BAT */
403 9a64fbe4 bellard
        ret = get_bat(env, physical, prot, address, rw, access_type);
404 9a64fbe4 bellard
        if (ret < 0) {
405 9a64fbe4 bellard
            /* We didn't match any BAT entry */
406 9a64fbe4 bellard
            ret = get_segment(env, physical, prot, address, rw, access_type);
407 9a64fbe4 bellard
        }
408 9a64fbe4 bellard
    }
409 9a64fbe4 bellard
    
410 9a64fbe4 bellard
    return ret;
411 9a64fbe4 bellard
}
412 9a64fbe4 bellard
413 a6b025d3 bellard
#if defined(CONFIG_USER_ONLY) 
414 a6b025d3 bellard
target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
415 a6b025d3 bellard
{
416 a6b025d3 bellard
    return addr;
417 a6b025d3 bellard
}
418 a6b025d3 bellard
#else
419 a6b025d3 bellard
target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
420 a6b025d3 bellard
{
421 a6b025d3 bellard
    uint32_t phys_addr;
422 a6b025d3 bellard
    int prot;
423 a6b025d3 bellard
424 a6b025d3 bellard
    if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0)
425 a6b025d3 bellard
        return -1;
426 a6b025d3 bellard
    return phys_addr;
427 a6b025d3 bellard
}
428 a6b025d3 bellard
#endif
429 9a64fbe4 bellard
430 9a64fbe4 bellard
#if !defined(CONFIG_USER_ONLY) 
431 9a64fbe4 bellard
432 9a64fbe4 bellard
#define MMUSUFFIX _mmu
433 9a64fbe4 bellard
#define GETPC() (__builtin_return_address(0))
434 9a64fbe4 bellard
435 9a64fbe4 bellard
#define SHIFT 0
436 9a64fbe4 bellard
#include "softmmu_template.h"
437 9a64fbe4 bellard
438 9a64fbe4 bellard
#define SHIFT 1
439 9a64fbe4 bellard
#include "softmmu_template.h"
440 9a64fbe4 bellard
441 9a64fbe4 bellard
#define SHIFT 2
442 9a64fbe4 bellard
#include "softmmu_template.h"
443 9a64fbe4 bellard
444 9a64fbe4 bellard
#define SHIFT 3
445 9a64fbe4 bellard
#include "softmmu_template.h"
446 9a64fbe4 bellard
447 9a64fbe4 bellard
/* try to fill the TLB and return an exception if error. If retaddr is
448 9a64fbe4 bellard
   NULL, it means that the function was called in C code (i.e. not
449 9a64fbe4 bellard
   from generated code or from helper.c) */
450 9a64fbe4 bellard
/* XXX: fix it to restore all registers */
451 9a64fbe4 bellard
void tlb_fill(unsigned long addr, int is_write, int flags, void *retaddr)
452 9a64fbe4 bellard
{
453 9a64fbe4 bellard
    TranslationBlock *tb;
454 9a64fbe4 bellard
    int ret, is_user;
455 9a64fbe4 bellard
    unsigned long pc;
456 9a64fbe4 bellard
    CPUState *saved_env;
457 9a64fbe4 bellard
458 9a64fbe4 bellard
    /* XXX: hack to restore env in all cases, even if not called from
459 9a64fbe4 bellard
       generated code */
460 9a64fbe4 bellard
    saved_env = env;
461 9a64fbe4 bellard
    env = cpu_single_env;
462 9a64fbe4 bellard
    is_user = flags & 0x01;
463 9a64fbe4 bellard
    {
464 9a64fbe4 bellard
        unsigned long tlb_addrr, tlb_addrw;
465 9a64fbe4 bellard
        int index;
466 9a64fbe4 bellard
        index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
467 9a64fbe4 bellard
        tlb_addrr = env->tlb_read[is_user][index].address;
468 9a64fbe4 bellard
        tlb_addrw = env->tlb_write[is_user][index].address;
469 9a64fbe4 bellard
#if 0
470 9a64fbe4 bellard
        printf("%s 1 %p %p idx=%d addr=0x%08lx tbl_addr=0x%08lx 0x%08lx "
471 9a64fbe4 bellard
               "(0x%08lx 0x%08lx)\n", __func__, env,
472 9a64fbe4 bellard
               &env->tlb_read[is_user][index], index, addr,
473 9a64fbe4 bellard
               tlb_addrr, tlb_addrw, addr & TARGET_PAGE_MASK,
474 9a64fbe4 bellard
               tlb_addrr & (TARGET_PAGE_MASK | TLB_INVALID_MASK));
475 9a64fbe4 bellard
#endif
476 9a64fbe4 bellard
    }
477 9a64fbe4 bellard
    ret = cpu_handle_mmu_fault(env, addr, is_write, flags, 1);
478 9a64fbe4 bellard
    if (ret) {
479 9a64fbe4 bellard
        if (retaddr) {
480 9a64fbe4 bellard
            /* now we have a real cpu fault */
481 9a64fbe4 bellard
            pc = (unsigned long)retaddr;
482 9a64fbe4 bellard
            tb = tb_find_pc(pc);
483 9a64fbe4 bellard
            if (tb) {
484 9a64fbe4 bellard
                /* the PC is inside the translated code. It means that we have
485 9a64fbe4 bellard
                   a virtual CPU fault */
486 b324e814 bellard
                cpu_restore_state(tb, env, pc, NULL);
487 9a64fbe4 bellard
            }
488 9a64fbe4 bellard
        }
489 9a64fbe4 bellard
        do_queue_exception_err(env->exception_index, env->error_code);
490 9a64fbe4 bellard
        do_process_exceptions();
491 9a64fbe4 bellard
    }
492 9a64fbe4 bellard
    {
493 9a64fbe4 bellard
        unsigned long tlb_addrr, tlb_addrw;
494 9a64fbe4 bellard
        int index;
495 9a64fbe4 bellard
        index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
496 9a64fbe4 bellard
        tlb_addrr = env->tlb_read[is_user][index].address;
497 9a64fbe4 bellard
        tlb_addrw = env->tlb_write[is_user][index].address;
498 9a64fbe4 bellard
#if 0
499 9a64fbe4 bellard
        printf("%s 2 %p %p idx=%d addr=0x%08lx tbl_addr=0x%08lx 0x%08lx "
500 9a64fbe4 bellard
               "(0x%08lx 0x%08lx)\n", __func__, env,
501 9a64fbe4 bellard
               &env->tlb_read[is_user][index], index, addr,
502 9a64fbe4 bellard
               tlb_addrr, tlb_addrw, addr & TARGET_PAGE_MASK,
503 9a64fbe4 bellard
               tlb_addrr & (TARGET_PAGE_MASK | TLB_INVALID_MASK));
504 9a64fbe4 bellard
#endif
505 9a64fbe4 bellard
    }
506 9a64fbe4 bellard
    env = saved_env;
507 9a64fbe4 bellard
}
508 9a64fbe4 bellard
509 9a64fbe4 bellard
void cpu_ppc_init_mmu(CPUPPCState *env)
510 9a64fbe4 bellard
{
511 9a64fbe4 bellard
    /* Nothing to do: all translation are disabled */
512 9a64fbe4 bellard
}
513 9a64fbe4 bellard
#endif
514 9a64fbe4 bellard
515 9a64fbe4 bellard
/* Perform address translation */
516 9a64fbe4 bellard
int cpu_ppc_handle_mmu_fault (CPUState *env, uint32_t address, int rw,
517 9a64fbe4 bellard
                              int flags, int is_softmmu)
518 9a64fbe4 bellard
{
519 9a64fbe4 bellard
    uint32_t physical;
520 9a64fbe4 bellard
    int prot;
521 9a64fbe4 bellard
    int exception = 0, error_code = 0;
522 9a64fbe4 bellard
    int is_user, access_type;
523 9a64fbe4 bellard
    int ret = 0;
524 9a64fbe4 bellard
525 9a64fbe4 bellard
//    printf("%s 0\n", __func__);
526 9a64fbe4 bellard
    is_user = flags & 0x01;
527 ac9eb073 bellard
    access_type = env->access_type;
528 9a64fbe4 bellard
    if (env->user_mode_only) {
529 9a64fbe4 bellard
        /* user mode only emulation */
530 9a64fbe4 bellard
        ret = -1;
531 9a64fbe4 bellard
        goto do_fault;
532 9a64fbe4 bellard
    }
533 9a64fbe4 bellard
    ret = get_physical_address(env, &physical, &prot,
534 9a64fbe4 bellard
                               address, rw, access_type);
535 9a64fbe4 bellard
    if (ret == 0) {
536 9a64fbe4 bellard
        ret = tlb_set_page(env, address, physical, prot, is_user, is_softmmu);
537 9a64fbe4 bellard
    } else if (ret < 0) {
538 9a64fbe4 bellard
    do_fault:
539 9a64fbe4 bellard
#if defined (DEBUG_MMU)
540 9a64fbe4 bellard
        printf("%s 5\n", __func__);
541 9a64fbe4 bellard
        printf("nip=0x%08x LR=0x%08x CTR=0x%08x MSR=0x%08x TBL=0x%08x\n",
542 9a64fbe4 bellard
               env->nip, env->lr, env->ctr, /*msr*/0, env->tb[0]);
543 9a64fbe4 bellard
        {
544 9a64fbe4 bellard
            int  i;
545 9a64fbe4 bellard
            for (i = 0; i < 32; i++) {
546 9a64fbe4 bellard
                if ((i & 7) == 0)
547 9a64fbe4 bellard
                    printf("GPR%02d:", i);
548 9a64fbe4 bellard
                printf(" %08x", env->gpr[i]);
549 9a64fbe4 bellard
                if ((i & 7) == 7)
550 9a64fbe4 bellard
                    printf("\n");
551 9a64fbe4 bellard
            }
552 9a64fbe4 bellard
            printf("CR: 0x");
553 9a64fbe4 bellard
            for (i = 0; i < 8; i++)
554 9a64fbe4 bellard
                printf("%01x", env->crf[i]);
555 9a64fbe4 bellard
            printf("  [");
556 9a64fbe4 bellard
            for (i = 0; i < 8; i++) {
557 9a64fbe4 bellard
                char a = '-';
558 9a64fbe4 bellard
                if (env->crf[i] & 0x08)
559 9a64fbe4 bellard
                    a = 'L';
560 9a64fbe4 bellard
                else if (env->crf[i] & 0x04)
561 9a64fbe4 bellard
                    a = 'G';
562 9a64fbe4 bellard
                else if (env->crf[i] & 0x02)
563 9a64fbe4 bellard
                    a = 'E';
564 9a64fbe4 bellard
                printf(" %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
565 9a64fbe4 bellard
            }
566 9a64fbe4 bellard
            printf(" ] ");
567 9a64fbe4 bellard
        }
568 9a64fbe4 bellard
        printf("TB: 0x%08x %08x\n", env->tb[1], env->tb[0]);
569 9a64fbe4 bellard
        printf("SRR0 0x%08x SRR1 0x%08x\n", env->spr[SRR0], env->spr[SRR1]);
570 9a64fbe4 bellard
#endif
571 9a64fbe4 bellard
        if (access_type == ACCESS_CODE) {
572 9a64fbe4 bellard
            exception = EXCP_ISI;
573 9a64fbe4 bellard
            switch (ret) {
574 9a64fbe4 bellard
            case -1:
575 9a64fbe4 bellard
                /* No matches in page tables */
576 9a64fbe4 bellard
                error_code = EXCP_ISI_TRANSLATE;
577 9a64fbe4 bellard
                break;
578 9a64fbe4 bellard
            case -2:
579 9a64fbe4 bellard
                /* Access rights violation */
580 9a64fbe4 bellard
                error_code = EXCP_ISI_PROT;
581 9a64fbe4 bellard
                break;
582 9a64fbe4 bellard
            case -3:
583 9a64fbe4 bellard
                error_code = EXCP_ISI_NOEXEC;
584 9a64fbe4 bellard
                break;
585 9a64fbe4 bellard
            case -4:
586 9a64fbe4 bellard
                /* Direct store exception */
587 9a64fbe4 bellard
                /* No code fetch is allowed in direct-store areas */
588 9a64fbe4 bellard
                exception = EXCP_ISI;
589 9a64fbe4 bellard
                error_code = EXCP_ISI_NOEXEC;
590 9a64fbe4 bellard
                break;
591 9a64fbe4 bellard
            }
592 9a64fbe4 bellard
        } else {
593 9a64fbe4 bellard
            exception = EXCP_DSI;
594 9a64fbe4 bellard
            switch (ret) {
595 9a64fbe4 bellard
            case -1:
596 9a64fbe4 bellard
                /* No matches in page tables */
597 9a64fbe4 bellard
                error_code = EXCP_DSI_TRANSLATE;
598 9a64fbe4 bellard
                break;
599 9a64fbe4 bellard
            case -2:
600 9a64fbe4 bellard
                /* Access rights violation */
601 9a64fbe4 bellard
                error_code = EXCP_DSI_PROT;
602 9a64fbe4 bellard
                break;
603 9a64fbe4 bellard
            case -4:
604 9a64fbe4 bellard
                /* Direct store exception */
605 9a64fbe4 bellard
                switch (access_type) {
606 9a64fbe4 bellard
                case ACCESS_FLOAT:
607 9a64fbe4 bellard
                    /* Floating point load/store */
608 9a64fbe4 bellard
                    exception = EXCP_ALIGN;
609 9a64fbe4 bellard
                    error_code = EXCP_ALIGN_FP;
610 9a64fbe4 bellard
                    break;
611 9a64fbe4 bellard
                case ACCESS_RES:
612 9a64fbe4 bellard
                    /* lwarx, ldarx or srwcx. */
613 9a64fbe4 bellard
                    exception = EXCP_DSI;
614 9a64fbe4 bellard
                    error_code = EXCP_DSI_NOTSUP | EXCP_DSI_DIRECT;
615 9a64fbe4 bellard
                    if (rw)
616 9a64fbe4 bellard
                        error_code |= EXCP_DSI_STORE;
617 9a64fbe4 bellard
                    break;
618 9a64fbe4 bellard
                case ACCESS_EXT:
619 9a64fbe4 bellard
                    /* eciwx or ecowx */
620 9a64fbe4 bellard
                    exception = EXCP_DSI;
621 9a64fbe4 bellard
                    error_code = EXCP_DSI_NOTSUP | EXCP_DSI_DIRECT | EXCP_ECXW;
622 9a64fbe4 bellard
                    break;
623 9a64fbe4 bellard
                default:
624 9a64fbe4 bellard
                    exception = EXCP_PROGRAM;
625 9a64fbe4 bellard
                    error_code = EXCP_INVAL | EXCP_INVAL_INVAL;
626 9a64fbe4 bellard
                    break;
627 9a64fbe4 bellard
                }
628 9a64fbe4 bellard
            }
629 9a64fbe4 bellard
            if (rw)
630 9a64fbe4 bellard
                error_code |= EXCP_DSI_STORE;
631 9a64fbe4 bellard
            /* Should find a better solution:
632 9a64fbe4 bellard
             * this will be invalid for some exception if more than one
633 9a64fbe4 bellard
             * exception occurs for one instruction
634 9a64fbe4 bellard
             */
635 9a64fbe4 bellard
            env->spr[DSISR] = 0;
636 9a64fbe4 bellard
            if (error_code & EXCP_DSI_DIRECT) {
637 9a64fbe4 bellard
                env->spr[DSISR] |= 0x80000000;
638 9a64fbe4 bellard
                if (access_type == ACCESS_EXT ||
639 9a64fbe4 bellard
                    access_type == ACCESS_RES)
640 9a64fbe4 bellard
                    env->spr[DSISR] |= 0x04000000;
641 9a64fbe4 bellard
            }
642 9a64fbe4 bellard
            if ((error_code & 0xF) == EXCP_DSI_TRANSLATE)
643 9a64fbe4 bellard
                env->spr[DSISR] |= 0x40000000;
644 9a64fbe4 bellard
            if (error_code & EXCP_DSI_PROT)
645 9a64fbe4 bellard
                env->spr[DSISR] |= 0x08000000;
646 9a64fbe4 bellard
            if (error_code & EXCP_DSI_STORE)
647 9a64fbe4 bellard
                env->spr[DSISR] |= 0x02000000;
648 9a64fbe4 bellard
            if ((error_code & 0xF) == EXCP_DSI_DABR)
649 9a64fbe4 bellard
                env->spr[DSISR] |= 0x00400000;
650 9a64fbe4 bellard
            if (access_type == ACCESS_EXT)
651 9a64fbe4 bellard
                env->spr[DSISR] |= 0x00100000;
652 9a64fbe4 bellard
        }
653 9a64fbe4 bellard
#if 0
654 9a64fbe4 bellard
        printf("%s: set exception to %d %02x\n",
655 9a64fbe4 bellard
               __func__, exception, error_code);
656 9a64fbe4 bellard
#endif
657 9a64fbe4 bellard
        env->exception_index = exception;
658 9a64fbe4 bellard
        env->error_code = error_code;
659 9a64fbe4 bellard
        /* Store fault address */
660 9a64fbe4 bellard
        env->spr[DAR] = address;
661 9a64fbe4 bellard
        ret = 1;
662 9a64fbe4 bellard
    }
663 9a64fbe4 bellard
664 9a64fbe4 bellard
    return ret;
665 9a64fbe4 bellard
}
666 9a64fbe4 bellard
667 9a64fbe4 bellard
uint32_t _load_xer (void)
668 79aceca5 bellard
{
669 79aceca5 bellard
    return (xer_so << XER_SO) |
670 79aceca5 bellard
        (xer_ov << XER_OV) |
671 79aceca5 bellard
        (xer_ca << XER_CA) |
672 79aceca5 bellard
        (xer_bc << XER_BC);
673 79aceca5 bellard
}
674 79aceca5 bellard
675 9a64fbe4 bellard
void _store_xer (uint32_t value)
676 79aceca5 bellard
{
677 79aceca5 bellard
    xer_so = (value >> XER_SO) & 0x01;
678 79aceca5 bellard
    xer_ov = (value >> XER_OV) & 0x01;
679 79aceca5 bellard
    xer_ca = (value >> XER_CA) & 0x01;
680 79aceca5 bellard
    xer_bc = (value >> XER_BC) & 0x1f;
681 79aceca5 bellard
}
682 79aceca5 bellard
683 9a64fbe4 bellard
uint32_t _load_msr (void)
684 79aceca5 bellard
{
685 79aceca5 bellard
    return (msr_pow << MSR_POW) |
686 79aceca5 bellard
        (msr_ile << MSR_ILE) |
687 79aceca5 bellard
        (msr_ee << MSR_EE) |
688 79aceca5 bellard
        (msr_pr << MSR_PR) |
689 79aceca5 bellard
        (msr_fp << MSR_FP) |
690 79aceca5 bellard
        (msr_me << MSR_ME) |
691 79aceca5 bellard
        (msr_fe0 << MSR_FE0) |
692 79aceca5 bellard
        (msr_se << MSR_SE) |
693 79aceca5 bellard
        (msr_be << MSR_BE) |
694 79aceca5 bellard
        (msr_fe1 << MSR_FE1) |
695 79aceca5 bellard
        (msr_ip << MSR_IP) |
696 79aceca5 bellard
        (msr_ir << MSR_IR) |
697 79aceca5 bellard
        (msr_dr << MSR_DR) |
698 79aceca5 bellard
        (msr_ri << MSR_RI) |
699 79aceca5 bellard
        (msr_le << MSR_LE);
700 79aceca5 bellard
}
701 79aceca5 bellard
702 9a64fbe4 bellard
void _store_msr (uint32_t value)
703 79aceca5 bellard
{
704 9a64fbe4 bellard
    msr_pow = (value >> MSR_POW) & 0x03;
705 9a64fbe4 bellard
    msr_ile = (value >> MSR_ILE) & 0x01;
706 9a64fbe4 bellard
    msr_ee = (value >> MSR_EE) & 0x01;
707 9a64fbe4 bellard
    msr_pr = (value >> MSR_PR) & 0x01;
708 9a64fbe4 bellard
    msr_fp = (value >> MSR_FP) & 0x01;
709 9a64fbe4 bellard
    msr_me = (value >> MSR_ME) & 0x01;
710 9a64fbe4 bellard
    msr_fe0 = (value >> MSR_FE0) & 0x01;
711 9a64fbe4 bellard
    msr_se = (value >> MSR_SE) & 0x01;
712 9a64fbe4 bellard
    msr_be = (value >> MSR_BE) & 0x01;
713 9a64fbe4 bellard
    msr_fe1 = (value >> MSR_FE1) & 0x01;
714 9a64fbe4 bellard
    msr_ip = (value >> MSR_IP) & 0x01;
715 9a64fbe4 bellard
    msr_ir = (value >> MSR_IR) & 0x01;
716 9a64fbe4 bellard
    msr_dr = (value >> MSR_DR) & 0x01;
717 9a64fbe4 bellard
    msr_ri = (value >> MSR_RI) & 0x01;
718 9a64fbe4 bellard
    msr_le = (value >> MSR_LE) & 0x01;
719 79aceca5 bellard
}
720 79aceca5 bellard
721 9a64fbe4 bellard
void do_interrupt (CPUState *env)
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{
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#if defined (CONFIG_USER_ONLY)
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    env->exception_index |= 0x100;
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#else
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    uint32_t msr;
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    int excp = env->exception_index;
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    /* Dequeue PPC exceptions */
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    if (excp < EXCP_PPC_MAX)
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        env->exceptions &= ~(1 << excp);
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    msr = _load_msr();
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#if defined (DEBUG_EXCEPTIONS)
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    if (excp != EXCP_DECR && excp == EXCP_PROGRAM && excp < EXCP_PPC_MAX) 
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    {
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        if (loglevel > 0) {
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            fprintf(logfile, "Raise exception at 0x%08x => 0x%08x (%02x)\n",
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                    env->nip, excp << 8, env->error_code);
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        } else {
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            printf("Raise exception at 0x%08x => 0x%08x (%02x)\n",
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                   env->nip, excp << 8, env->error_code);
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        }
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        printf("nip=0x%08x LR=0x%08x CTR=0x%08x MSR=0x%08x DECR=0x%08x\n",
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               env->nip, env->lr, env->ctr, msr, env->decr);
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        {
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    int i;
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            for (i = 0; i < 32; i++) {
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                if ((i & 7) == 0)
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                    printf("GPR%02d:", i);
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                printf(" %08x", env->gpr[i]);
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                if ((i & 7) == 7)
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                    printf("\n");
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    }
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            printf("CR: 0x");
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    for (i = 0; i < 8; i++)
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                printf("%01x", env->crf[i]);
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            printf("  [");
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            for (i = 0; i < 8; i++) {
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                char a = '-';
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                if (env->crf[i] & 0x08)
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                    a = 'L';
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                else if (env->crf[i] & 0x04)
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                    a = 'G';
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                else if (env->crf[i] & 0x02)
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                    a = 'E';
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                printf(" %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
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    }
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            printf(" ] ");
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    }
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        printf("TB: 0x%08x %08x\n", env->tb[1], env->tb[0]);
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        printf("XER 0x%08x SRR0 0x%08x SRR1 0x%08x\n",
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               _load_xer(), env->spr[SRR0], env->spr[SRR1]);
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    }
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#endif
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    /* Generate informations in save/restore registers */
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    switch (excp) {
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    case EXCP_OFCALL:
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#if defined (USE_OPEN_FIRMWARE)
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        env->gpr[3] = OF_client_entry((void *)env->gpr[3]);
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#endif
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        return;
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    case EXCP_RTASCALL:
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#if defined (USE_OPEN_FIRMWARE)
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        printf("RTAS call !\n");
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        env->gpr[3] = RTAS_entry((void *)env->gpr[3]);
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        printf("RTAS call done\n");
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#endif
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        return;
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    case EXCP_NONE:
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        /* Do nothing */
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#if defined (DEBUG_EXCEPTIONS)
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        printf("%s: escape EXCP_NONE\n", __func__);
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#endif
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        return;
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    case EXCP_RESET:
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        if (msr_ip)
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            excp += 0xFFC00;
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        goto store_next;
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    case EXCP_MACHINE_CHECK:
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        if (msr_me == 0) {
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            printf("Machine check exception while not allowed !\n");
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            if (loglevel) {
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                fprintf(logfile,
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                        "Machine check exception while not allowed !\n");
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        }
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            abort();
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    }
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        msr_me = 0;
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        break;
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    case EXCP_DSI:
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        /* Store exception cause */
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        /* data location address has been stored
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         * when the fault has been detected
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     */
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        goto store_current;
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    case EXCP_ISI:
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        /* Store exception cause */
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        if (env->error_code == EXCP_ISI_TRANSLATE)
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            msr |= 0x40000000;
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        else if (env->error_code == EXCP_ISI_NOEXEC ||
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            env->error_code == EXCP_ISI_GUARD)
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            msr |= 0x10000000;
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        else
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            msr |= 0x08000000;
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        goto store_next;
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    case EXCP_EXTERNAL:
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        if (msr_ee == 0) {
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#if defined (DEBUG_EXCEPTIONS)
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            if (loglevel > 0) {
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                fprintf(logfile, "Skipping hardware interrupt\n");
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            } else {
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                printf("Skipping hardware interrupt\n");
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    }
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#endif
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            return;
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            }
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        goto store_next;
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    case EXCP_ALIGN:
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        /* Store exception cause */
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        /* Get rS/rD and rA from faulting opcode */
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        env->spr[DSISR] |=
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            (ldl_code((void *)(env->nip - 4)) & 0x03FF0000) >> 16;
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        /* data location address has been stored
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         * when the fault has been detected
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         */
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        goto store_current;
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    case EXCP_PROGRAM:
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        msr &= ~0xFFFF0000;
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        switch (env->error_code & ~0xF) {
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        case EXCP_FP:
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            if (msr_fe0 == 0 && msr_fe1 == 0) {
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#if defined (DEBUG_EXCEPTIONS)
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                printf("Ignore floating point exception\n");
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#endif
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                return;
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        }
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            msr |= 0x00100000;
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            /* Set FX */
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            env->fpscr[7] |= 0x8;
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            /* Finally, update FEX */
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            if ((((env->fpscr[7] & 0x3) << 3) | (env->fpscr[6] >> 1)) &
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                ((env->fpscr[1] << 1) | (env->fpscr[0] >> 3)))
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                env->fpscr[7] |= 0x4;
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        break;
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        case EXCP_INVAL:
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            msr |= 0x00080000;
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        break;
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        case EXCP_PRIV:
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            msr |= 0x00040000;
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        break;
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        case EXCP_TRAP:
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            msr |= 0x00020000;
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            break;
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        default:
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            /* Should never occur */
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        break;
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    }
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        msr |= 0x00010000;
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        goto store_current;
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    case EXCP_NO_FP:
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        goto store_current;
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    case EXCP_DECR:
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        if (msr_ee == 0) {
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            /* Requeue it */
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            do_queue_exception(EXCP_DECR);
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            return;
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        }
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        goto store_next;
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    case EXCP_SYSCALL:
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#if defined (DEBUG_EXCEPTIONS)
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        printf("syscall %d 0x%08x 0x%08x 0x%08x 0x%08x\n",
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               env->gpr[0], env->gpr[3], env->gpr[4], env->gpr[5], env->gpr[6]);
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#endif
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        goto store_next;
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    case EXCP_TRACE:
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        goto store_next;
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    case EXCP_FP_ASSIST:
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        goto store_next;
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    case EXCP_MTMSR:
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        /* Nothing to do */
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#if defined (DEBUG_EXCEPTIONS)
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        printf("%s: escape EXCP_MTMSR\n", __func__);
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#endif
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        return;
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    case EXCP_BRANCH:
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        /* Nothing to do */
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#if defined (DEBUG_EXCEPTIONS)
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        printf("%s: escape EXCP_BRANCH\n", __func__);
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#endif
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        return;
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    case EXCP_RFI:
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        /* Restore user-mode state */
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#if defined (DEBUG_EXCEPTIONS)
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        printf("%s: escape EXCP_RFI\n", __func__);
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#endif
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        return;
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    store_current:
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        /* SRR0 is set to current instruction */
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        env->spr[SRR0] = (uint32_t)env->nip - 4;
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        break;
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    store_next:
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        /* SRR0 is set to next instruction */
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        env->spr[SRR0] = (uint32_t)env->nip;
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        break;
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    }
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    env->spr[SRR1] = msr;
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    /* reload MSR with correct bits */
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    msr_pow = 0;
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    msr_ee = 0;
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    msr_pr = 0;
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    msr_fp = 0;
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    msr_fe0 = 0;
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    msr_se = 0;
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    msr_be = 0;
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    msr_fe1 = 0;
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    msr_ir = 0;
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    msr_dr = 0;
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    msr_ri = 0;
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    msr_le = msr_ile;
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    /* Jump to handler */
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    env->nip = excp << 8;
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    env->exception_index = EXCP_NONE;
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    /* Invalidate all TLB as we may have changed translation mode */
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    do_tlbia();
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    /* ensure that no TB jump will be modified as
946 9a64fbe4 bellard
       the program flow was changed */
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#ifdef __sparc__
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    tmp_T0 = 0;
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#else
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    T0 = 0;
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#endif
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#endif
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}