root / target-ppc / helper.c @ 97eb5b14
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1 | 79aceca5 | bellard | /*
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2 | 79aceca5 | bellard | * PPC emulation helpers for qemu.
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3 | 79aceca5 | bellard | *
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4 | 79aceca5 | bellard | * Copyright (c) 2003 Jocelyn Mayer
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5 | 79aceca5 | bellard | *
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6 | 79aceca5 | bellard | * This library is free software; you can redistribute it and/or
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7 | 79aceca5 | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 79aceca5 | bellard | * License as published by the Free Software Foundation; either
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9 | 79aceca5 | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 79aceca5 | bellard | *
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11 | 79aceca5 | bellard | * This library is distributed in the hope that it will be useful,
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12 | 79aceca5 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 79aceca5 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 79aceca5 | bellard | * Lesser General Public License for more details.
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15 | 79aceca5 | bellard | *
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16 | 79aceca5 | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 79aceca5 | bellard | * License along with this library; if not, write to the Free Software
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18 | 79aceca5 | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | 79aceca5 | bellard | */
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20 | 9a64fbe4 | bellard | #include <sys/mman.h> |
21 | 9a64fbe4 | bellard | |
22 | 79aceca5 | bellard | #include "exec.h" |
23 | 9a64fbe4 | bellard | #if defined (USE_OPEN_FIRMWARE)
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24 | 9a64fbe4 | bellard | #include "of.h" |
25 | 9a64fbe4 | bellard | #endif
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26 | 9a64fbe4 | bellard | |
27 | 9a64fbe4 | bellard | //#define DEBUG_MMU
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28 | 9a64fbe4 | bellard | //#define DEBUG_BATS
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29 | 9a64fbe4 | bellard | //#define DEBUG_EXCEPTIONS
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30 | 9a64fbe4 | bellard | |
31 | 9a64fbe4 | bellard | extern FILE *logfile, *stderr;
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32 | 9a64fbe4 | bellard | void exit (int); |
33 | 9a64fbe4 | bellard | void abort (void); |
34 | 79aceca5 | bellard | |
35 | 79aceca5 | bellard | void cpu_loop_exit(void) |
36 | 79aceca5 | bellard | { |
37 | 79aceca5 | bellard | longjmp(env->jmp_env, 1);
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38 | 79aceca5 | bellard | } |
39 | 79aceca5 | bellard | |
40 | 9a64fbe4 | bellard | void do_process_exceptions (void) |
41 | 79aceca5 | bellard | { |
42 | 79aceca5 | bellard | cpu_loop_exit(); |
43 | 79aceca5 | bellard | } |
44 | 79aceca5 | bellard | |
45 | 9a64fbe4 | bellard | int check_exception_state (CPUState *env)
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46 | 79aceca5 | bellard | { |
47 | 9a64fbe4 | bellard | int i;
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48 | 79aceca5 | bellard | |
49 | 9a64fbe4 | bellard | /* Process PPC exceptions */
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50 | 9a64fbe4 | bellard | for (i = 1; i < EXCP_PPC_MAX; i++) { |
51 | 9a64fbe4 | bellard | if (env->exceptions & (1 << i)) { |
52 | 9a64fbe4 | bellard | switch (i) {
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53 | 9a64fbe4 | bellard | case EXCP_EXTERNAL:
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54 | 9a64fbe4 | bellard | case EXCP_DECR:
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55 | 9a64fbe4 | bellard | if (msr_ee == 0) |
56 | 9a64fbe4 | bellard | return 0; |
57 | 9a64fbe4 | bellard | break;
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58 | 9a64fbe4 | bellard | case EXCP_PROGRAM:
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59 | 9a64fbe4 | bellard | if (env->errors[EXCP_PROGRAM] == EXCP_FP &&
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60 | 9a64fbe4 | bellard | msr_fe0 == 0 && msr_fe1 == 0) |
61 | 9a64fbe4 | bellard | return 0; |
62 | 9a64fbe4 | bellard | break;
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63 | 9a64fbe4 | bellard | default:
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64 | 9a64fbe4 | bellard | break;
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65 | 9a64fbe4 | bellard | } |
66 | 9a64fbe4 | bellard | env->exception_index = i; |
67 | 9a64fbe4 | bellard | env->error_code = env->errors[i]; |
68 | 9a64fbe4 | bellard | return 1; |
69 | 9a64fbe4 | bellard | } |
70 | 9a64fbe4 | bellard | } |
71 | 9a64fbe4 | bellard | |
72 | 9a64fbe4 | bellard | return 0; |
73 | 9a64fbe4 | bellard | } |
74 | 9a64fbe4 | bellard | |
75 | 9a64fbe4 | bellard | /*****************************************************************************/
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76 | 9a64fbe4 | bellard | /* PPC MMU emulation */
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77 | 9a64fbe4 | bellard | /* Perform BAT hit & translation */
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78 | 9a64fbe4 | bellard | static int get_bat (CPUState *env, uint32_t *real, int *prot, |
79 | 9a64fbe4 | bellard | uint32_t virtual, int rw, int type) |
80 | 9a64fbe4 | bellard | { |
81 | 9a64fbe4 | bellard | uint32_t *BATlt, *BATut, *BATu, *BATl; |
82 | 9a64fbe4 | bellard | uint32_t base, BEPIl, BEPIu, bl; |
83 | 9a64fbe4 | bellard | int i;
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84 | 9a64fbe4 | bellard | int ret = -1; |
85 | 9a64fbe4 | bellard | |
86 | 9a64fbe4 | bellard | #if defined (DEBUG_BATS)
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87 | 9a64fbe4 | bellard | if (loglevel > 0) { |
88 | 9a64fbe4 | bellard | fprintf(logfile, "%s: %cBAT v 0x%08x\n", __func__,
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89 | 9a64fbe4 | bellard | type == ACCESS_CODE ? 'I' : 'D', virtual); |
90 | 9a64fbe4 | bellard | } |
91 | 9a64fbe4 | bellard | printf("%s: %cBAT v 0x%08x\n", __func__,
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92 | 9a64fbe4 | bellard | type == ACCESS_CODE ? 'I' : 'D', virtual); |
93 | 9a64fbe4 | bellard | #endif
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94 | 9a64fbe4 | bellard | switch (type) {
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95 | 9a64fbe4 | bellard | case ACCESS_CODE:
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96 | 9a64fbe4 | bellard | BATlt = env->IBAT[1];
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97 | 9a64fbe4 | bellard | BATut = env->IBAT[0];
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98 | 9a64fbe4 | bellard | break;
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99 | 9a64fbe4 | bellard | default:
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100 | 9a64fbe4 | bellard | BATlt = env->DBAT[1];
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101 | 9a64fbe4 | bellard | BATut = env->DBAT[0];
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102 | 9a64fbe4 | bellard | break;
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103 | 9a64fbe4 | bellard | } |
104 | 9a64fbe4 | bellard | #if defined (DEBUG_BATS)
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105 | 9a64fbe4 | bellard | if (loglevel > 0) { |
106 | 9a64fbe4 | bellard | fprintf(logfile, "%s...: %cBAT v 0x%08x\n", __func__,
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107 | 9a64fbe4 | bellard | type == ACCESS_CODE ? 'I' : 'D', virtual); |
108 | 9a64fbe4 | bellard | } |
109 | 9a64fbe4 | bellard | printf("%s...: %cBAT v 0x%08x\n", __func__,
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110 | 9a64fbe4 | bellard | type == ACCESS_CODE ? 'I' : 'D', virtual); |
111 | 9a64fbe4 | bellard | #endif
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112 | 9a64fbe4 | bellard | base = virtual & 0xFFFC0000;
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113 | 9a64fbe4 | bellard | for (i = 0; i < 4; i++) { |
114 | 9a64fbe4 | bellard | BATu = &BATut[i]; |
115 | 9a64fbe4 | bellard | BATl = &BATlt[i]; |
116 | 9a64fbe4 | bellard | BEPIu = *BATu & 0xF0000000;
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117 | 9a64fbe4 | bellard | BEPIl = *BATu & 0x0FFE0000;
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118 | 9a64fbe4 | bellard | bl = (*BATu & 0x00001FFC) << 15; |
119 | 9a64fbe4 | bellard | #if defined (DEBUG_BATS)
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120 | 9a64fbe4 | bellard | if (loglevel > 0) { |
121 | 9a64fbe4 | bellard | fprintf(logfile, "%s: %cBAT%d v 0x%08x BATu 0x%08x BATl 0x%08x\n",
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122 | 9a64fbe4 | bellard | __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual, |
123 | 9a64fbe4 | bellard | *BATu, *BATl); |
124 | 9a64fbe4 | bellard | } else {
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125 | 9a64fbe4 | bellard | printf("%s: %cBAT%d v 0x%08x BATu 0x%08x BATl 0x%08x\n",
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126 | 9a64fbe4 | bellard | __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual, |
127 | 9a64fbe4 | bellard | *BATu, *BATl); |
128 | 9a64fbe4 | bellard | } |
129 | 9a64fbe4 | bellard | #endif
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130 | 9a64fbe4 | bellard | if ((virtual & 0xF0000000) == BEPIu && |
131 | 9a64fbe4 | bellard | ((virtual & 0x0FFE0000) & ~bl) == BEPIl) {
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132 | 9a64fbe4 | bellard | /* BAT matches */
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133 | 9a64fbe4 | bellard | if ((msr_pr == 0 && (*BATu & 0x00000002)) || |
134 | 9a64fbe4 | bellard | (msr_pr == 1 && (*BATu & 0x00000001))) { |
135 | 9a64fbe4 | bellard | /* Get physical address */
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136 | 9a64fbe4 | bellard | *real = (*BATl & 0xF0000000) |
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137 | 9a64fbe4 | bellard | ((virtual & 0x0FFE0000 & bl) | (*BATl & 0x0FFE0000)) | |
138 | 9a64fbe4 | bellard | (virtual & 0x0001FFFF);
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139 | 9a64fbe4 | bellard | if (*BATl & 0x00000001) |
140 | 9a64fbe4 | bellard | *prot = PROT_READ; |
141 | 9a64fbe4 | bellard | if (*BATl & 0x00000002) |
142 | 9a64fbe4 | bellard | *prot = PROT_WRITE | PROT_READ; |
143 | 9a64fbe4 | bellard | #if defined (DEBUG_BATS)
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144 | 9a64fbe4 | bellard | if (loglevel > 0) { |
145 | 9a64fbe4 | bellard | fprintf(logfile, "BAT %d match: r 0x%08x prot=%c%c\n",
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146 | 9a64fbe4 | bellard | i, *real, *prot & PROT_READ ? 'R' : '-', |
147 | 9a64fbe4 | bellard | *prot & PROT_WRITE ? 'W' : '-'); |
148 | 9a64fbe4 | bellard | } else {
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149 | 9a64fbe4 | bellard | printf("BAT %d match: 0x%08x => 0x%08x prot=%c%c\n",
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150 | 9a64fbe4 | bellard | i, virtual, *real, *prot & PROT_READ ? 'R' : '-', |
151 | 9a64fbe4 | bellard | *prot & PROT_WRITE ? 'W' : '-'); |
152 | 9a64fbe4 | bellard | } |
153 | 9a64fbe4 | bellard | #endif
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154 | 9a64fbe4 | bellard | ret = 0;
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155 | 9a64fbe4 | bellard | break;
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156 | 9a64fbe4 | bellard | } |
157 | 9a64fbe4 | bellard | } |
158 | 9a64fbe4 | bellard | } |
159 | 9a64fbe4 | bellard | if (ret < 0) { |
160 | 9a64fbe4 | bellard | #if defined (DEBUG_BATS)
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161 | 9a64fbe4 | bellard | printf("no BAT match for 0x%08x:\n", virtual);
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162 | 9a64fbe4 | bellard | for (i = 0; i < 4; i++) { |
163 | 9a64fbe4 | bellard | BATu = &BATut[i]; |
164 | 9a64fbe4 | bellard | BATl = &BATlt[i]; |
165 | 9a64fbe4 | bellard | BEPIu = *BATu & 0xF0000000;
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166 | 9a64fbe4 | bellard | BEPIl = *BATu & 0x0FFE0000;
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167 | 9a64fbe4 | bellard | bl = (*BATu & 0x00001FFC) << 15; |
168 | 9a64fbe4 | bellard | printf("%s: %cBAT%d v 0x%08x BATu 0x%08x BATl 0x%08x \n\t"
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169 | 9a64fbe4 | bellard | "0x%08x 0x%08x 0x%08x\n",
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170 | 9a64fbe4 | bellard | __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual, |
171 | 9a64fbe4 | bellard | *BATu, *BATl, BEPIu, BEPIl, bl); |
172 | 9a64fbe4 | bellard | } |
173 | 9a64fbe4 | bellard | #endif
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174 | 9a64fbe4 | bellard | env->spr[DAR] = virtual; |
175 | 9a64fbe4 | bellard | } |
176 | 9a64fbe4 | bellard | /* No hit */
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177 | 9a64fbe4 | bellard | return ret;
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178 | 9a64fbe4 | bellard | } |
179 | 9a64fbe4 | bellard | |
180 | 9a64fbe4 | bellard | /* PTE table lookup */
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181 | 9a64fbe4 | bellard | static int find_pte (uint32_t *RPN, int *prot, uint32_t base, uint32_t va, |
182 | 9a64fbe4 | bellard | int h, int key, int rw) |
183 | 9a64fbe4 | bellard | { |
184 | 9a64fbe4 | bellard | uint32_t pte0, pte1, keep = 0;
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185 | 9a64fbe4 | bellard | int i, good = -1, store = 0; |
186 | 9a64fbe4 | bellard | int ret = -1; /* No entry found */ |
187 | 9a64fbe4 | bellard | |
188 | 9a64fbe4 | bellard | for (i = 0; i < 8; i++) { |
189 | 9a64fbe4 | bellard | pte0 = ldl_raw((void *)((uint32_t)phys_ram_base + base + (i * 8))); |
190 | 9a64fbe4 | bellard | pte1 = ldl_raw((void *)((uint32_t)phys_ram_base + base + (i * 8) + 4)); |
191 | 9a64fbe4 | bellard | #if defined (DEBUG_MMU)
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192 | 9a64fbe4 | bellard | printf("Load pte from 0x%08x => 0x%08x 0x%08x\n", base + (i * 8), |
193 | 9a64fbe4 | bellard | pte0, pte1); |
194 | 9a64fbe4 | bellard | #endif
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195 | 9a64fbe4 | bellard | /* Check validity and table match */
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196 | 9a64fbe4 | bellard | if (pte0 & 0x80000000 && (h == ((pte0 >> 6) & 1))) { |
197 | 9a64fbe4 | bellard | #if defined (DEBUG_MMU)
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198 | 9a64fbe4 | bellard | printf("PTE is valid and table matches... compare 0x%08x:%08x\n",
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199 | 9a64fbe4 | bellard | pte0 & 0x7FFFFFBF, va);
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200 | 9a64fbe4 | bellard | #endif
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201 | 9a64fbe4 | bellard | /* Check vsid & api */
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202 | 9a64fbe4 | bellard | if ((pte0 & 0x7FFFFFBF) == va) { |
203 | 9a64fbe4 | bellard | #if defined (DEBUG_MMU)
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204 | 9a64fbe4 | bellard | printf("PTE match !\n");
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205 | 9a64fbe4 | bellard | #endif
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206 | 9a64fbe4 | bellard | if (good == -1) { |
207 | 9a64fbe4 | bellard | good = i; |
208 | 9a64fbe4 | bellard | keep = pte1; |
209 | 9a64fbe4 | bellard | } else {
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210 | 9a64fbe4 | bellard | /* All matches should have equal RPN, WIMG & PP */
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211 | 9a64fbe4 | bellard | if ((keep & 0xFFFFF07B) != (pte1 & 0xFFFFF07B)) { |
212 | 9a64fbe4 | bellard | printf("Bad RPN/WIMG/PP\n");
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213 | 9a64fbe4 | bellard | return -1; |
214 | 9a64fbe4 | bellard | } |
215 | 9a64fbe4 | bellard | } |
216 | 9a64fbe4 | bellard | /* Check access rights */
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217 | 9a64fbe4 | bellard | if (key == 0) { |
218 | 9a64fbe4 | bellard | *prot = PROT_READ; |
219 | 9a64fbe4 | bellard | if ((pte1 & 0x00000003) != 0x3) |
220 | 9a64fbe4 | bellard | *prot |= PROT_WRITE; |
221 | 9a64fbe4 | bellard | } else {
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222 | 9a64fbe4 | bellard | switch (pte1 & 0x00000003) { |
223 | 9a64fbe4 | bellard | case 0x0: |
224 | 9a64fbe4 | bellard | *prot = 0;
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225 | 9a64fbe4 | bellard | break;
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226 | 9a64fbe4 | bellard | case 0x1: |
227 | 9a64fbe4 | bellard | case 0x3: |
228 | 9a64fbe4 | bellard | *prot = PROT_READ; |
229 | 9a64fbe4 | bellard | break;
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230 | 9a64fbe4 | bellard | case 0x2: |
231 | 9a64fbe4 | bellard | *prot = PROT_READ | PROT_WRITE; |
232 | 9a64fbe4 | bellard | break;
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233 | 9a64fbe4 | bellard | } |
234 | 9a64fbe4 | bellard | } |
235 | 9a64fbe4 | bellard | if ((rw == 0 && *prot != 0) || |
236 | 9a64fbe4 | bellard | (rw == 1 && (*prot & PROT_WRITE))) {
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237 | 9a64fbe4 | bellard | #if defined (DEBUG_MMU)
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238 | 9a64fbe4 | bellard | printf("PTE access granted !\n");
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239 | 9a64fbe4 | bellard | #endif
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240 | 9a64fbe4 | bellard | good = i; |
241 | 9a64fbe4 | bellard | keep = pte1; |
242 | 9a64fbe4 | bellard | ret = 0;
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243 | 9a64fbe4 | bellard | } else if (ret == -1) { |
244 | 9a64fbe4 | bellard | ret = -2; /* Access right violation */ |
245 | 9a64fbe4 | bellard | #if defined (DEBUG_MMU)
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246 | 9a64fbe4 | bellard | printf("PTE access rejected\n");
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247 | 9a64fbe4 | bellard | #endif
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248 | 9a64fbe4 | bellard | } |
249 | 9a64fbe4 | bellard | } |
250 | 9a64fbe4 | bellard | } |
251 | 9a64fbe4 | bellard | } |
252 | 9a64fbe4 | bellard | if (good != -1) { |
253 | 9a64fbe4 | bellard | *RPN = keep & 0xFFFFF000;
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254 | 9a64fbe4 | bellard | #if defined (DEBUG_MMU)
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255 | 9a64fbe4 | bellard | printf("found PTE at addr 0x%08x prot=0x%01x ret=%d\n",
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256 | 9a64fbe4 | bellard | *RPN, *prot, ret); |
257 | 9a64fbe4 | bellard | #endif
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258 | 9a64fbe4 | bellard | /* Update page flags */
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259 | 9a64fbe4 | bellard | if (!(keep & 0x00000100)) { |
260 | 9a64fbe4 | bellard | keep |= 0x00000100;
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261 | 9a64fbe4 | bellard | store = 1;
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262 | 9a64fbe4 | bellard | } |
263 | 9a64fbe4 | bellard | if (rw) {
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264 | 9a64fbe4 | bellard | if (!(keep & 0x00000080)) { |
265 | 9a64fbe4 | bellard | keep |= 0x00000080;
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266 | 9a64fbe4 | bellard | store = 1;
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267 | 9a64fbe4 | bellard | } |
268 | 9a64fbe4 | bellard | } |
269 | 9a64fbe4 | bellard | if (store)
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270 | 9a64fbe4 | bellard | stl_raw((void *)(base + (good * 2) + 1), keep); |
271 | 9a64fbe4 | bellard | } |
272 | 9a64fbe4 | bellard | |
273 | 9a64fbe4 | bellard | return ret;
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274 | 79aceca5 | bellard | } |
275 | 79aceca5 | bellard | |
276 | 9a64fbe4 | bellard | static inline uint32_t get_pgaddr (uint32_t sdr1, uint32_t hash, uint32_t mask) |
277 | 79aceca5 | bellard | { |
278 | 9a64fbe4 | bellard | return (sdr1 & 0xFFFF0000) | (hash & mask); |
279 | 79aceca5 | bellard | } |
280 | 79aceca5 | bellard | |
281 | 9a64fbe4 | bellard | /* Perform segment based translation */
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282 | 9a64fbe4 | bellard | static int get_segment (CPUState *env, uint32_t *real, int *prot, |
283 | 9a64fbe4 | bellard | uint32_t virtual, int rw, int type) |
284 | 79aceca5 | bellard | { |
285 | 9a64fbe4 | bellard | uint32_t pg_addr, sdr, ptem, vsid, pgidx; |
286 | 9a64fbe4 | bellard | uint32_t hash, mask; |
287 | 9a64fbe4 | bellard | uint32_t sr; |
288 | 9a64fbe4 | bellard | int key;
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289 | 9a64fbe4 | bellard | int ret = -1, ret2; |
290 | 79aceca5 | bellard | |
291 | 9a64fbe4 | bellard | sr = env->sr[virtual >> 28];
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292 | 9a64fbe4 | bellard | #if defined (DEBUG_MMU)
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293 | 9a64fbe4 | bellard | printf("Check segment v=0x%08x %d 0x%08x nip=0x%08x lr=0x%08x ir=%d dr=%d "
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294 | 9a64fbe4 | bellard | "pr=%d t=%d\n", virtual, virtual >> 28, sr, env->nip, |
295 | 9a64fbe4 | bellard | env->lr, msr_ir, msr_dr, msr_pr, type); |
296 | 9a64fbe4 | bellard | #endif
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297 | 9a64fbe4 | bellard | key = ((sr & 0x20000000) && msr_pr == 1) || |
298 | 9a64fbe4 | bellard | ((sr & 0x40000000) && msr_pr == 0) ? 1 : 0; |
299 | 9a64fbe4 | bellard | if ((sr & 0x80000000) == 0) { |
300 | 9a64fbe4 | bellard | #if defined (DEBUG_MMU)
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301 | 9a64fbe4 | bellard | printf("pte segment: key=%d n=0x%08x\n", key, sr & 0x10000000); |
302 | 9a64fbe4 | bellard | #endif
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303 | 9a64fbe4 | bellard | /* Check if instruction fetch is allowed, if needed */
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304 | 9a64fbe4 | bellard | if (type != ACCESS_CODE || (sr & 0x10000000) == 0) { |
305 | 9a64fbe4 | bellard | /* Page address translation */
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306 | 9a64fbe4 | bellard | vsid = sr & 0x00FFFFFF;
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307 | 9a64fbe4 | bellard | pgidx = (virtual >> 12) & 0xFFFF; |
308 | 9a64fbe4 | bellard | sdr = env->spr[SDR1]; |
309 | 9a64fbe4 | bellard | hash = ((vsid ^ pgidx) & 0x07FFFF) << 6; |
310 | 9a64fbe4 | bellard | mask = ((sdr & 0x000001FF) << 16) | 0xFFC0; |
311 | 9a64fbe4 | bellard | pg_addr = get_pgaddr(sdr, hash, mask); |
312 | 9a64fbe4 | bellard | ptem = (vsid << 7) | (pgidx >> 10); |
313 | 9a64fbe4 | bellard | #if defined (DEBUG_MMU)
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314 | 9a64fbe4 | bellard | printf("0 sdr1=0x%08x vsid=0x%06x api=0x%04x hash=0x%07x "
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315 | 9a64fbe4 | bellard | "pg_addr=0x%08x\n", sdr, vsid, pgidx, hash, pg_addr);
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316 | 9a64fbe4 | bellard | #endif
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317 | 9a64fbe4 | bellard | /* Primary table lookup */
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318 | 9a64fbe4 | bellard | ret = find_pte(real, prot, pg_addr, ptem, 0, key, rw);
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319 | 9a64fbe4 | bellard | if (ret < 0) { |
320 | 9a64fbe4 | bellard | /* Secondary table lookup */
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321 | 9a64fbe4 | bellard | hash = (~hash) & 0x01FFFFC0;
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322 | 9a64fbe4 | bellard | pg_addr = get_pgaddr(sdr, hash, mask); |
323 | 9a64fbe4 | bellard | #if defined (DEBUG_MMU)
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324 | 9a64fbe4 | bellard | printf("1 sdr1=0x%08x vsid=0x%06x api=0x%04x hash=0x%05x "
|
325 | 9a64fbe4 | bellard | "pg_addr=0x%08x\n", sdr, vsid, pgidx, hash, pg_addr);
|
326 | 9a64fbe4 | bellard | #endif
|
327 | 9a64fbe4 | bellard | ret2 = find_pte(real, prot, pg_addr, ptem, 1, key, rw);
|
328 | 9a64fbe4 | bellard | if (ret2 != -1) |
329 | 9a64fbe4 | bellard | ret = ret2; |
330 | 9a64fbe4 | bellard | } |
331 | 9a64fbe4 | bellard | if (ret != -1) |
332 | 9a64fbe4 | bellard | *real |= (virtual & 0x00000FFF);
|
333 | 9a64fbe4 | bellard | if (ret == -2 && type == ACCESS_CODE && (sr & 0x10000000)) |
334 | 9a64fbe4 | bellard | ret = -3;
|
335 | 9a64fbe4 | bellard | } else {
|
336 | 9a64fbe4 | bellard | #if defined (DEBUG_MMU)
|
337 | 9a64fbe4 | bellard | printf("No access allowed\n");
|
338 | 9a64fbe4 | bellard | #endif
|
339 | 9a64fbe4 | bellard | } |
340 | 9a64fbe4 | bellard | } else {
|
341 | 9a64fbe4 | bellard | #if defined (DEBUG_MMU)
|
342 | 9a64fbe4 | bellard | printf("direct store...\n");
|
343 | 9a64fbe4 | bellard | #endif
|
344 | 9a64fbe4 | bellard | /* Direct-store segment : absolutely *BUGGY* for now */
|
345 | 9a64fbe4 | bellard | switch (type) {
|
346 | 9a64fbe4 | bellard | case ACCESS_INT:
|
347 | 9a64fbe4 | bellard | /* Integer load/store : only access allowed */
|
348 | 9a64fbe4 | bellard | break;
|
349 | 9a64fbe4 | bellard | case ACCESS_CODE:
|
350 | 9a64fbe4 | bellard | /* No code fetch is allowed in direct-store areas */
|
351 | 9a64fbe4 | bellard | return -4; |
352 | 9a64fbe4 | bellard | case ACCESS_FLOAT:
|
353 | 9a64fbe4 | bellard | /* Floating point load/store */
|
354 | 9a64fbe4 | bellard | return -4; |
355 | 9a64fbe4 | bellard | case ACCESS_RES:
|
356 | 9a64fbe4 | bellard | /* lwarx, ldarx or srwcx. */
|
357 | 9a64fbe4 | bellard | return -4; |
358 | 9a64fbe4 | bellard | case ACCESS_CACHE:
|
359 | 9a64fbe4 | bellard | /* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi */
|
360 | 9a64fbe4 | bellard | /* Should make the instruction do no-op.
|
361 | 9a64fbe4 | bellard | * As it already do no-op, it's quite easy :-)
|
362 | 9a64fbe4 | bellard | */
|
363 | 9a64fbe4 | bellard | *real = virtual; |
364 | 9a64fbe4 | bellard | return 0; |
365 | 9a64fbe4 | bellard | case ACCESS_EXT:
|
366 | 9a64fbe4 | bellard | /* eciwx or ecowx */
|
367 | 9a64fbe4 | bellard | return -4; |
368 | 9a64fbe4 | bellard | default:
|
369 | 9a64fbe4 | bellard | if (logfile) {
|
370 | 9a64fbe4 | bellard | fprintf(logfile, "ERROR: instruction should not need "
|
371 | 9a64fbe4 | bellard | "address translation\n");
|
372 | 9a64fbe4 | bellard | } |
373 | 9a64fbe4 | bellard | printf("ERROR: instruction should not need "
|
374 | 9a64fbe4 | bellard | "address translation\n");
|
375 | 9a64fbe4 | bellard | return -4; |
376 | 9a64fbe4 | bellard | } |
377 | 9a64fbe4 | bellard | if ((rw == 1 || key != 1) && (rw == 0 || key != 0)) { |
378 | 9a64fbe4 | bellard | *real = virtual; |
379 | 9a64fbe4 | bellard | ret = 2;
|
380 | 9a64fbe4 | bellard | } else {
|
381 | 9a64fbe4 | bellard | ret = -2;
|
382 | 9a64fbe4 | bellard | } |
383 | 79aceca5 | bellard | } |
384 | 9a64fbe4 | bellard | |
385 | 9a64fbe4 | bellard | return ret;
|
386 | 79aceca5 | bellard | } |
387 | 79aceca5 | bellard | |
388 | 9a64fbe4 | bellard | int get_physical_address (CPUState *env, uint32_t *physical, int *prot, |
389 | 9a64fbe4 | bellard | uint32_t address, int rw, int access_type) |
390 | 9a64fbe4 | bellard | { |
391 | 9a64fbe4 | bellard | int ret;
|
392 | 9a64fbe4 | bellard | |
393 | 9a64fbe4 | bellard | if (loglevel > 0) { |
394 | 9a64fbe4 | bellard | fprintf(logfile, "%s\n", __func__);
|
395 | 9a64fbe4 | bellard | } |
396 | 9a64fbe4 | bellard | if ((access_type == ACCESS_CODE && msr_ir == 0) || msr_dr == 0) { |
397 | 9a64fbe4 | bellard | /* No address translation */
|
398 | 9a64fbe4 | bellard | *physical = address; |
399 | 9a64fbe4 | bellard | *prot = PROT_READ | PROT_WRITE; |
400 | 9a64fbe4 | bellard | ret = 0;
|
401 | 9a64fbe4 | bellard | } else {
|
402 | 9a64fbe4 | bellard | /* Try to find a BAT */
|
403 | 9a64fbe4 | bellard | ret = get_bat(env, physical, prot, address, rw, access_type); |
404 | 9a64fbe4 | bellard | if (ret < 0) { |
405 | 9a64fbe4 | bellard | /* We didn't match any BAT entry */
|
406 | 9a64fbe4 | bellard | ret = get_segment(env, physical, prot, address, rw, access_type); |
407 | 9a64fbe4 | bellard | } |
408 | 9a64fbe4 | bellard | } |
409 | 9a64fbe4 | bellard | |
410 | 9a64fbe4 | bellard | return ret;
|
411 | 9a64fbe4 | bellard | } |
412 | 9a64fbe4 | bellard | |
413 | a6b025d3 | bellard | #if defined(CONFIG_USER_ONLY)
|
414 | a6b025d3 | bellard | target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
415 | a6b025d3 | bellard | { |
416 | a6b025d3 | bellard | return addr;
|
417 | a6b025d3 | bellard | } |
418 | a6b025d3 | bellard | #else
|
419 | a6b025d3 | bellard | target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
420 | a6b025d3 | bellard | { |
421 | a6b025d3 | bellard | uint32_t phys_addr; |
422 | a6b025d3 | bellard | int prot;
|
423 | a6b025d3 | bellard | |
424 | a6b025d3 | bellard | if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0) |
425 | a6b025d3 | bellard | return -1; |
426 | a6b025d3 | bellard | return phys_addr;
|
427 | a6b025d3 | bellard | } |
428 | a6b025d3 | bellard | #endif
|
429 | 9a64fbe4 | bellard | |
430 | 9a64fbe4 | bellard | #if !defined(CONFIG_USER_ONLY)
|
431 | 9a64fbe4 | bellard | |
432 | 9a64fbe4 | bellard | #define MMUSUFFIX _mmu
|
433 | 9a64fbe4 | bellard | #define GETPC() (__builtin_return_address(0)) |
434 | 9a64fbe4 | bellard | |
435 | 9a64fbe4 | bellard | #define SHIFT 0 |
436 | 9a64fbe4 | bellard | #include "softmmu_template.h" |
437 | 9a64fbe4 | bellard | |
438 | 9a64fbe4 | bellard | #define SHIFT 1 |
439 | 9a64fbe4 | bellard | #include "softmmu_template.h" |
440 | 9a64fbe4 | bellard | |
441 | 9a64fbe4 | bellard | #define SHIFT 2 |
442 | 9a64fbe4 | bellard | #include "softmmu_template.h" |
443 | 9a64fbe4 | bellard | |
444 | 9a64fbe4 | bellard | #define SHIFT 3 |
445 | 9a64fbe4 | bellard | #include "softmmu_template.h" |
446 | 9a64fbe4 | bellard | |
447 | 9a64fbe4 | bellard | /* try to fill the TLB and return an exception if error. If retaddr is
|
448 | 9a64fbe4 | bellard | NULL, it means that the function was called in C code (i.e. not
|
449 | 9a64fbe4 | bellard | from generated code or from helper.c) */
|
450 | 9a64fbe4 | bellard | /* XXX: fix it to restore all registers */
|
451 | 9a64fbe4 | bellard | void tlb_fill(unsigned long addr, int is_write, int flags, void *retaddr) |
452 | 9a64fbe4 | bellard | { |
453 | 9a64fbe4 | bellard | TranslationBlock *tb; |
454 | 9a64fbe4 | bellard | int ret, is_user;
|
455 | 9a64fbe4 | bellard | unsigned long pc; |
456 | 9a64fbe4 | bellard | CPUState *saved_env; |
457 | 9a64fbe4 | bellard | |
458 | 9a64fbe4 | bellard | /* XXX: hack to restore env in all cases, even if not called from
|
459 | 9a64fbe4 | bellard | generated code */
|
460 | 9a64fbe4 | bellard | saved_env = env; |
461 | 9a64fbe4 | bellard | env = cpu_single_env; |
462 | 9a64fbe4 | bellard | is_user = flags & 0x01;
|
463 | 9a64fbe4 | bellard | { |
464 | 9a64fbe4 | bellard | unsigned long tlb_addrr, tlb_addrw; |
465 | 9a64fbe4 | bellard | int index;
|
466 | 9a64fbe4 | bellard | index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
|
467 | 9a64fbe4 | bellard | tlb_addrr = env->tlb_read[is_user][index].address; |
468 | 9a64fbe4 | bellard | tlb_addrw = env->tlb_write[is_user][index].address; |
469 | 9a64fbe4 | bellard | #if 0
|
470 | 9a64fbe4 | bellard | printf("%s 1 %p %p idx=%d addr=0x%08lx tbl_addr=0x%08lx 0x%08lx "
|
471 | 9a64fbe4 | bellard | "(0x%08lx 0x%08lx)\n", __func__, env,
|
472 | 9a64fbe4 | bellard | &env->tlb_read[is_user][index], index, addr,
|
473 | 9a64fbe4 | bellard | tlb_addrr, tlb_addrw, addr & TARGET_PAGE_MASK,
|
474 | 9a64fbe4 | bellard | tlb_addrr & (TARGET_PAGE_MASK | TLB_INVALID_MASK));
|
475 | 9a64fbe4 | bellard | #endif
|
476 | 9a64fbe4 | bellard | } |
477 | 9a64fbe4 | bellard | ret = cpu_handle_mmu_fault(env, addr, is_write, flags, 1);
|
478 | 9a64fbe4 | bellard | if (ret) {
|
479 | 9a64fbe4 | bellard | if (retaddr) {
|
480 | 9a64fbe4 | bellard | /* now we have a real cpu fault */
|
481 | 9a64fbe4 | bellard | pc = (unsigned long)retaddr; |
482 | 9a64fbe4 | bellard | tb = tb_find_pc(pc); |
483 | 9a64fbe4 | bellard | if (tb) {
|
484 | 9a64fbe4 | bellard | /* the PC is inside the translated code. It means that we have
|
485 | 9a64fbe4 | bellard | a virtual CPU fault */
|
486 | b324e814 | bellard | cpu_restore_state(tb, env, pc, NULL);
|
487 | 9a64fbe4 | bellard | } |
488 | 9a64fbe4 | bellard | } |
489 | 9a64fbe4 | bellard | do_queue_exception_err(env->exception_index, env->error_code); |
490 | 9a64fbe4 | bellard | do_process_exceptions(); |
491 | 9a64fbe4 | bellard | } |
492 | 9a64fbe4 | bellard | { |
493 | 9a64fbe4 | bellard | unsigned long tlb_addrr, tlb_addrw; |
494 | 9a64fbe4 | bellard | int index;
|
495 | 9a64fbe4 | bellard | index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
|
496 | 9a64fbe4 | bellard | tlb_addrr = env->tlb_read[is_user][index].address; |
497 | 9a64fbe4 | bellard | tlb_addrw = env->tlb_write[is_user][index].address; |
498 | 9a64fbe4 | bellard | #if 0
|
499 | 9a64fbe4 | bellard | printf("%s 2 %p %p idx=%d addr=0x%08lx tbl_addr=0x%08lx 0x%08lx "
|
500 | 9a64fbe4 | bellard | "(0x%08lx 0x%08lx)\n", __func__, env,
|
501 | 9a64fbe4 | bellard | &env->tlb_read[is_user][index], index, addr,
|
502 | 9a64fbe4 | bellard | tlb_addrr, tlb_addrw, addr & TARGET_PAGE_MASK,
|
503 | 9a64fbe4 | bellard | tlb_addrr & (TARGET_PAGE_MASK | TLB_INVALID_MASK));
|
504 | 9a64fbe4 | bellard | #endif
|
505 | 9a64fbe4 | bellard | } |
506 | 9a64fbe4 | bellard | env = saved_env; |
507 | 9a64fbe4 | bellard | } |
508 | 9a64fbe4 | bellard | |
509 | 9a64fbe4 | bellard | void cpu_ppc_init_mmu(CPUPPCState *env)
|
510 | 9a64fbe4 | bellard | { |
511 | 9a64fbe4 | bellard | /* Nothing to do: all translation are disabled */
|
512 | 9a64fbe4 | bellard | } |
513 | 9a64fbe4 | bellard | #endif
|
514 | 9a64fbe4 | bellard | |
515 | 9a64fbe4 | bellard | /* Perform address translation */
|
516 | 9a64fbe4 | bellard | int cpu_ppc_handle_mmu_fault (CPUState *env, uint32_t address, int rw, |
517 | 9a64fbe4 | bellard | int flags, int is_softmmu) |
518 | 9a64fbe4 | bellard | { |
519 | 9a64fbe4 | bellard | uint32_t physical; |
520 | 9a64fbe4 | bellard | int prot;
|
521 | 9a64fbe4 | bellard | int exception = 0, error_code = 0; |
522 | 9a64fbe4 | bellard | int is_user, access_type;
|
523 | 9a64fbe4 | bellard | int ret = 0; |
524 | 9a64fbe4 | bellard | |
525 | 9a64fbe4 | bellard | // printf("%s 0\n", __func__);
|
526 | 9a64fbe4 | bellard | is_user = flags & 0x01;
|
527 | ac9eb073 | bellard | access_type = env->access_type; |
528 | 9a64fbe4 | bellard | if (env->user_mode_only) {
|
529 | 9a64fbe4 | bellard | /* user mode only emulation */
|
530 | 9a64fbe4 | bellard | ret = -1;
|
531 | 9a64fbe4 | bellard | goto do_fault;
|
532 | 9a64fbe4 | bellard | } |
533 | 9a64fbe4 | bellard | ret = get_physical_address(env, &physical, &prot, |
534 | 9a64fbe4 | bellard | address, rw, access_type); |
535 | 9a64fbe4 | bellard | if (ret == 0) { |
536 | 9a64fbe4 | bellard | ret = tlb_set_page(env, address, physical, prot, is_user, is_softmmu); |
537 | 9a64fbe4 | bellard | } else if (ret < 0) { |
538 | 9a64fbe4 | bellard | do_fault:
|
539 | 9a64fbe4 | bellard | #if defined (DEBUG_MMU)
|
540 | 9a64fbe4 | bellard | printf("%s 5\n", __func__);
|
541 | 9a64fbe4 | bellard | printf("nip=0x%08x LR=0x%08x CTR=0x%08x MSR=0x%08x TBL=0x%08x\n",
|
542 | 9a64fbe4 | bellard | env->nip, env->lr, env->ctr, /*msr*/0, env->tb[0]); |
543 | 9a64fbe4 | bellard | { |
544 | 9a64fbe4 | bellard | int i;
|
545 | 9a64fbe4 | bellard | for (i = 0; i < 32; i++) { |
546 | 9a64fbe4 | bellard | if ((i & 7) == 0) |
547 | 9a64fbe4 | bellard | printf("GPR%02d:", i);
|
548 | 9a64fbe4 | bellard | printf(" %08x", env->gpr[i]);
|
549 | 9a64fbe4 | bellard | if ((i & 7) == 7) |
550 | 9a64fbe4 | bellard | printf("\n");
|
551 | 9a64fbe4 | bellard | } |
552 | 9a64fbe4 | bellard | printf("CR: 0x");
|
553 | 9a64fbe4 | bellard | for (i = 0; i < 8; i++) |
554 | 9a64fbe4 | bellard | printf("%01x", env->crf[i]);
|
555 | 9a64fbe4 | bellard | printf(" [");
|
556 | 9a64fbe4 | bellard | for (i = 0; i < 8; i++) { |
557 | 9a64fbe4 | bellard | char a = '-'; |
558 | 9a64fbe4 | bellard | if (env->crf[i] & 0x08) |
559 | 9a64fbe4 | bellard | a = 'L';
|
560 | 9a64fbe4 | bellard | else if (env->crf[i] & 0x04) |
561 | 9a64fbe4 | bellard | a = 'G';
|
562 | 9a64fbe4 | bellard | else if (env->crf[i] & 0x02) |
563 | 9a64fbe4 | bellard | a = 'E';
|
564 | 9a64fbe4 | bellard | printf(" %c%c", a, env->crf[i] & 0x01 ? 'O' : ' '); |
565 | 9a64fbe4 | bellard | } |
566 | 9a64fbe4 | bellard | printf(" ] ");
|
567 | 9a64fbe4 | bellard | } |
568 | 9a64fbe4 | bellard | printf("TB: 0x%08x %08x\n", env->tb[1], env->tb[0]); |
569 | 9a64fbe4 | bellard | printf("SRR0 0x%08x SRR1 0x%08x\n", env->spr[SRR0], env->spr[SRR1]);
|
570 | 9a64fbe4 | bellard | #endif
|
571 | 9a64fbe4 | bellard | if (access_type == ACCESS_CODE) {
|
572 | 9a64fbe4 | bellard | exception = EXCP_ISI; |
573 | 9a64fbe4 | bellard | switch (ret) {
|
574 | 9a64fbe4 | bellard | case -1: |
575 | 9a64fbe4 | bellard | /* No matches in page tables */
|
576 | 9a64fbe4 | bellard | error_code = EXCP_ISI_TRANSLATE; |
577 | 9a64fbe4 | bellard | break;
|
578 | 9a64fbe4 | bellard | case -2: |
579 | 9a64fbe4 | bellard | /* Access rights violation */
|
580 | 9a64fbe4 | bellard | error_code = EXCP_ISI_PROT; |
581 | 9a64fbe4 | bellard | break;
|
582 | 9a64fbe4 | bellard | case -3: |
583 | 9a64fbe4 | bellard | error_code = EXCP_ISI_NOEXEC; |
584 | 9a64fbe4 | bellard | break;
|
585 | 9a64fbe4 | bellard | case -4: |
586 | 9a64fbe4 | bellard | /* Direct store exception */
|
587 | 9a64fbe4 | bellard | /* No code fetch is allowed in direct-store areas */
|
588 | 9a64fbe4 | bellard | exception = EXCP_ISI; |
589 | 9a64fbe4 | bellard | error_code = EXCP_ISI_NOEXEC; |
590 | 9a64fbe4 | bellard | break;
|
591 | 9a64fbe4 | bellard | } |
592 | 9a64fbe4 | bellard | } else {
|
593 | 9a64fbe4 | bellard | exception = EXCP_DSI; |
594 | 9a64fbe4 | bellard | switch (ret) {
|
595 | 9a64fbe4 | bellard | case -1: |
596 | 9a64fbe4 | bellard | /* No matches in page tables */
|
597 | 9a64fbe4 | bellard | error_code = EXCP_DSI_TRANSLATE; |
598 | 9a64fbe4 | bellard | break;
|
599 | 9a64fbe4 | bellard | case -2: |
600 | 9a64fbe4 | bellard | /* Access rights violation */
|
601 | 9a64fbe4 | bellard | error_code = EXCP_DSI_PROT; |
602 | 9a64fbe4 | bellard | break;
|
603 | 9a64fbe4 | bellard | case -4: |
604 | 9a64fbe4 | bellard | /* Direct store exception */
|
605 | 9a64fbe4 | bellard | switch (access_type) {
|
606 | 9a64fbe4 | bellard | case ACCESS_FLOAT:
|
607 | 9a64fbe4 | bellard | /* Floating point load/store */
|
608 | 9a64fbe4 | bellard | exception = EXCP_ALIGN; |
609 | 9a64fbe4 | bellard | error_code = EXCP_ALIGN_FP; |
610 | 9a64fbe4 | bellard | break;
|
611 | 9a64fbe4 | bellard | case ACCESS_RES:
|
612 | 9a64fbe4 | bellard | /* lwarx, ldarx or srwcx. */
|
613 | 9a64fbe4 | bellard | exception = EXCP_DSI; |
614 | 9a64fbe4 | bellard | error_code = EXCP_DSI_NOTSUP | EXCP_DSI_DIRECT; |
615 | 9a64fbe4 | bellard | if (rw)
|
616 | 9a64fbe4 | bellard | error_code |= EXCP_DSI_STORE; |
617 | 9a64fbe4 | bellard | break;
|
618 | 9a64fbe4 | bellard | case ACCESS_EXT:
|
619 | 9a64fbe4 | bellard | /* eciwx or ecowx */
|
620 | 9a64fbe4 | bellard | exception = EXCP_DSI; |
621 | 9a64fbe4 | bellard | error_code = EXCP_DSI_NOTSUP | EXCP_DSI_DIRECT | EXCP_ECXW; |
622 | 9a64fbe4 | bellard | break;
|
623 | 9a64fbe4 | bellard | default:
|
624 | 9a64fbe4 | bellard | exception = EXCP_PROGRAM; |
625 | 9a64fbe4 | bellard | error_code = EXCP_INVAL | EXCP_INVAL_INVAL; |
626 | 9a64fbe4 | bellard | break;
|
627 | 9a64fbe4 | bellard | } |
628 | 9a64fbe4 | bellard | } |
629 | 9a64fbe4 | bellard | if (rw)
|
630 | 9a64fbe4 | bellard | error_code |= EXCP_DSI_STORE; |
631 | 9a64fbe4 | bellard | /* Should find a better solution:
|
632 | 9a64fbe4 | bellard | * this will be invalid for some exception if more than one
|
633 | 9a64fbe4 | bellard | * exception occurs for one instruction
|
634 | 9a64fbe4 | bellard | */
|
635 | 9a64fbe4 | bellard | env->spr[DSISR] = 0;
|
636 | 9a64fbe4 | bellard | if (error_code & EXCP_DSI_DIRECT) {
|
637 | 9a64fbe4 | bellard | env->spr[DSISR] |= 0x80000000;
|
638 | 9a64fbe4 | bellard | if (access_type == ACCESS_EXT ||
|
639 | 9a64fbe4 | bellard | access_type == ACCESS_RES) |
640 | 9a64fbe4 | bellard | env->spr[DSISR] |= 0x04000000;
|
641 | 9a64fbe4 | bellard | } |
642 | 9a64fbe4 | bellard | if ((error_code & 0xF) == EXCP_DSI_TRANSLATE) |
643 | 9a64fbe4 | bellard | env->spr[DSISR] |= 0x40000000;
|
644 | 9a64fbe4 | bellard | if (error_code & EXCP_DSI_PROT)
|
645 | 9a64fbe4 | bellard | env->spr[DSISR] |= 0x08000000;
|
646 | 9a64fbe4 | bellard | if (error_code & EXCP_DSI_STORE)
|
647 | 9a64fbe4 | bellard | env->spr[DSISR] |= 0x02000000;
|
648 | 9a64fbe4 | bellard | if ((error_code & 0xF) == EXCP_DSI_DABR) |
649 | 9a64fbe4 | bellard | env->spr[DSISR] |= 0x00400000;
|
650 | 9a64fbe4 | bellard | if (access_type == ACCESS_EXT)
|
651 | 9a64fbe4 | bellard | env->spr[DSISR] |= 0x00100000;
|
652 | 9a64fbe4 | bellard | } |
653 | 9a64fbe4 | bellard | #if 0
|
654 | 9a64fbe4 | bellard | printf("%s: set exception to %d %02x\n",
|
655 | 9a64fbe4 | bellard | __func__, exception, error_code);
|
656 | 9a64fbe4 | bellard | #endif
|
657 | 9a64fbe4 | bellard | env->exception_index = exception; |
658 | 9a64fbe4 | bellard | env->error_code = error_code; |
659 | 9a64fbe4 | bellard | /* Store fault address */
|
660 | 9a64fbe4 | bellard | env->spr[DAR] = address; |
661 | 9a64fbe4 | bellard | ret = 1;
|
662 | 9a64fbe4 | bellard | } |
663 | 9a64fbe4 | bellard | |
664 | 9a64fbe4 | bellard | return ret;
|
665 | 9a64fbe4 | bellard | } |
666 | 9a64fbe4 | bellard | |
667 | 9a64fbe4 | bellard | uint32_t _load_xer (void)
|
668 | 79aceca5 | bellard | { |
669 | 79aceca5 | bellard | return (xer_so << XER_SO) |
|
670 | 79aceca5 | bellard | (xer_ov << XER_OV) | |
671 | 79aceca5 | bellard | (xer_ca << XER_CA) | |
672 | 79aceca5 | bellard | (xer_bc << XER_BC); |
673 | 79aceca5 | bellard | } |
674 | 79aceca5 | bellard | |
675 | 9a64fbe4 | bellard | void _store_xer (uint32_t value)
|
676 | 79aceca5 | bellard | { |
677 | 79aceca5 | bellard | xer_so = (value >> XER_SO) & 0x01;
|
678 | 79aceca5 | bellard | xer_ov = (value >> XER_OV) & 0x01;
|
679 | 79aceca5 | bellard | xer_ca = (value >> XER_CA) & 0x01;
|
680 | 79aceca5 | bellard | xer_bc = (value >> XER_BC) & 0x1f;
|
681 | 79aceca5 | bellard | } |
682 | 79aceca5 | bellard | |
683 | 9a64fbe4 | bellard | uint32_t _load_msr (void)
|
684 | 79aceca5 | bellard | { |
685 | 79aceca5 | bellard | return (msr_pow << MSR_POW) |
|
686 | 79aceca5 | bellard | (msr_ile << MSR_ILE) | |
687 | 79aceca5 | bellard | (msr_ee << MSR_EE) | |
688 | 79aceca5 | bellard | (msr_pr << MSR_PR) | |
689 | 79aceca5 | bellard | (msr_fp << MSR_FP) | |
690 | 79aceca5 | bellard | (msr_me << MSR_ME) | |
691 | 79aceca5 | bellard | (msr_fe0 << MSR_FE0) | |
692 | 79aceca5 | bellard | (msr_se << MSR_SE) | |
693 | 79aceca5 | bellard | (msr_be << MSR_BE) | |
694 | 79aceca5 | bellard | (msr_fe1 << MSR_FE1) | |
695 | 79aceca5 | bellard | (msr_ip << MSR_IP) | |
696 | 79aceca5 | bellard | (msr_ir << MSR_IR) | |
697 | 79aceca5 | bellard | (msr_dr << MSR_DR) | |
698 | 79aceca5 | bellard | (msr_ri << MSR_RI) | |
699 | 79aceca5 | bellard | (msr_le << MSR_LE); |
700 | 79aceca5 | bellard | } |
701 | 79aceca5 | bellard | |
702 | 9a64fbe4 | bellard | void _store_msr (uint32_t value)
|
703 | 79aceca5 | bellard | { |
704 | 9a64fbe4 | bellard | msr_pow = (value >> MSR_POW) & 0x03;
|
705 | 9a64fbe4 | bellard | msr_ile = (value >> MSR_ILE) & 0x01;
|
706 | 9a64fbe4 | bellard | msr_ee = (value >> MSR_EE) & 0x01;
|
707 | 9a64fbe4 | bellard | msr_pr = (value >> MSR_PR) & 0x01;
|
708 | 9a64fbe4 | bellard | msr_fp = (value >> MSR_FP) & 0x01;
|
709 | 9a64fbe4 | bellard | msr_me = (value >> MSR_ME) & 0x01;
|
710 | 9a64fbe4 | bellard | msr_fe0 = (value >> MSR_FE0) & 0x01;
|
711 | 9a64fbe4 | bellard | msr_se = (value >> MSR_SE) & 0x01;
|
712 | 9a64fbe4 | bellard | msr_be = (value >> MSR_BE) & 0x01;
|
713 | 9a64fbe4 | bellard | msr_fe1 = (value >> MSR_FE1) & 0x01;
|
714 | 9a64fbe4 | bellard | msr_ip = (value >> MSR_IP) & 0x01;
|
715 | 9a64fbe4 | bellard | msr_ir = (value >> MSR_IR) & 0x01;
|
716 | 9a64fbe4 | bellard | msr_dr = (value >> MSR_DR) & 0x01;
|
717 | 9a64fbe4 | bellard | msr_ri = (value >> MSR_RI) & 0x01;
|
718 | 9a64fbe4 | bellard | msr_le = (value >> MSR_LE) & 0x01;
|
719 | 79aceca5 | bellard | } |
720 | 79aceca5 | bellard | |
721 | 9a64fbe4 | bellard | void do_interrupt (CPUState *env)
|
722 | 79aceca5 | bellard | { |
723 | 9a64fbe4 | bellard | #if defined (CONFIG_USER_ONLY)
|
724 | 9a64fbe4 | bellard | env->exception_index |= 0x100;
|
725 | 9a64fbe4 | bellard | #else
|
726 | 9a64fbe4 | bellard | uint32_t msr; |
727 | 9a64fbe4 | bellard | int excp = env->exception_index;
|
728 | 79aceca5 | bellard | |
729 | 9a64fbe4 | bellard | /* Dequeue PPC exceptions */
|
730 | 9a64fbe4 | bellard | if (excp < EXCP_PPC_MAX)
|
731 | 9a64fbe4 | bellard | env->exceptions &= ~(1 << excp);
|
732 | 9a64fbe4 | bellard | msr = _load_msr(); |
733 | 9a64fbe4 | bellard | #if defined (DEBUG_EXCEPTIONS)
|
734 | 9a64fbe4 | bellard | if (excp != EXCP_DECR && excp == EXCP_PROGRAM && excp < EXCP_PPC_MAX)
|
735 | 9a64fbe4 | bellard | { |
736 | 9a64fbe4 | bellard | if (loglevel > 0) { |
737 | 9a64fbe4 | bellard | fprintf(logfile, "Raise exception at 0x%08x => 0x%08x (%02x)\n",
|
738 | 9a64fbe4 | bellard | env->nip, excp << 8, env->error_code);
|
739 | 9a64fbe4 | bellard | } else {
|
740 | 9a64fbe4 | bellard | printf("Raise exception at 0x%08x => 0x%08x (%02x)\n",
|
741 | 9a64fbe4 | bellard | env->nip, excp << 8, env->error_code);
|
742 | 9a64fbe4 | bellard | } |
743 | 9a64fbe4 | bellard | printf("nip=0x%08x LR=0x%08x CTR=0x%08x MSR=0x%08x DECR=0x%08x\n",
|
744 | 9a64fbe4 | bellard | env->nip, env->lr, env->ctr, msr, env->decr); |
745 | 9a64fbe4 | bellard | { |
746 | 79aceca5 | bellard | int i;
|
747 | 9a64fbe4 | bellard | for (i = 0; i < 32; i++) { |
748 | 9a64fbe4 | bellard | if ((i & 7) == 0) |
749 | 9a64fbe4 | bellard | printf("GPR%02d:", i);
|
750 | 9a64fbe4 | bellard | printf(" %08x", env->gpr[i]);
|
751 | 9a64fbe4 | bellard | if ((i & 7) == 7) |
752 | 9a64fbe4 | bellard | printf("\n");
|
753 | fb0eaffc | bellard | } |
754 | 9a64fbe4 | bellard | printf("CR: 0x");
|
755 | 9a64fbe4 | bellard | for (i = 0; i < 8; i++) |
756 | 9a64fbe4 | bellard | printf("%01x", env->crf[i]);
|
757 | 9a64fbe4 | bellard | printf(" [");
|
758 | 9a64fbe4 | bellard | for (i = 0; i < 8; i++) { |
759 | 9a64fbe4 | bellard | char a = '-'; |
760 | 9a64fbe4 | bellard | if (env->crf[i] & 0x08) |
761 | 9a64fbe4 | bellard | a = 'L';
|
762 | 9a64fbe4 | bellard | else if (env->crf[i] & 0x04) |
763 | 9a64fbe4 | bellard | a = 'G';
|
764 | 9a64fbe4 | bellard | else if (env->crf[i] & 0x02) |
765 | 9a64fbe4 | bellard | a = 'E';
|
766 | 9a64fbe4 | bellard | printf(" %c%c", a, env->crf[i] & 0x01 ? 'O' : ' '); |
767 | 79aceca5 | bellard | } |
768 | 9a64fbe4 | bellard | printf(" ] ");
|
769 | 79aceca5 | bellard | } |
770 | 9a64fbe4 | bellard | printf("TB: 0x%08x %08x\n", env->tb[1], env->tb[0]); |
771 | 9a64fbe4 | bellard | printf("XER 0x%08x SRR0 0x%08x SRR1 0x%08x\n",
|
772 | 9a64fbe4 | bellard | _load_xer(), env->spr[SRR0], env->spr[SRR1]); |
773 | 79aceca5 | bellard | } |
774 | 9a64fbe4 | bellard | #endif
|
775 | 9a64fbe4 | bellard | /* Generate informations in save/restore registers */
|
776 | 9a64fbe4 | bellard | switch (excp) {
|
777 | 9a64fbe4 | bellard | case EXCP_OFCALL:
|
778 | 9a64fbe4 | bellard | #if defined (USE_OPEN_FIRMWARE)
|
779 | 9a64fbe4 | bellard | env->gpr[3] = OF_client_entry((void *)env->gpr[3]); |
780 | 9a64fbe4 | bellard | #endif
|
781 | 9a64fbe4 | bellard | return;
|
782 | 9a64fbe4 | bellard | case EXCP_RTASCALL:
|
783 | 9a64fbe4 | bellard | #if defined (USE_OPEN_FIRMWARE)
|
784 | 9a64fbe4 | bellard | printf("RTAS call !\n");
|
785 | 9a64fbe4 | bellard | env->gpr[3] = RTAS_entry((void *)env->gpr[3]); |
786 | 9a64fbe4 | bellard | printf("RTAS call done\n");
|
787 | 9a64fbe4 | bellard | #endif
|
788 | 9a64fbe4 | bellard | return;
|
789 | 9a64fbe4 | bellard | case EXCP_NONE:
|
790 | 9a64fbe4 | bellard | /* Do nothing */
|
791 | 9a64fbe4 | bellard | #if defined (DEBUG_EXCEPTIONS)
|
792 | 9a64fbe4 | bellard | printf("%s: escape EXCP_NONE\n", __func__);
|
793 | 9a64fbe4 | bellard | #endif
|
794 | 9a64fbe4 | bellard | return;
|
795 | 9a64fbe4 | bellard | case EXCP_RESET:
|
796 | 9a64fbe4 | bellard | if (msr_ip)
|
797 | 9a64fbe4 | bellard | excp += 0xFFC00;
|
798 | 9a64fbe4 | bellard | goto store_next;
|
799 | 9a64fbe4 | bellard | case EXCP_MACHINE_CHECK:
|
800 | 9a64fbe4 | bellard | if (msr_me == 0) { |
801 | 9a64fbe4 | bellard | printf("Machine check exception while not allowed !\n");
|
802 | 9a64fbe4 | bellard | if (loglevel) {
|
803 | 9a64fbe4 | bellard | fprintf(logfile, |
804 | 9a64fbe4 | bellard | "Machine check exception while not allowed !\n");
|
805 | 79aceca5 | bellard | } |
806 | 9a64fbe4 | bellard | abort(); |
807 | 79aceca5 | bellard | } |
808 | 9a64fbe4 | bellard | msr_me = 0;
|
809 | 9a64fbe4 | bellard | break;
|
810 | 9a64fbe4 | bellard | case EXCP_DSI:
|
811 | 9a64fbe4 | bellard | /* Store exception cause */
|
812 | 9a64fbe4 | bellard | /* data location address has been stored
|
813 | 9a64fbe4 | bellard | * when the fault has been detected
|
814 | 9a64fbe4 | bellard | */
|
815 | 9a64fbe4 | bellard | goto store_current;
|
816 | 9a64fbe4 | bellard | case EXCP_ISI:
|
817 | 9a64fbe4 | bellard | /* Store exception cause */
|
818 | 9a64fbe4 | bellard | if (env->error_code == EXCP_ISI_TRANSLATE)
|
819 | 9a64fbe4 | bellard | msr |= 0x40000000;
|
820 | 9a64fbe4 | bellard | else if (env->error_code == EXCP_ISI_NOEXEC || |
821 | 9a64fbe4 | bellard | env->error_code == EXCP_ISI_GUARD) |
822 | 9a64fbe4 | bellard | msr |= 0x10000000;
|
823 | 9a64fbe4 | bellard | else
|
824 | 9a64fbe4 | bellard | msr |= 0x08000000;
|
825 | 9a64fbe4 | bellard | goto store_next;
|
826 | 9a64fbe4 | bellard | case EXCP_EXTERNAL:
|
827 | 9a64fbe4 | bellard | if (msr_ee == 0) { |
828 | 9a64fbe4 | bellard | #if defined (DEBUG_EXCEPTIONS)
|
829 | 9a64fbe4 | bellard | if (loglevel > 0) { |
830 | 9a64fbe4 | bellard | fprintf(logfile, "Skipping hardware interrupt\n");
|
831 | 9a64fbe4 | bellard | } else {
|
832 | 9a64fbe4 | bellard | printf("Skipping hardware interrupt\n");
|
833 | 79aceca5 | bellard | } |
834 | 9a64fbe4 | bellard | #endif
|
835 | 9a64fbe4 | bellard | return;
|
836 | 79aceca5 | bellard | } |
837 | 9a64fbe4 | bellard | goto store_next;
|
838 | 9a64fbe4 | bellard | case EXCP_ALIGN:
|
839 | 9a64fbe4 | bellard | /* Store exception cause */
|
840 | 9a64fbe4 | bellard | /* Get rS/rD and rA from faulting opcode */
|
841 | 9a64fbe4 | bellard | env->spr[DSISR] |= |
842 | 9a64fbe4 | bellard | (ldl_code((void *)(env->nip - 4)) & 0x03FF0000) >> 16; |
843 | 9a64fbe4 | bellard | /* data location address has been stored
|
844 | 9a64fbe4 | bellard | * when the fault has been detected
|
845 | 9a64fbe4 | bellard | */
|
846 | 9a64fbe4 | bellard | goto store_current;
|
847 | 9a64fbe4 | bellard | case EXCP_PROGRAM:
|
848 | 9a64fbe4 | bellard | msr &= ~0xFFFF0000;
|
849 | 9a64fbe4 | bellard | switch (env->error_code & ~0xF) { |
850 | 9a64fbe4 | bellard | case EXCP_FP:
|
851 | 9a64fbe4 | bellard | if (msr_fe0 == 0 && msr_fe1 == 0) { |
852 | 9a64fbe4 | bellard | #if defined (DEBUG_EXCEPTIONS)
|
853 | 9a64fbe4 | bellard | printf("Ignore floating point exception\n");
|
854 | 9a64fbe4 | bellard | #endif
|
855 | 9a64fbe4 | bellard | return;
|
856 | 79aceca5 | bellard | } |
857 | 9a64fbe4 | bellard | msr |= 0x00100000;
|
858 | 9a64fbe4 | bellard | /* Set FX */
|
859 | 9a64fbe4 | bellard | env->fpscr[7] |= 0x8; |
860 | 9a64fbe4 | bellard | /* Finally, update FEX */
|
861 | 9a64fbe4 | bellard | if ((((env->fpscr[7] & 0x3) << 3) | (env->fpscr[6] >> 1)) & |
862 | 9a64fbe4 | bellard | ((env->fpscr[1] << 1) | (env->fpscr[0] >> 3))) |
863 | 9a64fbe4 | bellard | env->fpscr[7] |= 0x4; |
864 | 9a64fbe4 | bellard | break;
|
865 | 9a64fbe4 | bellard | case EXCP_INVAL:
|
866 | 9a64fbe4 | bellard | msr |= 0x00080000;
|
867 | 9a64fbe4 | bellard | break;
|
868 | 9a64fbe4 | bellard | case EXCP_PRIV:
|
869 | 9a64fbe4 | bellard | msr |= 0x00040000;
|
870 | 9a64fbe4 | bellard | break;
|
871 | 9a64fbe4 | bellard | case EXCP_TRAP:
|
872 | 9a64fbe4 | bellard | msr |= 0x00020000;
|
873 | 9a64fbe4 | bellard | break;
|
874 | 9a64fbe4 | bellard | default:
|
875 | 9a64fbe4 | bellard | /* Should never occur */
|
876 | 9a64fbe4 | bellard | break;
|
877 | 79aceca5 | bellard | } |
878 | 9a64fbe4 | bellard | msr |= 0x00010000;
|
879 | 9a64fbe4 | bellard | goto store_current;
|
880 | 9a64fbe4 | bellard | case EXCP_NO_FP:
|
881 | 9a64fbe4 | bellard | goto store_current;
|
882 | 9a64fbe4 | bellard | case EXCP_DECR:
|
883 | 9a64fbe4 | bellard | if (msr_ee == 0) { |
884 | 9a64fbe4 | bellard | /* Requeue it */
|
885 | 9a64fbe4 | bellard | do_queue_exception(EXCP_DECR); |
886 | 9a64fbe4 | bellard | return;
|
887 | 9a64fbe4 | bellard | } |
888 | 9a64fbe4 | bellard | goto store_next;
|
889 | 9a64fbe4 | bellard | case EXCP_SYSCALL:
|
890 | 9a64fbe4 | bellard | #if defined (DEBUG_EXCEPTIONS)
|
891 | 9a64fbe4 | bellard | printf("syscall %d 0x%08x 0x%08x 0x%08x 0x%08x\n",
|
892 | 9a64fbe4 | bellard | env->gpr[0], env->gpr[3], env->gpr[4], env->gpr[5], env->gpr[6]); |
893 | 9a64fbe4 | bellard | #endif
|
894 | 9a64fbe4 | bellard | goto store_next;
|
895 | 9a64fbe4 | bellard | case EXCP_TRACE:
|
896 | 9a64fbe4 | bellard | goto store_next;
|
897 | 9a64fbe4 | bellard | case EXCP_FP_ASSIST:
|
898 | 9a64fbe4 | bellard | goto store_next;
|
899 | 9a64fbe4 | bellard | case EXCP_MTMSR:
|
900 | 9a64fbe4 | bellard | /* Nothing to do */
|
901 | 9a64fbe4 | bellard | #if defined (DEBUG_EXCEPTIONS)
|
902 | 9a64fbe4 | bellard | printf("%s: escape EXCP_MTMSR\n", __func__);
|
903 | 9a64fbe4 | bellard | #endif
|
904 | 9a64fbe4 | bellard | return;
|
905 | 9a64fbe4 | bellard | case EXCP_BRANCH:
|
906 | 9a64fbe4 | bellard | /* Nothing to do */
|
907 | 9a64fbe4 | bellard | #if defined (DEBUG_EXCEPTIONS)
|
908 | 9a64fbe4 | bellard | printf("%s: escape EXCP_BRANCH\n", __func__);
|
909 | 9a64fbe4 | bellard | #endif
|
910 | 9a64fbe4 | bellard | return;
|
911 | 9a64fbe4 | bellard | case EXCP_RFI:
|
912 | 9a64fbe4 | bellard | /* Restore user-mode state */
|
913 | 9a64fbe4 | bellard | #if defined (DEBUG_EXCEPTIONS)
|
914 | 9a64fbe4 | bellard | printf("%s: escape EXCP_RFI\n", __func__);
|
915 | 9a64fbe4 | bellard | #endif
|
916 | 9a64fbe4 | bellard | return;
|
917 | 9a64fbe4 | bellard | store_current:
|
918 | 9a64fbe4 | bellard | /* SRR0 is set to current instruction */
|
919 | 9a64fbe4 | bellard | env->spr[SRR0] = (uint32_t)env->nip - 4;
|
920 | 9a64fbe4 | bellard | break;
|
921 | 9a64fbe4 | bellard | store_next:
|
922 | 9a64fbe4 | bellard | /* SRR0 is set to next instruction */
|
923 | 9a64fbe4 | bellard | env->spr[SRR0] = (uint32_t)env->nip; |
924 | 9a64fbe4 | bellard | break;
|
925 | 9a64fbe4 | bellard | } |
926 | 9a64fbe4 | bellard | env->spr[SRR1] = msr; |
927 | 9a64fbe4 | bellard | /* reload MSR with correct bits */
|
928 | 9a64fbe4 | bellard | msr_pow = 0;
|
929 | 9a64fbe4 | bellard | msr_ee = 0;
|
930 | 9a64fbe4 | bellard | msr_pr = 0;
|
931 | 9a64fbe4 | bellard | msr_fp = 0;
|
932 | 9a64fbe4 | bellard | msr_fe0 = 0;
|
933 | 9a64fbe4 | bellard | msr_se = 0;
|
934 | 9a64fbe4 | bellard | msr_be = 0;
|
935 | 9a64fbe4 | bellard | msr_fe1 = 0;
|
936 | 9a64fbe4 | bellard | msr_ir = 0;
|
937 | 9a64fbe4 | bellard | msr_dr = 0;
|
938 | 9a64fbe4 | bellard | msr_ri = 0;
|
939 | 9a64fbe4 | bellard | msr_le = msr_ile; |
940 | 9a64fbe4 | bellard | /* Jump to handler */
|
941 | 9a64fbe4 | bellard | env->nip = excp << 8;
|
942 | 9a64fbe4 | bellard | env->exception_index = EXCP_NONE; |
943 | 9a64fbe4 | bellard | /* Invalidate all TLB as we may have changed translation mode */
|
944 | 9a64fbe4 | bellard | do_tlbia(); |
945 | 9a64fbe4 | bellard | /* ensure that no TB jump will be modified as
|
946 | 9a64fbe4 | bellard | the program flow was changed */
|
947 | 9a64fbe4 | bellard | #ifdef __sparc__
|
948 | 9a64fbe4 | bellard | tmp_T0 = 0;
|
949 | 9a64fbe4 | bellard | #else
|
950 | 9a64fbe4 | bellard | T0 = 0;
|
951 | 9a64fbe4 | bellard | #endif
|
952 | 9a64fbe4 | bellard | #endif
|
953 | fb0eaffc | bellard | } |