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1 | 79aceca5 | bellard | /*
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2 | 79aceca5 | bellard | * PPC emulation micro-operations for qemu.
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3 | 79aceca5 | bellard | *
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4 | 79aceca5 | bellard | * Copyright (c) 2003 Jocelyn Mayer
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5 | 79aceca5 | bellard | *
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6 | 79aceca5 | bellard | * This library is free software; you can redistribute it and/or
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7 | 79aceca5 | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 79aceca5 | bellard | * License as published by the Free Software Foundation; either
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9 | 79aceca5 | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 79aceca5 | bellard | *
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11 | 79aceca5 | bellard | * This library is distributed in the hope that it will be useful,
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12 | 79aceca5 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 79aceca5 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 79aceca5 | bellard | * Lesser General Public License for more details.
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15 | 79aceca5 | bellard | *
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16 | 79aceca5 | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 79aceca5 | bellard | * License along with this library; if not, write to the Free Software
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18 | 79aceca5 | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | 79aceca5 | bellard | */
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20 | 79aceca5 | bellard | |
21 | 79aceca5 | bellard | #include "config.h" |
22 | 79aceca5 | bellard | #include "exec.h" |
23 | 79aceca5 | bellard | |
24 | 9a64fbe4 | bellard | //#define DEBUG_OP
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25 | 9a64fbe4 | bellard | |
26 | 79aceca5 | bellard | #define regs (env)
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27 | 79aceca5 | bellard | #define Ts0 (int32_t)T0
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28 | 79aceca5 | bellard | #define Ts1 (int32_t)T1
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29 | 79aceca5 | bellard | #define Ts2 (int32_t)T2
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30 | 79aceca5 | bellard | |
31 | 28b6751f | bellard | #define FT0 (env->ft0)
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32 | fb0eaffc | bellard | #define FT1 (env->ft1)
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33 | fb0eaffc | bellard | #define FT2 (env->ft2)
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34 | fb0eaffc | bellard | |
35 | fb0eaffc | bellard | #define FTS0 ((float)env->ft0) |
36 | fb0eaffc | bellard | #define FTS1 ((float)env->ft1) |
37 | fb0eaffc | bellard | #define FTS2 ((float)env->ft2) |
38 | 79aceca5 | bellard | |
39 | 9a64fbe4 | bellard | #define PPC_OP(name) void glue(op_, name)(void) |
40 | 79aceca5 | bellard | |
41 | 28b6751f | bellard | #define REG 0 |
42 | 28b6751f | bellard | #include "op_template.h" |
43 | 28b6751f | bellard | |
44 | 28b6751f | bellard | #define REG 1 |
45 | 28b6751f | bellard | #include "op_template.h" |
46 | 28b6751f | bellard | |
47 | 28b6751f | bellard | #define REG 2 |
48 | 28b6751f | bellard | #include "op_template.h" |
49 | 28b6751f | bellard | |
50 | 28b6751f | bellard | #define REG 3 |
51 | 28b6751f | bellard | #include "op_template.h" |
52 | 28b6751f | bellard | |
53 | 28b6751f | bellard | #define REG 4 |
54 | 28b6751f | bellard | #include "op_template.h" |
55 | 28b6751f | bellard | |
56 | 28b6751f | bellard | #define REG 5 |
57 | 28b6751f | bellard | #include "op_template.h" |
58 | 28b6751f | bellard | |
59 | 28b6751f | bellard | #define REG 6 |
60 | 28b6751f | bellard | #include "op_template.h" |
61 | 28b6751f | bellard | |
62 | 28b6751f | bellard | #define REG 7 |
63 | 28b6751f | bellard | #include "op_template.h" |
64 | 28b6751f | bellard | |
65 | 28b6751f | bellard | #define REG 8 |
66 | 28b6751f | bellard | #include "op_template.h" |
67 | 28b6751f | bellard | |
68 | 28b6751f | bellard | #define REG 9 |
69 | 28b6751f | bellard | #include "op_template.h" |
70 | 28b6751f | bellard | |
71 | 28b6751f | bellard | #define REG 10 |
72 | 28b6751f | bellard | #include "op_template.h" |
73 | 28b6751f | bellard | |
74 | 28b6751f | bellard | #define REG 11 |
75 | 28b6751f | bellard | #include "op_template.h" |
76 | 28b6751f | bellard | |
77 | 28b6751f | bellard | #define REG 12 |
78 | 28b6751f | bellard | #include "op_template.h" |
79 | 28b6751f | bellard | |
80 | 28b6751f | bellard | #define REG 13 |
81 | 28b6751f | bellard | #include "op_template.h" |
82 | 28b6751f | bellard | |
83 | 28b6751f | bellard | #define REG 14 |
84 | 28b6751f | bellard | #include "op_template.h" |
85 | 28b6751f | bellard | |
86 | 28b6751f | bellard | #define REG 15 |
87 | 28b6751f | bellard | #include "op_template.h" |
88 | 28b6751f | bellard | |
89 | 28b6751f | bellard | #define REG 16 |
90 | 28b6751f | bellard | #include "op_template.h" |
91 | 28b6751f | bellard | |
92 | 28b6751f | bellard | #define REG 17 |
93 | 28b6751f | bellard | #include "op_template.h" |
94 | 28b6751f | bellard | |
95 | 28b6751f | bellard | #define REG 18 |
96 | 28b6751f | bellard | #include "op_template.h" |
97 | 28b6751f | bellard | |
98 | 28b6751f | bellard | #define REG 19 |
99 | 28b6751f | bellard | #include "op_template.h" |
100 | 28b6751f | bellard | |
101 | 28b6751f | bellard | #define REG 20 |
102 | 28b6751f | bellard | #include "op_template.h" |
103 | 28b6751f | bellard | |
104 | 28b6751f | bellard | #define REG 21 |
105 | 28b6751f | bellard | #include "op_template.h" |
106 | 28b6751f | bellard | |
107 | 28b6751f | bellard | #define REG 22 |
108 | 28b6751f | bellard | #include "op_template.h" |
109 | 28b6751f | bellard | |
110 | 28b6751f | bellard | #define REG 23 |
111 | 28b6751f | bellard | #include "op_template.h" |
112 | 28b6751f | bellard | |
113 | 28b6751f | bellard | #define REG 24 |
114 | 28b6751f | bellard | #include "op_template.h" |
115 | 28b6751f | bellard | |
116 | 28b6751f | bellard | #define REG 25 |
117 | 28b6751f | bellard | #include "op_template.h" |
118 | 28b6751f | bellard | |
119 | 28b6751f | bellard | #define REG 26 |
120 | 28b6751f | bellard | #include "op_template.h" |
121 | 28b6751f | bellard | |
122 | 28b6751f | bellard | #define REG 27 |
123 | 28b6751f | bellard | #include "op_template.h" |
124 | 28b6751f | bellard | |
125 | 28b6751f | bellard | #define REG 28 |
126 | 28b6751f | bellard | #include "op_template.h" |
127 | 28b6751f | bellard | |
128 | 28b6751f | bellard | #define REG 29 |
129 | 28b6751f | bellard | #include "op_template.h" |
130 | 28b6751f | bellard | |
131 | 28b6751f | bellard | #define REG 30 |
132 | 28b6751f | bellard | #include "op_template.h" |
133 | 28b6751f | bellard | |
134 | 28b6751f | bellard | #define REG 31 |
135 | 28b6751f | bellard | #include "op_template.h" |
136 | 28b6751f | bellard | |
137 | 79aceca5 | bellard | /* PPC state maintenance operations */
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138 | 79aceca5 | bellard | /* set_Rc0 */
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139 | 79aceca5 | bellard | PPC_OP(set_Rc0) |
140 | 79aceca5 | bellard | { |
141 | 79aceca5 | bellard | uint32_t tmp; |
142 | 79aceca5 | bellard | |
143 | 79aceca5 | bellard | if (Ts0 < 0) { |
144 | 79aceca5 | bellard | tmp = 0x08;
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145 | 79aceca5 | bellard | } else if (Ts0 > 0) { |
146 | 79aceca5 | bellard | tmp = 0x04;
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147 | 79aceca5 | bellard | } else {
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148 | 79aceca5 | bellard | tmp = 0x02;
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149 | 79aceca5 | bellard | } |
150 | 9a64fbe4 | bellard | env->crf[0] = tmp;
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151 | 79aceca5 | bellard | RETURN(); |
152 | 79aceca5 | bellard | } |
153 | 79aceca5 | bellard | |
154 | 79aceca5 | bellard | PPC_OP(set_Rc0_ov) |
155 | 79aceca5 | bellard | { |
156 | 79aceca5 | bellard | uint32_t tmp; |
157 | 79aceca5 | bellard | |
158 | 79aceca5 | bellard | if (Ts0 < 0) { |
159 | 79aceca5 | bellard | tmp = 0x08;
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160 | 79aceca5 | bellard | } else if (Ts0 > 0) { |
161 | 79aceca5 | bellard | tmp = 0x04;
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162 | 79aceca5 | bellard | } else {
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163 | 79aceca5 | bellard | tmp = 0x02;
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164 | 79aceca5 | bellard | } |
165 | 79aceca5 | bellard | tmp |= xer_ov; |
166 | 9a64fbe4 | bellard | env->crf[0] = tmp;
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167 | 79aceca5 | bellard | RETURN(); |
168 | 79aceca5 | bellard | } |
169 | 79aceca5 | bellard | |
170 | 79aceca5 | bellard | /* reset_Rc0 */
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171 | 79aceca5 | bellard | PPC_OP(reset_Rc0) |
172 | 79aceca5 | bellard | { |
173 | 9a64fbe4 | bellard | env->crf[0] = 0x02 | xer_ov; |
174 | 79aceca5 | bellard | RETURN(); |
175 | 79aceca5 | bellard | } |
176 | 79aceca5 | bellard | |
177 | 79aceca5 | bellard | /* set_Rc0_1 */
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178 | 79aceca5 | bellard | PPC_OP(set_Rc0_1) |
179 | 79aceca5 | bellard | { |
180 | 9a64fbe4 | bellard | env->crf[0] = 0x04 | xer_ov; |
181 | 79aceca5 | bellard | RETURN(); |
182 | 79aceca5 | bellard | } |
183 | 79aceca5 | bellard | |
184 | fb0eaffc | bellard | /* Set Rc1 (for floating point arithmetic) */
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185 | fb0eaffc | bellard | PPC_OP(set_Rc1) |
186 | fb0eaffc | bellard | { |
187 | fb0eaffc | bellard | env->crf[1] = regs->fpscr[7]; |
188 | fb0eaffc | bellard | RETURN(); |
189 | fb0eaffc | bellard | } |
190 | fb0eaffc | bellard | |
191 | 9a64fbe4 | bellard | /* Constants load */
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192 | 79aceca5 | bellard | PPC_OP(set_T0) |
193 | 79aceca5 | bellard | { |
194 | 79aceca5 | bellard | T0 = PARAM(1);
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195 | 79aceca5 | bellard | RETURN(); |
196 | 79aceca5 | bellard | } |
197 | 79aceca5 | bellard | |
198 | 79aceca5 | bellard | PPC_OP(set_T1) |
199 | 79aceca5 | bellard | { |
200 | 79aceca5 | bellard | T1 = PARAM(1);
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201 | 79aceca5 | bellard | RETURN(); |
202 | 79aceca5 | bellard | } |
203 | 79aceca5 | bellard | |
204 | 79aceca5 | bellard | PPC_OP(set_T2) |
205 | 79aceca5 | bellard | { |
206 | 79aceca5 | bellard | T2 = PARAM(1);
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207 | 79aceca5 | bellard | RETURN(); |
208 | 79aceca5 | bellard | } |
209 | 79aceca5 | bellard | |
210 | 9a64fbe4 | bellard | /* Generate exceptions */
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211 | 9a64fbe4 | bellard | PPC_OP(queue_exception_err) |
212 | 79aceca5 | bellard | { |
213 | 9a64fbe4 | bellard | do_queue_exception_err(PARAM(1), PARAM(2)); |
214 | 9a64fbe4 | bellard | } |
215 | 9a64fbe4 | bellard | |
216 | 9a64fbe4 | bellard | PPC_OP(queue_exception) |
217 | 9a64fbe4 | bellard | { |
218 | 9a64fbe4 | bellard | do_queue_exception(PARAM(1));
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219 | 9a64fbe4 | bellard | } |
220 | 9a64fbe4 | bellard | |
221 | 9a64fbe4 | bellard | PPC_OP(process_exceptions) |
222 | 9a64fbe4 | bellard | { |
223 | 004bc62c | bellard | env->nip = PARAM(1);
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224 | 9a64fbe4 | bellard | if (env->exceptions != 0) { |
225 | 9a64fbe4 | bellard | do_check_exception_state(); |
226 | 79aceca5 | bellard | } |
227 | 9a64fbe4 | bellard | } |
228 | 9a64fbe4 | bellard | |
229 | 9a64fbe4 | bellard | /* Segment registers load and store with immediate index */
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230 | 9a64fbe4 | bellard | PPC_OP(load_srin) |
231 | 9a64fbe4 | bellard | { |
232 | 9a64fbe4 | bellard | T0 = regs->sr[T1 >> 28];
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233 | 9a64fbe4 | bellard | RETURN(); |
234 | 9a64fbe4 | bellard | } |
235 | 9a64fbe4 | bellard | |
236 | 9a64fbe4 | bellard | PPC_OP(store_srin) |
237 | 9a64fbe4 | bellard | { |
238 | 9a64fbe4 | bellard | #if defined (DEBUG_OP)
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239 | 9a64fbe4 | bellard | dump_store_sr(T1 >> 28);
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240 | 9a64fbe4 | bellard | #endif
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241 | 9a64fbe4 | bellard | regs->sr[T1 >> 28] = T0;
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242 | 9a64fbe4 | bellard | RETURN(); |
243 | 9a64fbe4 | bellard | } |
244 | 9a64fbe4 | bellard | |
245 | 9a64fbe4 | bellard | PPC_OP(load_sdr1) |
246 | 9a64fbe4 | bellard | { |
247 | 9a64fbe4 | bellard | T0 = regs->sdr1; |
248 | 79aceca5 | bellard | RETURN(); |
249 | 79aceca5 | bellard | } |
250 | 79aceca5 | bellard | |
251 | 9a64fbe4 | bellard | PPC_OP(store_sdr1) |
252 | 79aceca5 | bellard | { |
253 | 9a64fbe4 | bellard | regs->sdr1 = T0; |
254 | 79aceca5 | bellard | RETURN(); |
255 | 79aceca5 | bellard | } |
256 | 79aceca5 | bellard | |
257 | 79aceca5 | bellard | PPC_OP(exit_tb) |
258 | 79aceca5 | bellard | { |
259 | 79aceca5 | bellard | EXIT_TB(); |
260 | 79aceca5 | bellard | } |
261 | 79aceca5 | bellard | |
262 | 9a64fbe4 | bellard | /* Load/store special registers */
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263 | 79aceca5 | bellard | PPC_OP(load_cr) |
264 | 79aceca5 | bellard | { |
265 | 9a64fbe4 | bellard | do_load_cr(); |
266 | 79aceca5 | bellard | RETURN(); |
267 | 79aceca5 | bellard | } |
268 | 79aceca5 | bellard | |
269 | 79aceca5 | bellard | PPC_OP(store_cr) |
270 | 79aceca5 | bellard | { |
271 | 9a64fbe4 | bellard | do_store_cr(PARAM(1));
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272 | 79aceca5 | bellard | RETURN(); |
273 | 79aceca5 | bellard | } |
274 | 79aceca5 | bellard | |
275 | 79aceca5 | bellard | PPC_OP(load_xer_cr) |
276 | 79aceca5 | bellard | { |
277 | 79aceca5 | bellard | T0 = (xer_so << 3) | (xer_ov << 2) | (xer_ca << 1); |
278 | 79aceca5 | bellard | RETURN(); |
279 | 79aceca5 | bellard | } |
280 | 79aceca5 | bellard | |
281 | 79aceca5 | bellard | PPC_OP(clear_xer_cr) |
282 | 79aceca5 | bellard | { |
283 | 79aceca5 | bellard | xer_so = 0;
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284 | 79aceca5 | bellard | xer_ov = 0;
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285 | 79aceca5 | bellard | xer_ca = 0;
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286 | 79aceca5 | bellard | RETURN(); |
287 | 79aceca5 | bellard | } |
288 | 79aceca5 | bellard | |
289 | 79aceca5 | bellard | PPC_OP(load_xer_bc) |
290 | 79aceca5 | bellard | { |
291 | 9a64fbe4 | bellard | T1 = xer_bc; |
292 | 79aceca5 | bellard | RETURN(); |
293 | 79aceca5 | bellard | } |
294 | 79aceca5 | bellard | |
295 | 79aceca5 | bellard | PPC_OP(load_xer) |
296 | 79aceca5 | bellard | { |
297 | 9a64fbe4 | bellard | do_load_xer(); |
298 | 79aceca5 | bellard | RETURN(); |
299 | 79aceca5 | bellard | } |
300 | 79aceca5 | bellard | |
301 | 79aceca5 | bellard | PPC_OP(store_xer) |
302 | 79aceca5 | bellard | { |
303 | 9a64fbe4 | bellard | do_store_xer(); |
304 | 79aceca5 | bellard | RETURN(); |
305 | 79aceca5 | bellard | } |
306 | 79aceca5 | bellard | |
307 | 79aceca5 | bellard | PPC_OP(load_msr) |
308 | 79aceca5 | bellard | { |
309 | 9a64fbe4 | bellard | do_load_msr(); |
310 | 79aceca5 | bellard | RETURN(); |
311 | 79aceca5 | bellard | } |
312 | 79aceca5 | bellard | |
313 | 79aceca5 | bellard | PPC_OP(store_msr) |
314 | 79aceca5 | bellard | { |
315 | 9a64fbe4 | bellard | do_store_msr(); |
316 | 9a64fbe4 | bellard | RETURN(); |
317 | 9a64fbe4 | bellard | } |
318 | 9a64fbe4 | bellard | |
319 | 9a64fbe4 | bellard | /* SPR */
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320 | 9a64fbe4 | bellard | PPC_OP(load_spr) |
321 | 9a64fbe4 | bellard | { |
322 | 9a64fbe4 | bellard | T0 = regs->spr[PARAM(1)];
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323 | 9a64fbe4 | bellard | RETURN(); |
324 | 9a64fbe4 | bellard | } |
325 | 9a64fbe4 | bellard | |
326 | 9a64fbe4 | bellard | PPC_OP(store_spr) |
327 | 9a64fbe4 | bellard | { |
328 | 9a64fbe4 | bellard | regs->spr[PARAM(1)] = T0;
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329 | 79aceca5 | bellard | RETURN(); |
330 | 79aceca5 | bellard | } |
331 | 79aceca5 | bellard | |
332 | 79aceca5 | bellard | PPC_OP(load_lr) |
333 | 79aceca5 | bellard | { |
334 | 9a64fbe4 | bellard | T0 = regs->lr; |
335 | 9a64fbe4 | bellard | RETURN(); |
336 | 9a64fbe4 | bellard | } |
337 | 9a64fbe4 | bellard | |
338 | 9a64fbe4 | bellard | PPC_OP(store_lr) |
339 | 9a64fbe4 | bellard | { |
340 | 9a64fbe4 | bellard | regs->lr = T0; |
341 | 9a64fbe4 | bellard | RETURN(); |
342 | 9a64fbe4 | bellard | } |
343 | 9a64fbe4 | bellard | |
344 | 9a64fbe4 | bellard | PPC_OP(load_ctr) |
345 | 9a64fbe4 | bellard | { |
346 | 9a64fbe4 | bellard | T0 = regs->ctr; |
347 | 9a64fbe4 | bellard | RETURN(); |
348 | 9a64fbe4 | bellard | } |
349 | 9a64fbe4 | bellard | |
350 | 9a64fbe4 | bellard | PPC_OP(store_ctr) |
351 | 9a64fbe4 | bellard | { |
352 | 9a64fbe4 | bellard | regs->ctr = T0; |
353 | 9a64fbe4 | bellard | RETURN(); |
354 | 9a64fbe4 | bellard | } |
355 | 9a64fbe4 | bellard | |
356 | 9a64fbe4 | bellard | /* Update time base */
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357 | 9a64fbe4 | bellard | PPC_OP(update_tb) |
358 | 9a64fbe4 | bellard | { |
359 | 9a64fbe4 | bellard | T0 = regs->tb[0];
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360 | 9a64fbe4 | bellard | T1 = T0; |
361 | 9a64fbe4 | bellard | T0 += PARAM(1);
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362 | 9a64fbe4 | bellard | #if defined (DEBUG_OP)
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363 | 9a64fbe4 | bellard | dump_update_tb(PARAM(1));
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364 | 9a64fbe4 | bellard | #endif
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365 | 9a64fbe4 | bellard | if (T0 < T1) {
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366 | 9a64fbe4 | bellard | T1 = regs->tb[1] + 1; |
367 | 9a64fbe4 | bellard | regs->tb[1] = T1;
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368 | 9a64fbe4 | bellard | } |
369 | 9a64fbe4 | bellard | regs->tb[0] = T0;
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370 | 9a64fbe4 | bellard | RETURN(); |
371 | 9a64fbe4 | bellard | } |
372 | 9a64fbe4 | bellard | |
373 | 9a64fbe4 | bellard | PPC_OP(load_tb) |
374 | 9a64fbe4 | bellard | { |
375 | 9a64fbe4 | bellard | T0 = regs->tb[PARAM(1)];
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376 | 9a64fbe4 | bellard | RETURN(); |
377 | 9a64fbe4 | bellard | } |
378 | 9a64fbe4 | bellard | |
379 | 9a64fbe4 | bellard | PPC_OP(store_tb) |
380 | 9a64fbe4 | bellard | { |
381 | 9a64fbe4 | bellard | regs->tb[PARAM(1)] = T0;
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382 | 9a64fbe4 | bellard | #if defined (DEBUG_OP)
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383 | 9a64fbe4 | bellard | dump_store_tb(PARAM(1));
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384 | 9a64fbe4 | bellard | #endif
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385 | 79aceca5 | bellard | RETURN(); |
386 | 79aceca5 | bellard | } |
387 | 79aceca5 | bellard | |
388 | 9a64fbe4 | bellard | /* Update decrementer */
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389 | 9a64fbe4 | bellard | PPC_OP(update_decr) |
390 | 9a64fbe4 | bellard | { |
391 | 9a64fbe4 | bellard | T0 = regs->decr; |
392 | 9a64fbe4 | bellard | T1 = T0; |
393 | 9a64fbe4 | bellard | T0 -= PARAM(1);
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394 | 9a64fbe4 | bellard | regs->decr = T0; |
395 | 9a64fbe4 | bellard | if (PARAM(1) > T1) { |
396 | 9a64fbe4 | bellard | do_queue_exception(EXCP_DECR); |
397 | 9a64fbe4 | bellard | } |
398 | 9a64fbe4 | bellard | RETURN(); |
399 | 9a64fbe4 | bellard | } |
400 | 9a64fbe4 | bellard | |
401 | 9a64fbe4 | bellard | PPC_OP(store_decr) |
402 | 9a64fbe4 | bellard | { |
403 | 9a64fbe4 | bellard | T1 = regs->decr; |
404 | 9a64fbe4 | bellard | regs->decr = T0; |
405 | 9a64fbe4 | bellard | if (Ts0 < 0 && Ts1 > 0) { |
406 | 9a64fbe4 | bellard | do_queue_exception(EXCP_DECR); |
407 | 9a64fbe4 | bellard | } |
408 | 9a64fbe4 | bellard | RETURN(); |
409 | 9a64fbe4 | bellard | } |
410 | 9a64fbe4 | bellard | |
411 | 9a64fbe4 | bellard | PPC_OP(load_ibat) |
412 | 9a64fbe4 | bellard | { |
413 | 9a64fbe4 | bellard | T0 = regs->IBAT[PARAM(1)][PARAM(2)]; |
414 | 9a64fbe4 | bellard | } |
415 | 9a64fbe4 | bellard | |
416 | 9a64fbe4 | bellard | PPC_OP(store_ibat) |
417 | 9a64fbe4 | bellard | { |
418 | 9a64fbe4 | bellard | #if defined (DEBUG_OP)
|
419 | 9a64fbe4 | bellard | dump_store_ibat(PARAM(1), PARAM(2)); |
420 | 9a64fbe4 | bellard | #endif
|
421 | 9a64fbe4 | bellard | regs->IBAT[PARAM(1)][PARAM(2)] = T0; |
422 | 9a64fbe4 | bellard | } |
423 | 9a64fbe4 | bellard | |
424 | 9a64fbe4 | bellard | PPC_OP(load_dbat) |
425 | 9a64fbe4 | bellard | { |
426 | 9a64fbe4 | bellard | T0 = regs->DBAT[PARAM(1)][PARAM(2)]; |
427 | 9a64fbe4 | bellard | } |
428 | 9a64fbe4 | bellard | |
429 | 9a64fbe4 | bellard | PPC_OP(store_dbat) |
430 | 9a64fbe4 | bellard | { |
431 | 9a64fbe4 | bellard | #if defined (DEBUG_OP)
|
432 | 9a64fbe4 | bellard | dump_store_dbat(PARAM(1), PARAM(2)); |
433 | 9a64fbe4 | bellard | #endif
|
434 | 9a64fbe4 | bellard | regs->DBAT[PARAM(1)][PARAM(2)] = T0; |
435 | 9a64fbe4 | bellard | } |
436 | 9a64fbe4 | bellard | |
437 | fb0eaffc | bellard | /* FPSCR */
|
438 | fb0eaffc | bellard | PPC_OP(load_fpscr) |
439 | fb0eaffc | bellard | { |
440 | fb0eaffc | bellard | do_load_fpscr(); |
441 | fb0eaffc | bellard | RETURN(); |
442 | fb0eaffc | bellard | } |
443 | fb0eaffc | bellard | |
444 | fb0eaffc | bellard | PPC_OP(store_fpscr) |
445 | fb0eaffc | bellard | { |
446 | fb0eaffc | bellard | do_store_fpscr(PARAM(1));
|
447 | fb0eaffc | bellard | RETURN(); |
448 | fb0eaffc | bellard | } |
449 | fb0eaffc | bellard | |
450 | fb0eaffc | bellard | PPC_OP(reset_scrfx) |
451 | fb0eaffc | bellard | { |
452 | fb0eaffc | bellard | regs->fpscr[7] &= ~0x8; |
453 | fb0eaffc | bellard | RETURN(); |
454 | fb0eaffc | bellard | } |
455 | fb0eaffc | bellard | |
456 | 79aceca5 | bellard | /* crf operations */
|
457 | 79aceca5 | bellard | PPC_OP(getbit_T0) |
458 | 79aceca5 | bellard | { |
459 | 79aceca5 | bellard | T0 = (T0 >> PARAM(1)) & 1; |
460 | 79aceca5 | bellard | RETURN(); |
461 | 79aceca5 | bellard | } |
462 | 79aceca5 | bellard | |
463 | 79aceca5 | bellard | PPC_OP(getbit_T1) |
464 | 79aceca5 | bellard | { |
465 | 79aceca5 | bellard | T1 = (T1 >> PARAM(1)) & 1; |
466 | 79aceca5 | bellard | RETURN(); |
467 | 79aceca5 | bellard | } |
468 | 79aceca5 | bellard | |
469 | 79aceca5 | bellard | PPC_OP(setcrfbit) |
470 | 79aceca5 | bellard | { |
471 | 79aceca5 | bellard | T1 = (T1 & PARAM(1)) | (T0 << PARAM(2)); |
472 | 79aceca5 | bellard | RETURN(); |
473 | 79aceca5 | bellard | } |
474 | 79aceca5 | bellard | |
475 | 79aceca5 | bellard | /* Branch */
|
476 | 9a64fbe4 | bellard | #define EIP regs->nip
|
477 | 9a64fbe4 | bellard | |
478 | e98a6e40 | bellard | PPC_OP(setlr) |
479 | e98a6e40 | bellard | { |
480 | e98a6e40 | bellard | regs->lr = PARAM1; |
481 | e98a6e40 | bellard | } |
482 | e98a6e40 | bellard | |
483 | e98a6e40 | bellard | PPC_OP(b) |
484 | e98a6e40 | bellard | { |
485 | e98a6e40 | bellard | JUMP_TB(b1, PARAM1, 0, PARAM2);
|
486 | e98a6e40 | bellard | } |
487 | e98a6e40 | bellard | |
488 | e98a6e40 | bellard | PPC_OP(b_T1) |
489 | e98a6e40 | bellard | { |
490 | e98a6e40 | bellard | regs->nip = T1; |
491 | e98a6e40 | bellard | } |
492 | e98a6e40 | bellard | |
493 | e98a6e40 | bellard | PPC_OP(btest) |
494 | e98a6e40 | bellard | { |
495 | e98a6e40 | bellard | if (T0) {
|
496 | e98a6e40 | bellard | JUMP_TB(btest, PARAM1, 0, PARAM2);
|
497 | e98a6e40 | bellard | } else {
|
498 | e98a6e40 | bellard | JUMP_TB(btest, PARAM1, 1, PARAM3);
|
499 | e98a6e40 | bellard | } |
500 | e98a6e40 | bellard | RETURN(); |
501 | e98a6e40 | bellard | } |
502 | e98a6e40 | bellard | |
503 | e98a6e40 | bellard | PPC_OP(btest_T1) |
504 | e98a6e40 | bellard | { |
505 | e98a6e40 | bellard | if (T0) {
|
506 | e98a6e40 | bellard | regs->nip = T1 & ~3;
|
507 | e98a6e40 | bellard | } else {
|
508 | e98a6e40 | bellard | regs->nip = PARAM1; |
509 | e98a6e40 | bellard | } |
510 | e98a6e40 | bellard | RETURN(); |
511 | e98a6e40 | bellard | } |
512 | e98a6e40 | bellard | |
513 | e98a6e40 | bellard | PPC_OP(movl_T1_ctr) |
514 | e98a6e40 | bellard | { |
515 | e98a6e40 | bellard | T1 = regs->ctr; |
516 | e98a6e40 | bellard | } |
517 | e98a6e40 | bellard | |
518 | e98a6e40 | bellard | PPC_OP(movl_T1_lr) |
519 | e98a6e40 | bellard | { |
520 | e98a6e40 | bellard | T1 = regs->lr; |
521 | e98a6e40 | bellard | } |
522 | e98a6e40 | bellard | |
523 | e98a6e40 | bellard | /* tests with result in T0 */
|
524 | e98a6e40 | bellard | |
525 | e98a6e40 | bellard | PPC_OP(test_ctr) |
526 | e98a6e40 | bellard | { |
527 | b88e4a9a | bellard | T0 = regs->ctr; |
528 | e98a6e40 | bellard | } |
529 | e98a6e40 | bellard | |
530 | e98a6e40 | bellard | PPC_OP(test_ctr_true) |
531 | e98a6e40 | bellard | { |
532 | e98a6e40 | bellard | T0 = (regs->ctr != 0 && (T0 & PARAM(1)) != 0); |
533 | e98a6e40 | bellard | } |
534 | e98a6e40 | bellard | |
535 | e98a6e40 | bellard | PPC_OP(test_ctr_false) |
536 | e98a6e40 | bellard | { |
537 | e98a6e40 | bellard | T0 = (regs->ctr != 0 && (T0 & PARAM(1)) == 0); |
538 | e98a6e40 | bellard | } |
539 | e98a6e40 | bellard | |
540 | e98a6e40 | bellard | PPC_OP(test_ctrz) |
541 | e98a6e40 | bellard | { |
542 | e98a6e40 | bellard | T0 = (regs->ctr == 0);
|
543 | e98a6e40 | bellard | } |
544 | e98a6e40 | bellard | |
545 | e98a6e40 | bellard | PPC_OP(test_ctrz_true) |
546 | e98a6e40 | bellard | { |
547 | e98a6e40 | bellard | T0 = (regs->ctr == 0 && (T0 & PARAM(1)) != 0); |
548 | e98a6e40 | bellard | } |
549 | e98a6e40 | bellard | |
550 | e98a6e40 | bellard | PPC_OP(test_ctrz_false) |
551 | e98a6e40 | bellard | { |
552 | e98a6e40 | bellard | T0 = (regs->ctr == 0 && (T0 & PARAM(1)) == 0); |
553 | e98a6e40 | bellard | } |
554 | e98a6e40 | bellard | |
555 | e98a6e40 | bellard | PPC_OP(test_true) |
556 | e98a6e40 | bellard | { |
557 | b88e4a9a | bellard | T0 = (T0 & PARAM(1));
|
558 | e98a6e40 | bellard | } |
559 | e98a6e40 | bellard | |
560 | e98a6e40 | bellard | PPC_OP(test_false) |
561 | e98a6e40 | bellard | { |
562 | e98a6e40 | bellard | T0 = ((T0 & PARAM(1)) == 0); |
563 | e98a6e40 | bellard | } |
564 | 79aceca5 | bellard | |
565 | 79aceca5 | bellard | /* CTR maintenance */
|
566 | 79aceca5 | bellard | PPC_OP(dec_ctr) |
567 | 79aceca5 | bellard | { |
568 | 9a64fbe4 | bellard | regs->ctr--; |
569 | 79aceca5 | bellard | RETURN(); |
570 | 79aceca5 | bellard | } |
571 | 79aceca5 | bellard | |
572 | 79aceca5 | bellard | /*** Integer arithmetic ***/
|
573 | 79aceca5 | bellard | /* add */
|
574 | 79aceca5 | bellard | PPC_OP(add) |
575 | 79aceca5 | bellard | { |
576 | 79aceca5 | bellard | T0 += T1; |
577 | 79aceca5 | bellard | RETURN(); |
578 | 79aceca5 | bellard | } |
579 | 79aceca5 | bellard | |
580 | 79aceca5 | bellard | PPC_OP(addo) |
581 | 79aceca5 | bellard | { |
582 | 79aceca5 | bellard | T2 = T0; |
583 | 79aceca5 | bellard | T0 += T1; |
584 | 79aceca5 | bellard | if ((T2 ^ T1 ^ (-1)) & (T2 ^ T0) & (1 << 31)) { |
585 | 79aceca5 | bellard | xer_so = 1;
|
586 | 79aceca5 | bellard | xer_ov = 1;
|
587 | 79aceca5 | bellard | } else {
|
588 | 79aceca5 | bellard | xer_ov = 0;
|
589 | 79aceca5 | bellard | } |
590 | 79aceca5 | bellard | RETURN(); |
591 | 79aceca5 | bellard | } |
592 | 79aceca5 | bellard | |
593 | 79aceca5 | bellard | /* add carrying */
|
594 | 79aceca5 | bellard | PPC_OP(addc) |
595 | 79aceca5 | bellard | { |
596 | 79aceca5 | bellard | T2 = T0; |
597 | 79aceca5 | bellard | T0 += T1; |
598 | 79aceca5 | bellard | if (T0 < T2) {
|
599 | 79aceca5 | bellard | xer_ca = 1;
|
600 | 79aceca5 | bellard | } else {
|
601 | 79aceca5 | bellard | xer_ca = 0;
|
602 | 79aceca5 | bellard | } |
603 | 79aceca5 | bellard | RETURN(); |
604 | 79aceca5 | bellard | } |
605 | 79aceca5 | bellard | |
606 | 79aceca5 | bellard | PPC_OP(addco) |
607 | 79aceca5 | bellard | { |
608 | 79aceca5 | bellard | T2 = T0; |
609 | 79aceca5 | bellard | T0 += T1; |
610 | 79aceca5 | bellard | if (T0 < T2) {
|
611 | 79aceca5 | bellard | xer_ca = 1;
|
612 | 79aceca5 | bellard | } else {
|
613 | 79aceca5 | bellard | xer_ca = 0;
|
614 | 79aceca5 | bellard | } |
615 | 79aceca5 | bellard | if ((T2 ^ T1 ^ (-1)) & (T2 ^ T0) & (1 << 31)) { |
616 | 79aceca5 | bellard | xer_so = 1;
|
617 | 79aceca5 | bellard | xer_ov = 1;
|
618 | 79aceca5 | bellard | } else {
|
619 | 79aceca5 | bellard | xer_ov = 0;
|
620 | 79aceca5 | bellard | } |
621 | 79aceca5 | bellard | RETURN(); |
622 | 79aceca5 | bellard | } |
623 | 79aceca5 | bellard | |
624 | 79aceca5 | bellard | /* add extended */
|
625 | 79aceca5 | bellard | /* candidate for helper (too long) */
|
626 | 79aceca5 | bellard | PPC_OP(adde) |
627 | 79aceca5 | bellard | { |
628 | 79aceca5 | bellard | T2 = T0; |
629 | 79aceca5 | bellard | T0 += T1 + xer_ca; |
630 | 79aceca5 | bellard | if (T0 < T2 || (xer_ca == 1 && T0 == T2)) { |
631 | 79aceca5 | bellard | xer_ca = 1;
|
632 | 79aceca5 | bellard | } else {
|
633 | 79aceca5 | bellard | xer_ca = 0;
|
634 | 79aceca5 | bellard | } |
635 | 79aceca5 | bellard | RETURN(); |
636 | 79aceca5 | bellard | } |
637 | 79aceca5 | bellard | |
638 | 79aceca5 | bellard | PPC_OP(addeo) |
639 | 79aceca5 | bellard | { |
640 | 79aceca5 | bellard | T2 = T0; |
641 | 79aceca5 | bellard | T0 += T1 + xer_ca; |
642 | 79aceca5 | bellard | if (T0 < T2 || (xer_ca == 1 && T0 == T2)) { |
643 | 79aceca5 | bellard | xer_ca = 1;
|
644 | 79aceca5 | bellard | } else {
|
645 | 79aceca5 | bellard | xer_ca = 0;
|
646 | 79aceca5 | bellard | } |
647 | 79aceca5 | bellard | if ((T2 ^ T1 ^ (-1)) & (T2 ^ T0) & (1 << 31)) { |
648 | 79aceca5 | bellard | xer_so = 1;
|
649 | 79aceca5 | bellard | xer_ov = 1;
|
650 | 79aceca5 | bellard | } else {
|
651 | 79aceca5 | bellard | xer_ov = 0;
|
652 | 79aceca5 | bellard | } |
653 | 79aceca5 | bellard | RETURN(); |
654 | 79aceca5 | bellard | } |
655 | 79aceca5 | bellard | |
656 | 79aceca5 | bellard | /* add immediate */
|
657 | 79aceca5 | bellard | PPC_OP(addi) |
658 | 79aceca5 | bellard | { |
659 | 79aceca5 | bellard | T0 += PARAM(1);
|
660 | 79aceca5 | bellard | RETURN(); |
661 | 79aceca5 | bellard | } |
662 | 79aceca5 | bellard | |
663 | 79aceca5 | bellard | /* add immediate carrying */
|
664 | 79aceca5 | bellard | PPC_OP(addic) |
665 | 79aceca5 | bellard | { |
666 | 79aceca5 | bellard | T1 = T0; |
667 | 79aceca5 | bellard | T0 += PARAM(1);
|
668 | 79aceca5 | bellard | if (T0 < T1) {
|
669 | 79aceca5 | bellard | xer_ca = 1;
|
670 | 79aceca5 | bellard | } else {
|
671 | 79aceca5 | bellard | xer_ca = 0;
|
672 | 79aceca5 | bellard | } |
673 | 79aceca5 | bellard | RETURN(); |
674 | 79aceca5 | bellard | } |
675 | 79aceca5 | bellard | |
676 | 79aceca5 | bellard | /* add to minus one extended */
|
677 | 79aceca5 | bellard | PPC_OP(addme) |
678 | 79aceca5 | bellard | { |
679 | 79aceca5 | bellard | T1 = T0; |
680 | 79aceca5 | bellard | T0 += xer_ca + (-1);
|
681 | 79aceca5 | bellard | if (T1 != 0) |
682 | 79aceca5 | bellard | xer_ca = 1;
|
683 | 79aceca5 | bellard | RETURN(); |
684 | 79aceca5 | bellard | } |
685 | 79aceca5 | bellard | |
686 | 79aceca5 | bellard | PPC_OP(addmeo) |
687 | 79aceca5 | bellard | { |
688 | 79aceca5 | bellard | T1 = T0; |
689 | 79aceca5 | bellard | T0 += xer_ca + (-1);
|
690 | 79aceca5 | bellard | if (T1 & (T1 ^ T0) & (1 << 31)) { |
691 | 79aceca5 | bellard | xer_so = 1;
|
692 | 79aceca5 | bellard | xer_ov = 1;
|
693 | 79aceca5 | bellard | } else {
|
694 | 79aceca5 | bellard | xer_ov = 0;
|
695 | 79aceca5 | bellard | } |
696 | 79aceca5 | bellard | if (T1 != 0) |
697 | 79aceca5 | bellard | xer_ca = 1;
|
698 | 79aceca5 | bellard | RETURN(); |
699 | 79aceca5 | bellard | } |
700 | 79aceca5 | bellard | |
701 | 79aceca5 | bellard | /* add to zero extended */
|
702 | 79aceca5 | bellard | PPC_OP(addze) |
703 | 79aceca5 | bellard | { |
704 | 79aceca5 | bellard | T1 = T0; |
705 | 79aceca5 | bellard | T0 += xer_ca; |
706 | 79aceca5 | bellard | if (T0 < T1) {
|
707 | 79aceca5 | bellard | xer_ca = 1;
|
708 | 79aceca5 | bellard | } else {
|
709 | 79aceca5 | bellard | xer_ca = 0;
|
710 | 79aceca5 | bellard | } |
711 | 79aceca5 | bellard | RETURN(); |
712 | 79aceca5 | bellard | } |
713 | 79aceca5 | bellard | |
714 | 79aceca5 | bellard | PPC_OP(addzeo) |
715 | 79aceca5 | bellard | { |
716 | 79aceca5 | bellard | T1 = T0; |
717 | 79aceca5 | bellard | T0 += xer_ca; |
718 | 79aceca5 | bellard | if ((T1 ^ (-1)) & (T1 ^ T0) & (1 << 31)) { |
719 | 79aceca5 | bellard | xer_so = 1;
|
720 | 79aceca5 | bellard | xer_ov = 1;
|
721 | 79aceca5 | bellard | } else {
|
722 | 79aceca5 | bellard | xer_ov = 0;
|
723 | 79aceca5 | bellard | } |
724 | 79aceca5 | bellard | if (T0 < T1) {
|
725 | 79aceca5 | bellard | xer_ca = 1;
|
726 | 79aceca5 | bellard | } else {
|
727 | 79aceca5 | bellard | xer_ca = 0;
|
728 | 79aceca5 | bellard | } |
729 | 79aceca5 | bellard | RETURN(); |
730 | 79aceca5 | bellard | } |
731 | 79aceca5 | bellard | |
732 | 79aceca5 | bellard | /* divide word */
|
733 | 79aceca5 | bellard | /* candidate for helper (too long) */
|
734 | 79aceca5 | bellard | PPC_OP(divw) |
735 | 79aceca5 | bellard | { |
736 | 79aceca5 | bellard | if ((Ts0 == INT32_MIN && Ts1 == -1) || Ts1 == 0) { |
737 | 79aceca5 | bellard | Ts0 = (-1) * (T0 >> 31); |
738 | 79aceca5 | bellard | } else {
|
739 | 79aceca5 | bellard | Ts0 /= Ts1; |
740 | 79aceca5 | bellard | } |
741 | 79aceca5 | bellard | RETURN(); |
742 | 79aceca5 | bellard | } |
743 | 79aceca5 | bellard | |
744 | 79aceca5 | bellard | PPC_OP(divwo) |
745 | 79aceca5 | bellard | { |
746 | 79aceca5 | bellard | if ((Ts0 == INT32_MIN && Ts1 == -1) || Ts1 == 0) { |
747 | 79aceca5 | bellard | xer_so = 1;
|
748 | 79aceca5 | bellard | xer_ov = 1;
|
749 | 79aceca5 | bellard | T0 = (-1) * (T0 >> 31); |
750 | 79aceca5 | bellard | } else {
|
751 | 79aceca5 | bellard | xer_ov = 0;
|
752 | 79aceca5 | bellard | Ts0 /= Ts1; |
753 | 79aceca5 | bellard | } |
754 | 79aceca5 | bellard | RETURN(); |
755 | 79aceca5 | bellard | } |
756 | 79aceca5 | bellard | |
757 | 79aceca5 | bellard | /* divide word unsigned */
|
758 | 79aceca5 | bellard | PPC_OP(divwu) |
759 | 79aceca5 | bellard | { |
760 | 79aceca5 | bellard | if (T1 == 0) { |
761 | 79aceca5 | bellard | T0 = 0;
|
762 | 79aceca5 | bellard | } else {
|
763 | 79aceca5 | bellard | T0 /= T1; |
764 | 79aceca5 | bellard | } |
765 | 79aceca5 | bellard | RETURN(); |
766 | 79aceca5 | bellard | } |
767 | 79aceca5 | bellard | |
768 | 79aceca5 | bellard | PPC_OP(divwuo) |
769 | 79aceca5 | bellard | { |
770 | 79aceca5 | bellard | if (T1 == 0) { |
771 | 79aceca5 | bellard | xer_so = 1;
|
772 | 79aceca5 | bellard | xer_ov = 1;
|
773 | 79aceca5 | bellard | T0 = 0;
|
774 | 79aceca5 | bellard | } else {
|
775 | 79aceca5 | bellard | xer_ov = 0;
|
776 | 79aceca5 | bellard | T0 /= T1; |
777 | 79aceca5 | bellard | } |
778 | 79aceca5 | bellard | RETURN(); |
779 | 79aceca5 | bellard | } |
780 | 79aceca5 | bellard | |
781 | 79aceca5 | bellard | /* multiply high word */
|
782 | 79aceca5 | bellard | PPC_OP(mulhw) |
783 | 79aceca5 | bellard | { |
784 | 79aceca5 | bellard | Ts0 = ((int64_t)Ts0 * (int64_t)Ts1) >> 32;
|
785 | 79aceca5 | bellard | RETURN(); |
786 | 79aceca5 | bellard | } |
787 | 79aceca5 | bellard | |
788 | 79aceca5 | bellard | /* multiply high word unsigned */
|
789 | 79aceca5 | bellard | PPC_OP(mulhwu) |
790 | 79aceca5 | bellard | { |
791 | 79aceca5 | bellard | T0 = ((uint64_t)T0 * (uint64_t)T1) >> 32;
|
792 | 79aceca5 | bellard | RETURN(); |
793 | 79aceca5 | bellard | } |
794 | 79aceca5 | bellard | |
795 | 79aceca5 | bellard | /* multiply low immediate */
|
796 | 79aceca5 | bellard | PPC_OP(mulli) |
797 | 79aceca5 | bellard | { |
798 | 79aceca5 | bellard | Ts0 *= SPARAM(1);
|
799 | 79aceca5 | bellard | RETURN(); |
800 | 79aceca5 | bellard | } |
801 | 79aceca5 | bellard | |
802 | 79aceca5 | bellard | /* multiply low word */
|
803 | 79aceca5 | bellard | PPC_OP(mullw) |
804 | 79aceca5 | bellard | { |
805 | 79aceca5 | bellard | T0 *= T1; |
806 | 79aceca5 | bellard | RETURN(); |
807 | 79aceca5 | bellard | } |
808 | 79aceca5 | bellard | |
809 | 79aceca5 | bellard | PPC_OP(mullwo) |
810 | 79aceca5 | bellard | { |
811 | 79aceca5 | bellard | int64_t res = (int64_t)Ts0 * (int64_t)Ts1; |
812 | 79aceca5 | bellard | |
813 | 79aceca5 | bellard | if ((int32_t)res != res) {
|
814 | 79aceca5 | bellard | xer_ov = 1;
|
815 | 79aceca5 | bellard | xer_so = 1;
|
816 | 79aceca5 | bellard | } else {
|
817 | 79aceca5 | bellard | xer_ov = 0;
|
818 | 79aceca5 | bellard | } |
819 | 79aceca5 | bellard | Ts0 = res; |
820 | 79aceca5 | bellard | RETURN(); |
821 | 79aceca5 | bellard | } |
822 | 79aceca5 | bellard | |
823 | 79aceca5 | bellard | /* negate */
|
824 | 79aceca5 | bellard | PPC_OP(neg) |
825 | 79aceca5 | bellard | { |
826 | 79aceca5 | bellard | if (T0 != 0x80000000) { |
827 | 79aceca5 | bellard | Ts0 = -Ts0; |
828 | 79aceca5 | bellard | } |
829 | 79aceca5 | bellard | RETURN(); |
830 | 79aceca5 | bellard | } |
831 | 79aceca5 | bellard | |
832 | 79aceca5 | bellard | PPC_OP(nego) |
833 | 79aceca5 | bellard | { |
834 | 79aceca5 | bellard | if (T0 == 0x80000000) { |
835 | 79aceca5 | bellard | xer_ov = 1;
|
836 | 79aceca5 | bellard | xer_so = 1;
|
837 | 79aceca5 | bellard | } else {
|
838 | 79aceca5 | bellard | xer_ov = 0;
|
839 | 79aceca5 | bellard | Ts0 = -Ts0; |
840 | 79aceca5 | bellard | } |
841 | 79aceca5 | bellard | RETURN(); |
842 | 79aceca5 | bellard | } |
843 | 79aceca5 | bellard | |
844 | 79aceca5 | bellard | /* substract from */
|
845 | 79aceca5 | bellard | PPC_OP(subf) |
846 | 79aceca5 | bellard | { |
847 | 79aceca5 | bellard | T0 = T1 - T0; |
848 | 79aceca5 | bellard | RETURN(); |
849 | 79aceca5 | bellard | } |
850 | 79aceca5 | bellard | |
851 | 79aceca5 | bellard | PPC_OP(subfo) |
852 | 79aceca5 | bellard | { |
853 | 79aceca5 | bellard | T2 = T0; |
854 | 79aceca5 | bellard | T0 = T1 - T0; |
855 | 79aceca5 | bellard | if (((~T2) ^ T1 ^ (-1)) & ((~T2) ^ T0) & (1 << 31)) { |
856 | 79aceca5 | bellard | xer_so = 1;
|
857 | 79aceca5 | bellard | xer_ov = 1;
|
858 | 79aceca5 | bellard | } else {
|
859 | 79aceca5 | bellard | xer_ov = 0;
|
860 | 79aceca5 | bellard | } |
861 | 79aceca5 | bellard | RETURN(); |
862 | 79aceca5 | bellard | } |
863 | 79aceca5 | bellard | |
864 | 79aceca5 | bellard | /* substract from carrying */
|
865 | 79aceca5 | bellard | PPC_OP(subfc) |
866 | 79aceca5 | bellard | { |
867 | 79aceca5 | bellard | T0 = T1 - T0; |
868 | 79aceca5 | bellard | if (T0 <= T1) {
|
869 | 79aceca5 | bellard | xer_ca = 1;
|
870 | 79aceca5 | bellard | } else {
|
871 | 79aceca5 | bellard | xer_ca = 0;
|
872 | 79aceca5 | bellard | } |
873 | 79aceca5 | bellard | RETURN(); |
874 | 79aceca5 | bellard | } |
875 | 79aceca5 | bellard | |
876 | 79aceca5 | bellard | PPC_OP(subfco) |
877 | 79aceca5 | bellard | { |
878 | 79aceca5 | bellard | T2 = T0; |
879 | 79aceca5 | bellard | T0 = T1 - T0; |
880 | 79aceca5 | bellard | if (T0 <= T1) {
|
881 | 79aceca5 | bellard | xer_ca = 1;
|
882 | 79aceca5 | bellard | } else {
|
883 | 79aceca5 | bellard | xer_ca = 0;
|
884 | 79aceca5 | bellard | } |
885 | 79aceca5 | bellard | if (((~T2) ^ T1 ^ (-1)) & ((~T2) ^ T0) & (1 << 31)) { |
886 | 79aceca5 | bellard | xer_so = 1;
|
887 | 79aceca5 | bellard | xer_ov = 1;
|
888 | 79aceca5 | bellard | } else {
|
889 | 79aceca5 | bellard | xer_ov = 0;
|
890 | 79aceca5 | bellard | } |
891 | 79aceca5 | bellard | RETURN(); |
892 | 79aceca5 | bellard | } |
893 | 79aceca5 | bellard | |
894 | 79aceca5 | bellard | /* substract from extended */
|
895 | 79aceca5 | bellard | /* candidate for helper (too long) */
|
896 | 79aceca5 | bellard | PPC_OP(subfe) |
897 | 79aceca5 | bellard | { |
898 | 79aceca5 | bellard | T0 = T1 + ~T0 + xer_ca; |
899 | 79aceca5 | bellard | if (T0 < T1 || (xer_ca == 1 && T0 == T1)) { |
900 | 79aceca5 | bellard | xer_ca = 1;
|
901 | 79aceca5 | bellard | } else {
|
902 | 79aceca5 | bellard | xer_ca = 0;
|
903 | 79aceca5 | bellard | } |
904 | 79aceca5 | bellard | RETURN(); |
905 | 79aceca5 | bellard | } |
906 | 79aceca5 | bellard | |
907 | 79aceca5 | bellard | PPC_OP(subfeo) |
908 | 79aceca5 | bellard | { |
909 | 79aceca5 | bellard | T2 = T0; |
910 | 79aceca5 | bellard | T0 = T1 + ~T0 + xer_ca; |
911 | 79aceca5 | bellard | if ((~T2 ^ T1 ^ (-1)) & (~T2 ^ T0) & (1 << 31)) { |
912 | 79aceca5 | bellard | xer_so = 1;
|
913 | 79aceca5 | bellard | xer_ov = 1;
|
914 | 79aceca5 | bellard | } else {
|
915 | 79aceca5 | bellard | xer_ov = 0;
|
916 | 79aceca5 | bellard | } |
917 | 79aceca5 | bellard | if (T0 < T1 || (xer_ca == 1 && T0 == T1)) { |
918 | 79aceca5 | bellard | xer_ca = 1;
|
919 | 79aceca5 | bellard | } else {
|
920 | 79aceca5 | bellard | xer_ca = 0;
|
921 | 79aceca5 | bellard | } |
922 | 79aceca5 | bellard | RETURN(); |
923 | 79aceca5 | bellard | } |
924 | 79aceca5 | bellard | |
925 | 79aceca5 | bellard | /* substract from immediate carrying */
|
926 | 79aceca5 | bellard | PPC_OP(subfic) |
927 | 79aceca5 | bellard | { |
928 | 79aceca5 | bellard | T0 = PARAM(1) + ~T0 + 1; |
929 | 79aceca5 | bellard | if (T0 <= PARAM(1)) { |
930 | 79aceca5 | bellard | xer_ca = 1;
|
931 | 79aceca5 | bellard | } else {
|
932 | 79aceca5 | bellard | xer_ca = 0;
|
933 | 79aceca5 | bellard | } |
934 | 79aceca5 | bellard | RETURN(); |
935 | 79aceca5 | bellard | } |
936 | 79aceca5 | bellard | |
937 | 79aceca5 | bellard | /* substract from minus one extended */
|
938 | 79aceca5 | bellard | PPC_OP(subfme) |
939 | 79aceca5 | bellard | { |
940 | 79aceca5 | bellard | T0 = ~T0 + xer_ca - 1;
|
941 | 79aceca5 | bellard | |
942 | 79aceca5 | bellard | if (T0 != -1) |
943 | 79aceca5 | bellard | xer_ca = 1;
|
944 | 79aceca5 | bellard | RETURN(); |
945 | 79aceca5 | bellard | } |
946 | 79aceca5 | bellard | |
947 | 79aceca5 | bellard | PPC_OP(subfmeo) |
948 | 79aceca5 | bellard | { |
949 | 79aceca5 | bellard | T1 = T0; |
950 | 79aceca5 | bellard | T0 = ~T0 + xer_ca - 1;
|
951 | 79aceca5 | bellard | if (~T1 & (~T1 ^ T0) & (1 << 31)) { |
952 | 79aceca5 | bellard | xer_so = 1;
|
953 | 79aceca5 | bellard | xer_ov = 1;
|
954 | 79aceca5 | bellard | } else {
|
955 | 79aceca5 | bellard | xer_ov = 0;
|
956 | 79aceca5 | bellard | } |
957 | 79aceca5 | bellard | if (T1 != -1) |
958 | 79aceca5 | bellard | xer_ca = 1;
|
959 | 79aceca5 | bellard | RETURN(); |
960 | 79aceca5 | bellard | } |
961 | 79aceca5 | bellard | |
962 | 79aceca5 | bellard | /* substract from zero extended */
|
963 | 79aceca5 | bellard | PPC_OP(subfze) |
964 | 79aceca5 | bellard | { |
965 | 79aceca5 | bellard | T1 = ~T0; |
966 | 79aceca5 | bellard | T0 = T1 + xer_ca; |
967 | 79aceca5 | bellard | if (T0 < T1) {
|
968 | 79aceca5 | bellard | xer_ca = 1;
|
969 | 79aceca5 | bellard | } else {
|
970 | 79aceca5 | bellard | xer_ca = 0;
|
971 | 79aceca5 | bellard | } |
972 | 79aceca5 | bellard | RETURN(); |
973 | 79aceca5 | bellard | } |
974 | 79aceca5 | bellard | |
975 | 79aceca5 | bellard | PPC_OP(subfzeo) |
976 | 79aceca5 | bellard | { |
977 | 79aceca5 | bellard | T1 = T0; |
978 | 79aceca5 | bellard | T0 = ~T0 + xer_ca; |
979 | 79aceca5 | bellard | if ((~T1 ^ (-1)) & ((~T1) ^ T0) & (1 << 31)) { |
980 | 79aceca5 | bellard | xer_ov = 1;
|
981 | 79aceca5 | bellard | xer_so = 1;
|
982 | 79aceca5 | bellard | } else {
|
983 | 79aceca5 | bellard | xer_ov = 0;
|
984 | 79aceca5 | bellard | } |
985 | 79aceca5 | bellard | if (T0 < ~T1) {
|
986 | 79aceca5 | bellard | xer_ca = 1;
|
987 | 79aceca5 | bellard | } else {
|
988 | 79aceca5 | bellard | xer_ca = 0;
|
989 | 79aceca5 | bellard | } |
990 | 79aceca5 | bellard | RETURN(); |
991 | 79aceca5 | bellard | } |
992 | 79aceca5 | bellard | |
993 | 79aceca5 | bellard | /*** Integer comparison ***/
|
994 | 79aceca5 | bellard | /* compare */
|
995 | 79aceca5 | bellard | PPC_OP(cmp) |
996 | 79aceca5 | bellard | { |
997 | 79aceca5 | bellard | if (Ts0 < Ts1) {
|
998 | 79aceca5 | bellard | T0 = 0x08;
|
999 | 79aceca5 | bellard | } else if (Ts0 > Ts1) { |
1000 | 79aceca5 | bellard | T0 = 0x04;
|
1001 | 79aceca5 | bellard | } else {
|
1002 | 79aceca5 | bellard | T0 = 0x02;
|
1003 | 79aceca5 | bellard | } |
1004 | 79aceca5 | bellard | RETURN(); |
1005 | 79aceca5 | bellard | } |
1006 | 79aceca5 | bellard | |
1007 | 79aceca5 | bellard | /* compare immediate */
|
1008 | 79aceca5 | bellard | PPC_OP(cmpi) |
1009 | 79aceca5 | bellard | { |
1010 | 79aceca5 | bellard | if (Ts0 < SPARAM(1)) { |
1011 | 79aceca5 | bellard | T0 = 0x08;
|
1012 | 79aceca5 | bellard | } else if (Ts0 > SPARAM(1)) { |
1013 | 79aceca5 | bellard | T0 = 0x04;
|
1014 | 79aceca5 | bellard | } else {
|
1015 | 79aceca5 | bellard | T0 = 0x02;
|
1016 | 79aceca5 | bellard | } |
1017 | 79aceca5 | bellard | RETURN(); |
1018 | 79aceca5 | bellard | } |
1019 | 79aceca5 | bellard | |
1020 | 79aceca5 | bellard | /* compare logical */
|
1021 | 79aceca5 | bellard | PPC_OP(cmpl) |
1022 | 79aceca5 | bellard | { |
1023 | 79aceca5 | bellard | if (T0 < T1) {
|
1024 | 79aceca5 | bellard | T0 = 0x08;
|
1025 | 79aceca5 | bellard | } else if (T0 > T1) { |
1026 | 79aceca5 | bellard | T0 = 0x04;
|
1027 | 79aceca5 | bellard | } else {
|
1028 | 79aceca5 | bellard | T0 = 0x02;
|
1029 | 79aceca5 | bellard | } |
1030 | 79aceca5 | bellard | RETURN(); |
1031 | 79aceca5 | bellard | } |
1032 | 79aceca5 | bellard | |
1033 | 79aceca5 | bellard | /* compare logical immediate */
|
1034 | 79aceca5 | bellard | PPC_OP(cmpli) |
1035 | 79aceca5 | bellard | { |
1036 | 79aceca5 | bellard | if (T0 < PARAM(1)) { |
1037 | 79aceca5 | bellard | T0 = 0x08;
|
1038 | 79aceca5 | bellard | } else if (T0 > PARAM(1)) { |
1039 | 79aceca5 | bellard | T0 = 0x04;
|
1040 | 79aceca5 | bellard | } else {
|
1041 | 79aceca5 | bellard | T0 = 0x02;
|
1042 | 79aceca5 | bellard | } |
1043 | 79aceca5 | bellard | RETURN(); |
1044 | 79aceca5 | bellard | } |
1045 | 79aceca5 | bellard | |
1046 | 79aceca5 | bellard | /*** Integer logical ***/
|
1047 | 79aceca5 | bellard | /* and */
|
1048 | 79aceca5 | bellard | PPC_OP(and) |
1049 | 79aceca5 | bellard | { |
1050 | 79aceca5 | bellard | T0 &= T1; |
1051 | 79aceca5 | bellard | RETURN(); |
1052 | 79aceca5 | bellard | } |
1053 | 79aceca5 | bellard | |
1054 | 79aceca5 | bellard | /* andc */
|
1055 | 79aceca5 | bellard | PPC_OP(andc) |
1056 | 79aceca5 | bellard | { |
1057 | 79aceca5 | bellard | T0 &= ~T1; |
1058 | 79aceca5 | bellard | RETURN(); |
1059 | 79aceca5 | bellard | } |
1060 | 79aceca5 | bellard | |
1061 | 79aceca5 | bellard | /* andi. */
|
1062 | 79aceca5 | bellard | PPC_OP(andi_) |
1063 | 79aceca5 | bellard | { |
1064 | 79aceca5 | bellard | T0 &= PARAM(1);
|
1065 | 79aceca5 | bellard | RETURN(); |
1066 | 79aceca5 | bellard | } |
1067 | 79aceca5 | bellard | |
1068 | 79aceca5 | bellard | /* count leading zero */
|
1069 | 79aceca5 | bellard | PPC_OP(cntlzw) |
1070 | 79aceca5 | bellard | { |
1071 | 79aceca5 | bellard | T1 = T0; |
1072 | 79aceca5 | bellard | for (T0 = 32; T1 > 0; T0--) |
1073 | 79aceca5 | bellard | T1 = T1 >> 1;
|
1074 | 79aceca5 | bellard | RETURN(); |
1075 | 79aceca5 | bellard | } |
1076 | 79aceca5 | bellard | |
1077 | 79aceca5 | bellard | /* eqv */
|
1078 | 79aceca5 | bellard | PPC_OP(eqv) |
1079 | 79aceca5 | bellard | { |
1080 | 79aceca5 | bellard | T0 = ~(T0 ^ T1); |
1081 | 79aceca5 | bellard | RETURN(); |
1082 | 79aceca5 | bellard | } |
1083 | 79aceca5 | bellard | |
1084 | 79aceca5 | bellard | /* extend sign byte */
|
1085 | 79aceca5 | bellard | PPC_OP(extsb) |
1086 | 79aceca5 | bellard | { |
1087 | 79aceca5 | bellard | Ts0 = s_ext8(Ts0); |
1088 | 79aceca5 | bellard | RETURN(); |
1089 | 79aceca5 | bellard | } |
1090 | 79aceca5 | bellard | |
1091 | 79aceca5 | bellard | /* extend sign half word */
|
1092 | 79aceca5 | bellard | PPC_OP(extsh) |
1093 | 79aceca5 | bellard | { |
1094 | 79aceca5 | bellard | Ts0 = s_ext16(Ts0); |
1095 | 79aceca5 | bellard | RETURN(); |
1096 | 79aceca5 | bellard | } |
1097 | 79aceca5 | bellard | |
1098 | 79aceca5 | bellard | /* nand */
|
1099 | 79aceca5 | bellard | PPC_OP(nand) |
1100 | 79aceca5 | bellard | { |
1101 | 79aceca5 | bellard | T0 = ~(T0 & T1); |
1102 | 79aceca5 | bellard | RETURN(); |
1103 | 79aceca5 | bellard | } |
1104 | 79aceca5 | bellard | |
1105 | 79aceca5 | bellard | /* nor */
|
1106 | 79aceca5 | bellard | PPC_OP(nor) |
1107 | 79aceca5 | bellard | { |
1108 | 79aceca5 | bellard | T0 = ~(T0 | T1); |
1109 | 79aceca5 | bellard | RETURN(); |
1110 | 79aceca5 | bellard | } |
1111 | 79aceca5 | bellard | |
1112 | 79aceca5 | bellard | /* or */
|
1113 | 79aceca5 | bellard | PPC_OP(or) |
1114 | 79aceca5 | bellard | { |
1115 | 79aceca5 | bellard | T0 |= T1; |
1116 | 79aceca5 | bellard | RETURN(); |
1117 | 79aceca5 | bellard | } |
1118 | 79aceca5 | bellard | |
1119 | 79aceca5 | bellard | /* orc */
|
1120 | 79aceca5 | bellard | PPC_OP(orc) |
1121 | 79aceca5 | bellard | { |
1122 | 79aceca5 | bellard | T0 |= ~T1; |
1123 | 79aceca5 | bellard | RETURN(); |
1124 | 79aceca5 | bellard | } |
1125 | 79aceca5 | bellard | |
1126 | 79aceca5 | bellard | /* ori */
|
1127 | 79aceca5 | bellard | PPC_OP(ori) |
1128 | 79aceca5 | bellard | { |
1129 | 79aceca5 | bellard | T0 |= PARAM(1);
|
1130 | 79aceca5 | bellard | RETURN(); |
1131 | 79aceca5 | bellard | } |
1132 | 79aceca5 | bellard | |
1133 | 79aceca5 | bellard | /* xor */
|
1134 | 79aceca5 | bellard | PPC_OP(xor) |
1135 | 79aceca5 | bellard | { |
1136 | 79aceca5 | bellard | T0 ^= T1; |
1137 | 79aceca5 | bellard | RETURN(); |
1138 | 79aceca5 | bellard | } |
1139 | 79aceca5 | bellard | |
1140 | 79aceca5 | bellard | /* xori */
|
1141 | 79aceca5 | bellard | PPC_OP(xori) |
1142 | 79aceca5 | bellard | { |
1143 | 79aceca5 | bellard | T0 ^= PARAM(1);
|
1144 | 79aceca5 | bellard | RETURN(); |
1145 | 79aceca5 | bellard | } |
1146 | 79aceca5 | bellard | |
1147 | 79aceca5 | bellard | /*** Integer rotate ***/
|
1148 | 79aceca5 | bellard | /* rotate left word immediate then mask insert */
|
1149 | 79aceca5 | bellard | PPC_OP(rlwimi) |
1150 | 79aceca5 | bellard | { |
1151 | fb0eaffc | bellard | T0 = (rotl(T0, PARAM(1)) & PARAM(2)) | (T1 & PARAM(3)); |
1152 | 79aceca5 | bellard | RETURN(); |
1153 | 79aceca5 | bellard | } |
1154 | 79aceca5 | bellard | |
1155 | 79aceca5 | bellard | /* rotate left immediate then and with mask insert */
|
1156 | 79aceca5 | bellard | PPC_OP(rotlwi) |
1157 | 79aceca5 | bellard | { |
1158 | 79aceca5 | bellard | T0 = rotl(T0, PARAM(1));
|
1159 | 79aceca5 | bellard | RETURN(); |
1160 | 79aceca5 | bellard | } |
1161 | 79aceca5 | bellard | |
1162 | 79aceca5 | bellard | PPC_OP(slwi) |
1163 | 79aceca5 | bellard | { |
1164 | 79aceca5 | bellard | T0 = T0 << PARAM(1);
|
1165 | 79aceca5 | bellard | RETURN(); |
1166 | 79aceca5 | bellard | } |
1167 | 79aceca5 | bellard | |
1168 | 79aceca5 | bellard | PPC_OP(srwi) |
1169 | 79aceca5 | bellard | { |
1170 | 79aceca5 | bellard | T0 = T0 >> PARAM(1);
|
1171 | 79aceca5 | bellard | RETURN(); |
1172 | 79aceca5 | bellard | } |
1173 | 79aceca5 | bellard | |
1174 | 79aceca5 | bellard | /* rotate left word then and with mask insert */
|
1175 | 79aceca5 | bellard | PPC_OP(rlwinm) |
1176 | 79aceca5 | bellard | { |
1177 | 79aceca5 | bellard | T0 = rotl(T0, PARAM(1)) & PARAM(2); |
1178 | 79aceca5 | bellard | RETURN(); |
1179 | 79aceca5 | bellard | } |
1180 | 79aceca5 | bellard | |
1181 | 79aceca5 | bellard | PPC_OP(rotl) |
1182 | 79aceca5 | bellard | { |
1183 | 79aceca5 | bellard | T0 = rotl(T0, T1); |
1184 | 79aceca5 | bellard | RETURN(); |
1185 | 79aceca5 | bellard | } |
1186 | 79aceca5 | bellard | |
1187 | 79aceca5 | bellard | PPC_OP(rlwnm) |
1188 | 79aceca5 | bellard | { |
1189 | 79aceca5 | bellard | T0 = rotl(T0, T1) & PARAM(1);
|
1190 | 79aceca5 | bellard | RETURN(); |
1191 | 79aceca5 | bellard | } |
1192 | 79aceca5 | bellard | |
1193 | 79aceca5 | bellard | /*** Integer shift ***/
|
1194 | 79aceca5 | bellard | /* shift left word */
|
1195 | 79aceca5 | bellard | PPC_OP(slw) |
1196 | 79aceca5 | bellard | { |
1197 | 79aceca5 | bellard | if (T1 & 0x20) { |
1198 | 79aceca5 | bellard | T0 = 0;
|
1199 | 79aceca5 | bellard | } else {
|
1200 | 79aceca5 | bellard | T0 = T0 << T1; |
1201 | 79aceca5 | bellard | } |
1202 | 79aceca5 | bellard | RETURN(); |
1203 | 79aceca5 | bellard | } |
1204 | 79aceca5 | bellard | |
1205 | 79aceca5 | bellard | /* shift right algebraic word */
|
1206 | 79aceca5 | bellard | PPC_OP(sraw) |
1207 | 79aceca5 | bellard | { |
1208 | 9a64fbe4 | bellard | do_sraw(); |
1209 | 79aceca5 | bellard | RETURN(); |
1210 | 79aceca5 | bellard | } |
1211 | 79aceca5 | bellard | |
1212 | 79aceca5 | bellard | /* shift right algebraic word immediate */
|
1213 | 79aceca5 | bellard | PPC_OP(srawi) |
1214 | 79aceca5 | bellard | { |
1215 | 79aceca5 | bellard | Ts1 = Ts0; |
1216 | 79aceca5 | bellard | Ts0 = Ts0 >> PARAM(1);
|
1217 | 79aceca5 | bellard | if (Ts1 < 0 && (Ts1 & PARAM(2)) != 0) { |
1218 | 79aceca5 | bellard | xer_ca = 1;
|
1219 | 79aceca5 | bellard | } else {
|
1220 | 79aceca5 | bellard | xer_ca = 0;
|
1221 | 79aceca5 | bellard | } |
1222 | 79aceca5 | bellard | RETURN(); |
1223 | 79aceca5 | bellard | } |
1224 | 79aceca5 | bellard | |
1225 | 79aceca5 | bellard | /* shift right word */
|
1226 | 79aceca5 | bellard | PPC_OP(srw) |
1227 | 79aceca5 | bellard | { |
1228 | 79aceca5 | bellard | if (T1 & 0x20) { |
1229 | 79aceca5 | bellard | T0 = 0;
|
1230 | 79aceca5 | bellard | } else {
|
1231 | 79aceca5 | bellard | T0 = T0 >> T1; |
1232 | 79aceca5 | bellard | } |
1233 | 79aceca5 | bellard | RETURN(); |
1234 | 79aceca5 | bellard | } |
1235 | 79aceca5 | bellard | |
1236 | 79aceca5 | bellard | /*** Floating-Point arithmetic ***/
|
1237 | 9a64fbe4 | bellard | /* fadd - fadd. */
|
1238 | 9a64fbe4 | bellard | PPC_OP(fadd) |
1239 | 79aceca5 | bellard | { |
1240 | 9a64fbe4 | bellard | FT0 += FT1; |
1241 | 79aceca5 | bellard | RETURN(); |
1242 | 79aceca5 | bellard | } |
1243 | 79aceca5 | bellard | |
1244 | 9a64fbe4 | bellard | /* fadds - fadds. */
|
1245 | 9a64fbe4 | bellard | PPC_OP(fadds) |
1246 | 79aceca5 | bellard | { |
1247 | 9a64fbe4 | bellard | FTS0 += FTS1; |
1248 | 79aceca5 | bellard | RETURN(); |
1249 | 79aceca5 | bellard | } |
1250 | 79aceca5 | bellard | |
1251 | 9a64fbe4 | bellard | /* fsub - fsub. */
|
1252 | 9a64fbe4 | bellard | PPC_OP(fsub) |
1253 | 79aceca5 | bellard | { |
1254 | 9a64fbe4 | bellard | FT0 -= FT1; |
1255 | 79aceca5 | bellard | RETURN(); |
1256 | 79aceca5 | bellard | } |
1257 | 79aceca5 | bellard | |
1258 | 9a64fbe4 | bellard | /* fsubs - fsubs. */
|
1259 | 9a64fbe4 | bellard | PPC_OP(fsubs) |
1260 | 79aceca5 | bellard | { |
1261 | 9a64fbe4 | bellard | FTS0 -= FTS1; |
1262 | 79aceca5 | bellard | RETURN(); |
1263 | 79aceca5 | bellard | } |
1264 | 79aceca5 | bellard | |
1265 | 9a64fbe4 | bellard | /* fmul - fmul. */
|
1266 | 9a64fbe4 | bellard | PPC_OP(fmul) |
1267 | 79aceca5 | bellard | { |
1268 | 9a64fbe4 | bellard | FT0 *= FT1; |
1269 | 79aceca5 | bellard | RETURN(); |
1270 | 79aceca5 | bellard | } |
1271 | 79aceca5 | bellard | |
1272 | 9a64fbe4 | bellard | /* fmuls - fmuls. */
|
1273 | 9a64fbe4 | bellard | PPC_OP(fmuls) |
1274 | 79aceca5 | bellard | { |
1275 | 9a64fbe4 | bellard | FTS0 *= FTS1; |
1276 | 79aceca5 | bellard | RETURN(); |
1277 | 79aceca5 | bellard | } |
1278 | 79aceca5 | bellard | |
1279 | 9a64fbe4 | bellard | /* fdiv - fdiv. */
|
1280 | 9a64fbe4 | bellard | PPC_OP(fdiv) |
1281 | 79aceca5 | bellard | { |
1282 | 9a64fbe4 | bellard | FT0 /= FT1; |
1283 | 79aceca5 | bellard | RETURN(); |
1284 | 79aceca5 | bellard | } |
1285 | 79aceca5 | bellard | |
1286 | 9a64fbe4 | bellard | /* fdivs - fdivs. */
|
1287 | 9a64fbe4 | bellard | PPC_OP(fdivs) |
1288 | 79aceca5 | bellard | { |
1289 | 9a64fbe4 | bellard | FTS0 /= FTS1; |
1290 | 79aceca5 | bellard | RETURN(); |
1291 | 79aceca5 | bellard | } |
1292 | 28b6751f | bellard | |
1293 | 9a64fbe4 | bellard | /* fsqrt - fsqrt. */
|
1294 | 9a64fbe4 | bellard | PPC_OP(fsqrt) |
1295 | 28b6751f | bellard | { |
1296 | 9a64fbe4 | bellard | do_fsqrt(); |
1297 | 9a64fbe4 | bellard | RETURN(); |
1298 | 28b6751f | bellard | } |
1299 | 28b6751f | bellard | |
1300 | 9a64fbe4 | bellard | /* fsqrts - fsqrts. */
|
1301 | 9a64fbe4 | bellard | PPC_OP(fsqrts) |
1302 | 28b6751f | bellard | { |
1303 | 9a64fbe4 | bellard | do_fsqrts(); |
1304 | 9a64fbe4 | bellard | RETURN(); |
1305 | 28b6751f | bellard | } |
1306 | 28b6751f | bellard | |
1307 | 9a64fbe4 | bellard | /* fres - fres. */
|
1308 | 9a64fbe4 | bellard | PPC_OP(fres) |
1309 | 28b6751f | bellard | { |
1310 | 9a64fbe4 | bellard | do_fres(); |
1311 | 9a64fbe4 | bellard | RETURN(); |
1312 | 28b6751f | bellard | } |
1313 | 28b6751f | bellard | |
1314 | 9a64fbe4 | bellard | /* frsqrte - frsqrte. */
|
1315 | 9a64fbe4 | bellard | PPC_OP(frsqrte) |
1316 | 28b6751f | bellard | { |
1317 | 9a64fbe4 | bellard | do_fsqrte(); |
1318 | 9a64fbe4 | bellard | RETURN(); |
1319 | 28b6751f | bellard | } |
1320 | 28b6751f | bellard | |
1321 | 9a64fbe4 | bellard | /* fsel - fsel. */
|
1322 | 9a64fbe4 | bellard | PPC_OP(fsel) |
1323 | 28b6751f | bellard | { |
1324 | 9a64fbe4 | bellard | do_fsel(); |
1325 | 9a64fbe4 | bellard | RETURN(); |
1326 | 28b6751f | bellard | } |
1327 | 28b6751f | bellard | |
1328 | 9a64fbe4 | bellard | /*** Floating-Point multiply-and-add ***/
|
1329 | 9a64fbe4 | bellard | /* fmadd - fmadd. */
|
1330 | 9a64fbe4 | bellard | PPC_OP(fmadd) |
1331 | 28b6751f | bellard | { |
1332 | 9a64fbe4 | bellard | FT0 = (FT0 * FT1) + FT2; |
1333 | 9a64fbe4 | bellard | RETURN(); |
1334 | 28b6751f | bellard | } |
1335 | 28b6751f | bellard | |
1336 | 9a64fbe4 | bellard | /* fmadds - fmadds. */
|
1337 | 9a64fbe4 | bellard | PPC_OP(fmadds) |
1338 | 28b6751f | bellard | { |
1339 | 9a64fbe4 | bellard | FTS0 = (FTS0 * FTS1) + FTS2; |
1340 | 9a64fbe4 | bellard | RETURN(); |
1341 | 28b6751f | bellard | } |
1342 | 28b6751f | bellard | |
1343 | 9a64fbe4 | bellard | /* fmsub - fmsub. */
|
1344 | 9a64fbe4 | bellard | PPC_OP(fmsub) |
1345 | 28b6751f | bellard | { |
1346 | 9a64fbe4 | bellard | FT0 = (FT0 * FT1) - FT2; |
1347 | 9a64fbe4 | bellard | RETURN(); |
1348 | 28b6751f | bellard | } |
1349 | 28b6751f | bellard | |
1350 | 9a64fbe4 | bellard | /* fmsubs - fmsubs. */
|
1351 | 9a64fbe4 | bellard | PPC_OP(fmsubs) |
1352 | 28b6751f | bellard | { |
1353 | 9a64fbe4 | bellard | FTS0 = (FTS0 * FTS1) - FTS2; |
1354 | 9a64fbe4 | bellard | RETURN(); |
1355 | 28b6751f | bellard | } |
1356 | 28b6751f | bellard | |
1357 | 9a64fbe4 | bellard | /* fnmadd - fnmadd. - fnmadds - fnmadds. */
|
1358 | 9a64fbe4 | bellard | PPC_OP(fnmadd) |
1359 | 28b6751f | bellard | { |
1360 | 9a64fbe4 | bellard | FT0 = -((FT0 * FT1) + FT2); |
1361 | 9a64fbe4 | bellard | RETURN(); |
1362 | 28b6751f | bellard | } |
1363 | 28b6751f | bellard | |
1364 | 9a64fbe4 | bellard | /* fnmadds - fnmadds. */
|
1365 | 9a64fbe4 | bellard | PPC_OP(fnmadds) |
1366 | 28b6751f | bellard | { |
1367 | 9a64fbe4 | bellard | FTS0 = -((FTS0 * FTS1) + FTS2); |
1368 | 9a64fbe4 | bellard | RETURN(); |
1369 | 28b6751f | bellard | } |
1370 | 28b6751f | bellard | |
1371 | 9a64fbe4 | bellard | /* fnmsub - fnmsub. */
|
1372 | 9a64fbe4 | bellard | PPC_OP(fnmsub) |
1373 | 28b6751f | bellard | { |
1374 | 9a64fbe4 | bellard | FT0 = -((FT0 * FT1) - FT2); |
1375 | 9a64fbe4 | bellard | RETURN(); |
1376 | 28b6751f | bellard | } |
1377 | 28b6751f | bellard | |
1378 | 9a64fbe4 | bellard | /* fnmsubs - fnmsubs. */
|
1379 | 9a64fbe4 | bellard | PPC_OP(fnmsubs) |
1380 | 28b6751f | bellard | { |
1381 | 9a64fbe4 | bellard | FTS0 = -((FTS0 * FTS1) - FTS2); |
1382 | 9a64fbe4 | bellard | RETURN(); |
1383 | 28b6751f | bellard | } |
1384 | 28b6751f | bellard | |
1385 | 9a64fbe4 | bellard | /*** Floating-Point round & convert ***/
|
1386 | 9a64fbe4 | bellard | /* frsp - frsp. */
|
1387 | 9a64fbe4 | bellard | PPC_OP(frsp) |
1388 | 28b6751f | bellard | { |
1389 | 9a64fbe4 | bellard | FT0 = FTS0; |
1390 | 9a64fbe4 | bellard | RETURN(); |
1391 | 28b6751f | bellard | } |
1392 | 28b6751f | bellard | |
1393 | 9a64fbe4 | bellard | /* fctiw - fctiw. */
|
1394 | 9a64fbe4 | bellard | PPC_OP(fctiw) |
1395 | 28b6751f | bellard | { |
1396 | 9a64fbe4 | bellard | do_fctiw(); |
1397 | 9a64fbe4 | bellard | RETURN(); |
1398 | 28b6751f | bellard | } |
1399 | 28b6751f | bellard | |
1400 | 9a64fbe4 | bellard | /* fctiwz - fctiwz. */
|
1401 | 9a64fbe4 | bellard | PPC_OP(fctiwz) |
1402 | 28b6751f | bellard | { |
1403 | 9a64fbe4 | bellard | do_fctiwz(); |
1404 | 9a64fbe4 | bellard | RETURN(); |
1405 | 28b6751f | bellard | } |
1406 | 28b6751f | bellard | |
1407 | 9a64fbe4 | bellard | |
1408 | 9a64fbe4 | bellard | /*** Floating-Point compare ***/
|
1409 | 9a64fbe4 | bellard | /* fcmpu */
|
1410 | 9a64fbe4 | bellard | PPC_OP(fcmpu) |
1411 | 28b6751f | bellard | { |
1412 | 9a64fbe4 | bellard | do_fcmpu(); |
1413 | 9a64fbe4 | bellard | RETURN(); |
1414 | 28b6751f | bellard | } |
1415 | 28b6751f | bellard | |
1416 | 9a64fbe4 | bellard | /* fcmpo */
|
1417 | 9a64fbe4 | bellard | PPC_OP(fcmpo) |
1418 | 28b6751f | bellard | { |
1419 | 9a64fbe4 | bellard | do_fcmpo(); |
1420 | 9a64fbe4 | bellard | RETURN(); |
1421 | fb0eaffc | bellard | } |
1422 | fb0eaffc | bellard | |
1423 | 9a64fbe4 | bellard | /*** Floating-point move ***/
|
1424 | 9a64fbe4 | bellard | /* fabs */
|
1425 | 9a64fbe4 | bellard | PPC_OP(fabs) |
1426 | fb0eaffc | bellard | { |
1427 | 9a64fbe4 | bellard | do_fabs(); |
1428 | fb0eaffc | bellard | RETURN(); |
1429 | fb0eaffc | bellard | } |
1430 | fb0eaffc | bellard | |
1431 | 9a64fbe4 | bellard | /* fnabs */
|
1432 | 9a64fbe4 | bellard | PPC_OP(fnabs) |
1433 | fb0eaffc | bellard | { |
1434 | 9a64fbe4 | bellard | do_fnabs(); |
1435 | fb0eaffc | bellard | RETURN(); |
1436 | fb0eaffc | bellard | } |
1437 | fb0eaffc | bellard | |
1438 | 9a64fbe4 | bellard | /* fneg */
|
1439 | 9a64fbe4 | bellard | PPC_OP(fneg) |
1440 | fb0eaffc | bellard | { |
1441 | 9a64fbe4 | bellard | FT0 = -FT0; |
1442 | fb0eaffc | bellard | RETURN(); |
1443 | fb0eaffc | bellard | } |
1444 | fb0eaffc | bellard | |
1445 | 9a64fbe4 | bellard | /* Load and store */
|
1446 | 9a64fbe4 | bellard | #if defined(CONFIG_USER_ONLY)
|
1447 | 9a64fbe4 | bellard | #define MEMSUFFIX _raw
|
1448 | 9a64fbe4 | bellard | #include "op_mem.h" |
1449 | 9a64fbe4 | bellard | #else
|
1450 | 9a64fbe4 | bellard | #define MEMSUFFIX _user
|
1451 | 9a64fbe4 | bellard | #include "op_mem.h" |
1452 | 9a64fbe4 | bellard | |
1453 | 9a64fbe4 | bellard | #define MEMSUFFIX _kernel
|
1454 | 9a64fbe4 | bellard | #include "op_mem.h" |
1455 | 9a64fbe4 | bellard | #endif
|
1456 | 9a64fbe4 | bellard | |
1457 | 9a64fbe4 | bellard | /* Return from interrupt */
|
1458 | 9a64fbe4 | bellard | PPC_OP(rfi) |
1459 | fb0eaffc | bellard | { |
1460 | 9a64fbe4 | bellard | T0 = regs->spr[SRR1] & ~0xFFFF0000;
|
1461 | 9a64fbe4 | bellard | do_store_msr(); |
1462 | 9a64fbe4 | bellard | do_tlbia(); |
1463 | 9a64fbe4 | bellard | dump_rfi(); |
1464 | 9a64fbe4 | bellard | regs->nip = regs->spr[SRR0] & ~0x00000003;
|
1465 | 9a64fbe4 | bellard | if (env->exceptions != 0) { |
1466 | 9a64fbe4 | bellard | do_check_exception_state(); |
1467 | fb0eaffc | bellard | } |
1468 | fb0eaffc | bellard | RETURN(); |
1469 | fb0eaffc | bellard | } |
1470 | fb0eaffc | bellard | |
1471 | 9a64fbe4 | bellard | /* Trap word */
|
1472 | 9a64fbe4 | bellard | PPC_OP(tw) |
1473 | fb0eaffc | bellard | { |
1474 | 9a64fbe4 | bellard | if ((Ts0 < Ts1 && (PARAM(1) & 0x10)) || |
1475 | 9a64fbe4 | bellard | (Ts0 > Ts1 && (PARAM(1) & 0x08)) || |
1476 | 9a64fbe4 | bellard | (Ts0 == Ts1 && (PARAM(1) & 0x04)) || |
1477 | 9a64fbe4 | bellard | (T0 < T1 && (PARAM(1) & 0x02)) || |
1478 | 9a64fbe4 | bellard | (T0 > T1 && (PARAM(1) & 0x01))) |
1479 | 9a64fbe4 | bellard | do_queue_exception_err(EXCP_PROGRAM, EXCP_TRAP); |
1480 | fb0eaffc | bellard | RETURN(); |
1481 | fb0eaffc | bellard | } |
1482 | fb0eaffc | bellard | |
1483 | 9a64fbe4 | bellard | PPC_OP(twi) |
1484 | fb0eaffc | bellard | { |
1485 | 9a64fbe4 | bellard | if ((Ts0 < SPARAM(1) && (PARAM(2) & 0x10)) || |
1486 | 9a64fbe4 | bellard | (Ts0 > SPARAM(1) && (PARAM(2) & 0x08)) || |
1487 | 9a64fbe4 | bellard | (Ts0 == SPARAM(1) && (PARAM(2) & 0x04)) || |
1488 | 9a64fbe4 | bellard | (T0 < (uint32_t)SPARAM(1) && (PARAM(2) & 0x02)) || |
1489 | 9a64fbe4 | bellard | (T0 > (uint32_t)SPARAM(1) && (PARAM(2) & 0x01))) |
1490 | 9a64fbe4 | bellard | do_queue_exception_err(EXCP_PROGRAM, EXCP_TRAP); |
1491 | fb0eaffc | bellard | RETURN(); |
1492 | fb0eaffc | bellard | } |
1493 | fb0eaffc | bellard | |
1494 | fb0eaffc | bellard | /* Instruction cache block invalidate */
|
1495 | 9a64fbe4 | bellard | PPC_OP(icbi) |
1496 | fb0eaffc | bellard | { |
1497 | fb0eaffc | bellard | do_icbi(); |
1498 | fb0eaffc | bellard | RETURN(); |
1499 | fb0eaffc | bellard | } |
1500 | fb0eaffc | bellard | |
1501 | 9a64fbe4 | bellard | /* tlbia */
|
1502 | 9a64fbe4 | bellard | PPC_OP(tlbia) |
1503 | fb0eaffc | bellard | { |
1504 | 9a64fbe4 | bellard | do_tlbia(); |
1505 | 9a64fbe4 | bellard | RETURN(); |
1506 | 9a64fbe4 | bellard | } |
1507 | 9a64fbe4 | bellard | |
1508 | 9a64fbe4 | bellard | /* tlbie */
|
1509 | 9a64fbe4 | bellard | PPC_OP(tlbie) |
1510 | 9a64fbe4 | bellard | { |
1511 | 9a64fbe4 | bellard | do_tlbie(); |
1512 | fb0eaffc | bellard | RETURN(); |
1513 | 28b6751f | bellard | } |