Revision 980f8a0b

b/hw/etraxfs.c
72 72
    /* allocate RAM */
73 73
    phys_ram = qemu_ram_alloc(ram_size);
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    cpu_register_physical_memory(0x40000000, ram_size, phys_ram | IO_MEM_RAM);
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    /* Unached mapping.  */
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    cpu_register_physical_memory(0xc0000000, ram_size, phys_ram | IO_MEM_RAM);
77 75

  
78 76
    /* The ETRAX-FS has 128Kb on chip ram, the docs refer to it as the 
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       internal memory. Cached and uncached mappings.  */
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       internal memory.  */
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    phys_intmem = qemu_ram_alloc(INTMEM_SIZE);
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    cpu_register_physical_memory(0xb8000000, INTMEM_SIZE,
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                                 phys_intmem | IO_MEM_RAM);
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    cpu_register_physical_memory(0x38000000, INTMEM_SIZE,
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                                 phys_intmem | IO_MEM_RAM);
85 81

  
86 82

  
87 83
    phys_flash = qemu_ram_alloc(FLASH_SIZE);
88 84
    i = drive_get_index(IF_PFLASH, 0, 0);
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    pflash_cfi02_register(0x80000000, phys_flash,
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                          drives_table[i].bdrv, (64 * 1024),
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                          FLASH_SIZE >> 16,
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                          1, 2, 0x0000, 0x0000, 0x0000, 0x0000,
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                          0x555, 0x2aa);
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    pflash_cfi02_register(0x0, phys_flash,
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                          drives_table[i].bdrv, (64 * 1024),
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                          FLASH_SIZE >> 16,
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                          1, 2, 0x0000, 0x0000, 0x0000, 0x0000,
98 89
                          0x555, 0x2aa);
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    pic = etraxfs_pic_init(env, 0xb001c000);
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    etraxfs_dmac = etraxfs_dmac_init(env, 0xb0000000, 10);
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    pic = etraxfs_pic_init(env, 0x3001c000);
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    etraxfs_dmac = etraxfs_dmac_init(env, 0x30000000, 10);
101 92
    for (i = 0; i < 10; i++) {
102 93
        /* On ETRAX, odd numbered channels are inputs.  */
103 94
        etraxfs_dmac_connect(etraxfs_dmac, i, pic->irq + 7 + i, i & 1);
104 95
    }
105 96

  
106 97
    /* Add the two ethernet blocks.  */
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    eth[0] = etraxfs_eth_init(&nd_table[0], env, pic->irq + 25, 0xb0034000);
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    eth[0] = etraxfs_eth_init(&nd_table[0], env, pic->irq + 25, 0x30034000);
108 99
    if (nb_nics > 1)
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        eth[1] = etraxfs_eth_init(&nd_table[1], env, pic->irq + 26, 0xb0036000);
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        eth[1] = etraxfs_eth_init(&nd_table[1], env, pic->irq + 26, 0x30036000);
110 101

  
111 102
    /* The DMA Connector block is missing, hardwire things for now.  */
112 103
    etraxfs_dmac_connect_client(etraxfs_dmac, 0, eth[0]);
......
117 108
    }
118 109

  
119 110
    /* 2 timers.  */
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    etraxfs_timer_init(env, pic->irq + 0x1b, pic->nmi + 1, 0xb001e000);
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    etraxfs_timer_init(env, pic->irq + 0x1b, pic->nmi + 1, 0xb005e000);
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    etraxfs_timer_init(env, pic->irq + 0x1b, pic->nmi + 1, 0x3001e000);
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    etraxfs_timer_init(env, pic->irq + 0x1b, pic->nmi + 1, 0x3005e000);
122 113

  
123 114
    for (i = 0; i < 4; i++) {
124 115
        if (serial_hds[i]) {
125 116
            etraxfs_ser_init(env, pic->irq + 0x14 + i,
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                             serial_hds[i], 0xb0026000 + i * 0x2000);
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                             serial_hds[i], 0x30026000 + i * 0x2000);
127 118
        }
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    }
129 120

  
b/target-cris/helper.c
89 89
	}
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	else
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	{
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		phy = res.phy;
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		/*
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		 * Mask off the cache selection bit. The ETRAX busses do not
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		 * see the top bit.
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		 */
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		phy = res.phy & ~0x80000000;
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		prot = res.prot;
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		r = tlb_set_page(env, address, phy, prot, mmu_idx, is_softmmu);
95 99
	}

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