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/*
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* Virtual page mapping
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "config.h" |
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#ifdef _WIN32
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#include <windows.h> |
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#else
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#include <sys/types.h> |
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#include <sys/mman.h> |
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#endif
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#include "qemu-common.h" |
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#include "cpu.h" |
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#include "tcg.h" |
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#include "hw/hw.h" |
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#include "hw/qdev.h" |
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#include "qemu/osdep.h" |
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#include "sysemu/kvm.h" |
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#include "sysemu/sysemu.h" |
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#include "hw/xen/xen.h" |
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#include "qemu/timer.h" |
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#include "qemu/config-file.h" |
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#include "exec/memory.h" |
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#include "sysemu/dma.h" |
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#include "exec/address-spaces.h" |
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#if defined(CONFIG_USER_ONLY)
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#include <qemu.h> |
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#else /* !CONFIG_USER_ONLY */ |
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#include "sysemu/xen-mapcache.h" |
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#include "trace.h" |
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#endif
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#include "exec/cpu-all.h" |
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#include "exec/cputlb.h" |
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#include "translate-all.h" |
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|
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#include "exec/memory-internal.h" |
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#include "qemu/cache-utils.h" |
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|
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#include "qemu/range.h" |
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|
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//#define DEBUG_SUBPAGE
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#if !defined(CONFIG_USER_ONLY)
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static bool in_migration; |
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RAMList ram_list = { .blocks = QTAILQ_HEAD_INITIALIZER(ram_list.blocks) };
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static MemoryRegion *system_memory;
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static MemoryRegion *system_io;
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AddressSpace address_space_io; |
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AddressSpace address_space_memory; |
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|
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MemoryRegion io_mem_rom, io_mem_notdirty; |
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static MemoryRegion io_mem_unassigned;
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#endif
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struct CPUTailQ cpus = QTAILQ_HEAD_INITIALIZER(cpus);
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/* current CPU in the current thread. It is only valid inside
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cpu_exec() */
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DEFINE_TLS(CPUState *, current_cpu); |
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/* 0 = Do not count executed instructions.
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1 = Precise instruction counting.
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2 = Adaptive rate instruction counting. */
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int use_icount;
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#if !defined(CONFIG_USER_ONLY)
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typedef struct PhysPageEntry PhysPageEntry; |
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struct PhysPageEntry {
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/* How many bits skip to next level (in units of L2_SIZE). 0 for a leaf. */
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uint32_t skip : 6;
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/* index into phys_sections (!skip) or phys_map_nodes (skip) */
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uint32_t ptr : 26;
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}; |
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#define PHYS_MAP_NODE_NIL (((uint32_t)~0) >> 6) |
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/* Size of the L2 (and L3, etc) page tables. */
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#define ADDR_SPACE_BITS 64 |
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#define P_L2_BITS 9 |
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#define P_L2_SIZE (1 << P_L2_BITS) |
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#define P_L2_LEVELS (((ADDR_SPACE_BITS - TARGET_PAGE_BITS - 1) / P_L2_BITS) + 1) |
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typedef PhysPageEntry Node[P_L2_SIZE];
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typedef struct PhysPageMap { |
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unsigned sections_nb;
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unsigned sections_nb_alloc;
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unsigned nodes_nb;
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unsigned nodes_nb_alloc;
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Node *nodes; |
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MemoryRegionSection *sections; |
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} PhysPageMap; |
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struct AddressSpaceDispatch {
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/* This is a multi-level map on the physical address space.
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* The bottom level has pointers to MemoryRegionSections.
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*/
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PhysPageEntry phys_map; |
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PhysPageMap map; |
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AddressSpace *as; |
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}; |
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#define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK)
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typedef struct subpage_t { |
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MemoryRegion iomem; |
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AddressSpace *as; |
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hwaddr base; |
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uint16_t sub_section[TARGET_PAGE_SIZE]; |
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} subpage_t; |
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#define PHYS_SECTION_UNASSIGNED 0 |
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#define PHYS_SECTION_NOTDIRTY 1 |
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#define PHYS_SECTION_ROM 2 |
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#define PHYS_SECTION_WATCH 3 |
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static void io_mem_init(void); |
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static void memory_map_init(void); |
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static MemoryRegion io_mem_watch;
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#endif
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#if !defined(CONFIG_USER_ONLY)
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static void phys_map_node_reserve(PhysPageMap *map, unsigned nodes) |
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{
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if (map->nodes_nb + nodes > map->nodes_nb_alloc) {
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map->nodes_nb_alloc = MAX(map->nodes_nb_alloc * 2, 16); |
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map->nodes_nb_alloc = MAX(map->nodes_nb_alloc, map->nodes_nb + nodes); |
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map->nodes = g_renew(Node, map->nodes, map->nodes_nb_alloc); |
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} |
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} |
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static uint32_t phys_map_node_alloc(PhysPageMap *map)
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{
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unsigned i;
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uint32_t ret; |
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ret = map->nodes_nb++; |
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assert(ret != PHYS_MAP_NODE_NIL); |
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assert(ret != map->nodes_nb_alloc); |
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for (i = 0; i < P_L2_SIZE; ++i) { |
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map->nodes[ret][i].skip = 1;
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map->nodes[ret][i].ptr = PHYS_MAP_NODE_NIL; |
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} |
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return ret;
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} |
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static void phys_page_set_level(PhysPageMap *map, PhysPageEntry *lp, |
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hwaddr *index, hwaddr *nb, uint16_t leaf, |
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int level)
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{
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PhysPageEntry *p; |
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int i;
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hwaddr step = (hwaddr)1 << (level * P_L2_BITS);
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if (lp->skip && lp->ptr == PHYS_MAP_NODE_NIL) {
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lp->ptr = phys_map_node_alloc(map); |
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p = map->nodes[lp->ptr]; |
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if (level == 0) { |
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for (i = 0; i < P_L2_SIZE; i++) { |
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p[i].skip = 0;
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p[i].ptr = PHYS_SECTION_UNASSIGNED; |
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} |
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} |
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} else {
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p = map->nodes[lp->ptr]; |
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} |
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lp = &p[(*index >> (level * P_L2_BITS)) & (P_L2_SIZE - 1)];
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while (*nb && lp < &p[P_L2_SIZE]) {
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if ((*index & (step - 1)) == 0 && *nb >= step) { |
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lp->skip = 0;
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lp->ptr = leaf; |
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*index += step; |
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*nb -= step; |
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} else {
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phys_page_set_level(map, lp, index, nb, leaf, level - 1);
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} |
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++lp; |
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} |
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} |
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static void phys_page_set(AddressSpaceDispatch *d, |
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hwaddr index, hwaddr nb, |
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uint16_t leaf) |
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{
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/* Wildly overreserve - it doesn't matter much. */
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phys_map_node_reserve(&d->map, 3 * P_L2_LEVELS);
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phys_page_set_level(&d->map, &d->phys_map, &index, &nb, leaf, P_L2_LEVELS - 1);
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} |
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/* Compact a non leaf page entry. Simply detect that the entry has a single child,
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* and update our entry so we can skip it and go directly to the destination.
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*/
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static void phys_page_compact(PhysPageEntry *lp, Node *nodes, unsigned long *compacted) |
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{
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unsigned valid_ptr = P_L2_SIZE;
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int valid = 0; |
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PhysPageEntry *p; |
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int i;
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if (lp->ptr == PHYS_MAP_NODE_NIL) {
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return;
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} |
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p = nodes[lp->ptr]; |
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for (i = 0; i < P_L2_SIZE; i++) { |
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if (p[i].ptr == PHYS_MAP_NODE_NIL) {
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continue;
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} |
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valid_ptr = i; |
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valid++; |
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if (p[i].skip) {
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phys_page_compact(&p[i], nodes, compacted); |
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} |
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} |
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/* We can only compress if there's only one child. */
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if (valid != 1) { |
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return;
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} |
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assert(valid_ptr < P_L2_SIZE); |
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/* Don't compress if it won't fit in the # of bits we have. */
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if (lp->skip + p[valid_ptr].skip >= (1 << 3)) { |
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return;
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} |
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lp->ptr = p[valid_ptr].ptr; |
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if (!p[valid_ptr].skip) {
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/* If our only child is a leaf, make this a leaf. */
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/* By design, we should have made this node a leaf to begin with so we
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* should never reach here.
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* But since it's so simple to handle this, let's do it just in case we
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* change this rule.
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*/
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lp->skip = 0;
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} else {
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lp->skip += p[valid_ptr].skip; |
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} |
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} |
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static void phys_page_compact_all(AddressSpaceDispatch *d, int nodes_nb) |
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{
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DECLARE_BITMAP(compacted, nodes_nb); |
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if (d->phys_map.skip) {
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phys_page_compact(&d->phys_map, d->map.nodes, compacted); |
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} |
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} |
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static MemoryRegionSection *phys_page_find(PhysPageEntry lp, hwaddr addr,
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Node *nodes, MemoryRegionSection *sections) |
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{
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PhysPageEntry *p; |
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hwaddr index = addr >> TARGET_PAGE_BITS; |
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int i;
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for (i = P_L2_LEVELS; lp.skip && (i -= lp.skip) >= 0;) { |
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if (lp.ptr == PHYS_MAP_NODE_NIL) {
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return §ions[PHYS_SECTION_UNASSIGNED];
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} |
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p = nodes[lp.ptr]; |
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lp = p[(index >> (i * P_L2_BITS)) & (P_L2_SIZE - 1)];
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} |
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if (sections[lp.ptr].size.hi ||
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range_covers_byte(sections[lp.ptr].offset_within_address_space, |
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sections[lp.ptr].size.lo, addr)) {
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return §ions[lp.ptr];
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} else {
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return §ions[PHYS_SECTION_UNASSIGNED];
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} |
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} |
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bool memory_region_is_unassigned(MemoryRegion *mr)
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{
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return mr != &io_mem_rom && mr != &io_mem_notdirty && !mr->rom_device
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&& mr != &io_mem_watch; |
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} |
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|
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static MemoryRegionSection *address_space_lookup_region(AddressSpaceDispatch *d,
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hwaddr addr, |
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bool resolve_subpage)
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{
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MemoryRegionSection *section; |
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subpage_t *subpage; |
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section = phys_page_find(d->phys_map, addr, d->map.nodes, d->map.sections); |
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if (resolve_subpage && section->mr->subpage) {
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subpage = container_of(section->mr, subpage_t, iomem); |
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section = &d->map.sections[subpage->sub_section[SUBPAGE_IDX(addr)]]; |
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} |
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return section;
|
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} |
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|
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static MemoryRegionSection *
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address_space_translate_internal(AddressSpaceDispatch *d, hwaddr addr, hwaddr *xlat, |
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hwaddr *plen, bool resolve_subpage)
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{
|
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MemoryRegionSection *section; |
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Int128 diff; |
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|
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section = address_space_lookup_region(d, addr, resolve_subpage); |
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/* Compute offset within MemoryRegionSection */
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addr -= section->offset_within_address_space; |
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|
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/* Compute offset within MemoryRegion */
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*xlat = addr + section->offset_within_region; |
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|
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diff = int128_sub(section->mr->size, int128_make64(addr)); |
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*plen = int128_get64(int128_min(diff, int128_make64(*plen))); |
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return section;
|
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} |
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|
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MemoryRegion *address_space_translate(AddressSpace *as, hwaddr addr, |
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hwaddr *xlat, hwaddr *plen, |
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bool is_write)
|
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{
|
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IOMMUTLBEntry iotlb; |
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MemoryRegionSection *section; |
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MemoryRegion *mr; |
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hwaddr len = *plen; |
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|
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for (;;) {
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section = address_space_translate_internal(as->dispatch, addr, &addr, plen, true);
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mr = section->mr; |
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|
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if (!mr->iommu_ops) {
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break;
|
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} |
| 357 |
|
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iotlb = mr->iommu_ops->translate(mr, addr); |
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addr = ((iotlb.translated_addr & ~iotlb.addr_mask) |
| 360 |
| (addr & iotlb.addr_mask)); |
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len = MIN(len, (addr | iotlb.addr_mask) - addr + 1);
|
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if (!(iotlb.perm & (1 << is_write))) { |
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mr = &io_mem_unassigned; |
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break;
|
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} |
| 366 |
|
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as = iotlb.target_as; |
| 368 |
} |
| 369 |
|
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*plen = len; |
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*xlat = addr; |
| 372 |
return mr;
|
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} |
| 374 |
|
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MemoryRegionSection * |
| 376 |
address_space_translate_for_iotlb(AddressSpace *as, hwaddr addr, hwaddr *xlat, |
| 377 |
hwaddr *plen) |
| 378 |
{
|
| 379 |
MemoryRegionSection *section; |
| 380 |
section = address_space_translate_internal(as->dispatch, addr, xlat, plen, false);
|
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|
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assert(!section->mr->iommu_ops); |
| 383 |
return section;
|
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} |
| 385 |
#endif
|
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|
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void cpu_exec_init_all(void) |
| 388 |
{
|
| 389 |
#if !defined(CONFIG_USER_ONLY)
|
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qemu_mutex_init(&ram_list.mutex); |
| 391 |
memory_map_init(); |
| 392 |
io_mem_init(); |
| 393 |
#endif
|
| 394 |
} |
| 395 |
|
| 396 |
#if !defined(CONFIG_USER_ONLY)
|
| 397 |
|
| 398 |
static int cpu_common_post_load(void *opaque, int version_id) |
| 399 |
{
|
| 400 |
CPUState *cpu = opaque; |
| 401 |
|
| 402 |
/* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the
|
| 403 |
version_id is increased. */
|
| 404 |
cpu->interrupt_request &= ~0x01;
|
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tlb_flush(cpu->env_ptr, 1);
|
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|
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return 0; |
| 408 |
} |
| 409 |
|
| 410 |
const VMStateDescription vmstate_cpu_common = {
|
| 411 |
.name = "cpu_common",
|
| 412 |
.version_id = 1,
|
| 413 |
.minimum_version_id = 1,
|
| 414 |
.minimum_version_id_old = 1,
|
| 415 |
.post_load = cpu_common_post_load, |
| 416 |
.fields = (VMStateField []) {
|
| 417 |
VMSTATE_UINT32(halted, CPUState), |
| 418 |
VMSTATE_UINT32(interrupt_request, CPUState), |
| 419 |
VMSTATE_END_OF_LIST() |
| 420 |
} |
| 421 |
}; |
| 422 |
|
| 423 |
#endif
|
| 424 |
|
| 425 |
CPUState *qemu_get_cpu(int index)
|
| 426 |
{
|
| 427 |
CPUState *cpu; |
| 428 |
|
| 429 |
CPU_FOREACH(cpu) {
|
| 430 |
if (cpu->cpu_index == index) {
|
| 431 |
return cpu;
|
| 432 |
} |
| 433 |
} |
| 434 |
|
| 435 |
return NULL; |
| 436 |
} |
| 437 |
|
| 438 |
void cpu_exec_init(CPUArchState *env)
|
| 439 |
{
|
| 440 |
CPUState *cpu = ENV_GET_CPU(env); |
| 441 |
CPUClass *cc = CPU_GET_CLASS(cpu); |
| 442 |
CPUState *some_cpu; |
| 443 |
int cpu_index;
|
| 444 |
|
| 445 |
#if defined(CONFIG_USER_ONLY)
|
| 446 |
cpu_list_lock(); |
| 447 |
#endif
|
| 448 |
cpu_index = 0;
|
| 449 |
CPU_FOREACH(some_cpu) {
|
| 450 |
cpu_index++; |
| 451 |
} |
| 452 |
cpu->cpu_index = cpu_index; |
| 453 |
cpu->numa_node = 0;
|
| 454 |
QTAILQ_INIT(&env->breakpoints); |
| 455 |
QTAILQ_INIT(&env->watchpoints); |
| 456 |
#ifndef CONFIG_USER_ONLY
|
| 457 |
cpu->thread_id = qemu_get_thread_id(); |
| 458 |
#endif
|
| 459 |
QTAILQ_INSERT_TAIL(&cpus, cpu, node); |
| 460 |
#if defined(CONFIG_USER_ONLY)
|
| 461 |
cpu_list_unlock(); |
| 462 |
#endif
|
| 463 |
if (qdev_get_vmsd(DEVICE(cpu)) == NULL) { |
| 464 |
vmstate_register(NULL, cpu_index, &vmstate_cpu_common, cpu);
|
| 465 |
} |
| 466 |
#if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY)
|
| 467 |
register_savevm(NULL, "cpu", cpu_index, CPU_SAVE_VERSION, |
| 468 |
cpu_save, cpu_load, env); |
| 469 |
assert(cc->vmsd == NULL);
|
| 470 |
assert(qdev_get_vmsd(DEVICE(cpu)) == NULL);
|
| 471 |
#endif
|
| 472 |
if (cc->vmsd != NULL) { |
| 473 |
vmstate_register(NULL, cpu_index, cc->vmsd, cpu);
|
| 474 |
} |
| 475 |
} |
| 476 |
|
| 477 |
#if defined(TARGET_HAS_ICE)
|
| 478 |
#if defined(CONFIG_USER_ONLY)
|
| 479 |
static void breakpoint_invalidate(CPUState *cpu, target_ulong pc) |
| 480 |
{
|
| 481 |
tb_invalidate_phys_page_range(pc, pc + 1, 0); |
| 482 |
} |
| 483 |
#else
|
| 484 |
static void breakpoint_invalidate(CPUState *cpu, target_ulong pc) |
| 485 |
{
|
| 486 |
hwaddr phys = cpu_get_phys_page_debug(cpu, pc); |
| 487 |
if (phys != -1) { |
| 488 |
tb_invalidate_phys_addr(phys | (pc & ~TARGET_PAGE_MASK)); |
| 489 |
} |
| 490 |
} |
| 491 |
#endif
|
| 492 |
#endif /* TARGET_HAS_ICE */ |
| 493 |
|
| 494 |
#if defined(CONFIG_USER_ONLY)
|
| 495 |
void cpu_watchpoint_remove_all(CPUArchState *env, int mask) |
| 496 |
|
| 497 |
{
|
| 498 |
} |
| 499 |
|
| 500 |
int cpu_watchpoint_insert(CPUArchState *env, target_ulong addr, target_ulong len,
|
| 501 |
int flags, CPUWatchpoint **watchpoint)
|
| 502 |
{
|
| 503 |
return -ENOSYS;
|
| 504 |
} |
| 505 |
#else
|
| 506 |
/* Add a watchpoint. */
|
| 507 |
int cpu_watchpoint_insert(CPUArchState *env, target_ulong addr, target_ulong len,
|
| 508 |
int flags, CPUWatchpoint **watchpoint)
|
| 509 |
{
|
| 510 |
target_ulong len_mask = ~(len - 1);
|
| 511 |
CPUWatchpoint *wp; |
| 512 |
|
| 513 |
/* sanity checks: allow power-of-2 lengths, deny unaligned watchpoints */
|
| 514 |
if ((len & (len - 1)) || (addr & ~len_mask) || |
| 515 |
len == 0 || len > TARGET_PAGE_SIZE) {
|
| 516 |
fprintf(stderr, "qemu: tried to set invalid watchpoint at "
|
| 517 |
TARGET_FMT_lx ", len=" TARGET_FMT_lu "\n", addr, len); |
| 518 |
return -EINVAL;
|
| 519 |
} |
| 520 |
wp = g_malloc(sizeof(*wp));
|
| 521 |
|
| 522 |
wp->vaddr = addr; |
| 523 |
wp->len_mask = len_mask; |
| 524 |
wp->flags = flags; |
| 525 |
|
| 526 |
/* keep all GDB-injected watchpoints in front */
|
| 527 |
if (flags & BP_GDB)
|
| 528 |
QTAILQ_INSERT_HEAD(&env->watchpoints, wp, entry); |
| 529 |
else
|
| 530 |
QTAILQ_INSERT_TAIL(&env->watchpoints, wp, entry); |
| 531 |
|
| 532 |
tlb_flush_page(env, addr); |
| 533 |
|
| 534 |
if (watchpoint)
|
| 535 |
*watchpoint = wp; |
| 536 |
return 0; |
| 537 |
} |
| 538 |
|
| 539 |
/* Remove a specific watchpoint. */
|
| 540 |
int cpu_watchpoint_remove(CPUArchState *env, target_ulong addr, target_ulong len,
|
| 541 |
int flags)
|
| 542 |
{
|
| 543 |
target_ulong len_mask = ~(len - 1);
|
| 544 |
CPUWatchpoint *wp; |
| 545 |
|
| 546 |
QTAILQ_FOREACH(wp, &env->watchpoints, entry) {
|
| 547 |
if (addr == wp->vaddr && len_mask == wp->len_mask
|
| 548 |
&& flags == (wp->flags & ~BP_WATCHPOINT_HIT)) {
|
| 549 |
cpu_watchpoint_remove_by_ref(env, wp); |
| 550 |
return 0; |
| 551 |
} |
| 552 |
} |
| 553 |
return -ENOENT;
|
| 554 |
} |
| 555 |
|
| 556 |
/* Remove a specific watchpoint by reference. */
|
| 557 |
void cpu_watchpoint_remove_by_ref(CPUArchState *env, CPUWatchpoint *watchpoint)
|
| 558 |
{
|
| 559 |
QTAILQ_REMOVE(&env->watchpoints, watchpoint, entry); |
| 560 |
|
| 561 |
tlb_flush_page(env, watchpoint->vaddr); |
| 562 |
|
| 563 |
g_free(watchpoint); |
| 564 |
} |
| 565 |
|
| 566 |
/* Remove all matching watchpoints. */
|
| 567 |
void cpu_watchpoint_remove_all(CPUArchState *env, int mask) |
| 568 |
{
|
| 569 |
CPUWatchpoint *wp, *next; |
| 570 |
|
| 571 |
QTAILQ_FOREACH_SAFE(wp, &env->watchpoints, entry, next) {
|
| 572 |
if (wp->flags & mask)
|
| 573 |
cpu_watchpoint_remove_by_ref(env, wp); |
| 574 |
} |
| 575 |
} |
| 576 |
#endif
|
| 577 |
|
| 578 |
/* Add a breakpoint. */
|
| 579 |
int cpu_breakpoint_insert(CPUArchState *env, target_ulong pc, int flags, |
| 580 |
CPUBreakpoint **breakpoint) |
| 581 |
{
|
| 582 |
#if defined(TARGET_HAS_ICE)
|
| 583 |
CPUBreakpoint *bp; |
| 584 |
|
| 585 |
bp = g_malloc(sizeof(*bp));
|
| 586 |
|
| 587 |
bp->pc = pc; |
| 588 |
bp->flags = flags; |
| 589 |
|
| 590 |
/* keep all GDB-injected breakpoints in front */
|
| 591 |
if (flags & BP_GDB) {
|
| 592 |
QTAILQ_INSERT_HEAD(&env->breakpoints, bp, entry); |
| 593 |
} else {
|
| 594 |
QTAILQ_INSERT_TAIL(&env->breakpoints, bp, entry); |
| 595 |
} |
| 596 |
|
| 597 |
breakpoint_invalidate(ENV_GET_CPU(env), pc); |
| 598 |
|
| 599 |
if (breakpoint) {
|
| 600 |
*breakpoint = bp; |
| 601 |
} |
| 602 |
return 0; |
| 603 |
#else
|
| 604 |
return -ENOSYS;
|
| 605 |
#endif
|
| 606 |
} |
| 607 |
|
| 608 |
/* Remove a specific breakpoint. */
|
| 609 |
int cpu_breakpoint_remove(CPUArchState *env, target_ulong pc, int flags) |
| 610 |
{
|
| 611 |
#if defined(TARGET_HAS_ICE)
|
| 612 |
CPUBreakpoint *bp; |
| 613 |
|
| 614 |
QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
|
| 615 |
if (bp->pc == pc && bp->flags == flags) {
|
| 616 |
cpu_breakpoint_remove_by_ref(env, bp); |
| 617 |
return 0; |
| 618 |
} |
| 619 |
} |
| 620 |
return -ENOENT;
|
| 621 |
#else
|
| 622 |
return -ENOSYS;
|
| 623 |
#endif
|
| 624 |
} |
| 625 |
|
| 626 |
/* Remove a specific breakpoint by reference. */
|
| 627 |
void cpu_breakpoint_remove_by_ref(CPUArchState *env, CPUBreakpoint *breakpoint)
|
| 628 |
{
|
| 629 |
#if defined(TARGET_HAS_ICE)
|
| 630 |
QTAILQ_REMOVE(&env->breakpoints, breakpoint, entry); |
| 631 |
|
| 632 |
breakpoint_invalidate(ENV_GET_CPU(env), breakpoint->pc); |
| 633 |
|
| 634 |
g_free(breakpoint); |
| 635 |
#endif
|
| 636 |
} |
| 637 |
|
| 638 |
/* Remove all matching breakpoints. */
|
| 639 |
void cpu_breakpoint_remove_all(CPUArchState *env, int mask) |
| 640 |
{
|
| 641 |
#if defined(TARGET_HAS_ICE)
|
| 642 |
CPUBreakpoint *bp, *next; |
| 643 |
|
| 644 |
QTAILQ_FOREACH_SAFE(bp, &env->breakpoints, entry, next) {
|
| 645 |
if (bp->flags & mask)
|
| 646 |
cpu_breakpoint_remove_by_ref(env, bp); |
| 647 |
} |
| 648 |
#endif
|
| 649 |
} |
| 650 |
|
| 651 |
/* enable or disable single step mode. EXCP_DEBUG is returned by the
|
| 652 |
CPU loop after each instruction */
|
| 653 |
void cpu_single_step(CPUState *cpu, int enabled) |
| 654 |
{
|
| 655 |
#if defined(TARGET_HAS_ICE)
|
| 656 |
if (cpu->singlestep_enabled != enabled) {
|
| 657 |
cpu->singlestep_enabled = enabled; |
| 658 |
if (kvm_enabled()) {
|
| 659 |
kvm_update_guest_debug(cpu, 0);
|
| 660 |
} else {
|
| 661 |
/* must flush all the translated code to avoid inconsistencies */
|
| 662 |
/* XXX: only flush what is necessary */
|
| 663 |
CPUArchState *env = cpu->env_ptr; |
| 664 |
tb_flush(env); |
| 665 |
} |
| 666 |
} |
| 667 |
#endif
|
| 668 |
} |
| 669 |
|
| 670 |
void cpu_abort(CPUArchState *env, const char *fmt, ...) |
| 671 |
{
|
| 672 |
CPUState *cpu = ENV_GET_CPU(env); |
| 673 |
va_list ap; |
| 674 |
va_list ap2; |
| 675 |
|
| 676 |
va_start(ap, fmt); |
| 677 |
va_copy(ap2, ap); |
| 678 |
fprintf(stderr, "qemu: fatal: ");
|
| 679 |
vfprintf(stderr, fmt, ap); |
| 680 |
fprintf(stderr, "\n");
|
| 681 |
cpu_dump_state(cpu, stderr, fprintf, CPU_DUMP_FPU | CPU_DUMP_CCOP); |
| 682 |
if (qemu_log_enabled()) {
|
| 683 |
qemu_log("qemu: fatal: ");
|
| 684 |
qemu_log_vprintf(fmt, ap2); |
| 685 |
qemu_log("\n");
|
| 686 |
log_cpu_state(cpu, CPU_DUMP_FPU | CPU_DUMP_CCOP); |
| 687 |
qemu_log_flush(); |
| 688 |
qemu_log_close(); |
| 689 |
} |
| 690 |
va_end(ap2); |
| 691 |
va_end(ap); |
| 692 |
#if defined(CONFIG_USER_ONLY)
|
| 693 |
{
|
| 694 |
struct sigaction act;
|
| 695 |
sigfillset(&act.sa_mask); |
| 696 |
act.sa_handler = SIG_DFL; |
| 697 |
sigaction(SIGABRT, &act, NULL);
|
| 698 |
} |
| 699 |
#endif
|
| 700 |
abort(); |
| 701 |
} |
| 702 |
|
| 703 |
#if !defined(CONFIG_USER_ONLY)
|
| 704 |
static RAMBlock *qemu_get_ram_block(ram_addr_t addr)
|
| 705 |
{
|
| 706 |
RAMBlock *block; |
| 707 |
|
| 708 |
/* The list is protected by the iothread lock here. */
|
| 709 |
block = ram_list.mru_block; |
| 710 |
if (block && addr - block->offset < block->length) {
|
| 711 |
goto found;
|
| 712 |
} |
| 713 |
QTAILQ_FOREACH(block, &ram_list.blocks, next) {
|
| 714 |
if (addr - block->offset < block->length) {
|
| 715 |
goto found;
|
| 716 |
} |
| 717 |
} |
| 718 |
|
| 719 |
fprintf(stderr, "Bad ram offset %" PRIx64 "\n", (uint64_t)addr); |
| 720 |
abort(); |
| 721 |
|
| 722 |
found:
|
| 723 |
ram_list.mru_block = block; |
| 724 |
return block;
|
| 725 |
} |
| 726 |
|
| 727 |
static void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t length) |
| 728 |
{
|
| 729 |
ram_addr_t start1; |
| 730 |
RAMBlock *block; |
| 731 |
ram_addr_t end; |
| 732 |
|
| 733 |
end = TARGET_PAGE_ALIGN(start + length); |
| 734 |
start &= TARGET_PAGE_MASK; |
| 735 |
|
| 736 |
block = qemu_get_ram_block(start); |
| 737 |
assert(block == qemu_get_ram_block(end - 1));
|
| 738 |
start1 = (uintptr_t)block->host + (start - block->offset); |
| 739 |
cpu_tlb_reset_dirty_all(start1, length); |
| 740 |
} |
| 741 |
|
| 742 |
/* Note: start and end must be within the same ram block. */
|
| 743 |
void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t length,
|
| 744 |
unsigned client)
|
| 745 |
{
|
| 746 |
if (length == 0) |
| 747 |
return;
|
| 748 |
cpu_physical_memory_clear_dirty_range(start, length, client); |
| 749 |
|
| 750 |
if (tcg_enabled()) {
|
| 751 |
tlb_reset_dirty_range_all(start, length); |
| 752 |
} |
| 753 |
} |
| 754 |
|
| 755 |
static void cpu_physical_memory_set_dirty_tracking(bool enable) |
| 756 |
{
|
| 757 |
in_migration = enable; |
| 758 |
} |
| 759 |
|
| 760 |
hwaddr memory_region_section_get_iotlb(CPUArchState *env, |
| 761 |
MemoryRegionSection *section, |
| 762 |
target_ulong vaddr, |
| 763 |
hwaddr paddr, hwaddr xlat, |
| 764 |
int prot,
|
| 765 |
target_ulong *address) |
| 766 |
{
|
| 767 |
hwaddr iotlb; |
| 768 |
CPUWatchpoint *wp; |
| 769 |
|
| 770 |
if (memory_region_is_ram(section->mr)) {
|
| 771 |
/* Normal RAM. */
|
| 772 |
iotlb = (memory_region_get_ram_addr(section->mr) & TARGET_PAGE_MASK) |
| 773 |
+ xlat; |
| 774 |
if (!section->readonly) {
|
| 775 |
iotlb |= PHYS_SECTION_NOTDIRTY; |
| 776 |
} else {
|
| 777 |
iotlb |= PHYS_SECTION_ROM; |
| 778 |
} |
| 779 |
} else {
|
| 780 |
iotlb = section - address_space_memory.dispatch->map.sections; |
| 781 |
iotlb += xlat; |
| 782 |
} |
| 783 |
|
| 784 |
/* Make accesses to pages with watchpoints go via the
|
| 785 |
watchpoint trap routines. */
|
| 786 |
QTAILQ_FOREACH(wp, &env->watchpoints, entry) {
|
| 787 |
if (vaddr == (wp->vaddr & TARGET_PAGE_MASK)) {
|
| 788 |
/* Avoid trapping reads of pages with a write breakpoint. */
|
| 789 |
if ((prot & PAGE_WRITE) || (wp->flags & BP_MEM_READ)) {
|
| 790 |
iotlb = PHYS_SECTION_WATCH + paddr; |
| 791 |
*address |= TLB_MMIO; |
| 792 |
break;
|
| 793 |
} |
| 794 |
} |
| 795 |
} |
| 796 |
|
| 797 |
return iotlb;
|
| 798 |
} |
| 799 |
#endif /* defined(CONFIG_USER_ONLY) */ |
| 800 |
|
| 801 |
#if !defined(CONFIG_USER_ONLY)
|
| 802 |
|
| 803 |
static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end, |
| 804 |
uint16_t section); |
| 805 |
static subpage_t *subpage_init(AddressSpace *as, hwaddr base);
|
| 806 |
|
| 807 |
static void *(*phys_mem_alloc)(size_t size) = qemu_anon_ram_alloc; |
| 808 |
|
| 809 |
/*
|
| 810 |
* Set a custom physical guest memory alloator.
|
| 811 |
* Accelerators with unusual needs may need this. Hopefully, we can
|
| 812 |
* get rid of it eventually.
|
| 813 |
*/
|
| 814 |
void phys_mem_set_alloc(void *(*alloc)(size_t)) |
| 815 |
{
|
| 816 |
phys_mem_alloc = alloc; |
| 817 |
} |
| 818 |
|
| 819 |
static uint16_t phys_section_add(PhysPageMap *map,
|
| 820 |
MemoryRegionSection *section) |
| 821 |
{
|
| 822 |
/* The physical section number is ORed with a page-aligned
|
| 823 |
* pointer to produce the iotlb entries. Thus it should
|
| 824 |
* never overflow into the page-aligned value.
|
| 825 |
*/
|
| 826 |
assert(map->sections_nb < TARGET_PAGE_SIZE); |
| 827 |
|
| 828 |
if (map->sections_nb == map->sections_nb_alloc) {
|
| 829 |
map->sections_nb_alloc = MAX(map->sections_nb_alloc * 2, 16); |
| 830 |
map->sections = g_renew(MemoryRegionSection, map->sections, |
| 831 |
map->sections_nb_alloc); |
| 832 |
} |
| 833 |
map->sections[map->sections_nb] = *section; |
| 834 |
memory_region_ref(section->mr); |
| 835 |
return map->sections_nb++;
|
| 836 |
} |
| 837 |
|
| 838 |
static void phys_section_destroy(MemoryRegion *mr) |
| 839 |
{
|
| 840 |
memory_region_unref(mr); |
| 841 |
|
| 842 |
if (mr->subpage) {
|
| 843 |
subpage_t *subpage = container_of(mr, subpage_t, iomem); |
| 844 |
memory_region_destroy(&subpage->iomem); |
| 845 |
g_free(subpage); |
| 846 |
} |
| 847 |
} |
| 848 |
|
| 849 |
static void phys_sections_free(PhysPageMap *map) |
| 850 |
{
|
| 851 |
while (map->sections_nb > 0) { |
| 852 |
MemoryRegionSection *section = &map->sections[--map->sections_nb]; |
| 853 |
phys_section_destroy(section->mr); |
| 854 |
} |
| 855 |
g_free(map->sections); |
| 856 |
g_free(map->nodes); |
| 857 |
} |
| 858 |
|
| 859 |
static void register_subpage(AddressSpaceDispatch *d, MemoryRegionSection *section) |
| 860 |
{
|
| 861 |
subpage_t *subpage; |
| 862 |
hwaddr base = section->offset_within_address_space |
| 863 |
& TARGET_PAGE_MASK; |
| 864 |
MemoryRegionSection *existing = phys_page_find(d->phys_map, base, |
| 865 |
d->map.nodes, d->map.sections); |
| 866 |
MemoryRegionSection subsection = {
|
| 867 |
.offset_within_address_space = base, |
| 868 |
.size = int128_make64(TARGET_PAGE_SIZE), |
| 869 |
}; |
| 870 |
hwaddr start, end; |
| 871 |
|
| 872 |
assert(existing->mr->subpage || existing->mr == &io_mem_unassigned); |
| 873 |
|
| 874 |
if (!(existing->mr->subpage)) {
|
| 875 |
subpage = subpage_init(d->as, base); |
| 876 |
subsection.mr = &subpage->iomem; |
| 877 |
phys_page_set(d, base >> TARGET_PAGE_BITS, 1,
|
| 878 |
phys_section_add(&d->map, &subsection)); |
| 879 |
} else {
|
| 880 |
subpage = container_of(existing->mr, subpage_t, iomem); |
| 881 |
} |
| 882 |
start = section->offset_within_address_space & ~TARGET_PAGE_MASK; |
| 883 |
end = start + int128_get64(section->size) - 1;
|
| 884 |
subpage_register(subpage, start, end, |
| 885 |
phys_section_add(&d->map, section)); |
| 886 |
} |
| 887 |
|
| 888 |
|
| 889 |
static void register_multipage(AddressSpaceDispatch *d, |
| 890 |
MemoryRegionSection *section) |
| 891 |
{
|
| 892 |
hwaddr start_addr = section->offset_within_address_space; |
| 893 |
uint16_t section_index = phys_section_add(&d->map, section); |
| 894 |
uint64_t num_pages = int128_get64(int128_rshift(section->size, |
| 895 |
TARGET_PAGE_BITS)); |
| 896 |
|
| 897 |
assert(num_pages); |
| 898 |
phys_page_set(d, start_addr >> TARGET_PAGE_BITS, num_pages, section_index); |
| 899 |
} |
| 900 |
|
| 901 |
static void mem_add(MemoryListener *listener, MemoryRegionSection *section) |
| 902 |
{
|
| 903 |
AddressSpace *as = container_of(listener, AddressSpace, dispatch_listener); |
| 904 |
AddressSpaceDispatch *d = as->next_dispatch; |
| 905 |
MemoryRegionSection now = *section, remain = *section; |
| 906 |
Int128 page_size = int128_make64(TARGET_PAGE_SIZE); |
| 907 |
|
| 908 |
if (now.offset_within_address_space & ~TARGET_PAGE_MASK) {
|
| 909 |
uint64_t left = TARGET_PAGE_ALIGN(now.offset_within_address_space) |
| 910 |
- now.offset_within_address_space; |
| 911 |
|
| 912 |
now.size = int128_min(int128_make64(left), now.size); |
| 913 |
register_subpage(d, &now); |
| 914 |
} else {
|
| 915 |
now.size = int128_zero(); |
| 916 |
} |
| 917 |
while (int128_ne(remain.size, now.size)) {
|
| 918 |
remain.size = int128_sub(remain.size, now.size); |
| 919 |
remain.offset_within_address_space += int128_get64(now.size); |
| 920 |
remain.offset_within_region += int128_get64(now.size); |
| 921 |
now = remain; |
| 922 |
if (int128_lt(remain.size, page_size)) {
|
| 923 |
register_subpage(d, &now); |
| 924 |
} else if (remain.offset_within_address_space & ~TARGET_PAGE_MASK) { |
| 925 |
now.size = page_size; |
| 926 |
register_subpage(d, &now); |
| 927 |
} else {
|
| 928 |
now.size = int128_and(now.size, int128_neg(page_size)); |
| 929 |
register_multipage(d, &now); |
| 930 |
} |
| 931 |
} |
| 932 |
} |
| 933 |
|
| 934 |
void qemu_flush_coalesced_mmio_buffer(void) |
| 935 |
{
|
| 936 |
if (kvm_enabled())
|
| 937 |
kvm_flush_coalesced_mmio_buffer(); |
| 938 |
} |
| 939 |
|
| 940 |
void qemu_mutex_lock_ramlist(void) |
| 941 |
{
|
| 942 |
qemu_mutex_lock(&ram_list.mutex); |
| 943 |
} |
| 944 |
|
| 945 |
void qemu_mutex_unlock_ramlist(void) |
| 946 |
{
|
| 947 |
qemu_mutex_unlock(&ram_list.mutex); |
| 948 |
} |
| 949 |
|
| 950 |
#ifdef __linux__
|
| 951 |
|
| 952 |
#include <sys/vfs.h> |
| 953 |
|
| 954 |
#define HUGETLBFS_MAGIC 0x958458f6 |
| 955 |
|
| 956 |
static long gethugepagesize(const char *path) |
| 957 |
{
|
| 958 |
struct statfs fs;
|
| 959 |
int ret;
|
| 960 |
|
| 961 |
do {
|
| 962 |
ret = statfs(path, &fs); |
| 963 |
} while (ret != 0 && errno == EINTR); |
| 964 |
|
| 965 |
if (ret != 0) { |
| 966 |
perror(path); |
| 967 |
return 0; |
| 968 |
} |
| 969 |
|
| 970 |
if (fs.f_type != HUGETLBFS_MAGIC)
|
| 971 |
fprintf(stderr, "Warning: path not on HugeTLBFS: %s\n", path);
|
| 972 |
|
| 973 |
return fs.f_bsize;
|
| 974 |
} |
| 975 |
|
| 976 |
static sigjmp_buf sigjump;
|
| 977 |
|
| 978 |
static void sigbus_handler(int signal) |
| 979 |
{
|
| 980 |
siglongjmp(sigjump, 1);
|
| 981 |
} |
| 982 |
|
| 983 |
static void *file_ram_alloc(RAMBlock *block, |
| 984 |
ram_addr_t memory, |
| 985 |
const char *path) |
| 986 |
{
|
| 987 |
char *filename;
|
| 988 |
char *sanitized_name;
|
| 989 |
char *c;
|
| 990 |
void *area;
|
| 991 |
int fd;
|
| 992 |
unsigned long hpagesize; |
| 993 |
|
| 994 |
hpagesize = gethugepagesize(path); |
| 995 |
if (!hpagesize) {
|
| 996 |
return NULL; |
| 997 |
} |
| 998 |
|
| 999 |
if (memory < hpagesize) {
|
| 1000 |
return NULL; |
| 1001 |
} |
| 1002 |
|
| 1003 |
if (kvm_enabled() && !kvm_has_sync_mmu()) {
|
| 1004 |
fprintf(stderr, "host lacks kvm mmu notifiers, -mem-path unsupported\n");
|
| 1005 |
return NULL; |
| 1006 |
} |
| 1007 |
|
| 1008 |
/* Make name safe to use with mkstemp by replacing '/' with '_'. */
|
| 1009 |
sanitized_name = g_strdup(block->mr->name); |
| 1010 |
for (c = sanitized_name; *c != '\0'; c++) { |
| 1011 |
if (*c == '/') |
| 1012 |
*c = '_';
|
| 1013 |
} |
| 1014 |
|
| 1015 |
filename = g_strdup_printf("%s/qemu_back_mem.%s.XXXXXX", path,
|
| 1016 |
sanitized_name); |
| 1017 |
g_free(sanitized_name); |
| 1018 |
|
| 1019 |
fd = mkstemp(filename); |
| 1020 |
if (fd < 0) { |
| 1021 |
perror("unable to create backing store for hugepages");
|
| 1022 |
g_free(filename); |
| 1023 |
return NULL; |
| 1024 |
} |
| 1025 |
unlink(filename); |
| 1026 |
g_free(filename); |
| 1027 |
|
| 1028 |
memory = (memory+hpagesize-1) & ~(hpagesize-1); |
| 1029 |
|
| 1030 |
/*
|
| 1031 |
* ftruncate is not supported by hugetlbfs in older
|
| 1032 |
* hosts, so don't bother bailing out on errors.
|
| 1033 |
* If anything goes wrong with it under other filesystems,
|
| 1034 |
* mmap will fail.
|
| 1035 |
*/
|
| 1036 |
if (ftruncate(fd, memory))
|
| 1037 |
perror("ftruncate");
|
| 1038 |
|
| 1039 |
area = mmap(0, memory, PROT_READ | PROT_WRITE, MAP_PRIVATE, fd, 0); |
| 1040 |
if (area == MAP_FAILED) {
|
| 1041 |
perror("file_ram_alloc: can't mmap RAM pages");
|
| 1042 |
close(fd); |
| 1043 |
return (NULL); |
| 1044 |
} |
| 1045 |
|
| 1046 |
if (mem_prealloc) {
|
| 1047 |
int ret, i;
|
| 1048 |
struct sigaction act, oldact;
|
| 1049 |
sigset_t set, oldset; |
| 1050 |
|
| 1051 |
memset(&act, 0, sizeof(act)); |
| 1052 |
act.sa_handler = &sigbus_handler; |
| 1053 |
act.sa_flags = 0;
|
| 1054 |
|
| 1055 |
ret = sigaction(SIGBUS, &act, &oldact); |
| 1056 |
if (ret) {
|
| 1057 |
perror("file_ram_alloc: failed to install signal handler");
|
| 1058 |
exit(1);
|
| 1059 |
} |
| 1060 |
|
| 1061 |
/* unblock SIGBUS */
|
| 1062 |
sigemptyset(&set); |
| 1063 |
sigaddset(&set, SIGBUS); |
| 1064 |
pthread_sigmask(SIG_UNBLOCK, &set, &oldset); |
| 1065 |
|
| 1066 |
if (sigsetjmp(sigjump, 1)) { |
| 1067 |
fprintf(stderr, "file_ram_alloc: failed to preallocate pages\n");
|
| 1068 |
exit(1);
|
| 1069 |
} |
| 1070 |
|
| 1071 |
/* MAP_POPULATE silently ignores failures */
|
| 1072 |
for (i = 0; i < (memory/hpagesize)-1; i++) { |
| 1073 |
memset(area + (hpagesize*i), 0, 1); |
| 1074 |
} |
| 1075 |
|
| 1076 |
ret = sigaction(SIGBUS, &oldact, NULL);
|
| 1077 |
if (ret) {
|
| 1078 |
perror("file_ram_alloc: failed to reinstall signal handler");
|
| 1079 |
exit(1);
|
| 1080 |
} |
| 1081 |
|
| 1082 |
pthread_sigmask(SIG_SETMASK, &oldset, NULL);
|
| 1083 |
} |
| 1084 |
|
| 1085 |
block->fd = fd; |
| 1086 |
return area;
|
| 1087 |
} |
| 1088 |
#else
|
| 1089 |
static void *file_ram_alloc(RAMBlock *block, |
| 1090 |
ram_addr_t memory, |
| 1091 |
const char *path) |
| 1092 |
{
|
| 1093 |
fprintf(stderr, "-mem-path not supported on this host\n");
|
| 1094 |
exit(1);
|
| 1095 |
} |
| 1096 |
#endif
|
| 1097 |
|
| 1098 |
static ram_addr_t find_ram_offset(ram_addr_t size)
|
| 1099 |
{
|
| 1100 |
RAMBlock *block, *next_block; |
| 1101 |
ram_addr_t offset = RAM_ADDR_MAX, mingap = RAM_ADDR_MAX; |
| 1102 |
|
| 1103 |
assert(size != 0); /* it would hand out same offset multiple times */ |
| 1104 |
|
| 1105 |
if (QTAILQ_EMPTY(&ram_list.blocks))
|
| 1106 |
return 0; |
| 1107 |
|
| 1108 |
QTAILQ_FOREACH(block, &ram_list.blocks, next) {
|
| 1109 |
ram_addr_t end, next = RAM_ADDR_MAX; |
| 1110 |
|
| 1111 |
end = block->offset + block->length; |
| 1112 |
|
| 1113 |
QTAILQ_FOREACH(next_block, &ram_list.blocks, next) {
|
| 1114 |
if (next_block->offset >= end) {
|
| 1115 |
next = MIN(next, next_block->offset); |
| 1116 |
} |
| 1117 |
} |
| 1118 |
if (next - end >= size && next - end < mingap) {
|
| 1119 |
offset = end; |
| 1120 |
mingap = next - end; |
| 1121 |
} |
| 1122 |
} |
| 1123 |
|
| 1124 |
if (offset == RAM_ADDR_MAX) {
|
| 1125 |
fprintf(stderr, "Failed to find gap of requested size: %" PRIu64 "\n", |
| 1126 |
(uint64_t)size); |
| 1127 |
abort(); |
| 1128 |
} |
| 1129 |
|
| 1130 |
return offset;
|
| 1131 |
} |
| 1132 |
|
| 1133 |
ram_addr_t last_ram_offset(void)
|
| 1134 |
{
|
| 1135 |
RAMBlock *block; |
| 1136 |
ram_addr_t last = 0;
|
| 1137 |
|
| 1138 |
QTAILQ_FOREACH(block, &ram_list.blocks, next) |
| 1139 |
last = MAX(last, block->offset + block->length); |
| 1140 |
|
| 1141 |
return last;
|
| 1142 |
} |
| 1143 |
|
| 1144 |
static void qemu_ram_setup_dump(void *addr, ram_addr_t size) |
| 1145 |
{
|
| 1146 |
int ret;
|
| 1147 |
|
| 1148 |
/* Use MADV_DONTDUMP, if user doesn't want the guest memory in the core */
|
| 1149 |
if (!qemu_opt_get_bool(qemu_get_machine_opts(),
|
| 1150 |
"dump-guest-core", true)) { |
| 1151 |
ret = qemu_madvise(addr, size, QEMU_MADV_DONTDUMP); |
| 1152 |
if (ret) {
|
| 1153 |
perror("qemu_madvise");
|
| 1154 |
fprintf(stderr, "madvise doesn't support MADV_DONTDUMP, "
|
| 1155 |
"but dump_guest_core=off specified\n");
|
| 1156 |
} |
| 1157 |
} |
| 1158 |
} |
| 1159 |
|
| 1160 |
void qemu_ram_set_idstr(ram_addr_t addr, const char *name, DeviceState *dev) |
| 1161 |
{
|
| 1162 |
RAMBlock *new_block, *block; |
| 1163 |
|
| 1164 |
new_block = NULL;
|
| 1165 |
QTAILQ_FOREACH(block, &ram_list.blocks, next) {
|
| 1166 |
if (block->offset == addr) {
|
| 1167 |
new_block = block; |
| 1168 |
break;
|
| 1169 |
} |
| 1170 |
} |
| 1171 |
assert(new_block); |
| 1172 |
assert(!new_block->idstr[0]);
|
| 1173 |
|
| 1174 |
if (dev) {
|
| 1175 |
char *id = qdev_get_dev_path(dev);
|
| 1176 |
if (id) {
|
| 1177 |
snprintf(new_block->idstr, sizeof(new_block->idstr), "%s/", id); |
| 1178 |
g_free(id); |
| 1179 |
} |
| 1180 |
} |
| 1181 |
pstrcat(new_block->idstr, sizeof(new_block->idstr), name);
|
| 1182 |
|
| 1183 |
/* This assumes the iothread lock is taken here too. */
|
| 1184 |
qemu_mutex_lock_ramlist(); |
| 1185 |
QTAILQ_FOREACH(block, &ram_list.blocks, next) {
|
| 1186 |
if (block != new_block && !strcmp(block->idstr, new_block->idstr)) {
|
| 1187 |
fprintf(stderr, "RAMBlock \"%s\" already registered, abort!\n",
|
| 1188 |
new_block->idstr); |
| 1189 |
abort(); |
| 1190 |
} |
| 1191 |
} |
| 1192 |
qemu_mutex_unlock_ramlist(); |
| 1193 |
} |
| 1194 |
|
| 1195 |
static int memory_try_enable_merging(void *addr, size_t len) |
| 1196 |
{
|
| 1197 |
if (!qemu_opt_get_bool(qemu_get_machine_opts(), "mem-merge", true)) { |
| 1198 |
/* disabled by the user */
|
| 1199 |
return 0; |
| 1200 |
} |
| 1201 |
|
| 1202 |
return qemu_madvise(addr, len, QEMU_MADV_MERGEABLE);
|
| 1203 |
} |
| 1204 |
|
| 1205 |
ram_addr_t qemu_ram_alloc_from_ptr(ram_addr_t size, void *host,
|
| 1206 |
MemoryRegion *mr) |
| 1207 |
{
|
| 1208 |
RAMBlock *block, *new_block; |
| 1209 |
ram_addr_t old_ram_size, new_ram_size; |
| 1210 |
|
| 1211 |
old_ram_size = last_ram_offset() >> TARGET_PAGE_BITS; |
| 1212 |
|
| 1213 |
size = TARGET_PAGE_ALIGN(size); |
| 1214 |
new_block = g_malloc0(sizeof(*new_block));
|
| 1215 |
new_block->fd = -1;
|
| 1216 |
|
| 1217 |
/* This assumes the iothread lock is taken here too. */
|
| 1218 |
qemu_mutex_lock_ramlist(); |
| 1219 |
new_block->mr = mr; |
| 1220 |
new_block->offset = find_ram_offset(size); |
| 1221 |
if (host) {
|
| 1222 |
new_block->host = host; |
| 1223 |
new_block->flags |= RAM_PREALLOC_MASK; |
| 1224 |
} else if (xen_enabled()) { |
| 1225 |
if (mem_path) {
|
| 1226 |
fprintf(stderr, "-mem-path not supported with Xen\n");
|
| 1227 |
exit(1);
|
| 1228 |
} |
| 1229 |
xen_ram_alloc(new_block->offset, size, mr); |
| 1230 |
} else {
|
| 1231 |
if (mem_path) {
|
| 1232 |
if (phys_mem_alloc != qemu_anon_ram_alloc) {
|
| 1233 |
/*
|
| 1234 |
* file_ram_alloc() needs to allocate just like
|
| 1235 |
* phys_mem_alloc, but we haven't bothered to provide
|
| 1236 |
* a hook there.
|
| 1237 |
*/
|
| 1238 |
fprintf(stderr, |
| 1239 |
"-mem-path not supported with this accelerator\n");
|
| 1240 |
exit(1);
|
| 1241 |
} |
| 1242 |
new_block->host = file_ram_alloc(new_block, size, mem_path); |
| 1243 |
} |
| 1244 |
if (!new_block->host) {
|
| 1245 |
new_block->host = phys_mem_alloc(size); |
| 1246 |
if (!new_block->host) {
|
| 1247 |
fprintf(stderr, "Cannot set up guest memory '%s': %s\n",
|
| 1248 |
new_block->mr->name, strerror(errno)); |
| 1249 |
exit(1);
|
| 1250 |
} |
| 1251 |
memory_try_enable_merging(new_block->host, size); |
| 1252 |
} |
| 1253 |
} |
| 1254 |
new_block->length = size; |
| 1255 |
|
| 1256 |
/* Keep the list sorted from biggest to smallest block. */
|
| 1257 |
QTAILQ_FOREACH(block, &ram_list.blocks, next) {
|
| 1258 |
if (block->length < new_block->length) {
|
| 1259 |
break;
|
| 1260 |
} |
| 1261 |
} |
| 1262 |
if (block) {
|
| 1263 |
QTAILQ_INSERT_BEFORE(block, new_block, next); |
| 1264 |
} else {
|
| 1265 |
QTAILQ_INSERT_TAIL(&ram_list.blocks, new_block, next); |
| 1266 |
} |
| 1267 |
ram_list.mru_block = NULL;
|
| 1268 |
|
| 1269 |
ram_list.version++; |
| 1270 |
qemu_mutex_unlock_ramlist(); |
| 1271 |
|
| 1272 |
new_ram_size = last_ram_offset() >> TARGET_PAGE_BITS; |
| 1273 |
|
| 1274 |
if (new_ram_size > old_ram_size) {
|
| 1275 |
int i;
|
| 1276 |
for (i = 0; i < DIRTY_MEMORY_NUM; i++) { |
| 1277 |
ram_list.dirty_memory[i] = |
| 1278 |
bitmap_zero_extend(ram_list.dirty_memory[i], |
| 1279 |
old_ram_size, new_ram_size); |
| 1280 |
} |
| 1281 |
} |
| 1282 |
cpu_physical_memory_set_dirty_range(new_block->offset, size); |
| 1283 |
|
| 1284 |
qemu_ram_setup_dump(new_block->host, size); |
| 1285 |
qemu_madvise(new_block->host, size, QEMU_MADV_HUGEPAGE); |
| 1286 |
qemu_madvise(new_block->host, size, QEMU_MADV_DONTFORK); |
| 1287 |
|
| 1288 |
if (kvm_enabled())
|
| 1289 |
kvm_setup_guest_memory(new_block->host, size); |
| 1290 |
|
| 1291 |
return new_block->offset;
|
| 1292 |
} |
| 1293 |
|
| 1294 |
ram_addr_t qemu_ram_alloc(ram_addr_t size, MemoryRegion *mr) |
| 1295 |
{
|
| 1296 |
return qemu_ram_alloc_from_ptr(size, NULL, mr); |
| 1297 |
} |
| 1298 |
|
| 1299 |
void qemu_ram_free_from_ptr(ram_addr_t addr)
|
| 1300 |
{
|
| 1301 |
RAMBlock *block; |
| 1302 |
|
| 1303 |
/* This assumes the iothread lock is taken here too. */
|
| 1304 |
qemu_mutex_lock_ramlist(); |
| 1305 |
QTAILQ_FOREACH(block, &ram_list.blocks, next) {
|
| 1306 |
if (addr == block->offset) {
|
| 1307 |
QTAILQ_REMOVE(&ram_list.blocks, block, next); |
| 1308 |
ram_list.mru_block = NULL;
|
| 1309 |
ram_list.version++; |
| 1310 |
g_free(block); |
| 1311 |
break;
|
| 1312 |
} |
| 1313 |
} |
| 1314 |
qemu_mutex_unlock_ramlist(); |
| 1315 |
} |
| 1316 |
|
| 1317 |
void qemu_ram_free(ram_addr_t addr)
|
| 1318 |
{
|
| 1319 |
RAMBlock *block; |
| 1320 |
|
| 1321 |
/* This assumes the iothread lock is taken here too. */
|
| 1322 |
qemu_mutex_lock_ramlist(); |
| 1323 |
QTAILQ_FOREACH(block, &ram_list.blocks, next) {
|
| 1324 |
if (addr == block->offset) {
|
| 1325 |
QTAILQ_REMOVE(&ram_list.blocks, block, next); |
| 1326 |
ram_list.mru_block = NULL;
|
| 1327 |
ram_list.version++; |
| 1328 |
if (block->flags & RAM_PREALLOC_MASK) {
|
| 1329 |
; |
| 1330 |
} else if (xen_enabled()) { |
| 1331 |
xen_invalidate_map_cache_entry(block->host); |
| 1332 |
#ifndef _WIN32
|
| 1333 |
} else if (block->fd >= 0) { |
| 1334 |
munmap(block->host, block->length); |
| 1335 |
close(block->fd); |
| 1336 |
#endif
|
| 1337 |
} else {
|
| 1338 |
qemu_anon_ram_free(block->host, block->length); |
| 1339 |
} |
| 1340 |
g_free(block); |
| 1341 |
break;
|
| 1342 |
} |
| 1343 |
} |
| 1344 |
qemu_mutex_unlock_ramlist(); |
| 1345 |
|
| 1346 |
} |
| 1347 |
|
| 1348 |
#ifndef _WIN32
|
| 1349 |
void qemu_ram_remap(ram_addr_t addr, ram_addr_t length)
|
| 1350 |
{
|
| 1351 |
RAMBlock *block; |
| 1352 |
ram_addr_t offset; |
| 1353 |
int flags;
|
| 1354 |
void *area, *vaddr;
|
| 1355 |
|
| 1356 |
QTAILQ_FOREACH(block, &ram_list.blocks, next) {
|
| 1357 |
offset = addr - block->offset; |
| 1358 |
if (offset < block->length) {
|
| 1359 |
vaddr = block->host + offset; |
| 1360 |
if (block->flags & RAM_PREALLOC_MASK) {
|
| 1361 |
; |
| 1362 |
} else if (xen_enabled()) { |
| 1363 |
abort(); |
| 1364 |
} else {
|
| 1365 |
flags = MAP_FIXED; |
| 1366 |
munmap(vaddr, length); |
| 1367 |
if (block->fd >= 0) { |
| 1368 |
#ifdef MAP_POPULATE
|
| 1369 |
flags |= mem_prealloc ? MAP_POPULATE | MAP_SHARED : |
| 1370 |
MAP_PRIVATE; |
| 1371 |
#else
|
| 1372 |
flags |= MAP_PRIVATE; |
| 1373 |
#endif
|
| 1374 |
area = mmap(vaddr, length, PROT_READ | PROT_WRITE, |
| 1375 |
flags, block->fd, offset); |
| 1376 |
} else {
|
| 1377 |
/*
|
| 1378 |
* Remap needs to match alloc. Accelerators that
|
| 1379 |
* set phys_mem_alloc never remap. If they did,
|
| 1380 |
* we'd need a remap hook here.
|
| 1381 |
*/
|
| 1382 |
assert(phys_mem_alloc == qemu_anon_ram_alloc); |
| 1383 |
|
| 1384 |
flags |= MAP_PRIVATE | MAP_ANONYMOUS; |
| 1385 |
area = mmap(vaddr, length, PROT_READ | PROT_WRITE, |
| 1386 |
flags, -1, 0); |
| 1387 |
} |
| 1388 |
if (area != vaddr) {
|
| 1389 |
fprintf(stderr, "Could not remap addr: "
|
| 1390 |
RAM_ADDR_FMT "@" RAM_ADDR_FMT "\n", |
| 1391 |
length, addr); |
| 1392 |
exit(1);
|
| 1393 |
} |
| 1394 |
memory_try_enable_merging(vaddr, length); |
| 1395 |
qemu_ram_setup_dump(vaddr, length); |
| 1396 |
} |
| 1397 |
return;
|
| 1398 |
} |
| 1399 |
} |
| 1400 |
} |
| 1401 |
#endif /* !_WIN32 */ |
| 1402 |
|
| 1403 |
/* Return a host pointer to ram allocated with qemu_ram_alloc.
|
| 1404 |
With the exception of the softmmu code in this file, this should
|
| 1405 |
only be used for local memory (e.g. video ram) that the device owns,
|
| 1406 |
and knows it isn't going to access beyond the end of the block.
|
| 1407 |
|
| 1408 |
It should not be used for general purpose DMA.
|
| 1409 |
Use cpu_physical_memory_map/cpu_physical_memory_rw instead.
|
| 1410 |
*/
|
| 1411 |
void *qemu_get_ram_ptr(ram_addr_t addr)
|
| 1412 |
{
|
| 1413 |
RAMBlock *block = qemu_get_ram_block(addr); |
| 1414 |
|
| 1415 |
if (xen_enabled()) {
|
| 1416 |
/* We need to check if the requested address is in the RAM
|
| 1417 |
* because we don't want to map the entire memory in QEMU.
|
| 1418 |
* In that case just map until the end of the page.
|
| 1419 |
*/
|
| 1420 |
if (block->offset == 0) { |
| 1421 |
return xen_map_cache(addr, 0, 0); |
| 1422 |
} else if (block->host == NULL) { |
| 1423 |
block->host = |
| 1424 |
xen_map_cache(block->offset, block->length, 1);
|
| 1425 |
} |
| 1426 |
} |
| 1427 |
return block->host + (addr - block->offset);
|
| 1428 |
} |
| 1429 |
|
| 1430 |
/* Return a host pointer to guest's ram. Similar to qemu_get_ram_ptr
|
| 1431 |
* but takes a size argument */
|
| 1432 |
static void *qemu_ram_ptr_length(ram_addr_t addr, hwaddr *size) |
| 1433 |
{
|
| 1434 |
if (*size == 0) { |
| 1435 |
return NULL; |
| 1436 |
} |
| 1437 |
if (xen_enabled()) {
|
| 1438 |
return xen_map_cache(addr, *size, 1); |
| 1439 |
} else {
|
| 1440 |
RAMBlock *block; |
| 1441 |
|
| 1442 |
QTAILQ_FOREACH(block, &ram_list.blocks, next) {
|
| 1443 |
if (addr - block->offset < block->length) {
|
| 1444 |
if (addr - block->offset + *size > block->length)
|
| 1445 |
*size = block->length - addr + block->offset; |
| 1446 |
return block->host + (addr - block->offset);
|
| 1447 |
} |
| 1448 |
} |
| 1449 |
|
| 1450 |
fprintf(stderr, "Bad ram offset %" PRIx64 "\n", (uint64_t)addr); |
| 1451 |
abort(); |
| 1452 |
} |
| 1453 |
} |
| 1454 |
|
| 1455 |
/* Some of the softmmu routines need to translate from a host pointer
|
| 1456 |
(typically a TLB entry) back to a ram offset. */
|
| 1457 |
MemoryRegion *qemu_ram_addr_from_host(void *ptr, ram_addr_t *ram_addr)
|
| 1458 |
{
|
| 1459 |
RAMBlock *block; |
| 1460 |
uint8_t *host = ptr; |
| 1461 |
|
| 1462 |
if (xen_enabled()) {
|
| 1463 |
*ram_addr = xen_ram_addr_from_mapcache(ptr); |
| 1464 |
return qemu_get_ram_block(*ram_addr)->mr;
|
| 1465 |
} |
| 1466 |
|
| 1467 |
block = ram_list.mru_block; |
| 1468 |
if (block && block->host && host - block->host < block->length) {
|
| 1469 |
goto found;
|
| 1470 |
} |
| 1471 |
|
| 1472 |
QTAILQ_FOREACH(block, &ram_list.blocks, next) {
|
| 1473 |
/* This case append when the block is not mapped. */
|
| 1474 |
if (block->host == NULL) { |
| 1475 |
continue;
|
| 1476 |
} |
| 1477 |
if (host - block->host < block->length) {
|
| 1478 |
goto found;
|
| 1479 |
} |
| 1480 |
} |
| 1481 |
|
| 1482 |
return NULL; |
| 1483 |
|
| 1484 |
found:
|
| 1485 |
*ram_addr = block->offset + (host - block->host); |
| 1486 |
return block->mr;
|
| 1487 |
} |
| 1488 |
|
| 1489 |
static void notdirty_mem_write(void *opaque, hwaddr ram_addr, |
| 1490 |
uint64_t val, unsigned size)
|
| 1491 |
{
|
| 1492 |
if (!cpu_physical_memory_get_dirty_flag(ram_addr, DIRTY_MEMORY_CODE)) {
|
| 1493 |
tb_invalidate_phys_page_fast(ram_addr, size); |
| 1494 |
} |
| 1495 |
switch (size) {
|
| 1496 |
case 1: |
| 1497 |
stb_p(qemu_get_ram_ptr(ram_addr), val); |
| 1498 |
break;
|
| 1499 |
case 2: |
| 1500 |
stw_p(qemu_get_ram_ptr(ram_addr), val); |
| 1501 |
break;
|
| 1502 |
case 4: |
| 1503 |
stl_p(qemu_get_ram_ptr(ram_addr), val); |
| 1504 |
break;
|
| 1505 |
default:
|
| 1506 |
abort(); |
| 1507 |
} |
| 1508 |
cpu_physical_memory_set_dirty_flag(ram_addr, DIRTY_MEMORY_MIGRATION); |
| 1509 |
cpu_physical_memory_set_dirty_flag(ram_addr, DIRTY_MEMORY_VGA); |
| 1510 |
/* we remove the notdirty callback only if the code has been
|
| 1511 |
flushed */
|
| 1512 |
if (!cpu_physical_memory_is_clean(ram_addr)) {
|
| 1513 |
CPUArchState *env = current_cpu->env_ptr; |
| 1514 |
tlb_set_dirty(env, env->mem_io_vaddr); |
| 1515 |
} |
| 1516 |
} |
| 1517 |
|
| 1518 |
static bool notdirty_mem_accepts(void *opaque, hwaddr addr, |
| 1519 |
unsigned size, bool is_write) |
| 1520 |
{
|
| 1521 |
return is_write;
|
| 1522 |
} |
| 1523 |
|
| 1524 |
static const MemoryRegionOps notdirty_mem_ops = { |
| 1525 |
.write = notdirty_mem_write, |
| 1526 |
.valid.accepts = notdirty_mem_accepts, |
| 1527 |
.endianness = DEVICE_NATIVE_ENDIAN, |
| 1528 |
}; |
| 1529 |
|
| 1530 |
/* Generate a debug exception if a watchpoint has been hit. */
|
| 1531 |
static void check_watchpoint(int offset, int len_mask, int flags) |
| 1532 |
{
|
| 1533 |
CPUArchState *env = current_cpu->env_ptr; |
| 1534 |
target_ulong pc, cs_base; |
| 1535 |
target_ulong vaddr; |
| 1536 |
CPUWatchpoint *wp; |
| 1537 |
int cpu_flags;
|
| 1538 |
|
| 1539 |
if (env->watchpoint_hit) {
|
| 1540 |
/* We re-entered the check after replacing the TB. Now raise
|
| 1541 |
* the debug interrupt so that is will trigger after the
|
| 1542 |
* current instruction. */
|
| 1543 |
cpu_interrupt(ENV_GET_CPU(env), CPU_INTERRUPT_DEBUG); |
| 1544 |
return;
|
| 1545 |
} |
| 1546 |
vaddr = (env->mem_io_vaddr & TARGET_PAGE_MASK) + offset; |
| 1547 |
QTAILQ_FOREACH(wp, &env->watchpoints, entry) {
|
| 1548 |
if ((vaddr == (wp->vaddr & len_mask) ||
|
| 1549 |
(vaddr & wp->len_mask) == wp->vaddr) && (wp->flags & flags)) {
|
| 1550 |
wp->flags |= BP_WATCHPOINT_HIT; |
| 1551 |
if (!env->watchpoint_hit) {
|
| 1552 |
env->watchpoint_hit = wp; |
| 1553 |
tb_check_watchpoint(env); |
| 1554 |
if (wp->flags & BP_STOP_BEFORE_ACCESS) {
|
| 1555 |
env->exception_index = EXCP_DEBUG; |
| 1556 |
cpu_loop_exit(env); |
| 1557 |
} else {
|
| 1558 |
cpu_get_tb_cpu_state(env, &pc, &cs_base, &cpu_flags); |
| 1559 |
tb_gen_code(env, pc, cs_base, cpu_flags, 1);
|
| 1560 |
cpu_resume_from_signal(env, NULL);
|
| 1561 |
} |
| 1562 |
} |
| 1563 |
} else {
|
| 1564 |
wp->flags &= ~BP_WATCHPOINT_HIT; |
| 1565 |
} |
| 1566 |
} |
| 1567 |
} |
| 1568 |
|
| 1569 |
/* Watchpoint access routines. Watchpoints are inserted using TLB tricks,
|
| 1570 |
so these check for a hit then pass through to the normal out-of-line
|
| 1571 |
phys routines. */
|
| 1572 |
static uint64_t watch_mem_read(void *opaque, hwaddr addr, |
| 1573 |
unsigned size)
|
| 1574 |
{
|
| 1575 |
check_watchpoint(addr & ~TARGET_PAGE_MASK, ~(size - 1), BP_MEM_READ);
|
| 1576 |
switch (size) {
|
| 1577 |
case 1: return ldub_phys(addr); |
| 1578 |
case 2: return lduw_phys(addr); |
| 1579 |
case 4: return ldl_phys(addr); |
| 1580 |
default: abort();
|
| 1581 |
} |
| 1582 |
} |
| 1583 |
|
| 1584 |
static void watch_mem_write(void *opaque, hwaddr addr, |
| 1585 |
uint64_t val, unsigned size)
|
| 1586 |
{
|
| 1587 |
check_watchpoint(addr & ~TARGET_PAGE_MASK, ~(size - 1), BP_MEM_WRITE);
|
| 1588 |
switch (size) {
|
| 1589 |
case 1: |
| 1590 |
stb_phys(addr, val); |
| 1591 |
break;
|
| 1592 |
case 2: |
| 1593 |
stw_phys(addr, val); |
| 1594 |
break;
|
| 1595 |
case 4: |
| 1596 |
stl_phys(addr, val); |
| 1597 |
break;
|
| 1598 |
default: abort();
|
| 1599 |
} |
| 1600 |
} |
| 1601 |
|
| 1602 |
static const MemoryRegionOps watch_mem_ops = { |
| 1603 |
.read = watch_mem_read, |
| 1604 |
.write = watch_mem_write, |
| 1605 |
.endianness = DEVICE_NATIVE_ENDIAN, |
| 1606 |
}; |
| 1607 |
|
| 1608 |
static uint64_t subpage_read(void *opaque, hwaddr addr, |
| 1609 |
unsigned len)
|
| 1610 |
{
|
| 1611 |
subpage_t *subpage = opaque; |
| 1612 |
uint8_t buf[4];
|
| 1613 |
|
| 1614 |
#if defined(DEBUG_SUBPAGE)
|
| 1615 |
printf("%s: subpage %p len %u addr " TARGET_FMT_plx "\n", __func__, |
| 1616 |
subpage, len, addr); |
| 1617 |
#endif
|
| 1618 |
address_space_read(subpage->as, addr + subpage->base, buf, len); |
| 1619 |
switch (len) {
|
| 1620 |
case 1: |
| 1621 |
return ldub_p(buf);
|
| 1622 |
case 2: |
| 1623 |
return lduw_p(buf);
|
| 1624 |
case 4: |
| 1625 |
return ldl_p(buf);
|
| 1626 |
default:
|
| 1627 |
abort(); |
| 1628 |
} |
| 1629 |
} |
| 1630 |
|
| 1631 |
static void subpage_write(void *opaque, hwaddr addr, |
| 1632 |
uint64_t value, unsigned len)
|
| 1633 |
{
|
| 1634 |
subpage_t *subpage = opaque; |
| 1635 |
uint8_t buf[4];
|
| 1636 |
|
| 1637 |
#if defined(DEBUG_SUBPAGE)
|
| 1638 |
printf("%s: subpage %p len %u addr " TARGET_FMT_plx
|
| 1639 |
" value %"PRIx64"\n", |
| 1640 |
__func__, subpage, len, addr, value); |
| 1641 |
#endif
|
| 1642 |
switch (len) {
|
| 1643 |
case 1: |
| 1644 |
stb_p(buf, value); |
| 1645 |
break;
|
| 1646 |
case 2: |
| 1647 |
stw_p(buf, value); |
| 1648 |
break;
|
| 1649 |
case 4: |
| 1650 |
stl_p(buf, value); |
| 1651 |
break;
|
| 1652 |
default:
|
| 1653 |
abort(); |
| 1654 |
} |
| 1655 |
address_space_write(subpage->as, addr + subpage->base, buf, len); |
| 1656 |
} |
| 1657 |
|
| 1658 |
static bool subpage_accepts(void *opaque, hwaddr addr, |
| 1659 |
unsigned len, bool is_write) |
| 1660 |
{
|
| 1661 |
subpage_t *subpage = opaque; |
| 1662 |
#if defined(DEBUG_SUBPAGE)
|
| 1663 |
printf("%s: subpage %p %c len %u addr " TARGET_FMT_plx "\n", |
| 1664 |
__func__, subpage, is_write ? 'w' : 'r', len, addr); |
| 1665 |
#endif
|
| 1666 |
|
| 1667 |
return address_space_access_valid(subpage->as, addr + subpage->base,
|
| 1668 |
len, is_write); |
| 1669 |
} |
| 1670 |
|
| 1671 |
static const MemoryRegionOps subpage_ops = { |
| 1672 |
.read = subpage_read, |
| 1673 |
.write = subpage_write, |
| 1674 |
.valid.accepts = subpage_accepts, |
| 1675 |
.endianness = DEVICE_NATIVE_ENDIAN, |
| 1676 |
}; |
| 1677 |
|
| 1678 |
static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end, |
| 1679 |
uint16_t section) |
| 1680 |
{
|
| 1681 |
int idx, eidx;
|
| 1682 |
|
| 1683 |
if (start >= TARGET_PAGE_SIZE || end >= TARGET_PAGE_SIZE)
|
| 1684 |
return -1; |
| 1685 |
idx = SUBPAGE_IDX(start); |
| 1686 |
eidx = SUBPAGE_IDX(end); |
| 1687 |
#if defined(DEBUG_SUBPAGE)
|
| 1688 |
printf("%s: %p start %08x end %08x idx %08x eidx %08x section %d\n",
|
| 1689 |
__func__, mmio, start, end, idx, eidx, section); |
| 1690 |
#endif
|
| 1691 |
for (; idx <= eidx; idx++) {
|
| 1692 |
mmio->sub_section[idx] = section; |
| 1693 |
} |
| 1694 |
|
| 1695 |
return 0; |
| 1696 |
} |
| 1697 |
|
| 1698 |
static subpage_t *subpage_init(AddressSpace *as, hwaddr base)
|
| 1699 |
{
|
| 1700 |
subpage_t *mmio; |
| 1701 |
|
| 1702 |
mmio = g_malloc0(sizeof(subpage_t));
|
| 1703 |
|
| 1704 |
mmio->as = as; |
| 1705 |
mmio->base = base; |
| 1706 |
memory_region_init_io(&mmio->iomem, NULL, &subpage_ops, mmio,
|
| 1707 |
"subpage", TARGET_PAGE_SIZE);
|
| 1708 |
mmio->iomem.subpage = true;
|
| 1709 |
#if defined(DEBUG_SUBPAGE)
|
| 1710 |
printf("%s: %p base " TARGET_FMT_plx " len %08x\n", __func__, |
| 1711 |
mmio, base, TARGET_PAGE_SIZE); |
| 1712 |
#endif
|
| 1713 |
subpage_register(mmio, 0, TARGET_PAGE_SIZE-1, PHYS_SECTION_UNASSIGNED); |
| 1714 |
|
| 1715 |
return mmio;
|
| 1716 |
} |
| 1717 |
|
| 1718 |
static uint16_t dummy_section(PhysPageMap *map, MemoryRegion *mr)
|
| 1719 |
{
|
| 1720 |
MemoryRegionSection section = {
|
| 1721 |
.mr = mr, |
| 1722 |
.offset_within_address_space = 0,
|
| 1723 |
.offset_within_region = 0,
|
| 1724 |
.size = int128_2_64(), |
| 1725 |
}; |
| 1726 |
|
| 1727 |
return phys_section_add(map, §ion);
|
| 1728 |
} |
| 1729 |
|
| 1730 |
MemoryRegion *iotlb_to_region(hwaddr index) |
| 1731 |
{
|
| 1732 |
return address_space_memory.dispatch->map.sections[
|
| 1733 |
index & ~TARGET_PAGE_MASK].mr; |
| 1734 |
} |
| 1735 |
|
| 1736 |
static void io_mem_init(void) |
| 1737 |
{
|
| 1738 |
memory_region_init_io(&io_mem_rom, NULL, &unassigned_mem_ops, NULL, "rom", UINT64_MAX); |
| 1739 |
memory_region_init_io(&io_mem_unassigned, NULL, &unassigned_mem_ops, NULL, |
| 1740 |
"unassigned", UINT64_MAX);
|
| 1741 |
memory_region_init_io(&io_mem_notdirty, NULL, ¬dirty_mem_ops, NULL, |
| 1742 |
"notdirty", UINT64_MAX);
|
| 1743 |
memory_region_init_io(&io_mem_watch, NULL, &watch_mem_ops, NULL, |
| 1744 |
"watch", UINT64_MAX);
|
| 1745 |
} |
| 1746 |
|
| 1747 |
static void mem_begin(MemoryListener *listener) |
| 1748 |
{
|
| 1749 |
AddressSpace *as = container_of(listener, AddressSpace, dispatch_listener); |
| 1750 |
AddressSpaceDispatch *d = g_new0(AddressSpaceDispatch, 1);
|
| 1751 |
uint16_t n; |
| 1752 |
|
| 1753 |
n = dummy_section(&d->map, &io_mem_unassigned); |
| 1754 |
assert(n == PHYS_SECTION_UNASSIGNED); |
| 1755 |
n = dummy_section(&d->map, &io_mem_notdirty); |
| 1756 |
assert(n == PHYS_SECTION_NOTDIRTY); |
| 1757 |
n = dummy_section(&d->map, &io_mem_rom); |
| 1758 |
assert(n == PHYS_SECTION_ROM); |
| 1759 |
n = dummy_section(&d->map, &io_mem_watch); |
| 1760 |
assert(n == PHYS_SECTION_WATCH); |
| 1761 |
|
| 1762 |
d->phys_map = (PhysPageEntry) { .ptr = PHYS_MAP_NODE_NIL, .skip = 1 };
|
| 1763 |
d->as = as; |
| 1764 |
as->next_dispatch = d; |
| 1765 |
} |
| 1766 |
|
| 1767 |
static void mem_commit(MemoryListener *listener) |
| 1768 |
{
|
| 1769 |
AddressSpace *as = container_of(listener, AddressSpace, dispatch_listener); |
| 1770 |
AddressSpaceDispatch *cur = as->dispatch; |
| 1771 |
AddressSpaceDispatch *next = as->next_dispatch; |
| 1772 |
|
| 1773 |
phys_page_compact_all(next, next->map.nodes_nb); |
| 1774 |
|
| 1775 |
as->dispatch = next; |
| 1776 |
|
| 1777 |
if (cur) {
|
| 1778 |
phys_sections_free(&cur->map); |
| 1779 |
g_free(cur); |
| 1780 |
} |
| 1781 |
} |
| 1782 |
|
| 1783 |
static void tcg_commit(MemoryListener *listener) |
| 1784 |
{
|
| 1785 |
CPUState *cpu; |
| 1786 |
|
| 1787 |
/* since each CPU stores ram addresses in its TLB cache, we must
|
| 1788 |
reset the modified entries */
|
| 1789 |
/* XXX: slow ! */
|
| 1790 |
CPU_FOREACH(cpu) {
|
| 1791 |
CPUArchState *env = cpu->env_ptr; |
| 1792 |
|
| 1793 |
tlb_flush(env, 1);
|
| 1794 |
} |
| 1795 |
} |
| 1796 |
|
| 1797 |
static void core_log_global_start(MemoryListener *listener) |
| 1798 |
{
|
| 1799 |
cpu_physical_memory_set_dirty_tracking(true);
|
| 1800 |
} |
| 1801 |
|
| 1802 |
static void core_log_global_stop(MemoryListener *listener) |
| 1803 |
{
|
| 1804 |
cpu_physical_memory_set_dirty_tracking(false);
|
| 1805 |
} |
| 1806 |
|
| 1807 |
static MemoryListener core_memory_listener = {
|
| 1808 |
.log_global_start = core_log_global_start, |
| 1809 |
.log_global_stop = core_log_global_stop, |
| 1810 |
.priority = 1,
|
| 1811 |
}; |
| 1812 |
|
| 1813 |
static MemoryListener tcg_memory_listener = {
|
| 1814 |
.commit = tcg_commit, |
| 1815 |
}; |
| 1816 |
|
| 1817 |
void address_space_init_dispatch(AddressSpace *as)
|
| 1818 |
{
|
| 1819 |
as->dispatch = NULL;
|
| 1820 |
as->dispatch_listener = (MemoryListener) {
|
| 1821 |
.begin = mem_begin, |
| 1822 |
.commit = mem_commit, |
| 1823 |
.region_add = mem_add, |
| 1824 |
.region_nop = mem_add, |
| 1825 |
.priority = 0,
|
| 1826 |
}; |
| 1827 |
memory_listener_register(&as->dispatch_listener, as); |
| 1828 |
} |
| 1829 |
|
| 1830 |
void address_space_destroy_dispatch(AddressSpace *as)
|
| 1831 |
{
|
| 1832 |
AddressSpaceDispatch *d = as->dispatch; |
| 1833 |
|
| 1834 |
memory_listener_unregister(&as->dispatch_listener); |
| 1835 |
g_free(d); |
| 1836 |
as->dispatch = NULL;
|
| 1837 |
} |
| 1838 |
|
| 1839 |
static void memory_map_init(void) |
| 1840 |
{
|
| 1841 |
system_memory = g_malloc(sizeof(*system_memory));
|
| 1842 |
|
| 1843 |
memory_region_init(system_memory, NULL, "system", UINT64_MAX); |
| 1844 |
address_space_init(&address_space_memory, system_memory, "memory");
|
| 1845 |
|
| 1846 |
system_io = g_malloc(sizeof(*system_io));
|
| 1847 |
memory_region_init_io(system_io, NULL, &unassigned_io_ops, NULL, "io", |
| 1848 |
65536);
|
| 1849 |
address_space_init(&address_space_io, system_io, "I/O");
|
| 1850 |
|
| 1851 |
memory_listener_register(&core_memory_listener, &address_space_memory); |
| 1852 |
if (tcg_enabled()) {
|
| 1853 |
memory_listener_register(&tcg_memory_listener, &address_space_memory); |
| 1854 |
} |
| 1855 |
} |
| 1856 |
|
| 1857 |
MemoryRegion *get_system_memory(void)
|
| 1858 |
{
|
| 1859 |
return system_memory;
|
| 1860 |
} |
| 1861 |
|
| 1862 |
MemoryRegion *get_system_io(void)
|
| 1863 |
{
|
| 1864 |
return system_io;
|
| 1865 |
} |
| 1866 |
|
| 1867 |
#endif /* !defined(CONFIG_USER_ONLY) */ |
| 1868 |
|
| 1869 |
/* physical memory access (slow version, mainly for debug) */
|
| 1870 |
#if defined(CONFIG_USER_ONLY)
|
| 1871 |
int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
|
| 1872 |
uint8_t *buf, int len, int is_write) |
| 1873 |
{
|
| 1874 |
int l, flags;
|
| 1875 |
target_ulong page; |
| 1876 |
void * p;
|
| 1877 |
|
| 1878 |
while (len > 0) { |
| 1879 |
page = addr & TARGET_PAGE_MASK; |
| 1880 |
l = (page + TARGET_PAGE_SIZE) - addr; |
| 1881 |
if (l > len)
|
| 1882 |
l = len; |
| 1883 |
flags = page_get_flags(page); |
| 1884 |
if (!(flags & PAGE_VALID))
|
| 1885 |
return -1; |
| 1886 |
if (is_write) {
|
| 1887 |
if (!(flags & PAGE_WRITE))
|
| 1888 |
return -1; |
| 1889 |
/* XXX: this code should not depend on lock_user */
|
| 1890 |
if (!(p = lock_user(VERIFY_WRITE, addr, l, 0))) |
| 1891 |
return -1; |
| 1892 |
memcpy(p, buf, l); |
| 1893 |
unlock_user(p, addr, l); |
| 1894 |
} else {
|
| 1895 |
if (!(flags & PAGE_READ))
|
| 1896 |
return -1; |
| 1897 |
/* XXX: this code should not depend on lock_user */
|
| 1898 |
if (!(p = lock_user(VERIFY_READ, addr, l, 1))) |
| 1899 |
return -1; |
| 1900 |
memcpy(buf, p, l); |
| 1901 |
unlock_user(p, addr, 0);
|
| 1902 |
} |
| 1903 |
len -= l; |
| 1904 |
buf += l; |
| 1905 |
addr += l; |
| 1906 |
} |
| 1907 |
return 0; |
| 1908 |
} |
| 1909 |
|
| 1910 |
#else
|
| 1911 |
|
| 1912 |
static void invalidate_and_set_dirty(hwaddr addr, |
| 1913 |
hwaddr length) |
| 1914 |
{
|
| 1915 |
if (cpu_physical_memory_is_clean(addr)) {
|
| 1916 |
/* invalidate code */
|
| 1917 |
tb_invalidate_phys_page_range(addr, addr + length, 0);
|
| 1918 |
/* set dirty bit */
|
| 1919 |
cpu_physical_memory_set_dirty_flag(addr, DIRTY_MEMORY_VGA); |
| 1920 |
cpu_physical_memory_set_dirty_flag(addr, DIRTY_MEMORY_MIGRATION); |
| 1921 |
} |
| 1922 |
xen_modified_memory(addr, length); |
| 1923 |
} |
| 1924 |
|
| 1925 |
static inline bool memory_access_is_direct(MemoryRegion *mr, bool is_write) |
| 1926 |
{
|
| 1927 |
if (memory_region_is_ram(mr)) {
|
| 1928 |
return !(is_write && mr->readonly);
|
| 1929 |
} |
| 1930 |
if (memory_region_is_romd(mr)) {
|
| 1931 |
return !is_write;
|
| 1932 |
} |
| 1933 |
|
| 1934 |
return false; |
| 1935 |
} |
| 1936 |
|
| 1937 |
static int memory_access_size(MemoryRegion *mr, unsigned l, hwaddr addr) |
| 1938 |
{
|
| 1939 |
unsigned access_size_max = mr->ops->valid.max_access_size;
|
| 1940 |
|
| 1941 |
/* Regions are assumed to support 1-4 byte accesses unless
|
| 1942 |
otherwise specified. */
|
| 1943 |
if (access_size_max == 0) { |
| 1944 |
access_size_max = 4;
|
| 1945 |
} |
| 1946 |
|
| 1947 |
/* Bound the maximum access by the alignment of the address. */
|
| 1948 |
if (!mr->ops->impl.unaligned) {
|
| 1949 |
unsigned align_size_max = addr & -addr;
|
| 1950 |
if (align_size_max != 0 && align_size_max < access_size_max) { |
| 1951 |
access_size_max = align_size_max; |
| 1952 |
} |
| 1953 |
} |
| 1954 |
|
| 1955 |
/* Don't attempt accesses larger than the maximum. */
|
| 1956 |
if (l > access_size_max) {
|
| 1957 |
l = access_size_max; |
| 1958 |
} |
| 1959 |
if (l & (l - 1)) { |
| 1960 |
l = 1 << (qemu_fls(l) - 1); |
| 1961 |
} |
| 1962 |
|
| 1963 |
return l;
|
| 1964 |
} |
| 1965 |
|
| 1966 |
bool address_space_rw(AddressSpace *as, hwaddr addr, uint8_t *buf,
|
| 1967 |
int len, bool is_write) |
| 1968 |
{
|
| 1969 |
hwaddr l; |
| 1970 |
uint8_t *ptr; |
| 1971 |
uint64_t val; |
| 1972 |
hwaddr addr1; |
| 1973 |
MemoryRegion *mr; |
| 1974 |
bool error = false; |
| 1975 |
|
| 1976 |
while (len > 0) { |
| 1977 |
l = len; |
| 1978 |
mr = address_space_translate(as, addr, &addr1, &l, is_write); |
| 1979 |
|
| 1980 |
if (is_write) {
|
| 1981 |
if (!memory_access_is_direct(mr, is_write)) {
|
| 1982 |
l = memory_access_size(mr, l, addr1); |
| 1983 |
/* XXX: could force current_cpu to NULL to avoid
|
| 1984 |
potential bugs */
|
| 1985 |
switch (l) {
|
| 1986 |
case 8: |
| 1987 |
/* 64 bit write access */
|
| 1988 |
val = ldq_p(buf); |
| 1989 |
error |= io_mem_write(mr, addr1, val, 8);
|
| 1990 |
break;
|
| 1991 |
case 4: |
| 1992 |
/* 32 bit write access */
|
| 1993 |
val = ldl_p(buf); |
| 1994 |
error |= io_mem_write(mr, addr1, val, 4);
|
| 1995 |
break;
|
| 1996 |
case 2: |
| 1997 |
/* 16 bit write access */
|
| 1998 |
val = lduw_p(buf); |
| 1999 |
error |= io_mem_write(mr, addr1, val, 2);
|
| 2000 |
break;
|
| 2001 |
case 1: |
| 2002 |
/* 8 bit write access */
|
| 2003 |
val = ldub_p(buf); |
| 2004 |
error |= io_mem_write(mr, addr1, val, 1);
|
| 2005 |
break;
|
| 2006 |
default:
|
| 2007 |
abort(); |
| 2008 |
} |
| 2009 |
} else {
|
| 2010 |
addr1 += memory_region_get_ram_addr(mr); |
| 2011 |
/* RAM case */
|
| 2012 |
ptr = qemu_get_ram_ptr(addr1); |
| 2013 |
memcpy(ptr, buf, l); |
| 2014 |
invalidate_and_set_dirty(addr1, l); |
| 2015 |
} |
| 2016 |
} else {
|
| 2017 |
if (!memory_access_is_direct(mr, is_write)) {
|
| 2018 |
/* I/O case */
|
| 2019 |
l = memory_access_size(mr, l, addr1); |
| 2020 |
switch (l) {
|
| 2021 |
case 8: |
| 2022 |
/* 64 bit read access */
|
| 2023 |
error |= io_mem_read(mr, addr1, &val, 8);
|
| 2024 |
stq_p(buf, val); |
| 2025 |
break;
|
| 2026 |
case 4: |
| 2027 |
/* 32 bit read access */
|
| 2028 |
error |= io_mem_read(mr, addr1, &val, 4);
|
| 2029 |
stl_p(buf, val); |
| 2030 |
break;
|
| 2031 |
case 2: |
| 2032 |
/* 16 bit read access */
|
| 2033 |
error |= io_mem_read(mr, addr1, &val, 2);
|
| 2034 |
stw_p(buf, val); |
| 2035 |
break;
|
| 2036 |
case 1: |
| 2037 |
/* 8 bit read access */
|
| 2038 |
error |= io_mem_read(mr, addr1, &val, 1);
|
| 2039 |
stb_p(buf, val); |
| 2040 |
break;
|
| 2041 |
default:
|
| 2042 |
abort(); |
| 2043 |
} |
| 2044 |
} else {
|
| 2045 |
/* RAM case */
|
| 2046 |
ptr = qemu_get_ram_ptr(mr->ram_addr + addr1); |
| 2047 |
memcpy(buf, ptr, l); |
| 2048 |
} |
| 2049 |
} |
| 2050 |
len -= l; |
| 2051 |
buf += l; |
| 2052 |
addr += l; |
| 2053 |
} |
| 2054 |
|
| 2055 |
return error;
|
| 2056 |
} |
| 2057 |
|
| 2058 |
bool address_space_write(AddressSpace *as, hwaddr addr,
|
| 2059 |
const uint8_t *buf, int len) |
| 2060 |
{
|
| 2061 |
return address_space_rw(as, addr, (uint8_t *)buf, len, true); |
| 2062 |
} |
| 2063 |
|
| 2064 |
bool address_space_read(AddressSpace *as, hwaddr addr, uint8_t *buf, int len) |
| 2065 |
{
|
| 2066 |
return address_space_rw(as, addr, buf, len, false); |
| 2067 |
} |
| 2068 |
|
| 2069 |
|
| 2070 |
void cpu_physical_memory_rw(hwaddr addr, uint8_t *buf,
|
| 2071 |
int len, int is_write) |
| 2072 |
{
|
| 2073 |
address_space_rw(&address_space_memory, addr, buf, len, is_write); |
| 2074 |
} |
| 2075 |
|
| 2076 |
enum write_rom_type {
|
| 2077 |
WRITE_DATA, |
| 2078 |
FLUSH_CACHE, |
| 2079 |
}; |
| 2080 |
|
| 2081 |
static inline void cpu_physical_memory_write_rom_internal( |
| 2082 |
hwaddr addr, const uint8_t *buf, int len, enum write_rom_type type) |
| 2083 |
{
|
| 2084 |
hwaddr l; |
| 2085 |
uint8_t *ptr; |
| 2086 |
hwaddr addr1; |
| 2087 |
MemoryRegion *mr; |
| 2088 |
|
| 2089 |
while (len > 0) { |
| 2090 |
l = len; |
| 2091 |
mr = address_space_translate(&address_space_memory, |
| 2092 |
addr, &addr1, &l, true);
|
| 2093 |
|
| 2094 |
if (!(memory_region_is_ram(mr) ||
|
| 2095 |
memory_region_is_romd(mr))) {
|
| 2096 |
/* do nothing */
|
| 2097 |
} else {
|
| 2098 |
addr1 += memory_region_get_ram_addr(mr); |
| 2099 |
/* ROM/RAM case */
|
| 2100 |
ptr = qemu_get_ram_ptr(addr1); |
| 2101 |
switch (type) {
|
| 2102 |
case WRITE_DATA:
|
| 2103 |
memcpy(ptr, buf, l); |
| 2104 |
invalidate_and_set_dirty(addr1, l); |
| 2105 |
break;
|
| 2106 |
case FLUSH_CACHE:
|
| 2107 |
flush_icache_range((uintptr_t)ptr, (uintptr_t)ptr + l); |
| 2108 |
break;
|
| 2109 |
} |
| 2110 |
} |
| 2111 |
len -= l; |
| 2112 |
buf += l; |
| 2113 |
addr += l; |
| 2114 |
} |
| 2115 |
} |
| 2116 |
|
| 2117 |
/* used for ROM loading : can write in RAM and ROM */
|
| 2118 |
void cpu_physical_memory_write_rom(hwaddr addr,
|
| 2119 |
const uint8_t *buf, int len) |
| 2120 |
{
|
| 2121 |
cpu_physical_memory_write_rom_internal(addr, buf, len, WRITE_DATA); |
| 2122 |
} |
| 2123 |
|
| 2124 |
void cpu_flush_icache_range(hwaddr start, int len) |
| 2125 |
{
|
| 2126 |
/*
|
| 2127 |
* This function should do the same thing as an icache flush that was
|
| 2128 |
* triggered from within the guest. For TCG we are always cache coherent,
|
| 2129 |
* so there is no need to flush anything. For KVM / Xen we need to flush
|
| 2130 |
* the host's instruction cache at least.
|
| 2131 |
*/
|
| 2132 |
if (tcg_enabled()) {
|
| 2133 |
return;
|
| 2134 |
} |
| 2135 |
|
| 2136 |
cpu_physical_memory_write_rom_internal(start, NULL, len, FLUSH_CACHE);
|
| 2137 |
} |
| 2138 |
|
| 2139 |
typedef struct { |
| 2140 |
MemoryRegion *mr; |
| 2141 |
void *buffer;
|
| 2142 |
hwaddr addr; |
| 2143 |
hwaddr len; |
| 2144 |
} BounceBuffer; |
| 2145 |
|
| 2146 |
static BounceBuffer bounce;
|
| 2147 |
|
| 2148 |
typedef struct MapClient { |
| 2149 |
void *opaque;
|
| 2150 |
void (*callback)(void *opaque); |
| 2151 |
QLIST_ENTRY(MapClient) link; |
| 2152 |
} MapClient; |
| 2153 |
|
| 2154 |
static QLIST_HEAD(map_client_list, MapClient) map_client_list
|
| 2155 |
= QLIST_HEAD_INITIALIZER(map_client_list); |
| 2156 |
|
| 2157 |
void *cpu_register_map_client(void *opaque, void (*callback)(void *opaque)) |
| 2158 |
{
|
| 2159 |
MapClient *client = g_malloc(sizeof(*client));
|
| 2160 |
|
| 2161 |
client->opaque = opaque; |
| 2162 |
client->callback = callback; |
| 2163 |
QLIST_INSERT_HEAD(&map_client_list, client, link); |
| 2164 |
return client;
|
| 2165 |
} |
| 2166 |
|
| 2167 |
static void cpu_unregister_map_client(void *_client) |
| 2168 |
{
|
| 2169 |
MapClient *client = (MapClient *)_client; |
| 2170 |
|
| 2171 |
QLIST_REMOVE(client, link); |
| 2172 |
g_free(client); |
| 2173 |
} |
| 2174 |
|
| 2175 |
static void cpu_notify_map_clients(void) |
| 2176 |
{
|
| 2177 |
MapClient *client; |
| 2178 |
|
| 2179 |
while (!QLIST_EMPTY(&map_client_list)) {
|
| 2180 |
client = QLIST_FIRST(&map_client_list); |
| 2181 |
client->callback(client->opaque); |
| 2182 |
cpu_unregister_map_client(client); |
| 2183 |
} |
| 2184 |
} |
| 2185 |
|
| 2186 |
bool address_space_access_valid(AddressSpace *as, hwaddr addr, int len, bool is_write) |
| 2187 |
{
|
| 2188 |
MemoryRegion *mr; |
| 2189 |
hwaddr l, xlat; |
| 2190 |
|
| 2191 |
while (len > 0) { |
| 2192 |
l = len; |
| 2193 |
mr = address_space_translate(as, addr, &xlat, &l, is_write); |
| 2194 |
if (!memory_access_is_direct(mr, is_write)) {
|
| 2195 |
l = memory_access_size(mr, l, addr); |
| 2196 |
if (!memory_region_access_valid(mr, xlat, l, is_write)) {
|
| 2197 |
return false; |
| 2198 |
} |
| 2199 |
} |
| 2200 |
|
| 2201 |
len -= l; |
| 2202 |
addr += l; |
| 2203 |
} |
| 2204 |
return true; |
| 2205 |
} |
| 2206 |
|
| 2207 |
/* Map a physical memory region into a host virtual address.
|
| 2208 |
* May map a subset of the requested range, given by and returned in *plen.
|
| 2209 |
* May return NULL if resources needed to perform the mapping are exhausted.
|
| 2210 |
* Use only for reads OR writes - not for read-modify-write operations.
|
| 2211 |
* Use cpu_register_map_client() to know when retrying the map operation is
|
| 2212 |
* likely to succeed.
|
| 2213 |
*/
|
| 2214 |
void *address_space_map(AddressSpace *as,
|
| 2215 |
hwaddr addr, |
| 2216 |
hwaddr *plen, |
| 2217 |
bool is_write)
|
| 2218 |
{
|
| 2219 |
hwaddr len = *plen; |
| 2220 |
hwaddr done = 0;
|
| 2221 |
hwaddr l, xlat, base; |
| 2222 |
MemoryRegion *mr, *this_mr; |
| 2223 |
ram_addr_t raddr; |
| 2224 |
|
| 2225 |
if (len == 0) { |
| 2226 |
return NULL; |
| 2227 |
} |
| 2228 |
|
| 2229 |
l = len; |
| 2230 |
mr = address_space_translate(as, addr, &xlat, &l, is_write); |
| 2231 |
if (!memory_access_is_direct(mr, is_write)) {
|
| 2232 |
if (bounce.buffer) {
|
| 2233 |
return NULL; |
| 2234 |
} |
| 2235 |
/* Avoid unbounded allocations */
|
| 2236 |
l = MIN(l, TARGET_PAGE_SIZE); |
| 2237 |
bounce.buffer = qemu_memalign(TARGET_PAGE_SIZE, l); |
| 2238 |
bounce.addr = addr; |
| 2239 |
bounce.len = l; |
| 2240 |
|
| 2241 |
memory_region_ref(mr); |
| 2242 |
bounce.mr = mr; |
| 2243 |
if (!is_write) {
|
| 2244 |
address_space_read(as, addr, bounce.buffer, l); |
| 2245 |
} |
| 2246 |
|
| 2247 |
*plen = l; |
| 2248 |
return bounce.buffer;
|
| 2249 |
} |
| 2250 |
|
| 2251 |
base = xlat; |
| 2252 |
raddr = memory_region_get_ram_addr(mr); |
| 2253 |
|
| 2254 |
for (;;) {
|
| 2255 |
len -= l; |
| 2256 |
addr += l; |
| 2257 |
done += l; |
| 2258 |
if (len == 0) { |
| 2259 |
break;
|
| 2260 |
} |
| 2261 |
|
| 2262 |
l = len; |
| 2263 |
this_mr = address_space_translate(as, addr, &xlat, &l, is_write); |
| 2264 |
if (this_mr != mr || xlat != base + done) {
|
| 2265 |
break;
|
| 2266 |
} |
| 2267 |
} |
| 2268 |
|
| 2269 |
memory_region_ref(mr); |
| 2270 |
*plen = done; |
| 2271 |
return qemu_ram_ptr_length(raddr + base, plen);
|
| 2272 |
} |
| 2273 |
|
| 2274 |
/* Unmaps a memory region previously mapped by address_space_map().
|
| 2275 |
* Will also mark the memory as dirty if is_write == 1. access_len gives
|
| 2276 |
* the amount of memory that was actually read or written by the caller.
|
| 2277 |
*/
|
| 2278 |
void address_space_unmap(AddressSpace *as, void *buffer, hwaddr len, |
| 2279 |
int is_write, hwaddr access_len)
|
| 2280 |
{
|
| 2281 |
if (buffer != bounce.buffer) {
|
| 2282 |
MemoryRegion *mr; |
| 2283 |
ram_addr_t addr1; |
| 2284 |
|
| 2285 |
mr = qemu_ram_addr_from_host(buffer, &addr1); |
| 2286 |
assert(mr != NULL);
|
| 2287 |
if (is_write) {
|
| 2288 |
while (access_len) {
|
| 2289 |
unsigned l;
|
| 2290 |
l = TARGET_PAGE_SIZE; |
| 2291 |
if (l > access_len)
|
| 2292 |
l = access_len; |
| 2293 |
invalidate_and_set_dirty(addr1, l); |
| 2294 |
addr1 += l; |
| 2295 |
access_len -= l; |
| 2296 |
} |
| 2297 |
} |
| 2298 |
if (xen_enabled()) {
|
| 2299 |
xen_invalidate_map_cache_entry(buffer); |
| 2300 |
} |
| 2301 |
memory_region_unref(mr); |
| 2302 |
return;
|
| 2303 |
} |
| 2304 |
if (is_write) {
|
| 2305 |
address_space_write(as, bounce.addr, bounce.buffer, access_len); |
| 2306 |
} |
| 2307 |
qemu_vfree(bounce.buffer); |
| 2308 |
bounce.buffer = NULL;
|
| 2309 |
memory_region_unref(bounce.mr); |
| 2310 |
cpu_notify_map_clients(); |
| 2311 |
} |
| 2312 |
|
| 2313 |
void *cpu_physical_memory_map(hwaddr addr,
|
| 2314 |
hwaddr *plen, |
| 2315 |
int is_write)
|
| 2316 |
{
|
| 2317 |
return address_space_map(&address_space_memory, addr, plen, is_write);
|
| 2318 |
} |
| 2319 |
|
| 2320 |
void cpu_physical_memory_unmap(void *buffer, hwaddr len, |
| 2321 |
int is_write, hwaddr access_len)
|
| 2322 |
{
|
| 2323 |
return address_space_unmap(&address_space_memory, buffer, len, is_write, access_len);
|
| 2324 |
} |
| 2325 |
|
| 2326 |
/* warning: addr must be aligned */
|
| 2327 |
static inline uint32_t ldl_phys_internal(hwaddr addr, |
| 2328 |
enum device_endian endian)
|
| 2329 |
{
|
| 2330 |
uint8_t *ptr; |
| 2331 |
uint64_t val; |
| 2332 |
MemoryRegion *mr; |
| 2333 |
hwaddr l = 4;
|
| 2334 |
hwaddr addr1; |
| 2335 |
|
| 2336 |
mr = address_space_translate(&address_space_memory, addr, &addr1, &l, |
| 2337 |
false);
|
| 2338 |
if (l < 4 || !memory_access_is_direct(mr, false)) { |
| 2339 |
/* I/O case */
|
| 2340 |
io_mem_read(mr, addr1, &val, 4);
|
| 2341 |
#if defined(TARGET_WORDS_BIGENDIAN)
|
| 2342 |
if (endian == DEVICE_LITTLE_ENDIAN) {
|
| 2343 |
val = bswap32(val); |
| 2344 |
} |
| 2345 |
#else
|
| 2346 |
if (endian == DEVICE_BIG_ENDIAN) {
|
| 2347 |
val = bswap32(val); |
| 2348 |
} |
| 2349 |
#endif
|
| 2350 |
} else {
|
| 2351 |
/* RAM case */
|
| 2352 |
ptr = qemu_get_ram_ptr((memory_region_get_ram_addr(mr) |
| 2353 |
& TARGET_PAGE_MASK) |
| 2354 |
+ addr1); |
| 2355 |
switch (endian) {
|
| 2356 |
case DEVICE_LITTLE_ENDIAN:
|
| 2357 |
val = ldl_le_p(ptr); |
| 2358 |
break;
|
| 2359 |
case DEVICE_BIG_ENDIAN:
|
| 2360 |
val = ldl_be_p(ptr); |
| 2361 |
break;
|
| 2362 |
default:
|
| 2363 |
val = ldl_p(ptr); |
| 2364 |
break;
|
| 2365 |
} |
| 2366 |
} |
| 2367 |
return val;
|
| 2368 |
} |
| 2369 |
|
| 2370 |
uint32_t ldl_phys(hwaddr addr) |
| 2371 |
{
|
| 2372 |
return ldl_phys_internal(addr, DEVICE_NATIVE_ENDIAN);
|
| 2373 |
} |
| 2374 |
|
| 2375 |
uint32_t ldl_le_phys(hwaddr addr) |
| 2376 |
{
|
| 2377 |
return ldl_phys_internal(addr, DEVICE_LITTLE_ENDIAN);
|
| 2378 |
} |
| 2379 |
|
| 2380 |
uint32_t ldl_be_phys(hwaddr addr) |
| 2381 |
{
|
| 2382 |
return ldl_phys_internal(addr, DEVICE_BIG_ENDIAN);
|
| 2383 |
} |
| 2384 |
|
| 2385 |
/* warning: addr must be aligned */
|
| 2386 |
static inline uint64_t ldq_phys_internal(hwaddr addr, |
| 2387 |
enum device_endian endian)
|
| 2388 |
{
|
| 2389 |
uint8_t *ptr; |
| 2390 |
uint64_t val; |
| 2391 |
MemoryRegion *mr; |
| 2392 |
hwaddr l = 8;
|
| 2393 |
hwaddr addr1; |
| 2394 |
|
| 2395 |
mr = address_space_translate(&address_space_memory, addr, &addr1, &l, |
| 2396 |
false);
|
| 2397 |
if (l < 8 || !memory_access_is_direct(mr, false)) { |
| 2398 |
/* I/O case */
|
| 2399 |
io_mem_read(mr, addr1, &val, 8);
|
| 2400 |
#if defined(TARGET_WORDS_BIGENDIAN)
|
| 2401 |
if (endian == DEVICE_LITTLE_ENDIAN) {
|
| 2402 |
val = bswap64(val); |
| 2403 |
} |
| 2404 |
#else
|
| 2405 |
if (endian == DEVICE_BIG_ENDIAN) {
|
| 2406 |
val = bswap64(val); |
| 2407 |
} |
| 2408 |
#endif
|
| 2409 |
} else {
|
| 2410 |
/* RAM case */
|
| 2411 |
ptr = qemu_get_ram_ptr((memory_region_get_ram_addr(mr) |
| 2412 |
& TARGET_PAGE_MASK) |
| 2413 |
+ addr1); |
| 2414 |
switch (endian) {
|
| 2415 |
case DEVICE_LITTLE_ENDIAN:
|
| 2416 |
val = ldq_le_p(ptr); |
| 2417 |
break;
|
| 2418 |
case DEVICE_BIG_ENDIAN:
|
| 2419 |
val = ldq_be_p(ptr); |
| 2420 |
break;
|
| 2421 |
default:
|
| 2422 |
val = ldq_p(ptr); |
| 2423 |
break;
|
| 2424 |
} |
| 2425 |
} |
| 2426 |
return val;
|
| 2427 |
} |
| 2428 |
|
| 2429 |
uint64_t ldq_phys(hwaddr addr) |
| 2430 |
{
|
| 2431 |
return ldq_phys_internal(addr, DEVICE_NATIVE_ENDIAN);
|
| 2432 |
} |
| 2433 |
|
| 2434 |
uint64_t ldq_le_phys(hwaddr addr) |
| 2435 |
{
|
| 2436 |
return ldq_phys_internal(addr, DEVICE_LITTLE_ENDIAN);
|
| 2437 |
} |
| 2438 |
|
| 2439 |
uint64_t ldq_be_phys(hwaddr addr) |
| 2440 |
{
|
| 2441 |
return ldq_phys_internal(addr, DEVICE_BIG_ENDIAN);
|
| 2442 |
} |
| 2443 |
|
| 2444 |
/* XXX: optimize */
|
| 2445 |
uint32_t ldub_phys(hwaddr addr) |
| 2446 |
{
|
| 2447 |
uint8_t val; |
| 2448 |
cpu_physical_memory_read(addr, &val, 1);
|
| 2449 |
return val;
|
| 2450 |
} |
| 2451 |
|
| 2452 |
/* warning: addr must be aligned */
|
| 2453 |
static inline uint32_t lduw_phys_internal(hwaddr addr, |
| 2454 |
enum device_endian endian)
|
| 2455 |
{
|
| 2456 |
uint8_t *ptr; |
| 2457 |
uint64_t val; |
| 2458 |
MemoryRegion *mr; |
| 2459 |
hwaddr l = 2;
|
| 2460 |
hwaddr addr1; |
| 2461 |
|
| 2462 |
mr = address_space_translate(&address_space_memory, addr, &addr1, &l, |
| 2463 |
false);
|
| 2464 |
if (l < 2 || !memory_access_is_direct(mr, false)) { |
| 2465 |
/* I/O case */
|
| 2466 |
io_mem_read(mr, addr1, &val, 2);
|
| 2467 |
#if defined(TARGET_WORDS_BIGENDIAN)
|
| 2468 |
if (endian == DEVICE_LITTLE_ENDIAN) {
|
| 2469 |
val = bswap16(val); |
| 2470 |
} |
| 2471 |
#else
|
| 2472 |
if (endian == DEVICE_BIG_ENDIAN) {
|
| 2473 |
val = bswap16(val); |
| 2474 |
} |
| 2475 |
#endif
|
| 2476 |
} else {
|
| 2477 |
/* RAM case */
|
| 2478 |
ptr = qemu_get_ram_ptr((memory_region_get_ram_addr(mr) |
| 2479 |
& TARGET_PAGE_MASK) |
| 2480 |
+ addr1); |
| 2481 |
switch (endian) {
|
| 2482 |
case DEVICE_LITTLE_ENDIAN:
|
| 2483 |
val = lduw_le_p(ptr); |
| 2484 |
break;
|
| 2485 |
case DEVICE_BIG_ENDIAN:
|
| 2486 |
val = lduw_be_p(ptr); |
| 2487 |
break;
|
| 2488 |
default:
|
| 2489 |
val = lduw_p(ptr); |
| 2490 |
break;
|
| 2491 |
} |
| 2492 |
} |
| 2493 |
return val;
|
| 2494 |
} |
| 2495 |
|
| 2496 |
uint32_t lduw_phys(hwaddr addr) |
| 2497 |
{
|
| 2498 |
return lduw_phys_internal(addr, DEVICE_NATIVE_ENDIAN);
|
| 2499 |
} |
| 2500 |
|
| 2501 |
uint32_t lduw_le_phys(hwaddr addr) |
| 2502 |
{
|
| 2503 |
return lduw_phys_internal(addr, DEVICE_LITTLE_ENDIAN);
|
| 2504 |
} |
| 2505 |
|
| 2506 |
uint32_t lduw_be_phys(hwaddr addr) |
| 2507 |
{
|
| 2508 |
return lduw_phys_internal(addr, DEVICE_BIG_ENDIAN);
|
| 2509 |
} |
| 2510 |
|
| 2511 |
/* warning: addr must be aligned. The ram page is not masked as dirty
|
| 2512 |
and the code inside is not invalidated. It is useful if the dirty
|
| 2513 |
bits are used to track modified PTEs */
|
| 2514 |
void stl_phys_notdirty(hwaddr addr, uint32_t val)
|
| 2515 |
{
|
| 2516 |
uint8_t *ptr; |
| 2517 |
MemoryRegion *mr; |
| 2518 |
hwaddr l = 4;
|
| 2519 |
hwaddr addr1; |
| 2520 |
|
| 2521 |
mr = address_space_translate(&address_space_memory, addr, &addr1, &l, |
| 2522 |
true);
|
| 2523 |
if (l < 4 || !memory_access_is_direct(mr, true)) { |
| 2524 |
io_mem_write(mr, addr1, val, 4);
|
| 2525 |
} else {
|
| 2526 |
addr1 += memory_region_get_ram_addr(mr) & TARGET_PAGE_MASK; |
| 2527 |
ptr = qemu_get_ram_ptr(addr1); |
| 2528 |
stl_p(ptr, val); |
| 2529 |
|
| 2530 |
if (unlikely(in_migration)) {
|
| 2531 |
if (cpu_physical_memory_is_clean(addr1)) {
|
| 2532 |
/* invalidate code */
|
| 2533 |
tb_invalidate_phys_page_range(addr1, addr1 + 4, 0); |
| 2534 |
/* set dirty bit */
|
| 2535 |
cpu_physical_memory_set_dirty_flag(addr1, |
| 2536 |
DIRTY_MEMORY_MIGRATION); |
| 2537 |
cpu_physical_memory_set_dirty_flag(addr1, DIRTY_MEMORY_VGA); |
| 2538 |
} |
| 2539 |
} |
| 2540 |
} |
| 2541 |
} |
| 2542 |
|
| 2543 |
/* warning: addr must be aligned */
|
| 2544 |
static inline void stl_phys_internal(hwaddr addr, uint32_t val, |
| 2545 |
enum device_endian endian)
|
| 2546 |
{
|
| 2547 |
uint8_t *ptr; |
| 2548 |
MemoryRegion *mr; |
| 2549 |
hwaddr l = 4;
|
| 2550 |
hwaddr addr1; |
| 2551 |
|
| 2552 |
mr = address_space_translate(&address_space_memory, addr, &addr1, &l, |
| 2553 |
true);
|
| 2554 |
if (l < 4 || !memory_access_is_direct(mr, true)) { |
| 2555 |
#if defined(TARGET_WORDS_BIGENDIAN)
|
| 2556 |
if (endian == DEVICE_LITTLE_ENDIAN) {
|
| 2557 |
val = bswap32(val); |
| 2558 |
} |
| 2559 |
#else
|
| 2560 |
if (endian == DEVICE_BIG_ENDIAN) {
|
| 2561 |
val = bswap32(val); |
| 2562 |
} |
| 2563 |
#endif
|
| 2564 |
io_mem_write(mr, addr1, val, 4);
|
| 2565 |
} else {
|
| 2566 |
/* RAM case */
|
| 2567 |
addr1 += memory_region_get_ram_addr(mr) & TARGET_PAGE_MASK; |
| 2568 |
ptr = qemu_get_ram_ptr(addr1); |
| 2569 |
switch (endian) {
|
| 2570 |
case DEVICE_LITTLE_ENDIAN:
|
| 2571 |
stl_le_p(ptr, val); |
| 2572 |
break;
|
| 2573 |
case DEVICE_BIG_ENDIAN:
|
| 2574 |
stl_be_p(ptr, val); |
| 2575 |
break;
|
| 2576 |
default:
|
| 2577 |
stl_p(ptr, val); |
| 2578 |
break;
|
| 2579 |
} |
| 2580 |
invalidate_and_set_dirty(addr1, 4);
|
| 2581 |
} |
| 2582 |
} |
| 2583 |
|
| 2584 |
void stl_phys(hwaddr addr, uint32_t val)
|
| 2585 |
{
|
| 2586 |
stl_phys_internal(addr, val, DEVICE_NATIVE_ENDIAN); |
| 2587 |
} |
| 2588 |
|
| 2589 |
void stl_le_phys(hwaddr addr, uint32_t val)
|
| 2590 |
{
|
| 2591 |
stl_phys_internal(addr, val, DEVICE_LITTLE_ENDIAN); |
| 2592 |
} |
| 2593 |
|
| 2594 |
void stl_be_phys(hwaddr addr, uint32_t val)
|
| 2595 |
{
|
| 2596 |
stl_phys_internal(addr, val, DEVICE_BIG_ENDIAN); |
| 2597 |
} |
| 2598 |
|
| 2599 |
/* XXX: optimize */
|
| 2600 |
void stb_phys(hwaddr addr, uint32_t val)
|
| 2601 |
{
|
| 2602 |
uint8_t v = val; |
| 2603 |
cpu_physical_memory_write(addr, &v, 1);
|
| 2604 |
} |
| 2605 |
|
| 2606 |
/* warning: addr must be aligned */
|
| 2607 |
static inline void stw_phys_internal(hwaddr addr, uint32_t val, |
| 2608 |
enum device_endian endian)
|
| 2609 |
{
|
| 2610 |
uint8_t *ptr; |
| 2611 |
MemoryRegion *mr; |
| 2612 |
hwaddr l = 2;
|
| 2613 |
hwaddr addr1; |
| 2614 |
|
| 2615 |
mr = address_space_translate(&address_space_memory, addr, &addr1, &l, |
| 2616 |
true);
|
| 2617 |
if (l < 2 || !memory_access_is_direct(mr, true)) { |
| 2618 |
#if defined(TARGET_WORDS_BIGENDIAN)
|
| 2619 |
if (endian == DEVICE_LITTLE_ENDIAN) {
|
| 2620 |
val = bswap16(val); |
| 2621 |
} |
| 2622 |
#else
|
| 2623 |
if (endian == DEVICE_BIG_ENDIAN) {
|
| 2624 |
val = bswap16(val); |
| 2625 |
} |
| 2626 |
#endif
|
| 2627 |
io_mem_write(mr, addr1, val, 2);
|
| 2628 |
} else {
|
| 2629 |
/* RAM case */
|
| 2630 |
addr1 += memory_region_get_ram_addr(mr) & TARGET_PAGE_MASK; |
| 2631 |
ptr = qemu_get_ram_ptr(addr1); |
| 2632 |
switch (endian) {
|
| 2633 |
case DEVICE_LITTLE_ENDIAN:
|
| 2634 |
stw_le_p(ptr, val); |
| 2635 |
break;
|
| 2636 |
case DEVICE_BIG_ENDIAN:
|
| 2637 |
stw_be_p(ptr, val); |
| 2638 |
break;
|
| 2639 |
default:
|
| 2640 |
stw_p(ptr, val); |
| 2641 |
break;
|
| 2642 |
} |
| 2643 |
invalidate_and_set_dirty(addr1, 2);
|
| 2644 |
} |
| 2645 |
} |
| 2646 |
|
| 2647 |
void stw_phys(hwaddr addr, uint32_t val)
|
| 2648 |
{
|
| 2649 |
stw_phys_internal(addr, val, DEVICE_NATIVE_ENDIAN); |
| 2650 |
} |
| 2651 |
|
| 2652 |
void stw_le_phys(hwaddr addr, uint32_t val)
|
| 2653 |
{
|
| 2654 |
stw_phys_internal(addr, val, DEVICE_LITTLE_ENDIAN); |
| 2655 |
} |
| 2656 |
|
| 2657 |
void stw_be_phys(hwaddr addr, uint32_t val)
|
| 2658 |
{
|
| 2659 |
stw_phys_internal(addr, val, DEVICE_BIG_ENDIAN); |
| 2660 |
} |
| 2661 |
|
| 2662 |
/* XXX: optimize */
|
| 2663 |
void stq_phys(hwaddr addr, uint64_t val)
|
| 2664 |
{
|
| 2665 |
val = tswap64(val); |
| 2666 |
cpu_physical_memory_write(addr, &val, 8);
|
| 2667 |
} |
| 2668 |
|
| 2669 |
void stq_le_phys(hwaddr addr, uint64_t val)
|
| 2670 |
{
|
| 2671 |
val = cpu_to_le64(val); |
| 2672 |
cpu_physical_memory_write(addr, &val, 8);
|
| 2673 |
} |
| 2674 |
|
| 2675 |
void stq_be_phys(hwaddr addr, uint64_t val)
|
| 2676 |
{
|
| 2677 |
val = cpu_to_be64(val); |
| 2678 |
cpu_physical_memory_write(addr, &val, 8);
|
| 2679 |
} |
| 2680 |
|
| 2681 |
/* virtual memory access for debug (includes writing to ROM) */
|
| 2682 |
int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
|
| 2683 |
uint8_t *buf, int len, int is_write) |
| 2684 |
{
|
| 2685 |
int l;
|
| 2686 |
hwaddr phys_addr; |
| 2687 |
target_ulong page; |
| 2688 |
|
| 2689 |
while (len > 0) { |
| 2690 |
page = addr & TARGET_PAGE_MASK; |
| 2691 |
phys_addr = cpu_get_phys_page_debug(cpu, page); |
| 2692 |
/* if no physical page mapped, return an error */
|
| 2693 |
if (phys_addr == -1) |
| 2694 |
return -1; |
| 2695 |
l = (page + TARGET_PAGE_SIZE) - addr; |
| 2696 |
if (l > len)
|
| 2697 |
l = len; |
| 2698 |
phys_addr += (addr & ~TARGET_PAGE_MASK); |
| 2699 |
if (is_write)
|
| 2700 |
cpu_physical_memory_write_rom(phys_addr, buf, l); |
| 2701 |
else
|
| 2702 |
cpu_physical_memory_rw(phys_addr, buf, l, is_write); |
| 2703 |
len -= l; |
| 2704 |
buf += l; |
| 2705 |
addr += l; |
| 2706 |
} |
| 2707 |
return 0; |
| 2708 |
} |
| 2709 |
#endif
|
| 2710 |
|
| 2711 |
#if !defined(CONFIG_USER_ONLY)
|
| 2712 |
|
| 2713 |
/*
|
| 2714 |
* A helper function for the _utterly broken_ virtio device model to find out if
|
| 2715 |
* it's running on a big endian machine. Don't do this at home kids!
|
| 2716 |
*/
|
| 2717 |
bool virtio_is_big_endian(void); |
| 2718 |
bool virtio_is_big_endian(void) |
| 2719 |
{
|
| 2720 |
#if defined(TARGET_WORDS_BIGENDIAN)
|
| 2721 |
return true; |
| 2722 |
#else
|
| 2723 |
return false; |
| 2724 |
#endif
|
| 2725 |
} |
| 2726 |
|
| 2727 |
#endif
|
| 2728 |
|
| 2729 |
#ifndef CONFIG_USER_ONLY
|
| 2730 |
bool cpu_physical_memory_is_io(hwaddr phys_addr)
|
| 2731 |
{
|
| 2732 |
MemoryRegion*mr; |
| 2733 |
hwaddr l = 1;
|
| 2734 |
|
| 2735 |
mr = address_space_translate(&address_space_memory, |
| 2736 |
phys_addr, &phys_addr, &l, false);
|
| 2737 |
|
| 2738 |
return !(memory_region_is_ram(mr) ||
|
| 2739 |
memory_region_is_romd(mr)); |
| 2740 |
} |
| 2741 |
|
| 2742 |
void qemu_ram_foreach_block(RAMBlockIterFunc func, void *opaque) |
| 2743 |
{
|
| 2744 |
RAMBlock *block; |
| 2745 |
|
| 2746 |
QTAILQ_FOREACH(block, &ram_list.blocks, next) {
|
| 2747 |
func(block->host, block->offset, block->length, opaque); |
| 2748 |
} |
| 2749 |
} |
| 2750 |
#endif
|