root / hw / mips_r4k.c @ 9827e95c
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#include "vl.h" |
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#define DEBUG_IRQ_COUNT
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#define BIOS_FILENAME "mips_bios.bin" |
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//#define BIOS_FILENAME "system.bin"
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#define KERNEL_LOAD_ADDR 0x80010000 |
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#define INITRD_LOAD_ADDR 0x80800000 |
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/* MIPS R4K IRQ controler */
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#if defined(DEBUG_IRQ_COUNT)
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static uint64_t irq_count[16]; |
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#endif
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extern FILE *logfile;
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void mips_set_irq (int n_IRQ, int level) |
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{ |
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uint32_t mask; |
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if (n_IRQ < 0 || n_IRQ >= 8) |
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return;
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mask = 0x100 << n_IRQ;
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if (level != 0) { |
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#if 1 |
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if (logfile) {
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fprintf(logfile, "%s n %d l %d mask %08x %08x\n",
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__func__, n_IRQ, level, mask, cpu_single_env->CP0_Status); |
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} |
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#endif
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cpu_single_env->CP0_Cause |= mask; |
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if ((cpu_single_env->CP0_Status & 0x00000001) && |
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(cpu_single_env->CP0_Status & mask)) { |
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#if defined(DEBUG_IRQ_COUNT)
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irq_count[n_IRQ]++; |
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#endif
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#if 1 |
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if (logfile)
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fprintf(logfile, "%s raise IRQ\n", __func__);
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#endif
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cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HARD); |
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} |
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} else {
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cpu_single_env->CP0_Cause &= ~mask; |
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} |
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} |
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void pic_set_irq (int n_IRQ, int level) |
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{ |
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mips_set_irq(n_IRQ + 2, level);
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} |
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void pic_info (void) |
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{ |
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term_printf("IRQ asserted: %02x mask: %02x\n",
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(cpu_single_env->CP0_Cause >> 8) & 0xFF, |
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(cpu_single_env->CP0_Status >> 8) & 0xFF); |
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} |
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void irq_info (void) |
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{ |
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#if !defined(DEBUG_IRQ_COUNT)
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term_printf("irq statistic code not compiled.\n");
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#else
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int i;
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int64_t count; |
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term_printf("IRQ statistics:\n");
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for (i = 0; i < 8; i++) { |
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count = irq_count[i]; |
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if (count > 0) |
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term_printf("%2d: %lld\n", i, count);
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} |
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#endif
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} |
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void cpu_mips_irqctrl_init (void) |
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{ |
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} |
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uint32_t cpu_mips_get_random (CPUState *env) |
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{ |
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uint32_t now = qemu_get_clock(vm_clock); |
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return now % (MIPS_TLB_NB - env->CP0_Wired) + env->CP0_Wired;
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} |
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/* MIPS R4K timer */
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uint32_t cpu_mips_get_count (CPUState *env) |
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{ |
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return env->CP0_Count +
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(uint32_t)muldiv64(qemu_get_clock(vm_clock), |
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100 * 1000 * 1000, ticks_per_sec); |
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} |
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static void cpu_mips_update_count (CPUState *env, uint32_t count, |
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uint32_t compare) |
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{ |
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uint64_t now, next; |
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uint32_t tmp; |
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tmp = count; |
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if (count == compare)
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tmp++; |
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now = qemu_get_clock(vm_clock); |
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next = now + muldiv64(compare - tmp, ticks_per_sec, 100 * 1000 * 1000); |
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if (next == now)
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next++; |
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#if 1 |
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if (logfile) {
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fprintf(logfile, "%s: 0x%08llx %08x %08x => 0x%08llx\n",
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__func__, now, count, compare, next - now); |
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} |
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#endif
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/* Store new count and compare registers */
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env->CP0_Compare = compare; |
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env->CP0_Count = |
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count - (uint32_t)muldiv64(now, 100 * 1000 * 1000, ticks_per_sec); |
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/* Adjust timer */
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qemu_mod_timer(env->timer, next); |
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} |
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void cpu_mips_store_count (CPUState *env, uint32_t value)
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{ |
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cpu_mips_update_count(env, value, env->CP0_Compare); |
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} |
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void cpu_mips_store_compare (CPUState *env, uint32_t value)
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{ |
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cpu_mips_update_count(env, cpu_mips_get_count(env), value); |
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pic_set_irq(5, 0); |
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} |
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static void mips_timer_cb (void *opaque) |
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{ |
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CPUState *env; |
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env = opaque; |
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#if 1 |
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if (logfile) {
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fprintf(logfile, "%s\n", __func__);
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} |
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#endif
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cpu_mips_update_count(env, cpu_mips_get_count(env), env->CP0_Compare); |
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pic_set_irq(5, 1); |
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} |
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void cpu_mips_clock_init (CPUState *env)
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{ |
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env->timer = qemu_new_timer(vm_clock, &mips_timer_cb, env); |
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env->CP0_Compare = 0;
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cpu_mips_update_count(env, 1, 0); |
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} |
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static void io_writeb (void *opaque, target_phys_addr_t addr, uint32_t value) |
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{ |
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if (logfile)
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fprintf(logfile, "%s: addr %08x val %08x\n", __func__, addr, value);
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cpu_outb(NULL, addr & 0xffff, value); |
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} |
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static uint32_t io_readb (void *opaque, target_phys_addr_t addr) |
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{ |
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uint32_t ret = cpu_inb(NULL, addr & 0xffff); |
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if (logfile)
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fprintf(logfile, "%s: addr %08x val %08x\n", __func__, addr, ret);
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return ret;
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} |
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static void io_writew (void *opaque, target_phys_addr_t addr, uint32_t value) |
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{ |
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if (logfile)
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fprintf(logfile, "%s: addr %08x val %08x\n", __func__, addr, value);
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#ifdef TARGET_WORDS_BIGENDIAN
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value = bswap16(value); |
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#endif
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cpu_outw(NULL, addr & 0xffff, value); |
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} |
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static uint32_t io_readw (void *opaque, target_phys_addr_t addr) |
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{ |
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uint32_t ret = cpu_inw(NULL, addr & 0xffff); |
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#ifdef TARGET_WORDS_BIGENDIAN
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ret = bswap16(ret); |
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#endif
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if (logfile)
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fprintf(logfile, "%s: addr %08x val %08x\n", __func__, addr, ret);
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return ret;
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} |
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static void io_writel (void *opaque, target_phys_addr_t addr, uint32_t value) |
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{ |
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if (logfile)
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fprintf(logfile, "%s: addr %08x val %08x\n", __func__, addr, value);
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#ifdef TARGET_WORDS_BIGENDIAN
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value = bswap32(value); |
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#endif
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cpu_outl(NULL, addr & 0xffff, value); |
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} |
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static uint32_t io_readl (void *opaque, target_phys_addr_t addr) |
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{ |
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uint32_t ret = cpu_inl(NULL, addr & 0xffff); |
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#ifdef TARGET_WORDS_BIGENDIAN
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ret = bswap32(ret); |
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#endif
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if (logfile)
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fprintf(logfile, "%s: addr %08x val %08x\n", __func__, addr, ret);
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return ret;
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} |
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CPUWriteMemoryFunc *io_write[] = { |
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&io_writeb, |
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&io_writew, |
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&io_writel, |
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}; |
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CPUReadMemoryFunc *io_read[] = { |
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&io_readb, |
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&io_readw, |
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&io_readl, |
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}; |
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void mips_r4k_init (int ram_size, int vga_ram_size, int boot_device, |
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DisplayState *ds, const char **fd_filename, int snapshot, |
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const char *kernel_filename, const char *kernel_cmdline, |
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const char *initrd_filename) |
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{ |
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char buf[1024]; |
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target_ulong kernel_base, kernel_size, initrd_base, initrd_size; |
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unsigned long bios_offset; |
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int io_memory;
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int linux_boot;
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int ret;
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printf("%s: start\n", __func__);
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linux_boot = (kernel_filename != NULL);
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/* allocate RAM */
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cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
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bios_offset = ram_size + vga_ram_size; |
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snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME); |
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printf("%s: load BIOS '%s' size %d\n", __func__, buf, BIOS_SIZE);
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ret = load_image(buf, phys_ram_base + bios_offset); |
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if (ret != BIOS_SIZE) {
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fprintf(stderr, "qemu: could not load MIPS bios '%s'\n", buf);
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exit(1);
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} |
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cpu_register_physical_memory((uint32_t)(0x1fc00000),
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BIOS_SIZE, bios_offset | IO_MEM_ROM); |
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#if 0
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memcpy(phys_ram_base + 0x10000, phys_ram_base + bios_offset, BIOS_SIZE);
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cpu_single_env->PC = 0x80010004;
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#else
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cpu_single_env->PC = 0xBFC00004;
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#endif
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if (linux_boot) {
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kernel_base = KERNEL_LOAD_ADDR; |
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/* now we can load the kernel */
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kernel_size = load_image(kernel_filename, |
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phys_ram_base + (kernel_base - 0x80000000));
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if (kernel_size == (target_ulong) -1) { |
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fprintf(stderr, "qemu: could not load kernel '%s'\n",
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kernel_filename); |
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exit(1);
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} |
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/* load initrd */
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if (initrd_filename) {
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initrd_base = INITRD_LOAD_ADDR; |
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initrd_size = load_image(initrd_filename, |
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phys_ram_base + initrd_base); |
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if (initrd_size == (target_ulong) -1) { |
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fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
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initrd_filename); |
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exit(1);
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} |
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} else {
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initrd_base = 0;
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initrd_size = 0;
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} |
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cpu_single_env->PC = KERNEL_LOAD_ADDR; |
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} else {
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kernel_base = 0;
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kernel_size = 0;
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initrd_base = 0;
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initrd_size = 0;
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} |
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/* Init internal devices */
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cpu_mips_clock_init(cpu_single_env); |
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cpu_mips_irqctrl_init(); |
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/* Register 64 KB of ISA IO space at 0x14000000 */
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io_memory = cpu_register_io_memory(0, io_read, io_write, NULL); |
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cpu_register_physical_memory(0x14000000, 0x00010000, io_memory); |
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isa_mem_base = 0x10000000;
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serial_init(0x3f8, 4, serial_hds[0]); |
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vga_initialize(NULL, ds, phys_ram_base + ram_size, ram_size,
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vga_ram_size); |
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isa_ne2000_init(0x300, 9, &nd_table[0]); |
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} |
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QEMUMachine mips_machine = { |
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"mips",
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"mips r4k platform",
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mips_r4k_init, |
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}; |