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/*
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 * QEMU Floppy disk emulator (Intel 82078)
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 *
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 * Copyright (c) 2003, 2007 Jocelyn Mayer
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 * Copyright (c) 2008 Herv? Poussineau
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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/*
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 * The controller is used in Sun4m systems in a slightly different
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 * way. There are changes in DOR register and DMA is not available.
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 */
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#include "hw.h"
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#include "fdc.h"
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#include "block.h"
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#include "qemu-timer.h"
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#include "isa.h"
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#include "sysbus.h"
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#include "qdev-addr.h"
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/********************************************************/
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/* debug Floppy devices */
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//#define DEBUG_FLOPPY
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#ifdef DEBUG_FLOPPY
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#define FLOPPY_DPRINTF(fmt, ...)                                \
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    do { printf("FLOPPY: " fmt , ## __VA_ARGS__); } while (0)
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#else
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#define FLOPPY_DPRINTF(fmt, ...)
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#endif
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#define FLOPPY_ERROR(fmt, ...)                                          \
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    do { printf("FLOPPY ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0)
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/********************************************************/
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/* Floppy drive emulation                               */
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#define GET_CUR_DRV(fdctrl) ((fdctrl)->cur_drv)
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#define SET_CUR_DRV(fdctrl, drive) ((fdctrl)->cur_drv = (drive))
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/* Will always be a fixed parameter for us */
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#define FD_SECTOR_LEN          512
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#define FD_SECTOR_SC           2   /* Sector size code */
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#define FD_RESET_SENSEI_COUNT  4   /* Number of sense interrupts on RESET */
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/* Floppy disk drive emulation */
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typedef enum FDiskType {
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    FDRIVE_DISK_288   = 0x01, /* 2.88 MB disk           */
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    FDRIVE_DISK_144   = 0x02, /* 1.44 MB disk           */
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    FDRIVE_DISK_720   = 0x03, /* 720 kB disk            */
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    FDRIVE_DISK_USER  = 0x04, /* User defined geometry  */
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    FDRIVE_DISK_NONE  = 0x05, /* No disk                */
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} FDiskType;
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typedef enum FDriveType {
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    FDRIVE_DRV_144  = 0x00,   /* 1.44 MB 3"5 drive      */
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    FDRIVE_DRV_288  = 0x01,   /* 2.88 MB 3"5 drive      */
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    FDRIVE_DRV_120  = 0x02,   /* 1.2  MB 5"25 drive     */
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    FDRIVE_DRV_NONE = 0x03,   /* No drive connected     */
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} FDriveType;
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typedef enum FDiskFlags {
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    FDISK_DBL_SIDES  = 0x01,
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} FDiskFlags;
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typedef struct FDrive {
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    DriveInfo *dinfo;
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    BlockDriverState *bs;
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    /* Drive status */
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    FDriveType drive;
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    uint8_t perpendicular;    /* 2.88 MB access mode    */
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    /* Position */
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    uint8_t head;
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    uint8_t track;
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    uint8_t sect;
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    /* Media */
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    FDiskFlags flags;
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    uint8_t last_sect;        /* Nb sector per track    */
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    uint8_t max_track;        /* Nb of tracks           */
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    uint16_t bps;             /* Bytes per sector       */
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    uint8_t ro;               /* Is read-only           */
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} FDrive;
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static void fd_init(FDrive *drv)
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{
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    /* Drive */
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    drv->bs = drv->dinfo ? drv->dinfo->bdrv : NULL;
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    drv->drive = FDRIVE_DRV_NONE;
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    drv->perpendicular = 0;
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    /* Disk */
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    drv->last_sect = 0;
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    drv->max_track = 0;
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}
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static int fd_sector_calc(uint8_t head, uint8_t track, uint8_t sect,
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                          uint8_t last_sect)
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{
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    return (((track * 2) + head) * last_sect) + sect - 1;
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}
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/* Returns current position, in sectors, for given drive */
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static int fd_sector(FDrive *drv)
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{
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    return fd_sector_calc(drv->head, drv->track, drv->sect, drv->last_sect);
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}
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/* Seek to a new position:
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 * returns 0 if already on right track
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 * returns 1 if track changed
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 * returns 2 if track is invalid
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 * returns 3 if sector is invalid
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 * returns 4 if seek is disabled
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 */
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static int fd_seek(FDrive *drv, uint8_t head, uint8_t track, uint8_t sect,
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                   int enable_seek)
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{
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    uint32_t sector;
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    int ret;
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    if (track > drv->max_track ||
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        (head != 0 && (drv->flags & FDISK_DBL_SIDES) == 0)) {
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        FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
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                       head, track, sect, 1,
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                       (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
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                       drv->max_track, drv->last_sect);
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        return 2;
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    }
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    if (sect > drv->last_sect) {
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        FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
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                       head, track, sect, 1,
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                       (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
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                       drv->max_track, drv->last_sect);
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        return 3;
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    }
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    sector = fd_sector_calc(head, track, sect, drv->last_sect);
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    ret = 0;
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    if (sector != fd_sector(drv)) {
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#if 0
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        if (!enable_seek) {
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            FLOPPY_ERROR("no implicit seek %d %02x %02x (max=%d %02x %02x)\n",
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                         head, track, sect, 1, drv->max_track, drv->last_sect);
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            return 4;
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        }
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#endif
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        drv->head = head;
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        if (drv->track != track)
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            ret = 1;
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        drv->track = track;
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        drv->sect = sect;
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    }
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    return ret;
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}
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/* Set drive back to track 0 */
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static void fd_recalibrate(FDrive *drv)
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{
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    FLOPPY_DPRINTF("recalibrate\n");
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    drv->head = 0;
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    drv->track = 0;
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    drv->sect = 1;
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}
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/* Recognize floppy formats */
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typedef struct FDFormat {
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    FDriveType drive;
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    FDiskType  disk;
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    uint8_t last_sect;
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    uint8_t max_track;
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    uint8_t max_head;
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    const char *str;
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} FDFormat;
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static const FDFormat fd_formats[] = {
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    /* First entry is default format */
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    /* 1.44 MB 3"1/2 floppy disks */
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    { FDRIVE_DRV_144, FDRIVE_DISK_144, 18, 80, 1, "1.44 MB 3\"1/2", },
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    { FDRIVE_DRV_144, FDRIVE_DISK_144, 20, 80, 1,  "1.6 MB 3\"1/2", },
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    { FDRIVE_DRV_144, FDRIVE_DISK_144, 21, 80, 1, "1.68 MB 3\"1/2", },
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    { FDRIVE_DRV_144, FDRIVE_DISK_144, 21, 82, 1, "1.72 MB 3\"1/2", },
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    { FDRIVE_DRV_144, FDRIVE_DISK_144, 21, 83, 1, "1.74 MB 3\"1/2", },
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    { FDRIVE_DRV_144, FDRIVE_DISK_144, 22, 80, 1, "1.76 MB 3\"1/2", },
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    { FDRIVE_DRV_144, FDRIVE_DISK_144, 23, 80, 1, "1.84 MB 3\"1/2", },
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    { FDRIVE_DRV_144, FDRIVE_DISK_144, 24, 80, 1, "1.92 MB 3\"1/2", },
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    /* 2.88 MB 3"1/2 floppy disks */
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    { FDRIVE_DRV_288, FDRIVE_DISK_288, 36, 80, 1, "2.88 MB 3\"1/2", },
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    { FDRIVE_DRV_288, FDRIVE_DISK_288, 39, 80, 1, "3.12 MB 3\"1/2", },
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    { FDRIVE_DRV_288, FDRIVE_DISK_288, 40, 80, 1,  "3.2 MB 3\"1/2", },
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    { FDRIVE_DRV_288, FDRIVE_DISK_288, 44, 80, 1, "3.52 MB 3\"1/2", },
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    { FDRIVE_DRV_288, FDRIVE_DISK_288, 48, 80, 1, "3.84 MB 3\"1/2", },
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    /* 720 kB 3"1/2 floppy disks */
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    { FDRIVE_DRV_144, FDRIVE_DISK_720,  9, 80, 1,  "720 kB 3\"1/2", },
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    { FDRIVE_DRV_144, FDRIVE_DISK_720, 10, 80, 1,  "800 kB 3\"1/2", },
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    { FDRIVE_DRV_144, FDRIVE_DISK_720, 10, 82, 1,  "820 kB 3\"1/2", },
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    { FDRIVE_DRV_144, FDRIVE_DISK_720, 10, 83, 1,  "830 kB 3\"1/2", },
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    { FDRIVE_DRV_144, FDRIVE_DISK_720, 13, 80, 1, "1.04 MB 3\"1/2", },
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    { FDRIVE_DRV_144, FDRIVE_DISK_720, 14, 80, 1, "1.12 MB 3\"1/2", },
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    /* 1.2 MB 5"1/4 floppy disks */
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    { FDRIVE_DRV_120, FDRIVE_DISK_288, 15, 80, 1,  "1.2 kB 5\"1/4", },
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    { FDRIVE_DRV_120, FDRIVE_DISK_288, 18, 80, 1, "1.44 MB 5\"1/4", },
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    { FDRIVE_DRV_120, FDRIVE_DISK_288, 18, 82, 1, "1.48 MB 5\"1/4", },
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    { FDRIVE_DRV_120, FDRIVE_DISK_288, 18, 83, 1, "1.49 MB 5\"1/4", },
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    { FDRIVE_DRV_120, FDRIVE_DISK_288, 20, 80, 1,  "1.6 MB 5\"1/4", },
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    /* 720 kB 5"1/4 floppy disks */
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    { FDRIVE_DRV_120, FDRIVE_DISK_288,  9, 80, 1,  "720 kB 5\"1/4", },
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    { FDRIVE_DRV_120, FDRIVE_DISK_288, 11, 80, 1,  "880 kB 5\"1/4", },
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    /* 360 kB 5"1/4 floppy disks */
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    { FDRIVE_DRV_120, FDRIVE_DISK_288,  9, 40, 1,  "360 kB 5\"1/4", },
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    { FDRIVE_DRV_120, FDRIVE_DISK_288,  9, 40, 0,  "180 kB 5\"1/4", },
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    { FDRIVE_DRV_120, FDRIVE_DISK_288, 10, 41, 1,  "410 kB 5\"1/4", },
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    { FDRIVE_DRV_120, FDRIVE_DISK_288, 10, 42, 1,  "420 kB 5\"1/4", },
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    /* 320 kB 5"1/4 floppy disks */
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    { FDRIVE_DRV_120, FDRIVE_DISK_288,  8, 40, 1,  "320 kB 5\"1/4", },
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    { FDRIVE_DRV_120, FDRIVE_DISK_288,  8, 40, 0,  "160 kB 5\"1/4", },
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    /* 360 kB must match 5"1/4 better than 3"1/2... */
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    { FDRIVE_DRV_144, FDRIVE_DISK_720,  9, 80, 0,  "360 kB 3\"1/2", },
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    /* end */
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    { FDRIVE_DRV_NONE, FDRIVE_DISK_NONE, -1, -1, 0, NULL, },
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};
237 a541f297 bellard
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/* Revalidate a disk drive after a disk change */
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static void fd_revalidate(FDrive *drv)
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{
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    const FDFormat *parse;
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    uint64_t nb_sectors, size;
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    int i, first_match, match;
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    int nb_heads, max_track, last_sect, ro;
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    FLOPPY_DPRINTF("revalidate\n");
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    if (drv->bs != NULL && bdrv_is_inserted(drv->bs)) {
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        ro = bdrv_is_read_only(drv->bs);
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        bdrv_get_geometry_hint(drv->bs, &nb_heads, &max_track, &last_sect);
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        if (nb_heads != 0 && max_track != 0 && last_sect != 0) {
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            FLOPPY_DPRINTF("User defined disk (%d %d %d)",
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                           nb_heads - 1, max_track, last_sect);
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        } else {
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            bdrv_get_geometry(drv->bs, &nb_sectors);
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            match = -1;
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            first_match = -1;
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            for (i = 0;; i++) {
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                parse = &fd_formats[i];
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                if (parse->drive == FDRIVE_DRV_NONE)
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                    break;
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                if (drv->drive == parse->drive ||
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                    drv->drive == FDRIVE_DRV_NONE) {
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                    size = (parse->max_head + 1) * parse->max_track *
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                        parse->last_sect;
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                    if (nb_sectors == size) {
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                        match = i;
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                        break;
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                    }
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                    if (first_match == -1)
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                        first_match = i;
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                }
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            }
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            if (match == -1) {
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                if (first_match == -1)
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                    match = 1;
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                else
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                    match = first_match;
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                parse = &fd_formats[match];
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            }
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            nb_heads = parse->max_head + 1;
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            max_track = parse->max_track;
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            last_sect = parse->last_sect;
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            drv->drive = parse->drive;
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            FLOPPY_DPRINTF("%s floppy disk (%d h %d t %d s) %s\n", parse->str,
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                           nb_heads, max_track, last_sect, ro ? "ro" : "rw");
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        }
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        if (nb_heads == 1) {
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            drv->flags &= ~FDISK_DBL_SIDES;
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        } else {
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            drv->flags |= FDISK_DBL_SIDES;
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        }
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        drv->max_track = max_track;
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        drv->last_sect = last_sect;
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        drv->ro = ro;
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    } else {
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        FLOPPY_DPRINTF("No disk in drive\n");
297 baca51fa bellard
        drv->last_sect = 0;
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        drv->max_track = 0;
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        drv->flags &= ~FDISK_DBL_SIDES;
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    }
301 caed8802 bellard
}
302 caed8802 bellard
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/********************************************************/
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/* Intel 82078 floppy disk controller emulation          */
305 8977f3c1 bellard
306 5c02c033 Blue Swirl
static void fdctrl_reset(FDCtrl *fdctrl, int do_irq);
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static void fdctrl_reset_fifo(FDCtrl *fdctrl);
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static int fdctrl_transfer_handler (void *opaque, int nchan,
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                                    int dma_pos, int dma_len);
310 5c02c033 Blue Swirl
static void fdctrl_raise_irq(FDCtrl *fdctrl, uint8_t status0);
311 5c02c033 Blue Swirl
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static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl);
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static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl);
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static uint32_t fdctrl_read_dor(FDCtrl *fdctrl);
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static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value);
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static uint32_t fdctrl_read_tape(FDCtrl *fdctrl);
317 5c02c033 Blue Swirl
static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value);
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static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl);
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static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value);
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static uint32_t fdctrl_read_data(FDCtrl *fdctrl);
321 5c02c033 Blue Swirl
static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value);
322 5c02c033 Blue Swirl
static uint32_t fdctrl_read_dir(FDCtrl *fdctrl);
323 8977f3c1 bellard
324 8977f3c1 bellard
enum {
325 8977f3c1 bellard
    FD_DIR_WRITE   = 0,
326 8977f3c1 bellard
    FD_DIR_READ    = 1,
327 8977f3c1 bellard
    FD_DIR_SCANE   = 2,
328 8977f3c1 bellard
    FD_DIR_SCANL   = 3,
329 8977f3c1 bellard
    FD_DIR_SCANH   = 4,
330 8977f3c1 bellard
};
331 8977f3c1 bellard
332 8977f3c1 bellard
enum {
333 b9b3d225 blueswir1
    FD_STATE_MULTI  = 0x01,        /* multi track flag */
334 b9b3d225 blueswir1
    FD_STATE_FORMAT = 0x02,        /* format flag */
335 b9b3d225 blueswir1
    FD_STATE_SEEK   = 0x04,        /* seek flag */
336 8977f3c1 bellard
};
337 8977f3c1 bellard
338 9fea808a blueswir1
enum {
339 8c6a4d77 blueswir1
    FD_REG_SRA = 0x00,
340 8c6a4d77 blueswir1
    FD_REG_SRB = 0x01,
341 9fea808a blueswir1
    FD_REG_DOR = 0x02,
342 9fea808a blueswir1
    FD_REG_TDR = 0x03,
343 9fea808a blueswir1
    FD_REG_MSR = 0x04,
344 9fea808a blueswir1
    FD_REG_DSR = 0x04,
345 9fea808a blueswir1
    FD_REG_FIFO = 0x05,
346 9fea808a blueswir1
    FD_REG_DIR = 0x07,
347 9fea808a blueswir1
};
348 9fea808a blueswir1
349 9fea808a blueswir1
enum {
350 65cef780 blueswir1
    FD_CMD_READ_TRACK = 0x02,
351 9fea808a blueswir1
    FD_CMD_SPECIFY = 0x03,
352 9fea808a blueswir1
    FD_CMD_SENSE_DRIVE_STATUS = 0x04,
353 65cef780 blueswir1
    FD_CMD_WRITE = 0x05,
354 65cef780 blueswir1
    FD_CMD_READ = 0x06,
355 9fea808a blueswir1
    FD_CMD_RECALIBRATE = 0x07,
356 9fea808a blueswir1
    FD_CMD_SENSE_INTERRUPT_STATUS = 0x08,
357 65cef780 blueswir1
    FD_CMD_WRITE_DELETED = 0x09,
358 65cef780 blueswir1
    FD_CMD_READ_ID = 0x0a,
359 65cef780 blueswir1
    FD_CMD_READ_DELETED = 0x0c,
360 65cef780 blueswir1
    FD_CMD_FORMAT_TRACK = 0x0d,
361 9fea808a blueswir1
    FD_CMD_DUMPREG = 0x0e,
362 9fea808a blueswir1
    FD_CMD_SEEK = 0x0f,
363 9fea808a blueswir1
    FD_CMD_VERSION = 0x10,
364 65cef780 blueswir1
    FD_CMD_SCAN_EQUAL = 0x11,
365 9fea808a blueswir1
    FD_CMD_PERPENDICULAR_MODE = 0x12,
366 9fea808a blueswir1
    FD_CMD_CONFIGURE = 0x13,
367 65cef780 blueswir1
    FD_CMD_LOCK = 0x14,
368 65cef780 blueswir1
    FD_CMD_VERIFY = 0x16,
369 9fea808a blueswir1
    FD_CMD_POWERDOWN_MODE = 0x17,
370 9fea808a blueswir1
    FD_CMD_PART_ID = 0x18,
371 65cef780 blueswir1
    FD_CMD_SCAN_LOW_OR_EQUAL = 0x19,
372 65cef780 blueswir1
    FD_CMD_SCAN_HIGH_OR_EQUAL = 0x1d,
373 9fea808a blueswir1
    FD_CMD_SAVE = 0x2c,
374 9fea808a blueswir1
    FD_CMD_OPTION = 0x33,
375 9fea808a blueswir1
    FD_CMD_RESTORE = 0x4c,
376 9fea808a blueswir1
    FD_CMD_DRIVE_SPECIFICATION_COMMAND = 0x8e,
377 9fea808a blueswir1
    FD_CMD_RELATIVE_SEEK_OUT = 0x8f,
378 9fea808a blueswir1
    FD_CMD_FORMAT_AND_WRITE = 0xcd,
379 9fea808a blueswir1
    FD_CMD_RELATIVE_SEEK_IN = 0xcf,
380 9fea808a blueswir1
};
381 9fea808a blueswir1
382 9fea808a blueswir1
enum {
383 9fea808a blueswir1
    FD_CONFIG_PRETRK = 0xff, /* Pre-compensation set to track 0 */
384 9fea808a blueswir1
    FD_CONFIG_FIFOTHR = 0x0f, /* FIFO threshold set to 1 byte */
385 9fea808a blueswir1
    FD_CONFIG_POLL  = 0x10, /* Poll enabled */
386 9fea808a blueswir1
    FD_CONFIG_EFIFO = 0x20, /* FIFO disabled */
387 9fea808a blueswir1
    FD_CONFIG_EIS   = 0x40, /* No implied seeks */
388 9fea808a blueswir1
};
389 9fea808a blueswir1
390 9fea808a blueswir1
enum {
391 9fea808a blueswir1
    FD_SR0_EQPMT    = 0x10,
392 9fea808a blueswir1
    FD_SR0_SEEK     = 0x20,
393 9fea808a blueswir1
    FD_SR0_ABNTERM  = 0x40,
394 9fea808a blueswir1
    FD_SR0_INVCMD   = 0x80,
395 9fea808a blueswir1
    FD_SR0_RDYCHG   = 0xc0,
396 9fea808a blueswir1
};
397 9fea808a blueswir1
398 9fea808a blueswir1
enum {
399 77370520 blueswir1
    FD_SR1_EC       = 0x80, /* End of cylinder */
400 77370520 blueswir1
};
401 77370520 blueswir1
402 77370520 blueswir1
enum {
403 77370520 blueswir1
    FD_SR2_SNS      = 0x04, /* Scan not satisfied */
404 77370520 blueswir1
    FD_SR2_SEH      = 0x08, /* Scan equal hit */
405 77370520 blueswir1
};
406 77370520 blueswir1
407 77370520 blueswir1
enum {
408 8c6a4d77 blueswir1
    FD_SRA_DIR      = 0x01,
409 8c6a4d77 blueswir1
    FD_SRA_nWP      = 0x02,
410 8c6a4d77 blueswir1
    FD_SRA_nINDX    = 0x04,
411 8c6a4d77 blueswir1
    FD_SRA_HDSEL    = 0x08,
412 8c6a4d77 blueswir1
    FD_SRA_nTRK0    = 0x10,
413 8c6a4d77 blueswir1
    FD_SRA_STEP     = 0x20,
414 8c6a4d77 blueswir1
    FD_SRA_nDRV2    = 0x40,
415 8c6a4d77 blueswir1
    FD_SRA_INTPEND  = 0x80,
416 8c6a4d77 blueswir1
};
417 8c6a4d77 blueswir1
418 8c6a4d77 blueswir1
enum {
419 8c6a4d77 blueswir1
    FD_SRB_MTR0     = 0x01,
420 8c6a4d77 blueswir1
    FD_SRB_MTR1     = 0x02,
421 8c6a4d77 blueswir1
    FD_SRB_WGATE    = 0x04,
422 8c6a4d77 blueswir1
    FD_SRB_RDATA    = 0x08,
423 8c6a4d77 blueswir1
    FD_SRB_WDATA    = 0x10,
424 8c6a4d77 blueswir1
    FD_SRB_DR0      = 0x20,
425 8c6a4d77 blueswir1
};
426 8c6a4d77 blueswir1
427 8c6a4d77 blueswir1
enum {
428 78ae820c blueswir1
#if MAX_FD == 4
429 78ae820c blueswir1
    FD_DOR_SELMASK  = 0x03,
430 78ae820c blueswir1
#else
431 9fea808a blueswir1
    FD_DOR_SELMASK  = 0x01,
432 78ae820c blueswir1
#endif
433 9fea808a blueswir1
    FD_DOR_nRESET   = 0x04,
434 9fea808a blueswir1
    FD_DOR_DMAEN    = 0x08,
435 9fea808a blueswir1
    FD_DOR_MOTEN0   = 0x10,
436 9fea808a blueswir1
    FD_DOR_MOTEN1   = 0x20,
437 9fea808a blueswir1
    FD_DOR_MOTEN2   = 0x40,
438 9fea808a blueswir1
    FD_DOR_MOTEN3   = 0x80,
439 9fea808a blueswir1
};
440 9fea808a blueswir1
441 9fea808a blueswir1
enum {
442 78ae820c blueswir1
#if MAX_FD == 4
443 9fea808a blueswir1
    FD_TDR_BOOTSEL  = 0x0c,
444 78ae820c blueswir1
#else
445 78ae820c blueswir1
    FD_TDR_BOOTSEL  = 0x04,
446 78ae820c blueswir1
#endif
447 9fea808a blueswir1
};
448 9fea808a blueswir1
449 9fea808a blueswir1
enum {
450 9fea808a blueswir1
    FD_DSR_DRATEMASK= 0x03,
451 9fea808a blueswir1
    FD_DSR_PWRDOWN  = 0x40,
452 9fea808a blueswir1
    FD_DSR_SWRESET  = 0x80,
453 9fea808a blueswir1
};
454 9fea808a blueswir1
455 9fea808a blueswir1
enum {
456 9fea808a blueswir1
    FD_MSR_DRV0BUSY = 0x01,
457 9fea808a blueswir1
    FD_MSR_DRV1BUSY = 0x02,
458 9fea808a blueswir1
    FD_MSR_DRV2BUSY = 0x04,
459 9fea808a blueswir1
    FD_MSR_DRV3BUSY = 0x08,
460 9fea808a blueswir1
    FD_MSR_CMDBUSY  = 0x10,
461 9fea808a blueswir1
    FD_MSR_NONDMA   = 0x20,
462 9fea808a blueswir1
    FD_MSR_DIO      = 0x40,
463 9fea808a blueswir1
    FD_MSR_RQM      = 0x80,
464 9fea808a blueswir1
};
465 9fea808a blueswir1
466 9fea808a blueswir1
enum {
467 9fea808a blueswir1
    FD_DIR_DSKCHG   = 0x80,
468 9fea808a blueswir1
};
469 9fea808a blueswir1
470 8977f3c1 bellard
#define FD_MULTI_TRACK(state) ((state) & FD_STATE_MULTI)
471 8977f3c1 bellard
#define FD_DID_SEEK(state) ((state) & FD_STATE_SEEK)
472 baca51fa bellard
#define FD_FORMAT_CMD(state) ((state) & FD_STATE_FORMAT)
473 8977f3c1 bellard
474 5c02c033 Blue Swirl
struct FDCtrl {
475 4b19ec0c bellard
    /* Controller's identification */
476 8977f3c1 bellard
    uint8_t version;
477 8977f3c1 bellard
    /* HW */
478 d537cf6c pbrook
    qemu_irq irq;
479 8977f3c1 bellard
    int dma_chann;
480 4b19ec0c bellard
    /* Controller state */
481 ed5fd2cc bellard
    QEMUTimer *result_timer;
482 8c6a4d77 blueswir1
    uint8_t sra;
483 8c6a4d77 blueswir1
    uint8_t srb;
484 368df94d blueswir1
    uint8_t dor;
485 d7a6c270 Juan Quintela
    uint8_t dor_vmstate; /* only used as temp during vmstate */
486 46d3233b blueswir1
    uint8_t tdr;
487 b9b3d225 blueswir1
    uint8_t dsr;
488 368df94d blueswir1
    uint8_t msr;
489 8977f3c1 bellard
    uint8_t cur_drv;
490 77370520 blueswir1
    uint8_t status0;
491 77370520 blueswir1
    uint8_t status1;
492 77370520 blueswir1
    uint8_t status2;
493 8977f3c1 bellard
    /* Command FIFO */
494 33f00271 balrog
    uint8_t *fifo;
495 d7a6c270 Juan Quintela
    int32_t fifo_size;
496 8977f3c1 bellard
    uint32_t data_pos;
497 8977f3c1 bellard
    uint32_t data_len;
498 8977f3c1 bellard
    uint8_t data_state;
499 8977f3c1 bellard
    uint8_t data_dir;
500 890fa6be bellard
    uint8_t eot; /* last wanted sector */
501 8977f3c1 bellard
    /* States kept only to be returned back */
502 8977f3c1 bellard
    /* Timers state */
503 8977f3c1 bellard
    uint8_t timer0;
504 8977f3c1 bellard
    uint8_t timer1;
505 8977f3c1 bellard
    /* precompensation */
506 8977f3c1 bellard
    uint8_t precomp_trk;
507 8977f3c1 bellard
    uint8_t config;
508 8977f3c1 bellard
    uint8_t lock;
509 8977f3c1 bellard
    /* Power down config (also with status regB access mode */
510 8977f3c1 bellard
    uint8_t pwrd;
511 741402f9 blueswir1
    /* Sun4m quirks? */
512 a06e5a3c blueswir1
    int sun4m;
513 8977f3c1 bellard
    /* Floppy drives */
514 d7a6c270 Juan Quintela
    uint8_t num_floppies;
515 5c02c033 Blue Swirl
    FDrive drives[MAX_FD];
516 f2d81b33 blueswir1
    int reset_sensei;
517 baca51fa bellard
};
518 baca51fa bellard
519 5c02c033 Blue Swirl
typedef struct FDCtrlSysBus {
520 8baf73ad Gerd Hoffmann
    SysBusDevice busdev;
521 5c02c033 Blue Swirl
    struct FDCtrl state;
522 5c02c033 Blue Swirl
} FDCtrlSysBus;
523 8baf73ad Gerd Hoffmann
524 5c02c033 Blue Swirl
typedef struct FDCtrlISABus {
525 8baf73ad Gerd Hoffmann
    ISADevice busdev;
526 5c02c033 Blue Swirl
    struct FDCtrl state;
527 5c02c033 Blue Swirl
} FDCtrlISABus;
528 8baf73ad Gerd Hoffmann
529 baca51fa bellard
static uint32_t fdctrl_read (void *opaque, uint32_t reg)
530 baca51fa bellard
{
531 5c02c033 Blue Swirl
    FDCtrl *fdctrl = opaque;
532 baca51fa bellard
    uint32_t retval;
533 baca51fa bellard
534 e64d7d59 blueswir1
    switch (reg) {
535 8c6a4d77 blueswir1
    case FD_REG_SRA:
536 8c6a4d77 blueswir1
        retval = fdctrl_read_statusA(fdctrl);
537 4f431960 j_mayer
        break;
538 8c6a4d77 blueswir1
    case FD_REG_SRB:
539 4f431960 j_mayer
        retval = fdctrl_read_statusB(fdctrl);
540 4f431960 j_mayer
        break;
541 9fea808a blueswir1
    case FD_REG_DOR:
542 4f431960 j_mayer
        retval = fdctrl_read_dor(fdctrl);
543 4f431960 j_mayer
        break;
544 9fea808a blueswir1
    case FD_REG_TDR:
545 baca51fa bellard
        retval = fdctrl_read_tape(fdctrl);
546 4f431960 j_mayer
        break;
547 9fea808a blueswir1
    case FD_REG_MSR:
548 baca51fa bellard
        retval = fdctrl_read_main_status(fdctrl);
549 4f431960 j_mayer
        break;
550 9fea808a blueswir1
    case FD_REG_FIFO:
551 baca51fa bellard
        retval = fdctrl_read_data(fdctrl);
552 4f431960 j_mayer
        break;
553 9fea808a blueswir1
    case FD_REG_DIR:
554 baca51fa bellard
        retval = fdctrl_read_dir(fdctrl);
555 4f431960 j_mayer
        break;
556 a541f297 bellard
    default:
557 4f431960 j_mayer
        retval = (uint32_t)(-1);
558 4f431960 j_mayer
        break;
559 a541f297 bellard
    }
560 ed5fd2cc bellard
    FLOPPY_DPRINTF("read reg%d: 0x%02x\n", reg & 7, retval);
561 baca51fa bellard
562 baca51fa bellard
    return retval;
563 baca51fa bellard
}
564 baca51fa bellard
565 baca51fa bellard
static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value)
566 baca51fa bellard
{
567 5c02c033 Blue Swirl
    FDCtrl *fdctrl = opaque;
568 baca51fa bellard
569 ed5fd2cc bellard
    FLOPPY_DPRINTF("write reg%d: 0x%02x\n", reg & 7, value);
570 ed5fd2cc bellard
571 e64d7d59 blueswir1
    switch (reg) {
572 9fea808a blueswir1
    case FD_REG_DOR:
573 4f431960 j_mayer
        fdctrl_write_dor(fdctrl, value);
574 4f431960 j_mayer
        break;
575 9fea808a blueswir1
    case FD_REG_TDR:
576 baca51fa bellard
        fdctrl_write_tape(fdctrl, value);
577 4f431960 j_mayer
        break;
578 9fea808a blueswir1
    case FD_REG_DSR:
579 baca51fa bellard
        fdctrl_write_rate(fdctrl, value);
580 4f431960 j_mayer
        break;
581 9fea808a blueswir1
    case FD_REG_FIFO:
582 baca51fa bellard
        fdctrl_write_data(fdctrl, value);
583 4f431960 j_mayer
        break;
584 a541f297 bellard
    default:
585 4f431960 j_mayer
        break;
586 a541f297 bellard
    }
587 baca51fa bellard
}
588 baca51fa bellard
589 e64d7d59 blueswir1
static uint32_t fdctrl_read_port (void *opaque, uint32_t reg)
590 e64d7d59 blueswir1
{
591 e64d7d59 blueswir1
    return fdctrl_read(opaque, reg & 7);
592 e64d7d59 blueswir1
}
593 e64d7d59 blueswir1
594 e64d7d59 blueswir1
static void fdctrl_write_port (void *opaque, uint32_t reg, uint32_t value)
595 e64d7d59 blueswir1
{
596 e64d7d59 blueswir1
    fdctrl_write(opaque, reg & 7, value);
597 e64d7d59 blueswir1
}
598 e64d7d59 blueswir1
599 c227f099 Anthony Liguori
static uint32_t fdctrl_read_mem (void *opaque, target_phys_addr_t reg)
600 62a46c61 bellard
{
601 5dcb6b91 blueswir1
    return fdctrl_read(opaque, (uint32_t)reg);
602 62a46c61 bellard
}
603 62a46c61 bellard
604 5fafdf24 ths
static void fdctrl_write_mem (void *opaque,
605 c227f099 Anthony Liguori
                              target_phys_addr_t reg, uint32_t value)
606 62a46c61 bellard
{
607 5dcb6b91 blueswir1
    fdctrl_write(opaque, (uint32_t)reg, value);
608 62a46c61 bellard
}
609 62a46c61 bellard
610 d60efc6b Blue Swirl
static CPUReadMemoryFunc * const fdctrl_mem_read[3] = {
611 62a46c61 bellard
    fdctrl_read_mem,
612 62a46c61 bellard
    fdctrl_read_mem,
613 62a46c61 bellard
    fdctrl_read_mem,
614 e80cfcfc bellard
};
615 e80cfcfc bellard
616 d60efc6b Blue Swirl
static CPUWriteMemoryFunc * const fdctrl_mem_write[3] = {
617 62a46c61 bellard
    fdctrl_write_mem,
618 62a46c61 bellard
    fdctrl_write_mem,
619 62a46c61 bellard
    fdctrl_write_mem,
620 e80cfcfc bellard
};
621 e80cfcfc bellard
622 d60efc6b Blue Swirl
static CPUReadMemoryFunc * const fdctrl_mem_read_strict[3] = {
623 7c560456 blueswir1
    fdctrl_read_mem,
624 7c560456 blueswir1
    NULL,
625 7c560456 blueswir1
    NULL,
626 7c560456 blueswir1
};
627 7c560456 blueswir1
628 d60efc6b Blue Swirl
static CPUWriteMemoryFunc * const fdctrl_mem_write_strict[3] = {
629 7c560456 blueswir1
    fdctrl_write_mem,
630 7c560456 blueswir1
    NULL,
631 7c560456 blueswir1
    NULL,
632 7c560456 blueswir1
};
633 7c560456 blueswir1
634 d7a6c270 Juan Quintela
static const VMStateDescription vmstate_fdrive = {
635 d7a6c270 Juan Quintela
    .name = "fdrive",
636 d7a6c270 Juan Quintela
    .version_id = 1,
637 d7a6c270 Juan Quintela
    .minimum_version_id = 1,
638 d7a6c270 Juan Quintela
    .minimum_version_id_old = 1,
639 d7a6c270 Juan Quintela
    .fields      = (VMStateField []) {
640 5c02c033 Blue Swirl
        VMSTATE_UINT8(head, FDrive),
641 5c02c033 Blue Swirl
        VMSTATE_UINT8(track, FDrive),
642 5c02c033 Blue Swirl
        VMSTATE_UINT8(sect, FDrive),
643 d7a6c270 Juan Quintela
        VMSTATE_END_OF_LIST()
644 d7a6c270 Juan Quintela
    }
645 d7a6c270 Juan Quintela
};
646 3ccacc4a blueswir1
647 d4bfa4d7 Juan Quintela
static void fdc_pre_save(void *opaque)
648 3ccacc4a blueswir1
{
649 5c02c033 Blue Swirl
    FDCtrl *s = opaque;
650 3ccacc4a blueswir1
651 d7a6c270 Juan Quintela
    s->dor_vmstate = s->dor | GET_CUR_DRV(s);
652 3ccacc4a blueswir1
}
653 3ccacc4a blueswir1
654 e59fb374 Juan Quintela
static int fdc_post_load(void *opaque, int version_id)
655 3ccacc4a blueswir1
{
656 5c02c033 Blue Swirl
    FDCtrl *s = opaque;
657 3ccacc4a blueswir1
658 d7a6c270 Juan Quintela
    SET_CUR_DRV(s, s->dor_vmstate & FD_DOR_SELMASK);
659 d7a6c270 Juan Quintela
    s->dor = s->dor_vmstate & ~FD_DOR_SELMASK;
660 3ccacc4a blueswir1
    return 0;
661 3ccacc4a blueswir1
}
662 3ccacc4a blueswir1
663 d7a6c270 Juan Quintela
static const VMStateDescription vmstate_fdc = {
664 aef30c3c Juan Quintela
    .name = "fdc",
665 d7a6c270 Juan Quintela
    .version_id = 2,
666 d7a6c270 Juan Quintela
    .minimum_version_id = 2,
667 d7a6c270 Juan Quintela
    .minimum_version_id_old = 2,
668 d7a6c270 Juan Quintela
    .pre_save = fdc_pre_save,
669 d7a6c270 Juan Quintela
    .post_load = fdc_post_load,
670 d7a6c270 Juan Quintela
    .fields      = (VMStateField []) {
671 d7a6c270 Juan Quintela
        /* Controller State */
672 5c02c033 Blue Swirl
        VMSTATE_UINT8(sra, FDCtrl),
673 5c02c033 Blue Swirl
        VMSTATE_UINT8(srb, FDCtrl),
674 5c02c033 Blue Swirl
        VMSTATE_UINT8(dor_vmstate, FDCtrl),
675 5c02c033 Blue Swirl
        VMSTATE_UINT8(tdr, FDCtrl),
676 5c02c033 Blue Swirl
        VMSTATE_UINT8(dsr, FDCtrl),
677 5c02c033 Blue Swirl
        VMSTATE_UINT8(msr, FDCtrl),
678 5c02c033 Blue Swirl
        VMSTATE_UINT8(status0, FDCtrl),
679 5c02c033 Blue Swirl
        VMSTATE_UINT8(status1, FDCtrl),
680 5c02c033 Blue Swirl
        VMSTATE_UINT8(status2, FDCtrl),
681 d7a6c270 Juan Quintela
        /* Command FIFO */
682 8ec68b06 Blue Swirl
        VMSTATE_VARRAY_INT32(fifo, FDCtrl, fifo_size, 0, vmstate_info_uint8,
683 8ec68b06 Blue Swirl
                             uint8_t),
684 5c02c033 Blue Swirl
        VMSTATE_UINT32(data_pos, FDCtrl),
685 5c02c033 Blue Swirl
        VMSTATE_UINT32(data_len, FDCtrl),
686 5c02c033 Blue Swirl
        VMSTATE_UINT8(data_state, FDCtrl),
687 5c02c033 Blue Swirl
        VMSTATE_UINT8(data_dir, FDCtrl),
688 5c02c033 Blue Swirl
        VMSTATE_UINT8(eot, FDCtrl),
689 d7a6c270 Juan Quintela
        /* States kept only to be returned back */
690 5c02c033 Blue Swirl
        VMSTATE_UINT8(timer0, FDCtrl),
691 5c02c033 Blue Swirl
        VMSTATE_UINT8(timer1, FDCtrl),
692 5c02c033 Blue Swirl
        VMSTATE_UINT8(precomp_trk, FDCtrl),
693 5c02c033 Blue Swirl
        VMSTATE_UINT8(config, FDCtrl),
694 5c02c033 Blue Swirl
        VMSTATE_UINT8(lock, FDCtrl),
695 5c02c033 Blue Swirl
        VMSTATE_UINT8(pwrd, FDCtrl),
696 5c02c033 Blue Swirl
        VMSTATE_UINT8_EQUAL(num_floppies, FDCtrl),
697 5c02c033 Blue Swirl
        VMSTATE_STRUCT_ARRAY(drives, FDCtrl, MAX_FD, 1,
698 5c02c033 Blue Swirl
                             vmstate_fdrive, FDrive),
699 d7a6c270 Juan Quintela
        VMSTATE_END_OF_LIST()
700 78ae820c blueswir1
    }
701 d7a6c270 Juan Quintela
};
702 3ccacc4a blueswir1
703 2be37833 Blue Swirl
static void fdctrl_external_reset_sysbus(DeviceState *d)
704 3ccacc4a blueswir1
{
705 5c02c033 Blue Swirl
    FDCtrlSysBus *sys = container_of(d, FDCtrlSysBus, busdev.qdev);
706 5c02c033 Blue Swirl
    FDCtrl *s = &sys->state;
707 2be37833 Blue Swirl
708 2be37833 Blue Swirl
    fdctrl_reset(s, 0);
709 2be37833 Blue Swirl
}
710 2be37833 Blue Swirl
711 2be37833 Blue Swirl
static void fdctrl_external_reset_isa(DeviceState *d)
712 2be37833 Blue Swirl
{
713 5c02c033 Blue Swirl
    FDCtrlISABus *isa = container_of(d, FDCtrlISABus, busdev.qdev);
714 5c02c033 Blue Swirl
    FDCtrl *s = &isa->state;
715 3ccacc4a blueswir1
716 3ccacc4a blueswir1
    fdctrl_reset(s, 0);
717 3ccacc4a blueswir1
}
718 3ccacc4a blueswir1
719 2be17ebd blueswir1
static void fdctrl_handle_tc(void *opaque, int irq, int level)
720 2be17ebd blueswir1
{
721 5c02c033 Blue Swirl
    //FDCtrl *s = opaque;
722 2be17ebd blueswir1
723 2be17ebd blueswir1
    if (level) {
724 2be17ebd blueswir1
        // XXX
725 2be17ebd blueswir1
        FLOPPY_DPRINTF("TC pulsed\n");
726 2be17ebd blueswir1
    }
727 2be17ebd blueswir1
}
728 2be17ebd blueswir1
729 baca51fa bellard
/* XXX: may change if moved to bdrv */
730 5c02c033 Blue Swirl
int fdctrl_get_drive_type(FDCtrl *fdctrl, int drive_num)
731 caed8802 bellard
{
732 baca51fa bellard
    return fdctrl->drives[drive_num].drive;
733 8977f3c1 bellard
}
734 8977f3c1 bellard
735 8977f3c1 bellard
/* Change IRQ state */
736 5c02c033 Blue Swirl
static void fdctrl_reset_irq(FDCtrl *fdctrl)
737 8977f3c1 bellard
{
738 8c6a4d77 blueswir1
    if (!(fdctrl->sra & FD_SRA_INTPEND))
739 8c6a4d77 blueswir1
        return;
740 ed5fd2cc bellard
    FLOPPY_DPRINTF("Reset interrupt\n");
741 d537cf6c pbrook
    qemu_set_irq(fdctrl->irq, 0);
742 8c6a4d77 blueswir1
    fdctrl->sra &= ~FD_SRA_INTPEND;
743 8977f3c1 bellard
}
744 8977f3c1 bellard
745 5c02c033 Blue Swirl
static void fdctrl_raise_irq(FDCtrl *fdctrl, uint8_t status0)
746 8977f3c1 bellard
{
747 b9b3d225 blueswir1
    /* Sparc mutation */
748 b9b3d225 blueswir1
    if (fdctrl->sun4m && (fdctrl->msr & FD_MSR_CMDBUSY)) {
749 b9b3d225 blueswir1
        /* XXX: not sure */
750 b9b3d225 blueswir1
        fdctrl->msr &= ~FD_MSR_CMDBUSY;
751 b9b3d225 blueswir1
        fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
752 77370520 blueswir1
        fdctrl->status0 = status0;
753 4f431960 j_mayer
        return;
754 6f7e9aec bellard
    }
755 8c6a4d77 blueswir1
    if (!(fdctrl->sra & FD_SRA_INTPEND)) {
756 d537cf6c pbrook
        qemu_set_irq(fdctrl->irq, 1);
757 8c6a4d77 blueswir1
        fdctrl->sra |= FD_SRA_INTPEND;
758 8977f3c1 bellard
    }
759 f2d81b33 blueswir1
    fdctrl->reset_sensei = 0;
760 77370520 blueswir1
    fdctrl->status0 = status0;
761 77370520 blueswir1
    FLOPPY_DPRINTF("Set interrupt status to 0x%02x\n", fdctrl->status0);
762 8977f3c1 bellard
}
763 8977f3c1 bellard
764 4b19ec0c bellard
/* Reset controller */
765 5c02c033 Blue Swirl
static void fdctrl_reset(FDCtrl *fdctrl, int do_irq)
766 8977f3c1 bellard
{
767 8977f3c1 bellard
    int i;
768 8977f3c1 bellard
769 4b19ec0c bellard
    FLOPPY_DPRINTF("reset controller\n");
770 baca51fa bellard
    fdctrl_reset_irq(fdctrl);
771 4b19ec0c bellard
    /* Initialise controller */
772 8c6a4d77 blueswir1
    fdctrl->sra = 0;
773 8c6a4d77 blueswir1
    fdctrl->srb = 0xc0;
774 8c6a4d77 blueswir1
    if (!fdctrl->drives[1].bs)
775 8c6a4d77 blueswir1
        fdctrl->sra |= FD_SRA_nDRV2;
776 baca51fa bellard
    fdctrl->cur_drv = 0;
777 1c346df2 blueswir1
    fdctrl->dor = FD_DOR_nRESET;
778 368df94d blueswir1
    fdctrl->dor |= (fdctrl->dma_chann != -1) ? FD_DOR_DMAEN : 0;
779 b9b3d225 blueswir1
    fdctrl->msr = FD_MSR_RQM;
780 8977f3c1 bellard
    /* FIFO state */
781 baca51fa bellard
    fdctrl->data_pos = 0;
782 baca51fa bellard
    fdctrl->data_len = 0;
783 b9b3d225 blueswir1
    fdctrl->data_state = 0;
784 baca51fa bellard
    fdctrl->data_dir = FD_DIR_WRITE;
785 8977f3c1 bellard
    for (i = 0; i < MAX_FD; i++)
786 1c346df2 blueswir1
        fd_recalibrate(&fdctrl->drives[i]);
787 baca51fa bellard
    fdctrl_reset_fifo(fdctrl);
788 77370520 blueswir1
    if (do_irq) {
789 9fea808a blueswir1
        fdctrl_raise_irq(fdctrl, FD_SR0_RDYCHG);
790 f2d81b33 blueswir1
        fdctrl->reset_sensei = FD_RESET_SENSEI_COUNT;
791 77370520 blueswir1
    }
792 baca51fa bellard
}
793 baca51fa bellard
794 5c02c033 Blue Swirl
static inline FDrive *drv0(FDCtrl *fdctrl)
795 baca51fa bellard
{
796 46d3233b blueswir1
    return &fdctrl->drives[(fdctrl->tdr & FD_TDR_BOOTSEL) >> 2];
797 baca51fa bellard
}
798 baca51fa bellard
799 5c02c033 Blue Swirl
static inline FDrive *drv1(FDCtrl *fdctrl)
800 baca51fa bellard
{
801 46d3233b blueswir1
    if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (1 << 2))
802 46d3233b blueswir1
        return &fdctrl->drives[1];
803 46d3233b blueswir1
    else
804 46d3233b blueswir1
        return &fdctrl->drives[0];
805 baca51fa bellard
}
806 baca51fa bellard
807 78ae820c blueswir1
#if MAX_FD == 4
808 5c02c033 Blue Swirl
static inline FDrive *drv2(FDCtrl *fdctrl)
809 78ae820c blueswir1
{
810 78ae820c blueswir1
    if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (2 << 2))
811 78ae820c blueswir1
        return &fdctrl->drives[2];
812 78ae820c blueswir1
    else
813 78ae820c blueswir1
        return &fdctrl->drives[1];
814 78ae820c blueswir1
}
815 78ae820c blueswir1
816 5c02c033 Blue Swirl
static inline FDrive *drv3(FDCtrl *fdctrl)
817 78ae820c blueswir1
{
818 78ae820c blueswir1
    if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (3 << 2))
819 78ae820c blueswir1
        return &fdctrl->drives[3];
820 78ae820c blueswir1
    else
821 78ae820c blueswir1
        return &fdctrl->drives[2];
822 78ae820c blueswir1
}
823 78ae820c blueswir1
#endif
824 78ae820c blueswir1
825 5c02c033 Blue Swirl
static FDrive *get_cur_drv(FDCtrl *fdctrl)
826 baca51fa bellard
{
827 78ae820c blueswir1
    switch (fdctrl->cur_drv) {
828 78ae820c blueswir1
        case 0: return drv0(fdctrl);
829 78ae820c blueswir1
        case 1: return drv1(fdctrl);
830 78ae820c blueswir1
#if MAX_FD == 4
831 78ae820c blueswir1
        case 2: return drv2(fdctrl);
832 78ae820c blueswir1
        case 3: return drv3(fdctrl);
833 78ae820c blueswir1
#endif
834 78ae820c blueswir1
        default: return NULL;
835 78ae820c blueswir1
    }
836 8977f3c1 bellard
}
837 8977f3c1 bellard
838 8c6a4d77 blueswir1
/* Status A register : 0x00 (read-only) */
839 5c02c033 Blue Swirl
static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl)
840 8c6a4d77 blueswir1
{
841 8c6a4d77 blueswir1
    uint32_t retval = fdctrl->sra;
842 8c6a4d77 blueswir1
843 8c6a4d77 blueswir1
    FLOPPY_DPRINTF("status register A: 0x%02x\n", retval);
844 8c6a4d77 blueswir1
845 8c6a4d77 blueswir1
    return retval;
846 8c6a4d77 blueswir1
}
847 8c6a4d77 blueswir1
848 8977f3c1 bellard
/* Status B register : 0x01 (read-only) */
849 5c02c033 Blue Swirl
static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl)
850 8977f3c1 bellard
{
851 8c6a4d77 blueswir1
    uint32_t retval = fdctrl->srb;
852 8c6a4d77 blueswir1
853 8c6a4d77 blueswir1
    FLOPPY_DPRINTF("status register B: 0x%02x\n", retval);
854 8c6a4d77 blueswir1
855 8c6a4d77 blueswir1
    return retval;
856 8977f3c1 bellard
}
857 8977f3c1 bellard
858 8977f3c1 bellard
/* Digital output register : 0x02 */
859 5c02c033 Blue Swirl
static uint32_t fdctrl_read_dor(FDCtrl *fdctrl)
860 8977f3c1 bellard
{
861 1c346df2 blueswir1
    uint32_t retval = fdctrl->dor;
862 8977f3c1 bellard
863 8977f3c1 bellard
    /* Selected drive */
864 baca51fa bellard
    retval |= fdctrl->cur_drv;
865 8977f3c1 bellard
    FLOPPY_DPRINTF("digital output register: 0x%02x\n", retval);
866 8977f3c1 bellard
867 8977f3c1 bellard
    return retval;
868 8977f3c1 bellard
}
869 8977f3c1 bellard
870 5c02c033 Blue Swirl
static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value)
871 8977f3c1 bellard
{
872 8977f3c1 bellard
    FLOPPY_DPRINTF("digital output register set to 0x%02x\n", value);
873 8c6a4d77 blueswir1
874 8c6a4d77 blueswir1
    /* Motors */
875 8c6a4d77 blueswir1
    if (value & FD_DOR_MOTEN0)
876 8c6a4d77 blueswir1
        fdctrl->srb |= FD_SRB_MTR0;
877 8c6a4d77 blueswir1
    else
878 8c6a4d77 blueswir1
        fdctrl->srb &= ~FD_SRB_MTR0;
879 8c6a4d77 blueswir1
    if (value & FD_DOR_MOTEN1)
880 8c6a4d77 blueswir1
        fdctrl->srb |= FD_SRB_MTR1;
881 8c6a4d77 blueswir1
    else
882 8c6a4d77 blueswir1
        fdctrl->srb &= ~FD_SRB_MTR1;
883 8c6a4d77 blueswir1
884 8c6a4d77 blueswir1
    /* Drive */
885 8c6a4d77 blueswir1
    if (value & 1)
886 8c6a4d77 blueswir1
        fdctrl->srb |= FD_SRB_DR0;
887 8c6a4d77 blueswir1
    else
888 8c6a4d77 blueswir1
        fdctrl->srb &= ~FD_SRB_DR0;
889 8c6a4d77 blueswir1
890 8977f3c1 bellard
    /* Reset */
891 9fea808a blueswir1
    if (!(value & FD_DOR_nRESET)) {
892 1c346df2 blueswir1
        if (fdctrl->dor & FD_DOR_nRESET) {
893 4b19ec0c bellard
            FLOPPY_DPRINTF("controller enter RESET state\n");
894 8977f3c1 bellard
        }
895 8977f3c1 bellard
    } else {
896 1c346df2 blueswir1
        if (!(fdctrl->dor & FD_DOR_nRESET)) {
897 4b19ec0c bellard
            FLOPPY_DPRINTF("controller out of RESET state\n");
898 fb6cf1d0 bellard
            fdctrl_reset(fdctrl, 1);
899 b9b3d225 blueswir1
            fdctrl->dsr &= ~FD_DSR_PWRDOWN;
900 8977f3c1 bellard
        }
901 8977f3c1 bellard
    }
902 8977f3c1 bellard
    /* Selected drive */
903 9fea808a blueswir1
    fdctrl->cur_drv = value & FD_DOR_SELMASK;
904 368df94d blueswir1
905 368df94d blueswir1
    fdctrl->dor = value;
906 8977f3c1 bellard
}
907 8977f3c1 bellard
908 8977f3c1 bellard
/* Tape drive register : 0x03 */
909 5c02c033 Blue Swirl
static uint32_t fdctrl_read_tape(FDCtrl *fdctrl)
910 8977f3c1 bellard
{
911 46d3233b blueswir1
    uint32_t retval = fdctrl->tdr;
912 8977f3c1 bellard
913 8977f3c1 bellard
    FLOPPY_DPRINTF("tape drive register: 0x%02x\n", retval);
914 8977f3c1 bellard
915 8977f3c1 bellard
    return retval;
916 8977f3c1 bellard
}
917 8977f3c1 bellard
918 5c02c033 Blue Swirl
static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value)
919 8977f3c1 bellard
{
920 8977f3c1 bellard
    /* Reset mode */
921 1c346df2 blueswir1
    if (!(fdctrl->dor & FD_DOR_nRESET)) {
922 4b19ec0c bellard
        FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
923 8977f3c1 bellard
        return;
924 8977f3c1 bellard
    }
925 8977f3c1 bellard
    FLOPPY_DPRINTF("tape drive register set to 0x%02x\n", value);
926 8977f3c1 bellard
    /* Disk boot selection indicator */
927 46d3233b blueswir1
    fdctrl->tdr = value & FD_TDR_BOOTSEL;
928 8977f3c1 bellard
    /* Tape indicators: never allow */
929 8977f3c1 bellard
}
930 8977f3c1 bellard
931 8977f3c1 bellard
/* Main status register : 0x04 (read) */
932 5c02c033 Blue Swirl
static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl)
933 8977f3c1 bellard
{
934 b9b3d225 blueswir1
    uint32_t retval = fdctrl->msr;
935 8977f3c1 bellard
936 b9b3d225 blueswir1
    fdctrl->dsr &= ~FD_DSR_PWRDOWN;
937 1c346df2 blueswir1
    fdctrl->dor |= FD_DOR_nRESET;
938 b9b3d225 blueswir1
939 82407d1a Artyom Tarasenko
    /* Sparc mutation */
940 82407d1a Artyom Tarasenko
    if (fdctrl->sun4m) {
941 82407d1a Artyom Tarasenko
        retval |= FD_MSR_DIO;
942 82407d1a Artyom Tarasenko
        fdctrl_reset_irq(fdctrl);
943 82407d1a Artyom Tarasenko
    };
944 82407d1a Artyom Tarasenko
945 8977f3c1 bellard
    FLOPPY_DPRINTF("main status register: 0x%02x\n", retval);
946 8977f3c1 bellard
947 8977f3c1 bellard
    return retval;
948 8977f3c1 bellard
}
949 8977f3c1 bellard
950 8977f3c1 bellard
/* Data select rate register : 0x04 (write) */
951 5c02c033 Blue Swirl
static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value)
952 8977f3c1 bellard
{
953 8977f3c1 bellard
    /* Reset mode */
954 1c346df2 blueswir1
    if (!(fdctrl->dor & FD_DOR_nRESET)) {
955 4f431960 j_mayer
        FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
956 4f431960 j_mayer
        return;
957 4f431960 j_mayer
    }
958 8977f3c1 bellard
    FLOPPY_DPRINTF("select rate register set to 0x%02x\n", value);
959 8977f3c1 bellard
    /* Reset: autoclear */
960 9fea808a blueswir1
    if (value & FD_DSR_SWRESET) {
961 1c346df2 blueswir1
        fdctrl->dor &= ~FD_DOR_nRESET;
962 baca51fa bellard
        fdctrl_reset(fdctrl, 1);
963 1c346df2 blueswir1
        fdctrl->dor |= FD_DOR_nRESET;
964 8977f3c1 bellard
    }
965 9fea808a blueswir1
    if (value & FD_DSR_PWRDOWN) {
966 baca51fa bellard
        fdctrl_reset(fdctrl, 1);
967 8977f3c1 bellard
    }
968 b9b3d225 blueswir1
    fdctrl->dsr = value;
969 8977f3c1 bellard
}
970 8977f3c1 bellard
971 5c02c033 Blue Swirl
static int fdctrl_media_changed(FDrive *drv)
972 ea185bbd bellard
{
973 ea185bbd bellard
    int ret;
974 4f431960 j_mayer
975 5fafdf24 ths
    if (!drv->bs)
976 ea185bbd bellard
        return 0;
977 ea185bbd bellard
    ret = bdrv_media_changed(drv->bs);
978 ea185bbd bellard
    if (ret) {
979 ea185bbd bellard
        fd_revalidate(drv);
980 ea185bbd bellard
    }
981 ea185bbd bellard
    return ret;
982 ea185bbd bellard
}
983 ea185bbd bellard
984 8977f3c1 bellard
/* Digital input register : 0x07 (read-only) */
985 5c02c033 Blue Swirl
static uint32_t fdctrl_read_dir(FDCtrl *fdctrl)
986 8977f3c1 bellard
{
987 8977f3c1 bellard
    uint32_t retval = 0;
988 8977f3c1 bellard
989 78ae820c blueswir1
    if (fdctrl_media_changed(drv0(fdctrl))
990 78ae820c blueswir1
     || fdctrl_media_changed(drv1(fdctrl))
991 78ae820c blueswir1
#if MAX_FD == 4
992 78ae820c blueswir1
     || fdctrl_media_changed(drv2(fdctrl))
993 78ae820c blueswir1
     || fdctrl_media_changed(drv3(fdctrl))
994 78ae820c blueswir1
#endif
995 78ae820c blueswir1
        )
996 9fea808a blueswir1
        retval |= FD_DIR_DSKCHG;
997 8977f3c1 bellard
    if (retval != 0)
998 baca51fa bellard
        FLOPPY_DPRINTF("Floppy digital input register: 0x%02x\n", retval);
999 8977f3c1 bellard
1000 8977f3c1 bellard
    return retval;
1001 8977f3c1 bellard
}
1002 8977f3c1 bellard
1003 8977f3c1 bellard
/* FIFO state control */
1004 5c02c033 Blue Swirl
static void fdctrl_reset_fifo(FDCtrl *fdctrl)
1005 8977f3c1 bellard
{
1006 baca51fa bellard
    fdctrl->data_dir = FD_DIR_WRITE;
1007 baca51fa bellard
    fdctrl->data_pos = 0;
1008 b9b3d225 blueswir1
    fdctrl->msr &= ~(FD_MSR_CMDBUSY | FD_MSR_DIO);
1009 8977f3c1 bellard
}
1010 8977f3c1 bellard
1011 8977f3c1 bellard
/* Set FIFO status for the host to read */
1012 5c02c033 Blue Swirl
static void fdctrl_set_fifo(FDCtrl *fdctrl, int fifo_len, int do_irq)
1013 8977f3c1 bellard
{
1014 baca51fa bellard
    fdctrl->data_dir = FD_DIR_READ;
1015 baca51fa bellard
    fdctrl->data_len = fifo_len;
1016 baca51fa bellard
    fdctrl->data_pos = 0;
1017 b9b3d225 blueswir1
    fdctrl->msr |= FD_MSR_CMDBUSY | FD_MSR_RQM | FD_MSR_DIO;
1018 8977f3c1 bellard
    if (do_irq)
1019 baca51fa bellard
        fdctrl_raise_irq(fdctrl, 0x00);
1020 8977f3c1 bellard
}
1021 8977f3c1 bellard
1022 8977f3c1 bellard
/* Set an error: unimplemented/unknown command */
1023 5c02c033 Blue Swirl
static void fdctrl_unimplemented(FDCtrl *fdctrl, int direction)
1024 8977f3c1 bellard
{
1025 77370520 blueswir1
    FLOPPY_ERROR("unimplemented command 0x%02x\n", fdctrl->fifo[0]);
1026 9fea808a blueswir1
    fdctrl->fifo[0] = FD_SR0_INVCMD;
1027 baca51fa bellard
    fdctrl_set_fifo(fdctrl, 1, 0);
1028 8977f3c1 bellard
}
1029 8977f3c1 bellard
1030 746d6de7 blueswir1
/* Seek to next sector */
1031 5c02c033 Blue Swirl
static int fdctrl_seek_to_next_sect(FDCtrl *fdctrl, FDrive *cur_drv)
1032 746d6de7 blueswir1
{
1033 746d6de7 blueswir1
    FLOPPY_DPRINTF("seek to next sector (%d %02x %02x => %d)\n",
1034 746d6de7 blueswir1
                   cur_drv->head, cur_drv->track, cur_drv->sect,
1035 746d6de7 blueswir1
                   fd_sector(cur_drv));
1036 746d6de7 blueswir1
    /* XXX: cur_drv->sect >= cur_drv->last_sect should be an
1037 746d6de7 blueswir1
       error in fact */
1038 746d6de7 blueswir1
    if (cur_drv->sect >= cur_drv->last_sect ||
1039 746d6de7 blueswir1
        cur_drv->sect == fdctrl->eot) {
1040 746d6de7 blueswir1
        cur_drv->sect = 1;
1041 746d6de7 blueswir1
        if (FD_MULTI_TRACK(fdctrl->data_state)) {
1042 746d6de7 blueswir1
            if (cur_drv->head == 0 &&
1043 746d6de7 blueswir1
                (cur_drv->flags & FDISK_DBL_SIDES) != 0) {
1044 746d6de7 blueswir1
                cur_drv->head = 1;
1045 746d6de7 blueswir1
            } else {
1046 746d6de7 blueswir1
                cur_drv->head = 0;
1047 746d6de7 blueswir1
                cur_drv->track++;
1048 746d6de7 blueswir1
                if ((cur_drv->flags & FDISK_DBL_SIDES) == 0)
1049 746d6de7 blueswir1
                    return 0;
1050 746d6de7 blueswir1
            }
1051 746d6de7 blueswir1
        } else {
1052 746d6de7 blueswir1
            cur_drv->track++;
1053 746d6de7 blueswir1
            return 0;
1054 746d6de7 blueswir1
        }
1055 746d6de7 blueswir1
        FLOPPY_DPRINTF("seek to next track (%d %02x %02x => %d)\n",
1056 746d6de7 blueswir1
                       cur_drv->head, cur_drv->track,
1057 746d6de7 blueswir1
                       cur_drv->sect, fd_sector(cur_drv));
1058 746d6de7 blueswir1
    } else {
1059 746d6de7 blueswir1
        cur_drv->sect++;
1060 746d6de7 blueswir1
    }
1061 746d6de7 blueswir1
    return 1;
1062 746d6de7 blueswir1
}
1063 746d6de7 blueswir1
1064 8977f3c1 bellard
/* Callback for transfer end (stop or abort) */
1065 5c02c033 Blue Swirl
static void fdctrl_stop_transfer(FDCtrl *fdctrl, uint8_t status0,
1066 5c02c033 Blue Swirl
                                 uint8_t status1, uint8_t status2)
1067 8977f3c1 bellard
{
1068 5c02c033 Blue Swirl
    FDrive *cur_drv;
1069 8977f3c1 bellard
1070 baca51fa bellard
    cur_drv = get_cur_drv(fdctrl);
1071 8977f3c1 bellard
    FLOPPY_DPRINTF("transfer status: %02x %02x %02x (%02x)\n",
1072 8977f3c1 bellard
                   status0, status1, status2,
1073 cefec4f5 blueswir1
                   status0 | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl));
1074 cefec4f5 blueswir1
    fdctrl->fifo[0] = status0 | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1075 baca51fa bellard
    fdctrl->fifo[1] = status1;
1076 baca51fa bellard
    fdctrl->fifo[2] = status2;
1077 baca51fa bellard
    fdctrl->fifo[3] = cur_drv->track;
1078 baca51fa bellard
    fdctrl->fifo[4] = cur_drv->head;
1079 baca51fa bellard
    fdctrl->fifo[5] = cur_drv->sect;
1080 baca51fa bellard
    fdctrl->fifo[6] = FD_SECTOR_SC;
1081 baca51fa bellard
    fdctrl->data_dir = FD_DIR_READ;
1082 368df94d blueswir1
    if (!(fdctrl->msr & FD_MSR_NONDMA)) {
1083 baca51fa bellard
        DMA_release_DREQ(fdctrl->dma_chann);
1084 ed5fd2cc bellard
    }
1085 b9b3d225 blueswir1
    fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
1086 368df94d blueswir1
    fdctrl->msr &= ~FD_MSR_NONDMA;
1087 baca51fa bellard
    fdctrl_set_fifo(fdctrl, 7, 1);
1088 8977f3c1 bellard
}
1089 8977f3c1 bellard
1090 8977f3c1 bellard
/* Prepare a data transfer (either DMA or FIFO) */
1091 5c02c033 Blue Swirl
static void fdctrl_start_transfer(FDCtrl *fdctrl, int direction)
1092 8977f3c1 bellard
{
1093 5c02c033 Blue Swirl
    FDrive *cur_drv;
1094 8977f3c1 bellard
    uint8_t kh, kt, ks;
1095 77370520 blueswir1
    int did_seek = 0;
1096 8977f3c1 bellard
1097 cefec4f5 blueswir1
    SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1098 baca51fa bellard
    cur_drv = get_cur_drv(fdctrl);
1099 baca51fa bellard
    kt = fdctrl->fifo[2];
1100 baca51fa bellard
    kh = fdctrl->fifo[3];
1101 baca51fa bellard
    ks = fdctrl->fifo[4];
1102 4b19ec0c bellard
    FLOPPY_DPRINTF("Start transfer at %d %d %02x %02x (%d)\n",
1103 cefec4f5 blueswir1
                   GET_CUR_DRV(fdctrl), kh, kt, ks,
1104 7859cb98 Blue Swirl
                   fd_sector_calc(kh, kt, ks, cur_drv->last_sect));
1105 77370520 blueswir1
    switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
1106 8977f3c1 bellard
    case 2:
1107 8977f3c1 bellard
        /* sect too big */
1108 9fea808a blueswir1
        fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1109 baca51fa bellard
        fdctrl->fifo[3] = kt;
1110 baca51fa bellard
        fdctrl->fifo[4] = kh;
1111 baca51fa bellard
        fdctrl->fifo[5] = ks;
1112 8977f3c1 bellard
        return;
1113 8977f3c1 bellard
    case 3:
1114 8977f3c1 bellard
        /* track too big */
1115 77370520 blueswir1
        fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
1116 baca51fa bellard
        fdctrl->fifo[3] = kt;
1117 baca51fa bellard
        fdctrl->fifo[4] = kh;
1118 baca51fa bellard
        fdctrl->fifo[5] = ks;
1119 8977f3c1 bellard
        return;
1120 8977f3c1 bellard
    case 4:
1121 8977f3c1 bellard
        /* No seek enabled */
1122 9fea808a blueswir1
        fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1123 baca51fa bellard
        fdctrl->fifo[3] = kt;
1124 baca51fa bellard
        fdctrl->fifo[4] = kh;
1125 baca51fa bellard
        fdctrl->fifo[5] = ks;
1126 8977f3c1 bellard
        return;
1127 8977f3c1 bellard
    case 1:
1128 8977f3c1 bellard
        did_seek = 1;
1129 8977f3c1 bellard
        break;
1130 8977f3c1 bellard
    default:
1131 8977f3c1 bellard
        break;
1132 8977f3c1 bellard
    }
1133 b9b3d225 blueswir1
1134 8977f3c1 bellard
    /* Set the FIFO state */
1135 baca51fa bellard
    fdctrl->data_dir = direction;
1136 baca51fa bellard
    fdctrl->data_pos = 0;
1137 b9b3d225 blueswir1
    fdctrl->msr |= FD_MSR_CMDBUSY;
1138 baca51fa bellard
    if (fdctrl->fifo[0] & 0x80)
1139 baca51fa bellard
        fdctrl->data_state |= FD_STATE_MULTI;
1140 baca51fa bellard
    else
1141 baca51fa bellard
        fdctrl->data_state &= ~FD_STATE_MULTI;
1142 8977f3c1 bellard
    if (did_seek)
1143 baca51fa bellard
        fdctrl->data_state |= FD_STATE_SEEK;
1144 baca51fa bellard
    else
1145 baca51fa bellard
        fdctrl->data_state &= ~FD_STATE_SEEK;
1146 baca51fa bellard
    if (fdctrl->fifo[5] == 00) {
1147 baca51fa bellard
        fdctrl->data_len = fdctrl->fifo[8];
1148 baca51fa bellard
    } else {
1149 4f431960 j_mayer
        int tmp;
1150 3bcb80f1 ths
        fdctrl->data_len = 128 << (fdctrl->fifo[5] > 7 ? 7 : fdctrl->fifo[5]);
1151 771effeb blueswir1
        tmp = (fdctrl->fifo[6] - ks + 1);
1152 baca51fa bellard
        if (fdctrl->fifo[0] & 0x80)
1153 771effeb blueswir1
            tmp += fdctrl->fifo[6];
1154 4f431960 j_mayer
        fdctrl->data_len *= tmp;
1155 baca51fa bellard
    }
1156 890fa6be bellard
    fdctrl->eot = fdctrl->fifo[6];
1157 368df94d blueswir1
    if (fdctrl->dor & FD_DOR_DMAEN) {
1158 8977f3c1 bellard
        int dma_mode;
1159 8977f3c1 bellard
        /* DMA transfer are enabled. Check if DMA channel is well programmed */
1160 baca51fa bellard
        dma_mode = DMA_get_channel_mode(fdctrl->dma_chann);
1161 8977f3c1 bellard
        dma_mode = (dma_mode >> 2) & 3;
1162 baca51fa bellard
        FLOPPY_DPRINTF("dma_mode=%d direction=%d (%d - %d)\n",
1163 4f431960 j_mayer
                       dma_mode, direction,
1164 baca51fa bellard
                       (128 << fdctrl->fifo[5]) *
1165 4f431960 j_mayer
                       (cur_drv->last_sect - ks + 1), fdctrl->data_len);
1166 8977f3c1 bellard
        if (((direction == FD_DIR_SCANE || direction == FD_DIR_SCANL ||
1167 8977f3c1 bellard
              direction == FD_DIR_SCANH) && dma_mode == 0) ||
1168 8977f3c1 bellard
            (direction == FD_DIR_WRITE && dma_mode == 2) ||
1169 8977f3c1 bellard
            (direction == FD_DIR_READ && dma_mode == 1)) {
1170 8977f3c1 bellard
            /* No access is allowed until DMA transfer has completed */
1171 b9b3d225 blueswir1
            fdctrl->msr &= ~FD_MSR_RQM;
1172 4b19ec0c bellard
            /* Now, we just have to wait for the DMA controller to
1173 8977f3c1 bellard
             * recall us...
1174 8977f3c1 bellard
             */
1175 baca51fa bellard
            DMA_hold_DREQ(fdctrl->dma_chann);
1176 baca51fa bellard
            DMA_schedule(fdctrl->dma_chann);
1177 8977f3c1 bellard
            return;
1178 baca51fa bellard
        } else {
1179 4f431960 j_mayer
            FLOPPY_ERROR("dma_mode=%d direction=%d\n", dma_mode, direction);
1180 8977f3c1 bellard
        }
1181 8977f3c1 bellard
    }
1182 8977f3c1 bellard
    FLOPPY_DPRINTF("start non-DMA transfer\n");
1183 368df94d blueswir1
    fdctrl->msr |= FD_MSR_NONDMA;
1184 b9b3d225 blueswir1
    if (direction != FD_DIR_WRITE)
1185 b9b3d225 blueswir1
        fdctrl->msr |= FD_MSR_DIO;
1186 8977f3c1 bellard
    /* IO based transfer: calculate len */
1187 baca51fa bellard
    fdctrl_raise_irq(fdctrl, 0x00);
1188 8977f3c1 bellard
1189 8977f3c1 bellard
    return;
1190 8977f3c1 bellard
}
1191 8977f3c1 bellard
1192 8977f3c1 bellard
/* Prepare a transfer of deleted data */
1193 5c02c033 Blue Swirl
static void fdctrl_start_transfer_del(FDCtrl *fdctrl, int direction)
1194 8977f3c1 bellard
{
1195 77370520 blueswir1
    FLOPPY_ERROR("fdctrl_start_transfer_del() unimplemented\n");
1196 77370520 blueswir1
1197 8977f3c1 bellard
    /* We don't handle deleted data,
1198 8977f3c1 bellard
     * so we don't return *ANYTHING*
1199 8977f3c1 bellard
     */
1200 9fea808a blueswir1
    fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1201 8977f3c1 bellard
}
1202 8977f3c1 bellard
1203 8977f3c1 bellard
/* handlers for DMA transfers */
1204 85571bc7 bellard
static int fdctrl_transfer_handler (void *opaque, int nchan,
1205 85571bc7 bellard
                                    int dma_pos, int dma_len)
1206 8977f3c1 bellard
{
1207 5c02c033 Blue Swirl
    FDCtrl *fdctrl;
1208 5c02c033 Blue Swirl
    FDrive *cur_drv;
1209 baca51fa bellard
    int len, start_pos, rel_pos;
1210 8977f3c1 bellard
    uint8_t status0 = 0x00, status1 = 0x00, status2 = 0x00;
1211 8977f3c1 bellard
1212 baca51fa bellard
    fdctrl = opaque;
1213 b9b3d225 blueswir1
    if (fdctrl->msr & FD_MSR_RQM) {
1214 8977f3c1 bellard
        FLOPPY_DPRINTF("Not in DMA transfer mode !\n");
1215 8977f3c1 bellard
        return 0;
1216 8977f3c1 bellard
    }
1217 baca51fa bellard
    cur_drv = get_cur_drv(fdctrl);
1218 baca51fa bellard
    if (fdctrl->data_dir == FD_DIR_SCANE || fdctrl->data_dir == FD_DIR_SCANL ||
1219 baca51fa bellard
        fdctrl->data_dir == FD_DIR_SCANH)
1220 77370520 blueswir1
        status2 = FD_SR2_SNS;
1221 85571bc7 bellard
    if (dma_len > fdctrl->data_len)
1222 85571bc7 bellard
        dma_len = fdctrl->data_len;
1223 890fa6be bellard
    if (cur_drv->bs == NULL) {
1224 4f431960 j_mayer
        if (fdctrl->data_dir == FD_DIR_WRITE)
1225 9fea808a blueswir1
            fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1226 4f431960 j_mayer
        else
1227 9fea808a blueswir1
            fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1228 4f431960 j_mayer
        len = 0;
1229 890fa6be bellard
        goto transfer_error;
1230 890fa6be bellard
    }
1231 baca51fa bellard
    rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1232 85571bc7 bellard
    for (start_pos = fdctrl->data_pos; fdctrl->data_pos < dma_len;) {
1233 85571bc7 bellard
        len = dma_len - fdctrl->data_pos;
1234 baca51fa bellard
        if (len + rel_pos > FD_SECTOR_LEN)
1235 baca51fa bellard
            len = FD_SECTOR_LEN - rel_pos;
1236 6f7e9aec bellard
        FLOPPY_DPRINTF("copy %d bytes (%d %d %d) %d pos %d %02x "
1237 6f7e9aec bellard
                       "(%d-0x%08x 0x%08x)\n", len, dma_len, fdctrl->data_pos,
1238 cefec4f5 blueswir1
                       fdctrl->data_len, GET_CUR_DRV(fdctrl), cur_drv->head,
1239 baca51fa bellard
                       cur_drv->track, cur_drv->sect, fd_sector(cur_drv),
1240 9fea808a blueswir1
                       fd_sector(cur_drv) * FD_SECTOR_LEN);
1241 baca51fa bellard
        if (fdctrl->data_dir != FD_DIR_WRITE ||
1242 4f431960 j_mayer
            len < FD_SECTOR_LEN || rel_pos != 0) {
1243 baca51fa bellard
            /* READ & SCAN commands and realign to a sector for WRITE */
1244 baca51fa bellard
            if (bdrv_read(cur_drv->bs, fd_sector(cur_drv),
1245 4f431960 j_mayer
                          fdctrl->fifo, 1) < 0) {
1246 8977f3c1 bellard
                FLOPPY_DPRINTF("Floppy: error getting sector %d\n",
1247 8977f3c1 bellard
                               fd_sector(cur_drv));
1248 8977f3c1 bellard
                /* Sure, image size is too small... */
1249 baca51fa bellard
                memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1250 8977f3c1 bellard
            }
1251 890fa6be bellard
        }
1252 4f431960 j_mayer
        switch (fdctrl->data_dir) {
1253 4f431960 j_mayer
        case FD_DIR_READ:
1254 4f431960 j_mayer
            /* READ commands */
1255 85571bc7 bellard
            DMA_write_memory (nchan, fdctrl->fifo + rel_pos,
1256 85571bc7 bellard
                              fdctrl->data_pos, len);
1257 4f431960 j_mayer
            break;
1258 4f431960 j_mayer
        case FD_DIR_WRITE:
1259 baca51fa bellard
            /* WRITE commands */
1260 85571bc7 bellard
            DMA_read_memory (nchan, fdctrl->fifo + rel_pos,
1261 85571bc7 bellard
                             fdctrl->data_pos, len);
1262 baca51fa bellard
            if (bdrv_write(cur_drv->bs, fd_sector(cur_drv),
1263 4f431960 j_mayer
                           fdctrl->fifo, 1) < 0) {
1264 77370520 blueswir1
                FLOPPY_ERROR("writing sector %d\n", fd_sector(cur_drv));
1265 9fea808a blueswir1
                fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1266 baca51fa bellard
                goto transfer_error;
1267 890fa6be bellard
            }
1268 4f431960 j_mayer
            break;
1269 4f431960 j_mayer
        default:
1270 4f431960 j_mayer
            /* SCAN commands */
1271 baca51fa bellard
            {
1272 4f431960 j_mayer
                uint8_t tmpbuf[FD_SECTOR_LEN];
1273 baca51fa bellard
                int ret;
1274 85571bc7 bellard
                DMA_read_memory (nchan, tmpbuf, fdctrl->data_pos, len);
1275 baca51fa bellard
                ret = memcmp(tmpbuf, fdctrl->fifo + rel_pos, len);
1276 8977f3c1 bellard
                if (ret == 0) {
1277 77370520 blueswir1
                    status2 = FD_SR2_SEH;
1278 8977f3c1 bellard
                    goto end_transfer;
1279 8977f3c1 bellard
                }
1280 baca51fa bellard
                if ((ret < 0 && fdctrl->data_dir == FD_DIR_SCANL) ||
1281 baca51fa bellard
                    (ret > 0 && fdctrl->data_dir == FD_DIR_SCANH)) {
1282 8977f3c1 bellard
                    status2 = 0x00;
1283 8977f3c1 bellard
                    goto end_transfer;
1284 8977f3c1 bellard
                }
1285 8977f3c1 bellard
            }
1286 4f431960 j_mayer
            break;
1287 8977f3c1 bellard
        }
1288 4f431960 j_mayer
        fdctrl->data_pos += len;
1289 4f431960 j_mayer
        rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1290 baca51fa bellard
        if (rel_pos == 0) {
1291 8977f3c1 bellard
            /* Seek to next sector */
1292 746d6de7 blueswir1
            if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv))
1293 746d6de7 blueswir1
                break;
1294 8977f3c1 bellard
        }
1295 8977f3c1 bellard
    }
1296 4f431960 j_mayer
 end_transfer:
1297 baca51fa bellard
    len = fdctrl->data_pos - start_pos;
1298 baca51fa bellard
    FLOPPY_DPRINTF("end transfer %d %d %d\n",
1299 4f431960 j_mayer
                   fdctrl->data_pos, len, fdctrl->data_len);
1300 baca51fa bellard
    if (fdctrl->data_dir == FD_DIR_SCANE ||
1301 baca51fa bellard
        fdctrl->data_dir == FD_DIR_SCANL ||
1302 baca51fa bellard
        fdctrl->data_dir == FD_DIR_SCANH)
1303 77370520 blueswir1
        status2 = FD_SR2_SEH;
1304 baca51fa bellard
    if (FD_DID_SEEK(fdctrl->data_state))
1305 9fea808a blueswir1
        status0 |= FD_SR0_SEEK;
1306 baca51fa bellard
    fdctrl->data_len -= len;
1307 890fa6be bellard
    fdctrl_stop_transfer(fdctrl, status0, status1, status2);
1308 4f431960 j_mayer
 transfer_error:
1309 8977f3c1 bellard
1310 baca51fa bellard
    return len;
1311 8977f3c1 bellard
}
1312 8977f3c1 bellard
1313 8977f3c1 bellard
/* Data register : 0x05 */
1314 5c02c033 Blue Swirl
static uint32_t fdctrl_read_data(FDCtrl *fdctrl)
1315 8977f3c1 bellard
{
1316 5c02c033 Blue Swirl
    FDrive *cur_drv;
1317 8977f3c1 bellard
    uint32_t retval = 0;
1318 746d6de7 blueswir1
    int pos;
1319 8977f3c1 bellard
1320 baca51fa bellard
    cur_drv = get_cur_drv(fdctrl);
1321 b9b3d225 blueswir1
    fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1322 b9b3d225 blueswir1
    if (!(fdctrl->msr & FD_MSR_RQM) || !(fdctrl->msr & FD_MSR_DIO)) {
1323 b9b3d225 blueswir1
        FLOPPY_ERROR("controller not ready for reading\n");
1324 8977f3c1 bellard
        return 0;
1325 8977f3c1 bellard
    }
1326 baca51fa bellard
    pos = fdctrl->data_pos;
1327 368df94d blueswir1
    if (fdctrl->msr & FD_MSR_NONDMA) {
1328 8977f3c1 bellard
        pos %= FD_SECTOR_LEN;
1329 8977f3c1 bellard
        if (pos == 0) {
1330 746d6de7 blueswir1
            if (fdctrl->data_pos != 0)
1331 746d6de7 blueswir1
                if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1332 746d6de7 blueswir1
                    FLOPPY_DPRINTF("error seeking to next sector %d\n",
1333 746d6de7 blueswir1
                                   fd_sector(cur_drv));
1334 746d6de7 blueswir1
                    return 0;
1335 746d6de7 blueswir1
                }
1336 77370520 blueswir1
            if (bdrv_read(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1337 77370520 blueswir1
                FLOPPY_DPRINTF("error getting sector %d\n",
1338 77370520 blueswir1
                               fd_sector(cur_drv));
1339 77370520 blueswir1
                /* Sure, image size is too small... */
1340 77370520 blueswir1
                memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1341 77370520 blueswir1
            }
1342 8977f3c1 bellard
        }
1343 8977f3c1 bellard
    }
1344 baca51fa bellard
    retval = fdctrl->fifo[pos];
1345 baca51fa bellard
    if (++fdctrl->data_pos == fdctrl->data_len) {
1346 baca51fa bellard
        fdctrl->data_pos = 0;
1347 890fa6be bellard
        /* Switch from transfer mode to status mode
1348 8977f3c1 bellard
         * then from status mode to command mode
1349 8977f3c1 bellard
         */
1350 368df94d blueswir1
        if (fdctrl->msr & FD_MSR_NONDMA) {
1351 9fea808a blueswir1
            fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1352 ed5fd2cc bellard
        } else {
1353 baca51fa bellard
            fdctrl_reset_fifo(fdctrl);
1354 ed5fd2cc bellard
            fdctrl_reset_irq(fdctrl);
1355 ed5fd2cc bellard
        }
1356 8977f3c1 bellard
    }
1357 8977f3c1 bellard
    FLOPPY_DPRINTF("data register: 0x%02x\n", retval);
1358 8977f3c1 bellard
1359 8977f3c1 bellard
    return retval;
1360 8977f3c1 bellard
}
1361 8977f3c1 bellard
1362 5c02c033 Blue Swirl
static void fdctrl_format_sector(FDCtrl *fdctrl)
1363 8977f3c1 bellard
{
1364 5c02c033 Blue Swirl
    FDrive *cur_drv;
1365 baca51fa bellard
    uint8_t kh, kt, ks;
1366 8977f3c1 bellard
1367 cefec4f5 blueswir1
    SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1368 baca51fa bellard
    cur_drv = get_cur_drv(fdctrl);
1369 baca51fa bellard
    kt = fdctrl->fifo[6];
1370 baca51fa bellard
    kh = fdctrl->fifo[7];
1371 baca51fa bellard
    ks = fdctrl->fifo[8];
1372 baca51fa bellard
    FLOPPY_DPRINTF("format sector at %d %d %02x %02x (%d)\n",
1373 cefec4f5 blueswir1
                   GET_CUR_DRV(fdctrl), kh, kt, ks,
1374 7859cb98 Blue Swirl
                   fd_sector_calc(kh, kt, ks, cur_drv->last_sect));
1375 9fea808a blueswir1
    switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
1376 baca51fa bellard
    case 2:
1377 baca51fa bellard
        /* sect too big */
1378 9fea808a blueswir1
        fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1379 baca51fa bellard
        fdctrl->fifo[3] = kt;
1380 baca51fa bellard
        fdctrl->fifo[4] = kh;
1381 baca51fa bellard
        fdctrl->fifo[5] = ks;
1382 baca51fa bellard
        return;
1383 baca51fa bellard
    case 3:
1384 baca51fa bellard
        /* track too big */
1385 77370520 blueswir1
        fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
1386 baca51fa bellard
        fdctrl->fifo[3] = kt;
1387 baca51fa bellard
        fdctrl->fifo[4] = kh;
1388 baca51fa bellard
        fdctrl->fifo[5] = ks;
1389 baca51fa bellard
        return;
1390 baca51fa bellard
    case 4:
1391 baca51fa bellard
        /* No seek enabled */
1392 9fea808a blueswir1
        fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1393 baca51fa bellard
        fdctrl->fifo[3] = kt;
1394 baca51fa bellard
        fdctrl->fifo[4] = kh;
1395 baca51fa bellard
        fdctrl->fifo[5] = ks;
1396 baca51fa bellard
        return;
1397 baca51fa bellard
    case 1:
1398 baca51fa bellard
        fdctrl->data_state |= FD_STATE_SEEK;
1399 baca51fa bellard
        break;
1400 baca51fa bellard
    default:
1401 baca51fa bellard
        break;
1402 baca51fa bellard
    }
1403 baca51fa bellard
    memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1404 baca51fa bellard
    if (cur_drv->bs == NULL ||
1405 baca51fa bellard
        bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1406 37a4c539 ths
        FLOPPY_ERROR("formatting sector %d\n", fd_sector(cur_drv));
1407 9fea808a blueswir1
        fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1408 baca51fa bellard
    } else {
1409 4f431960 j_mayer
        if (cur_drv->sect == cur_drv->last_sect) {
1410 4f431960 j_mayer
            fdctrl->data_state &= ~FD_STATE_FORMAT;
1411 4f431960 j_mayer
            /* Last sector done */
1412 4f431960 j_mayer
            if (FD_DID_SEEK(fdctrl->data_state))
1413 9fea808a blueswir1
                fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1414 4f431960 j_mayer
            else
1415 4f431960 j_mayer
                fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1416 4f431960 j_mayer
        } else {
1417 4f431960 j_mayer
            /* More to do */
1418 4f431960 j_mayer
            fdctrl->data_pos = 0;
1419 4f431960 j_mayer
            fdctrl->data_len = 4;
1420 4f431960 j_mayer
        }
1421 baca51fa bellard
    }
1422 baca51fa bellard
}
1423 baca51fa bellard
1424 5c02c033 Blue Swirl
static void fdctrl_handle_lock(FDCtrl *fdctrl, int direction)
1425 65cef780 blueswir1
{
1426 65cef780 blueswir1
    fdctrl->lock = (fdctrl->fifo[0] & 0x80) ? 1 : 0;
1427 65cef780 blueswir1
    fdctrl->fifo[0] = fdctrl->lock << 4;
1428 65cef780 blueswir1
    fdctrl_set_fifo(fdctrl, 1, fdctrl->lock);
1429 65cef780 blueswir1
}
1430 65cef780 blueswir1
1431 5c02c033 Blue Swirl
static void fdctrl_handle_dumpreg(FDCtrl *fdctrl, int direction)
1432 65cef780 blueswir1
{
1433 5c02c033 Blue Swirl
    FDrive *cur_drv = get_cur_drv(fdctrl);
1434 65cef780 blueswir1
1435 65cef780 blueswir1
    /* Drives position */
1436 65cef780 blueswir1
    fdctrl->fifo[0] = drv0(fdctrl)->track;
1437 65cef780 blueswir1
    fdctrl->fifo[1] = drv1(fdctrl)->track;
1438 78ae820c blueswir1
#if MAX_FD == 4
1439 78ae820c blueswir1
    fdctrl->fifo[2] = drv2(fdctrl)->track;
1440 78ae820c blueswir1
    fdctrl->fifo[3] = drv3(fdctrl)->track;
1441 78ae820c blueswir1
#else
1442 65cef780 blueswir1
    fdctrl->fifo[2] = 0;
1443 65cef780 blueswir1
    fdctrl->fifo[3] = 0;
1444 78ae820c blueswir1
#endif
1445 65cef780 blueswir1
    /* timers */
1446 65cef780 blueswir1
    fdctrl->fifo[4] = fdctrl->timer0;
1447 368df94d blueswir1
    fdctrl->fifo[5] = (fdctrl->timer1 << 1) | (fdctrl->dor & FD_DOR_DMAEN ? 1 : 0);
1448 65cef780 blueswir1
    fdctrl->fifo[6] = cur_drv->last_sect;
1449 65cef780 blueswir1
    fdctrl->fifo[7] = (fdctrl->lock << 7) |
1450 65cef780 blueswir1
        (cur_drv->perpendicular << 2);
1451 65cef780 blueswir1
    fdctrl->fifo[8] = fdctrl->config;
1452 65cef780 blueswir1
    fdctrl->fifo[9] = fdctrl->precomp_trk;
1453 65cef780 blueswir1
    fdctrl_set_fifo(fdctrl, 10, 0);
1454 65cef780 blueswir1
}
1455 65cef780 blueswir1
1456 5c02c033 Blue Swirl
static void fdctrl_handle_version(FDCtrl *fdctrl, int direction)
1457 65cef780 blueswir1
{
1458 65cef780 blueswir1
    /* Controller's version */
1459 65cef780 blueswir1
    fdctrl->fifo[0] = fdctrl->version;
1460 65cef780 blueswir1
    fdctrl_set_fifo(fdctrl, 1, 1);
1461 65cef780 blueswir1
}
1462 65cef780 blueswir1
1463 5c02c033 Blue Swirl
static void fdctrl_handle_partid(FDCtrl *fdctrl, int direction)
1464 65cef780 blueswir1
{
1465 65cef780 blueswir1
    fdctrl->fifo[0] = 0x41; /* Stepping 1 */
1466 65cef780 blueswir1
    fdctrl_set_fifo(fdctrl, 1, 0);
1467 65cef780 blueswir1
}
1468 65cef780 blueswir1
1469 5c02c033 Blue Swirl
static void fdctrl_handle_restore(FDCtrl *fdctrl, int direction)
1470 65cef780 blueswir1
{
1471 5c02c033 Blue Swirl
    FDrive *cur_drv = get_cur_drv(fdctrl);
1472 65cef780 blueswir1
1473 65cef780 blueswir1
    /* Drives position */
1474 65cef780 blueswir1
    drv0(fdctrl)->track = fdctrl->fifo[3];
1475 65cef780 blueswir1
    drv1(fdctrl)->track = fdctrl->fifo[4];
1476 78ae820c blueswir1
#if MAX_FD == 4
1477 78ae820c blueswir1
    drv2(fdctrl)->track = fdctrl->fifo[5];
1478 78ae820c blueswir1
    drv3(fdctrl)->track = fdctrl->fifo[6];
1479 78ae820c blueswir1
#endif
1480 65cef780 blueswir1
    /* timers */
1481 65cef780 blueswir1
    fdctrl->timer0 = fdctrl->fifo[7];
1482 65cef780 blueswir1
    fdctrl->timer1 = fdctrl->fifo[8];
1483 65cef780 blueswir1
    cur_drv->last_sect = fdctrl->fifo[9];
1484 65cef780 blueswir1
    fdctrl->lock = fdctrl->fifo[10] >> 7;
1485 65cef780 blueswir1
    cur_drv->perpendicular = (fdctrl->fifo[10] >> 2) & 0xF;
1486 65cef780 blueswir1
    fdctrl->config = fdctrl->fifo[11];
1487 65cef780 blueswir1
    fdctrl->precomp_trk = fdctrl->fifo[12];
1488 65cef780 blueswir1
    fdctrl->pwrd = fdctrl->fifo[13];
1489 65cef780 blueswir1
    fdctrl_reset_fifo(fdctrl);
1490 65cef780 blueswir1
}
1491 65cef780 blueswir1
1492 5c02c033 Blue Swirl
static void fdctrl_handle_save(FDCtrl *fdctrl, int direction)
1493 65cef780 blueswir1
{
1494 5c02c033 Blue Swirl
    FDrive *cur_drv = get_cur_drv(fdctrl);
1495 65cef780 blueswir1
1496 65cef780 blueswir1
    fdctrl->fifo[0] = 0;
1497 65cef780 blueswir1
    fdctrl->fifo[1] = 0;
1498 65cef780 blueswir1
    /* Drives position */
1499 65cef780 blueswir1
    fdctrl->fifo[2] = drv0(fdctrl)->track;
1500 65cef780 blueswir1
    fdctrl->fifo[3] = drv1(fdctrl)->track;
1501 78ae820c blueswir1
#if MAX_FD == 4
1502 78ae820c blueswir1
    fdctrl->fifo[4] = drv2(fdctrl)->track;
1503 78ae820c blueswir1
    fdctrl->fifo[5] = drv3(fdctrl)->track;
1504 78ae820c blueswir1
#else
1505 65cef780 blueswir1
    fdctrl->fifo[4] = 0;
1506 65cef780 blueswir1
    fdctrl->fifo[5] = 0;
1507 78ae820c blueswir1
#endif
1508 65cef780 blueswir1
    /* timers */
1509 65cef780 blueswir1
    fdctrl->fifo[6] = fdctrl->timer0;
1510 65cef780 blueswir1
    fdctrl->fifo[7] = fdctrl->timer1;
1511 65cef780 blueswir1
    fdctrl->fifo[8] = cur_drv->last_sect;
1512 65cef780 blueswir1
    fdctrl->fifo[9] = (fdctrl->lock << 7) |
1513 65cef780 blueswir1
        (cur_drv->perpendicular << 2);
1514 65cef780 blueswir1
    fdctrl->fifo[10] = fdctrl->config;
1515 65cef780 blueswir1
    fdctrl->fifo[11] = fdctrl->precomp_trk;
1516 65cef780 blueswir1
    fdctrl->fifo[12] = fdctrl->pwrd;
1517 65cef780 blueswir1
    fdctrl->fifo[13] = 0;
1518 65cef780 blueswir1
    fdctrl->fifo[14] = 0;
1519 65cef780 blueswir1
    fdctrl_set_fifo(fdctrl, 15, 1);
1520 65cef780 blueswir1
}
1521 65cef780 blueswir1
1522 5c02c033 Blue Swirl
static void fdctrl_handle_readid(FDCtrl *fdctrl, int direction)
1523 65cef780 blueswir1
{
1524 5c02c033 Blue Swirl
    FDrive *cur_drv = get_cur_drv(fdctrl);
1525 65cef780 blueswir1
1526 65cef780 blueswir1
    /* XXX: should set main status register to busy */
1527 65cef780 blueswir1
    cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
1528 65cef780 blueswir1
    qemu_mod_timer(fdctrl->result_timer,
1529 6ee093c9 Juan Quintela
                   qemu_get_clock(vm_clock) + (get_ticks_per_sec() / 50));
1530 65cef780 blueswir1
}
1531 65cef780 blueswir1
1532 5c02c033 Blue Swirl
static void fdctrl_handle_format_track(FDCtrl *fdctrl, int direction)
1533 65cef780 blueswir1
{
1534 5c02c033 Blue Swirl
    FDrive *cur_drv;
1535 65cef780 blueswir1
1536 cefec4f5 blueswir1
    SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1537 65cef780 blueswir1
    cur_drv = get_cur_drv(fdctrl);
1538 65cef780 blueswir1
    fdctrl->data_state |= FD_STATE_FORMAT;
1539 65cef780 blueswir1
    if (fdctrl->fifo[0] & 0x80)
1540 65cef780 blueswir1
        fdctrl->data_state |= FD_STATE_MULTI;
1541 65cef780 blueswir1
    else
1542 65cef780 blueswir1
        fdctrl->data_state &= ~FD_STATE_MULTI;
1543 65cef780 blueswir1
    fdctrl->data_state &= ~FD_STATE_SEEK;
1544 65cef780 blueswir1
    cur_drv->bps =
1545 65cef780 blueswir1
        fdctrl->fifo[2] > 7 ? 16384 : 128 << fdctrl->fifo[2];
1546 65cef780 blueswir1
#if 0
1547 65cef780 blueswir1
    cur_drv->last_sect =
1548 65cef780 blueswir1
        cur_drv->flags & FDISK_DBL_SIDES ? fdctrl->fifo[3] :
1549 65cef780 blueswir1
        fdctrl->fifo[3] / 2;
1550 65cef780 blueswir1
#else
1551 65cef780 blueswir1
    cur_drv->last_sect = fdctrl->fifo[3];
1552 65cef780 blueswir1
#endif
1553 65cef780 blueswir1
    /* TODO: implement format using DMA expected by the Bochs BIOS
1554 65cef780 blueswir1
     * and Linux fdformat (read 3 bytes per sector via DMA and fill
1555 65cef780 blueswir1
     * the sector with the specified fill byte
1556 65cef780 blueswir1
     */
1557 65cef780 blueswir1
    fdctrl->data_state &= ~FD_STATE_FORMAT;
1558 65cef780 blueswir1
    fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1559 65cef780 blueswir1
}
1560 65cef780 blueswir1
1561 5c02c033 Blue Swirl
static void fdctrl_handle_specify(FDCtrl *fdctrl, int direction)
1562 65cef780 blueswir1
{
1563 65cef780 blueswir1
    fdctrl->timer0 = (fdctrl->fifo[1] >> 4) & 0xF;
1564 65cef780 blueswir1
    fdctrl->timer1 = fdctrl->fifo[2] >> 1;
1565 368df94d blueswir1
    if (fdctrl->fifo[2] & 1)
1566 368df94d blueswir1
        fdctrl->dor &= ~FD_DOR_DMAEN;
1567 368df94d blueswir1
    else
1568 368df94d blueswir1
        fdctrl->dor |= FD_DOR_DMAEN;
1569 65cef780 blueswir1
    /* No result back */
1570 65cef780 blueswir1
    fdctrl_reset_fifo(fdctrl);
1571 65cef780 blueswir1
}
1572 65cef780 blueswir1
1573 5c02c033 Blue Swirl
static void fdctrl_handle_sense_drive_status(FDCtrl *fdctrl, int direction)
1574 65cef780 blueswir1
{
1575 5c02c033 Blue Swirl
    FDrive *cur_drv;
1576 65cef780 blueswir1
1577 cefec4f5 blueswir1
    SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1578 65cef780 blueswir1
    cur_drv = get_cur_drv(fdctrl);
1579 65cef780 blueswir1
    cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
1580 65cef780 blueswir1
    /* 1 Byte status back */
1581 65cef780 blueswir1
    fdctrl->fifo[0] = (cur_drv->ro << 6) |
1582 65cef780 blueswir1
        (cur_drv->track == 0 ? 0x10 : 0x00) |
1583 65cef780 blueswir1
        (cur_drv->head << 2) |
1584 cefec4f5 blueswir1
        GET_CUR_DRV(fdctrl) |
1585 65cef780 blueswir1
        0x28;
1586 65cef780 blueswir1
    fdctrl_set_fifo(fdctrl, 1, 0);
1587 65cef780 blueswir1
}
1588 65cef780 blueswir1
1589 5c02c033 Blue Swirl
static void fdctrl_handle_recalibrate(FDCtrl *fdctrl, int direction)
1590 65cef780 blueswir1
{
1591 5c02c033 Blue Swirl
    FDrive *cur_drv;
1592 65cef780 blueswir1
1593 cefec4f5 blueswir1
    SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1594 65cef780 blueswir1
    cur_drv = get_cur_drv(fdctrl);
1595 65cef780 blueswir1
    fd_recalibrate(cur_drv);
1596 65cef780 blueswir1
    fdctrl_reset_fifo(fdctrl);
1597 65cef780 blueswir1
    /* Raise Interrupt */
1598 65cef780 blueswir1
    fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1599 65cef780 blueswir1
}
1600 65cef780 blueswir1
1601 5c02c033 Blue Swirl
static void fdctrl_handle_sense_interrupt_status(FDCtrl *fdctrl, int direction)
1602 65cef780 blueswir1
{
1603 5c02c033 Blue Swirl
    FDrive *cur_drv = get_cur_drv(fdctrl);
1604 65cef780 blueswir1
1605 f2d81b33 blueswir1
    if(fdctrl->reset_sensei > 0) {
1606 f2d81b33 blueswir1
        fdctrl->fifo[0] =
1607 f2d81b33 blueswir1
            FD_SR0_RDYCHG + FD_RESET_SENSEI_COUNT - fdctrl->reset_sensei;
1608 f2d81b33 blueswir1
        fdctrl->reset_sensei--;
1609 f2d81b33 blueswir1
    } else {
1610 f2d81b33 blueswir1
        /* XXX: status0 handling is broken for read/write
1611 f2d81b33 blueswir1
           commands, so we do this hack. It should be suppressed
1612 f2d81b33 blueswir1
           ASAP */
1613 f2d81b33 blueswir1
        fdctrl->fifo[0] =
1614 f2d81b33 blueswir1
            FD_SR0_SEEK | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1615 f2d81b33 blueswir1
    }
1616 f2d81b33 blueswir1
1617 65cef780 blueswir1
    fdctrl->fifo[1] = cur_drv->track;
1618 65cef780 blueswir1
    fdctrl_set_fifo(fdctrl, 2, 0);
1619 65cef780 blueswir1
    fdctrl_reset_irq(fdctrl);
1620 77370520 blueswir1
    fdctrl->status0 = FD_SR0_RDYCHG;
1621 65cef780 blueswir1
}
1622 65cef780 blueswir1
1623 5c02c033 Blue Swirl
static void fdctrl_handle_seek(FDCtrl *fdctrl, int direction)
1624 65cef780 blueswir1
{
1625 5c02c033 Blue Swirl
    FDrive *cur_drv;
1626 65cef780 blueswir1
1627 cefec4f5 blueswir1
    SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1628 65cef780 blueswir1
    cur_drv = get_cur_drv(fdctrl);
1629 65cef780 blueswir1
    fdctrl_reset_fifo(fdctrl);
1630 65cef780 blueswir1
    if (fdctrl->fifo[2] > cur_drv->max_track) {
1631 65cef780 blueswir1
        fdctrl_raise_irq(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK);
1632 65cef780 blueswir1
    } else {
1633 65cef780 blueswir1
        cur_drv->track = fdctrl->fifo[2];
1634 65cef780 blueswir1
        /* Raise Interrupt */
1635 65cef780 blueswir1
        fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1636 65cef780 blueswir1
    }
1637 65cef780 blueswir1
}
1638 65cef780 blueswir1
1639 5c02c033 Blue Swirl
static void fdctrl_handle_perpendicular_mode(FDCtrl *fdctrl, int direction)
1640 65cef780 blueswir1
{
1641 5c02c033 Blue Swirl
    FDrive *cur_drv = get_cur_drv(fdctrl);
1642 65cef780 blueswir1
1643 65cef780 blueswir1
    if (fdctrl->fifo[1] & 0x80)
1644 65cef780 blueswir1
        cur_drv->perpendicular = fdctrl->fifo[1] & 0x7;
1645 65cef780 blueswir1
    /* No result back */
1646 1c346df2 blueswir1
    fdctrl_reset_fifo(fdctrl);
1647 65cef780 blueswir1
}
1648 65cef780 blueswir1
1649 5c02c033 Blue Swirl
static void fdctrl_handle_configure(FDCtrl *fdctrl, int direction)
1650 65cef780 blueswir1
{
1651 65cef780 blueswir1
    fdctrl->config = fdctrl->fifo[2];
1652 65cef780 blueswir1
    fdctrl->precomp_trk =  fdctrl->fifo[3];
1653 65cef780 blueswir1
    /* No result back */
1654 65cef780 blueswir1
    fdctrl_reset_fifo(fdctrl);
1655 65cef780 blueswir1
}
1656 65cef780 blueswir1
1657 5c02c033 Blue Swirl
static void fdctrl_handle_powerdown_mode(FDCtrl *fdctrl, int direction)
1658 65cef780 blueswir1
{
1659 65cef780 blueswir1
    fdctrl->pwrd = fdctrl->fifo[1];
1660 65cef780 blueswir1
    fdctrl->fifo[0] = fdctrl->fifo[1];
1661 65cef780 blueswir1
    fdctrl_set_fifo(fdctrl, 1, 1);
1662 65cef780 blueswir1
}
1663 65cef780 blueswir1
1664 5c02c033 Blue Swirl
static void fdctrl_handle_option(FDCtrl *fdctrl, int direction)
1665 65cef780 blueswir1
{
1666 65cef780 blueswir1
    /* No result back */
1667 65cef780 blueswir1
    fdctrl_reset_fifo(fdctrl);
1668 65cef780 blueswir1
}
1669 65cef780 blueswir1
1670 5c02c033 Blue Swirl
static void fdctrl_handle_drive_specification_command(FDCtrl *fdctrl, int direction)
1671 65cef780 blueswir1
{
1672 5c02c033 Blue Swirl
    FDrive *cur_drv = get_cur_drv(fdctrl);
1673 65cef780 blueswir1
1674 65cef780 blueswir1
    if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x80) {
1675 65cef780 blueswir1
        /* Command parameters done */
1676 65cef780 blueswir1
        if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x40) {
1677 65cef780 blueswir1
            fdctrl->fifo[0] = fdctrl->fifo[1];
1678 65cef780 blueswir1
            fdctrl->fifo[2] = 0;
1679 65cef780 blueswir1
            fdctrl->fifo[3] = 0;
1680 65cef780 blueswir1
            fdctrl_set_fifo(fdctrl, 4, 1);
1681 65cef780 blueswir1
        } else {
1682 65cef780 blueswir1
            fdctrl_reset_fifo(fdctrl);
1683 65cef780 blueswir1
        }
1684 65cef780 blueswir1
    } else if (fdctrl->data_len > 7) {
1685 65cef780 blueswir1
        /* ERROR */
1686 65cef780 blueswir1
        fdctrl->fifo[0] = 0x80 |
1687 cefec4f5 blueswir1
            (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1688 65cef780 blueswir1
        fdctrl_set_fifo(fdctrl, 1, 1);
1689 65cef780 blueswir1
    }
1690 65cef780 blueswir1
}
1691 65cef780 blueswir1
1692 5c02c033 Blue Swirl
static void fdctrl_handle_relative_seek_out(FDCtrl *fdctrl, int direction)
1693 65cef780 blueswir1
{
1694 5c02c033 Blue Swirl
    FDrive *cur_drv;
1695 65cef780 blueswir1
1696 cefec4f5 blueswir1
    SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1697 65cef780 blueswir1
    cur_drv = get_cur_drv(fdctrl);
1698 65cef780 blueswir1
    if (fdctrl->fifo[2] + cur_drv->track >= cur_drv->max_track) {
1699 65cef780 blueswir1
        cur_drv->track = cur_drv->max_track - 1;
1700 65cef780 blueswir1
    } else {
1701 65cef780 blueswir1
        cur_drv->track += fdctrl->fifo[2];
1702 65cef780 blueswir1
    }
1703 65cef780 blueswir1
    fdctrl_reset_fifo(fdctrl);
1704 77370520 blueswir1
    /* Raise Interrupt */
1705 65cef780 blueswir1
    fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1706 65cef780 blueswir1
}
1707 65cef780 blueswir1
1708 5c02c033 Blue Swirl
static void fdctrl_handle_relative_seek_in(FDCtrl *fdctrl, int direction)
1709 65cef780 blueswir1
{
1710 5c02c033 Blue Swirl
    FDrive *cur_drv;
1711 65cef780 blueswir1
1712 cefec4f5 blueswir1
    SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1713 65cef780 blueswir1
    cur_drv = get_cur_drv(fdctrl);
1714 65cef780 blueswir1
    if (fdctrl->fifo[2] > cur_drv->track) {
1715 65cef780 blueswir1
        cur_drv->track = 0;
1716 65cef780 blueswir1
    } else {
1717 65cef780 blueswir1
        cur_drv->track -= fdctrl->fifo[2];
1718 65cef780 blueswir1
    }
1719 65cef780 blueswir1
    fdctrl_reset_fifo(fdctrl);
1720 65cef780 blueswir1
    /* Raise Interrupt */
1721 65cef780 blueswir1
    fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1722 65cef780 blueswir1
}
1723 65cef780 blueswir1
1724 678803ab blueswir1
static const struct {
1725 678803ab blueswir1
    uint8_t value;
1726 678803ab blueswir1
    uint8_t mask;
1727 678803ab blueswir1
    const char* name;
1728 678803ab blueswir1
    int parameters;
1729 5c02c033 Blue Swirl
    void (*handler)(FDCtrl *fdctrl, int direction);
1730 678803ab blueswir1
    int direction;
1731 678803ab blueswir1
} handlers[] = {
1732 678803ab blueswir1
    { FD_CMD_READ, 0x1f, "READ", 8, fdctrl_start_transfer, FD_DIR_READ },
1733 678803ab blueswir1
    { FD_CMD_WRITE, 0x3f, "WRITE", 8, fdctrl_start_transfer, FD_DIR_WRITE },
1734 678803ab blueswir1
    { FD_CMD_SEEK, 0xff, "SEEK", 2, fdctrl_handle_seek },
1735 678803ab blueswir1
    { FD_CMD_SENSE_INTERRUPT_STATUS, 0xff, "SENSE INTERRUPT STATUS", 0, fdctrl_handle_sense_interrupt_status },
1736 678803ab blueswir1
    { FD_CMD_RECALIBRATE, 0xff, "RECALIBRATE", 1, fdctrl_handle_recalibrate },
1737 678803ab blueswir1
    { FD_CMD_FORMAT_TRACK, 0xbf, "FORMAT TRACK", 5, fdctrl_handle_format_track },
1738 678803ab blueswir1
    { FD_CMD_READ_TRACK, 0xbf, "READ TRACK", 8, fdctrl_start_transfer, FD_DIR_READ },
1739 678803ab blueswir1
    { FD_CMD_RESTORE, 0xff, "RESTORE", 17, fdctrl_handle_restore }, /* part of READ DELETED DATA */
1740 678803ab blueswir1
    { FD_CMD_SAVE, 0xff, "SAVE", 0, fdctrl_handle_save }, /* part of READ DELETED DATA */
1741 678803ab blueswir1
    { FD_CMD_READ_DELETED, 0x1f, "READ DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_READ },
1742 678803ab blueswir1
    { FD_CMD_SCAN_EQUAL, 0x1f, "SCAN EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANE },
1743 678803ab blueswir1
    { FD_CMD_VERIFY, 0x1f, "VERIFY", 8, fdctrl_unimplemented },
1744 678803ab blueswir1
    { FD_CMD_SCAN_LOW_OR_EQUAL, 0x1f, "SCAN LOW OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANL },
1745 678803ab blueswir1
    { FD_CMD_SCAN_HIGH_OR_EQUAL, 0x1f, "SCAN HIGH OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANH },
1746 678803ab blueswir1
    { FD_CMD_WRITE_DELETED, 0x3f, "WRITE DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_WRITE },
1747 678803ab blueswir1
    { FD_CMD_READ_ID, 0xbf, "READ ID", 1, fdctrl_handle_readid },
1748 678803ab blueswir1
    { FD_CMD_SPECIFY, 0xff, "SPECIFY", 2, fdctrl_handle_specify },
1749 678803ab blueswir1
    { FD_CMD_SENSE_DRIVE_STATUS, 0xff, "SENSE DRIVE STATUS", 1, fdctrl_handle_sense_drive_status },
1750 678803ab blueswir1
    { FD_CMD_PERPENDICULAR_MODE, 0xff, "PERPENDICULAR MODE", 1, fdctrl_handle_perpendicular_mode },
1751 678803ab blueswir1
    { FD_CMD_CONFIGURE, 0xff, "CONFIGURE", 3, fdctrl_handle_configure },
1752 678803ab blueswir1
    { FD_CMD_POWERDOWN_MODE, 0xff, "POWERDOWN MODE", 2, fdctrl_handle_powerdown_mode },
1753 678803ab blueswir1
    { FD_CMD_OPTION, 0xff, "OPTION", 1, fdctrl_handle_option },
1754 678803ab blueswir1
    { FD_CMD_DRIVE_SPECIFICATION_COMMAND, 0xff, "DRIVE SPECIFICATION COMMAND", 5, fdctrl_handle_drive_specification_command },
1755 678803ab blueswir1
    { FD_CMD_RELATIVE_SEEK_OUT, 0xff, "RELATIVE SEEK OUT", 2, fdctrl_handle_relative_seek_out },
1756 678803ab blueswir1
    { FD_CMD_FORMAT_AND_WRITE, 0xff, "FORMAT AND WRITE", 10, fdctrl_unimplemented },
1757 678803ab blueswir1
    { FD_CMD_RELATIVE_SEEK_IN, 0xff, "RELATIVE SEEK IN", 2, fdctrl_handle_relative_seek_in },
1758 678803ab blueswir1
    { FD_CMD_LOCK, 0x7f, "LOCK", 0, fdctrl_handle_lock },
1759 678803ab blueswir1
    { FD_CMD_DUMPREG, 0xff, "DUMPREG", 0, fdctrl_handle_dumpreg },
1760 678803ab blueswir1
    { FD_CMD_VERSION, 0xff, "VERSION", 0, fdctrl_handle_version },
1761 678803ab blueswir1
    { FD_CMD_PART_ID, 0xff, "PART ID", 0, fdctrl_handle_partid },
1762 678803ab blueswir1
    { FD_CMD_WRITE, 0x1f, "WRITE (BeOS)", 8, fdctrl_start_transfer, FD_DIR_WRITE }, /* not in specification ; BeOS 4.5 bug */
1763 678803ab blueswir1
    { 0, 0, "unknown", 0, fdctrl_unimplemented }, /* default handler */
1764 678803ab blueswir1
};
1765 678803ab blueswir1
/* Associate command to an index in the 'handlers' array */
1766 678803ab blueswir1
static uint8_t command_to_handler[256];
1767 678803ab blueswir1
1768 5c02c033 Blue Swirl
static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value)
1769 baca51fa bellard
{
1770 5c02c033 Blue Swirl
    FDrive *cur_drv;
1771 65cef780 blueswir1
    int pos;
1772 baca51fa bellard
1773 8977f3c1 bellard
    /* Reset mode */
1774 1c346df2 blueswir1
    if (!(fdctrl->dor & FD_DOR_nRESET)) {
1775 4b19ec0c bellard
        FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
1776 8977f3c1 bellard
        return;
1777 8977f3c1 bellard
    }
1778 b9b3d225 blueswir1
    if (!(fdctrl->msr & FD_MSR_RQM) || (fdctrl->msr & FD_MSR_DIO)) {
1779 b9b3d225 blueswir1
        FLOPPY_ERROR("controller not ready for writing\n");
1780 8977f3c1 bellard
        return;
1781 8977f3c1 bellard
    }
1782 b9b3d225 blueswir1
    fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1783 8977f3c1 bellard
    /* Is it write command time ? */
1784 368df94d blueswir1
    if (fdctrl->msr & FD_MSR_NONDMA) {
1785 8977f3c1 bellard
        /* FIFO data write */
1786 b3bc1540 blueswir1
        pos = fdctrl->data_pos++;
1787 b3bc1540 blueswir1
        pos %= FD_SECTOR_LEN;
1788 b3bc1540 blueswir1
        fdctrl->fifo[pos] = value;
1789 b3bc1540 blueswir1
        if (pos == FD_SECTOR_LEN - 1 ||
1790 baca51fa bellard
            fdctrl->data_pos == fdctrl->data_len) {
1791 77370520 blueswir1
            cur_drv = get_cur_drv(fdctrl);
1792 77370520 blueswir1
            if (bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1793 77370520 blueswir1
                FLOPPY_ERROR("writing sector %d\n", fd_sector(cur_drv));
1794 77370520 blueswir1
                return;
1795 77370520 blueswir1
            }
1796 746d6de7 blueswir1
            if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1797 746d6de7 blueswir1
                FLOPPY_DPRINTF("error seeking to next sector %d\n",
1798 746d6de7 blueswir1
                               fd_sector(cur_drv));
1799 746d6de7 blueswir1
                return;
1800 746d6de7 blueswir1
            }
1801 8977f3c1 bellard
        }
1802 890fa6be bellard
        /* Switch from transfer mode to status mode
1803 8977f3c1 bellard
         * then from status mode to command mode
1804 8977f3c1 bellard
         */
1805 b9b3d225 blueswir1
        if (fdctrl->data_pos == fdctrl->data_len)
1806 9fea808a blueswir1
            fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1807 8977f3c1 bellard
        return;
1808 8977f3c1 bellard
    }
1809 baca51fa bellard
    if (fdctrl->data_pos == 0) {
1810 8977f3c1 bellard
        /* Command */
1811 678803ab blueswir1
        pos = command_to_handler[value & 0xff];
1812 678803ab blueswir1
        FLOPPY_DPRINTF("%s command\n", handlers[pos].name);
1813 678803ab blueswir1
        fdctrl->data_len = handlers[pos].parameters + 1;
1814 8977f3c1 bellard
    }
1815 678803ab blueswir1
1816 baca51fa bellard
    FLOPPY_DPRINTF("%s: %02x\n", __func__, value);
1817 77370520 blueswir1
    fdctrl->fifo[fdctrl->data_pos++] = value;
1818 77370520 blueswir1
    if (fdctrl->data_pos == fdctrl->data_len) {
1819 8977f3c1 bellard
        /* We now have all parameters
1820 8977f3c1 bellard
         * and will be able to treat the command
1821 8977f3c1 bellard
         */
1822 4f431960 j_mayer
        if (fdctrl->data_state & FD_STATE_FORMAT) {
1823 4f431960 j_mayer
            fdctrl_format_sector(fdctrl);
1824 8977f3c1 bellard
            return;
1825 8977f3c1 bellard
        }
1826 65cef780 blueswir1
1827 678803ab blueswir1
        pos = command_to_handler[fdctrl->fifo[0] & 0xff];
1828 678803ab blueswir1
        FLOPPY_DPRINTF("treat %s command\n", handlers[pos].name);
1829 678803ab blueswir1
        (*handlers[pos].handler)(fdctrl, handlers[pos].direction);
1830 8977f3c1 bellard
    }
1831 8977f3c1 bellard
}
1832 ed5fd2cc bellard
1833 ed5fd2cc bellard
static void fdctrl_result_timer(void *opaque)
1834 ed5fd2cc bellard
{
1835 5c02c033 Blue Swirl
    FDCtrl *fdctrl = opaque;
1836 5c02c033 Blue Swirl
    FDrive *cur_drv = get_cur_drv(fdctrl);
1837 4f431960 j_mayer
1838 b7ffa3b1 ths
    /* Pretend we are spinning.
1839 b7ffa3b1 ths
     * This is needed for Coherent, which uses READ ID to check for
1840 b7ffa3b1 ths
     * sector interleaving.
1841 b7ffa3b1 ths
     */
1842 b7ffa3b1 ths
    if (cur_drv->last_sect != 0) {
1843 b7ffa3b1 ths
        cur_drv->sect = (cur_drv->sect % cur_drv->last_sect) + 1;
1844 b7ffa3b1 ths
    }
1845 ed5fd2cc bellard
    fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1846 ed5fd2cc bellard
}
1847 678803ab blueswir1
1848 678803ab blueswir1
/* Init functions */
1849 5c02c033 Blue Swirl
static void fdctrl_connect_drives(FDCtrl *fdctrl)
1850 678803ab blueswir1
{
1851 12a71a02 Blue Swirl
    unsigned int i;
1852 678803ab blueswir1
1853 678803ab blueswir1
    for (i = 0; i < MAX_FD; i++) {
1854 fd8014e1 Gerd Hoffmann
        fd_init(&fdctrl->drives[i]);
1855 678803ab blueswir1
        fd_revalidate(&fdctrl->drives[i]);
1856 678803ab blueswir1
    }
1857 678803ab blueswir1
}
1858 678803ab blueswir1
1859 5c02c033 Blue Swirl
FDCtrl *fdctrl_init_isa(DriveInfo **fds)
1860 678803ab blueswir1
{
1861 2091ba23 Gerd Hoffmann
    ISADevice *dev;
1862 678803ab blueswir1
1863 fd8014e1 Gerd Hoffmann
    dev = isa_create("isa-fdc");
1864 995bf0ca Gerd Hoffmann
    if (fds[0]) {
1865 995bf0ca Gerd Hoffmann
        qdev_prop_set_drive(&dev->qdev, "driveA", fds[0]);
1866 995bf0ca Gerd Hoffmann
    }
1867 995bf0ca Gerd Hoffmann
    if (fds[1]) {
1868 995bf0ca Gerd Hoffmann
        qdev_prop_set_drive(&dev->qdev, "driveB", fds[1]);
1869 995bf0ca Gerd Hoffmann
    }
1870 5c17ca25 Markus Armbruster
    if (qdev_init(&dev->qdev) < 0)
1871 fd8014e1 Gerd Hoffmann
        return NULL;
1872 5c02c033 Blue Swirl
    return &(DO_UPCAST(FDCtrlISABus, busdev, dev)->state);
1873 2091ba23 Gerd Hoffmann
}
1874 2091ba23 Gerd Hoffmann
1875 5c02c033 Blue Swirl
FDCtrl *fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
1876 5c02c033 Blue Swirl
                           target_phys_addr_t mmio_base, DriveInfo **fds)
1877 2091ba23 Gerd Hoffmann
{
1878 5c02c033 Blue Swirl
    FDCtrl *fdctrl;
1879 2091ba23 Gerd Hoffmann
    DeviceState *dev;
1880 5c02c033 Blue Swirl
    FDCtrlSysBus *sys;
1881 2091ba23 Gerd Hoffmann
1882 2091ba23 Gerd Hoffmann
    dev = qdev_create(NULL, "sysbus-fdc");
1883 5c02c033 Blue Swirl
    sys = DO_UPCAST(FDCtrlSysBus, busdev.qdev, dev);
1884 99244fa1 Gerd Hoffmann
    fdctrl = &sys->state;
1885 99244fa1 Gerd Hoffmann
    fdctrl->dma_chann = dma_chann; /* FIXME */
1886 995bf0ca Gerd Hoffmann
    if (fds[0]) {
1887 995bf0ca Gerd Hoffmann
        qdev_prop_set_drive(dev, "driveA", fds[0]);
1888 995bf0ca Gerd Hoffmann
    }
1889 995bf0ca Gerd Hoffmann
    if (fds[1]) {
1890 995bf0ca Gerd Hoffmann
        qdev_prop_set_drive(dev, "driveB", fds[1]);
1891 995bf0ca Gerd Hoffmann
    }
1892 e23a1b33 Markus Armbruster
    qdev_init_nofail(dev);
1893 2091ba23 Gerd Hoffmann
    sysbus_connect_irq(&sys->busdev, 0, irq);
1894 2091ba23 Gerd Hoffmann
    sysbus_mmio_map(&sys->busdev, 0, mmio_base);
1895 8baf73ad Gerd Hoffmann
1896 678803ab blueswir1
    return fdctrl;
1897 678803ab blueswir1
}
1898 678803ab blueswir1
1899 5c02c033 Blue Swirl
FDCtrl *sun4m_fdctrl_init(qemu_irq irq, target_phys_addr_t io_base,
1900 5c02c033 Blue Swirl
                          DriveInfo **fds, qemu_irq *fdc_tc)
1901 678803ab blueswir1
{
1902 f64ab228 Blue Swirl
    DeviceState *dev;
1903 5c02c033 Blue Swirl
    FDCtrlSysBus *sys;
1904 5c02c033 Blue Swirl
    FDCtrl *fdctrl;
1905 678803ab blueswir1
1906 12a71a02 Blue Swirl
    dev = qdev_create(NULL, "SUNW,fdtwo");
1907 995bf0ca Gerd Hoffmann
    if (fds[0]) {
1908 995bf0ca Gerd Hoffmann
        qdev_prop_set_drive(dev, "drive", fds[0]);
1909 995bf0ca Gerd Hoffmann
    }
1910 e23a1b33 Markus Armbruster
    qdev_init_nofail(dev);
1911 5c02c033 Blue Swirl
    sys = DO_UPCAST(FDCtrlSysBus, busdev.qdev, dev);
1912 8baf73ad Gerd Hoffmann
    fdctrl = &sys->state;
1913 8baf73ad Gerd Hoffmann
    sysbus_connect_irq(&sys->busdev, 0, irq);
1914 8baf73ad Gerd Hoffmann
    sysbus_mmio_map(&sys->busdev, 0, io_base);
1915 f64ab228 Blue Swirl
    *fdc_tc = qdev_get_gpio_in(dev, 0);
1916 f64ab228 Blue Swirl
1917 678803ab blueswir1
    return fdctrl;
1918 678803ab blueswir1
}
1919 f64ab228 Blue Swirl
1920 5c02c033 Blue Swirl
static int fdctrl_init_common(FDCtrl *fdctrl, target_phys_addr_t io_base)
1921 f64ab228 Blue Swirl
{
1922 12a71a02 Blue Swirl
    int i, j;
1923 12a71a02 Blue Swirl
    static int command_tables_inited = 0;
1924 f64ab228 Blue Swirl
1925 12a71a02 Blue Swirl
    /* Fill 'command_to_handler' lookup table */
1926 12a71a02 Blue Swirl
    if (!command_tables_inited) {
1927 12a71a02 Blue Swirl
        command_tables_inited = 1;
1928 12a71a02 Blue Swirl
        for (i = ARRAY_SIZE(handlers) - 1; i >= 0; i--) {
1929 12a71a02 Blue Swirl
            for (j = 0; j < sizeof(command_to_handler); j++) {
1930 12a71a02 Blue Swirl
                if ((j & handlers[i].mask) == handlers[i].value) {
1931 12a71a02 Blue Swirl
                    command_to_handler[j] = i;
1932 12a71a02 Blue Swirl
                }
1933 12a71a02 Blue Swirl
            }
1934 12a71a02 Blue Swirl
        }
1935 12a71a02 Blue Swirl
    }
1936 12a71a02 Blue Swirl
1937 12a71a02 Blue Swirl
    FLOPPY_DPRINTF("init controller\n");
1938 12a71a02 Blue Swirl
    fdctrl->fifo = qemu_memalign(512, FD_SECTOR_LEN);
1939 d7a6c270 Juan Quintela
    fdctrl->fifo_size = 512;
1940 12a71a02 Blue Swirl
    fdctrl->result_timer = qemu_new_timer(vm_clock,
1941 12a71a02 Blue Swirl
                                          fdctrl_result_timer, fdctrl);
1942 12a71a02 Blue Swirl
1943 12a71a02 Blue Swirl
    fdctrl->version = 0x90; /* Intel 82078 controller */
1944 12a71a02 Blue Swirl
    fdctrl->config = FD_CONFIG_EIS | FD_CONFIG_EFIFO; /* Implicit seek, polling & FIFO enabled */
1945 d7a6c270 Juan Quintela
    fdctrl->num_floppies = MAX_FD;
1946 12a71a02 Blue Swirl
1947 99244fa1 Gerd Hoffmann
    if (fdctrl->dma_chann != -1)
1948 99244fa1 Gerd Hoffmann
        DMA_register_channel(fdctrl->dma_chann, &fdctrl_transfer_handler, fdctrl);
1949 99244fa1 Gerd Hoffmann
    fdctrl_connect_drives(fdctrl);
1950 99244fa1 Gerd Hoffmann
1951 47f5ba72 Juan Quintela
    vmstate_register(io_base, &vmstate_fdc, fdctrl);
1952 81a322d4 Gerd Hoffmann
    return 0;
1953 f64ab228 Blue Swirl
}
1954 f64ab228 Blue Swirl
1955 81a322d4 Gerd Hoffmann
static int isabus_fdc_init1(ISADevice *dev)
1956 8baf73ad Gerd Hoffmann
{
1957 5c02c033 Blue Swirl
    FDCtrlISABus *isa = DO_UPCAST(FDCtrlISABus, busdev, dev);
1958 5c02c033 Blue Swirl
    FDCtrl *fdctrl = &isa->state;
1959 86c86157 Gerd Hoffmann
    int iobase = 0x3f0;
1960 2e15e23b Gerd Hoffmann
    int isairq = 6;
1961 99244fa1 Gerd Hoffmann
    int dma_chann = 2;
1962 2be37833 Blue Swirl
    int ret;
1963 8baf73ad Gerd Hoffmann
1964 86c86157 Gerd Hoffmann
    register_ioport_read(iobase + 0x01, 5, 1,
1965 8baf73ad Gerd Hoffmann
                         &fdctrl_read_port, fdctrl);
1966 86c86157 Gerd Hoffmann
    register_ioport_read(iobase + 0x07, 1, 1,
1967 8baf73ad Gerd Hoffmann
                         &fdctrl_read_port, fdctrl);
1968 86c86157 Gerd Hoffmann
    register_ioport_write(iobase + 0x01, 5, 1,
1969 8baf73ad Gerd Hoffmann
                          &fdctrl_write_port, fdctrl);
1970 86c86157 Gerd Hoffmann
    register_ioport_write(iobase + 0x07, 1, 1,
1971 8baf73ad Gerd Hoffmann
                          &fdctrl_write_port, fdctrl);
1972 2e15e23b Gerd Hoffmann
    isa_init_irq(&isa->busdev, &fdctrl->irq, isairq);
1973 99244fa1 Gerd Hoffmann
    fdctrl->dma_chann = dma_chann;
1974 8baf73ad Gerd Hoffmann
1975 47f5ba72 Juan Quintela
    ret = fdctrl_init_common(fdctrl, iobase);
1976 2be37833 Blue Swirl
1977 2be37833 Blue Swirl
    return ret;
1978 8baf73ad Gerd Hoffmann
}
1979 8baf73ad Gerd Hoffmann
1980 81a322d4 Gerd Hoffmann
static int sysbus_fdc_init1(SysBusDevice *dev)
1981 12a71a02 Blue Swirl
{
1982 5c02c033 Blue Swirl
    FDCtrlSysBus *sys = DO_UPCAST(FDCtrlSysBus, busdev, dev);
1983 5c02c033 Blue Swirl
    FDCtrl *fdctrl = &sys->state;
1984 12a71a02 Blue Swirl
    int io;
1985 2be37833 Blue Swirl
    int ret;
1986 12a71a02 Blue Swirl
1987 12a71a02 Blue Swirl
    io = cpu_register_io_memory(fdctrl_mem_read, fdctrl_mem_write, fdctrl);
1988 8baf73ad Gerd Hoffmann
    sysbus_init_mmio(dev, 0x08, io);
1989 8baf73ad Gerd Hoffmann
    sysbus_init_irq(dev, &fdctrl->irq);
1990 8baf73ad Gerd Hoffmann
    qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1);
1991 99244fa1 Gerd Hoffmann
    fdctrl->dma_chann = -1;
1992 8baf73ad Gerd Hoffmann
1993 47f5ba72 Juan Quintela
    ret = fdctrl_init_common(fdctrl, io);
1994 2be37833 Blue Swirl
1995 2be37833 Blue Swirl
    return ret;
1996 12a71a02 Blue Swirl
}
1997 12a71a02 Blue Swirl
1998 81a322d4 Gerd Hoffmann
static int sun4m_fdc_init1(SysBusDevice *dev)
1999 12a71a02 Blue Swirl
{
2000 5c02c033 Blue Swirl
    FDCtrl *fdctrl = &(FROM_SYSBUS(FDCtrlSysBus, dev)->state);
2001 12a71a02 Blue Swirl
    int io;
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    io = cpu_register_io_memory(fdctrl_mem_read_strict,
2004 12a71a02 Blue Swirl
                                fdctrl_mem_write_strict, fdctrl);
2005 8baf73ad Gerd Hoffmann
    sysbus_init_mmio(dev, 0x08, io);
2006 8baf73ad Gerd Hoffmann
    sysbus_init_irq(dev, &fdctrl->irq);
2007 8baf73ad Gerd Hoffmann
    qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1);
2008 8baf73ad Gerd Hoffmann
2009 8baf73ad Gerd Hoffmann
    fdctrl->sun4m = 1;
2010 47f5ba72 Juan Quintela
    return fdctrl_init_common(fdctrl, io);
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}
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2013 8baf73ad Gerd Hoffmann
static ISADeviceInfo isa_fdc_info = {
2014 8baf73ad Gerd Hoffmann
    .init = isabus_fdc_init1,
2015 8baf73ad Gerd Hoffmann
    .qdev.name  = "isa-fdc",
2016 5c02c033 Blue Swirl
    .qdev.size  = sizeof(FDCtrlISABus),
2017 39a51dfd Markus Armbruster
    .qdev.no_user = 1,
2018 2be37833 Blue Swirl
    .qdev.reset = fdctrl_external_reset_isa,
2019 fd8014e1 Gerd Hoffmann
    .qdev.props = (Property[]) {
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        DEFINE_PROP_DRIVE("driveA", FDCtrlISABus, state.drives[0].dinfo),
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        DEFINE_PROP_DRIVE("driveB", FDCtrlISABus, state.drives[1].dinfo),
2022 fd8014e1 Gerd Hoffmann
        DEFINE_PROP_END_OF_LIST(),
2023 fd8014e1 Gerd Hoffmann
    },
2024 8baf73ad Gerd Hoffmann
};
2025 8baf73ad Gerd Hoffmann
2026 8baf73ad Gerd Hoffmann
static SysBusDeviceInfo sysbus_fdc_info = {
2027 8baf73ad Gerd Hoffmann
    .init = sysbus_fdc_init1,
2028 8baf73ad Gerd Hoffmann
    .qdev.name  = "sysbus-fdc",
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    .qdev.size  = sizeof(FDCtrlSysBus),
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    .qdev.reset = fdctrl_external_reset_sysbus,
2031 fd8014e1 Gerd Hoffmann
    .qdev.props = (Property[]) {
2032 5c02c033 Blue Swirl
        DEFINE_PROP_DRIVE("driveA", FDCtrlSysBus, state.drives[0].dinfo),
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        DEFINE_PROP_DRIVE("driveB", FDCtrlSysBus, state.drives[1].dinfo),
2034 fd8014e1 Gerd Hoffmann
        DEFINE_PROP_END_OF_LIST(),
2035 fd8014e1 Gerd Hoffmann
    },
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};
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static SysBusDeviceInfo sun4m_fdc_info = {
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    .init = sun4m_fdc_init1,
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    .qdev.name  = "SUNW,fdtwo",
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    .qdev.size  = sizeof(FDCtrlSysBus),
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    .qdev.reset = fdctrl_external_reset_sysbus,
2043 fd8014e1 Gerd Hoffmann
    .qdev.props = (Property[]) {
2044 5c02c033 Blue Swirl
        DEFINE_PROP_DRIVE("drive", FDCtrlSysBus, state.drives[0].dinfo),
2045 fd8014e1 Gerd Hoffmann
        DEFINE_PROP_END_OF_LIST(),
2046 fd8014e1 Gerd Hoffmann
    },
2047 f64ab228 Blue Swirl
};
2048 f64ab228 Blue Swirl
2049 f64ab228 Blue Swirl
static void fdc_register_devices(void)
2050 f64ab228 Blue Swirl
{
2051 8baf73ad Gerd Hoffmann
    isa_qdev_register(&isa_fdc_info);
2052 8baf73ad Gerd Hoffmann
    sysbus_register_withprop(&sysbus_fdc_info);
2053 12a71a02 Blue Swirl
    sysbus_register_withprop(&sun4m_fdc_info);
2054 f64ab228 Blue Swirl
}
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2056 f64ab228 Blue Swirl
device_init(fdc_register_devices)