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1 | 79aceca5 | bellard | /*
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2 | 79aceca5 | bellard | * PPC emulation cpu definitions for qemu.
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3 | 79aceca5 | bellard | *
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4 | 79aceca5 | bellard | * Copyright (c) 2003 Jocelyn Mayer
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5 | 79aceca5 | bellard | *
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6 | 79aceca5 | bellard | * This library is free software; you can redistribute it and/or
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7 | 79aceca5 | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 79aceca5 | bellard | * License as published by the Free Software Foundation; either
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9 | 79aceca5 | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 79aceca5 | bellard | *
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11 | 79aceca5 | bellard | * This library is distributed in the hope that it will be useful,
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12 | 79aceca5 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 79aceca5 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 79aceca5 | bellard | * Lesser General Public License for more details.
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15 | 79aceca5 | bellard | *
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16 | 79aceca5 | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 79aceca5 | bellard | * License along with this library; if not, write to the Free Software
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18 | 79aceca5 | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | 79aceca5 | bellard | */
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20 | 79aceca5 | bellard | #if !defined (__CPU_PPC_H__)
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21 | 79aceca5 | bellard | #define __CPU_PPC_H__
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22 | 79aceca5 | bellard | |
23 | 79aceca5 | bellard | #include <endian.h> |
24 | 79aceca5 | bellard | #include <asm/byteorder.h> |
25 | 79aceca5 | bellard | |
26 | 79aceca5 | bellard | #include "cpu-defs.h" |
27 | 79aceca5 | bellard | |
28 | 9a64fbe4 | bellard | //#define USE_OPEN_FIRMWARE
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29 | 9a64fbe4 | bellard | |
30 | 79aceca5 | bellard | /*** Sign extend constants ***/
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31 | 79aceca5 | bellard | /* 8 to 32 bits */
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32 | 79aceca5 | bellard | static inline int32_t s_ext8 (uint8_t value) |
33 | 79aceca5 | bellard | { |
34 | 79aceca5 | bellard | int8_t *tmp = &value; |
35 | 79aceca5 | bellard | |
36 | 79aceca5 | bellard | return *tmp;
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37 | 79aceca5 | bellard | } |
38 | 79aceca5 | bellard | |
39 | 79aceca5 | bellard | /* 16 to 32 bits */
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40 | 79aceca5 | bellard | static inline int32_t s_ext16 (uint16_t value) |
41 | 79aceca5 | bellard | { |
42 | 79aceca5 | bellard | int16_t *tmp = &value; |
43 | 79aceca5 | bellard | |
44 | 79aceca5 | bellard | return *tmp;
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45 | 79aceca5 | bellard | } |
46 | 79aceca5 | bellard | |
47 | 79aceca5 | bellard | /* 24 to 32 bits */
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48 | 79aceca5 | bellard | static inline int32_t s_ext24 (uint32_t value) |
49 | 79aceca5 | bellard | { |
50 | 79aceca5 | bellard | uint16_t utmp = (value >> 8) & 0xFFFF; |
51 | 79aceca5 | bellard | int16_t *tmp = &utmp; |
52 | 79aceca5 | bellard | |
53 | 79aceca5 | bellard | return (*tmp << 8) | (value & 0xFF); |
54 | 79aceca5 | bellard | } |
55 | 79aceca5 | bellard | |
56 | 79aceca5 | bellard | #include "config.h" |
57 | 79aceca5 | bellard | #include <setjmp.h> |
58 | 79aceca5 | bellard | |
59 | 9a64fbe4 | bellard | /* Instruction types */
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60 | 9a64fbe4 | bellard | enum {
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61 | 9a64fbe4 | bellard | PPC_NONE = 0x0000,
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62 | 9a64fbe4 | bellard | PPC_INTEGER = 0x0001, /* CPU has integer operations instructions */ |
63 | 9a64fbe4 | bellard | PPC_FLOAT = 0x0002, /* CPU has floating point operations instructions */ |
64 | 9a64fbe4 | bellard | PPC_FLOW = 0x0004, /* CPU has flow control instructions */ |
65 | 9a64fbe4 | bellard | PPC_MEM = 0x0008, /* CPU has virtual memory instructions */ |
66 | 9a64fbe4 | bellard | PPC_RES = 0x0010, /* CPU has ld/st with reservation instructions */ |
67 | 9a64fbe4 | bellard | PPC_CACHE = 0x0020, /* CPU has cache control instructions */ |
68 | 9a64fbe4 | bellard | PPC_MISC = 0x0040, /* CPU has spr/msr access instructions */ |
69 | 9a64fbe4 | bellard | PPC_EXTERN = 0x0080, /* CPU has external control instructions */ |
70 | 9a64fbe4 | bellard | PPC_SEGMENT = 0x0100, /* CPU has memory segment instructions */ |
71 | 9a64fbe4 | bellard | PPC_CACHE_OPT= 0x0200,
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72 | 9a64fbe4 | bellard | PPC_FLOAT_OPT= 0x0400,
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73 | 9a64fbe4 | bellard | PPC_MEM_OPT = 0x0800,
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74 | 9a64fbe4 | bellard | }; |
75 | 79aceca5 | bellard | |
76 | 9a64fbe4 | bellard | #define PPC_COMMON (PPC_INTEGER | PPC_FLOAT | PPC_FLOW | PPC_MEM | \
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77 | 9a64fbe4 | bellard | PPC_RES | PPC_CACHE | PPC_MISC | PPC_SEGMENT) |
78 | 9a64fbe4 | bellard | /* PPC 740/745/750/755 (aka G3) has external access instructions */
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79 | 9a64fbe4 | bellard | #define PPC_750 (PPC_INTEGER | PPC_FLOAT | PPC_FLOW | PPC_MEM | \
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80 | 9a64fbe4 | bellard | PPC_RES | PPC_CACHE | PPC_MISC | PPC_EXTERN | PPC_SEGMENT) |
81 | 79aceca5 | bellard | |
82 | 79aceca5 | bellard | /* Supervisor mode registers */
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83 | 79aceca5 | bellard | /* Machine state register */
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84 | 79aceca5 | bellard | #define MSR_POW 18 |
85 | 79aceca5 | bellard | #define MSR_ILE 16 |
86 | 79aceca5 | bellard | #define MSR_EE 15 |
87 | 79aceca5 | bellard | #define MSR_PR 14 |
88 | 79aceca5 | bellard | #define MSR_FP 13 |
89 | 79aceca5 | bellard | #define MSR_ME 12 |
90 | 79aceca5 | bellard | #define MSR_FE0 11 |
91 | 79aceca5 | bellard | #define MSR_SE 10 |
92 | 79aceca5 | bellard | #define MSR_BE 9 |
93 | 79aceca5 | bellard | #define MSR_FE1 8 |
94 | 79aceca5 | bellard | #define MSR_IP 6 |
95 | 79aceca5 | bellard | #define MSR_IR 5 |
96 | 79aceca5 | bellard | #define MSR_DR 4 |
97 | 79aceca5 | bellard | #define MSR_RI 1 |
98 | 79aceca5 | bellard | #define MSR_LE 0 |
99 | 79aceca5 | bellard | #define msr_pow env->msr[MSR_POW]
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100 | 79aceca5 | bellard | #define msr_ile env->msr[MSR_ILE]
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101 | 79aceca5 | bellard | #define msr_ee env->msr[MSR_EE]
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102 | 79aceca5 | bellard | #define msr_pr env->msr[MSR_PR]
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103 | 79aceca5 | bellard | #define msr_fp env->msr[MSR_FP]
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104 | 79aceca5 | bellard | #define msr_me env->msr[MSR_ME]
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105 | 79aceca5 | bellard | #define msr_fe0 env->msr[MSR_FE0]
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106 | 79aceca5 | bellard | #define msr_se env->msr[MSR_SE]
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107 | 79aceca5 | bellard | #define msr_be env->msr[MSR_BE]
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108 | 79aceca5 | bellard | #define msr_fe1 env->msr[MSR_FE1]
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109 | 79aceca5 | bellard | #define msr_ip env->msr[MSR_IP]
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110 | 79aceca5 | bellard | #define msr_ir env->msr[MSR_IR]
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111 | 79aceca5 | bellard | #define msr_dr env->msr[MSR_DR]
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112 | 79aceca5 | bellard | #define msr_ri env->msr[MSR_RI]
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113 | 79aceca5 | bellard | #define msr_le env->msr[MSR_LE]
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114 | 79aceca5 | bellard | |
115 | 79aceca5 | bellard | /* Segment registers */
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116 | 79aceca5 | bellard | typedef struct CPUPPCState { |
117 | 79aceca5 | bellard | /* general purpose registers */
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118 | 79aceca5 | bellard | uint32_t gpr[32];
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119 | 79aceca5 | bellard | /* floating point registers */
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120 | fb0eaffc | bellard | double fpr[32]; |
121 | 79aceca5 | bellard | /* segment registers */
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122 | 9a64fbe4 | bellard | uint32_t sdr1; |
123 | 9a64fbe4 | bellard | uint32_t sr[16];
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124 | 79aceca5 | bellard | /* XER */
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125 | 9a64fbe4 | bellard | uint8_t xer[4];
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126 | 79aceca5 | bellard | /* Reservation address */
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127 | 79aceca5 | bellard | uint32_t reserve; |
128 | 79aceca5 | bellard | /* machine state register */
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129 | 79aceca5 | bellard | uint8_t msr[32];
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130 | 79aceca5 | bellard | /* condition register */
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131 | 79aceca5 | bellard | uint8_t crf[8];
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132 | 79aceca5 | bellard | /* floating point status and control register */
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133 | 9a64fbe4 | bellard | uint8_t fpscr[8];
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134 | 79aceca5 | bellard | uint32_t nip; |
135 | 9a64fbe4 | bellard | /* special purpose registers */
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136 | 9a64fbe4 | bellard | uint32_t lr; |
137 | 9a64fbe4 | bellard | uint32_t ctr; |
138 | 9a64fbe4 | bellard | /* Time base */
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139 | 9a64fbe4 | bellard | uint32_t tb[2];
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140 | 9a64fbe4 | bellard | /* decrementer */
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141 | 9a64fbe4 | bellard | uint32_t decr; |
142 | 9a64fbe4 | bellard | /* BATs */
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143 | 9a64fbe4 | bellard | uint32_t DBAT[2][8]; |
144 | 9a64fbe4 | bellard | uint32_t IBAT[2][8]; |
145 | 9a64fbe4 | bellard | /* all others */
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146 | 9a64fbe4 | bellard | uint32_t spr[1024];
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147 | 79aceca5 | bellard | /* qemu dedicated */
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148 | fb0eaffc | bellard | /* temporary float registers */
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149 | fb0eaffc | bellard | double ft0;
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150 | fb0eaffc | bellard | double ft1;
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151 | fb0eaffc | bellard | double ft2;
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152 | 79aceca5 | bellard | int interrupt_request;
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153 | 79aceca5 | bellard | jmp_buf jmp_env; |
154 | 79aceca5 | bellard | int exception_index;
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155 | 79aceca5 | bellard | int error_code;
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156 | ac9eb073 | bellard | int access_type; /* when a memory exception occurs, the access |
157 | ac9eb073 | bellard | type is stored here */
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158 | 9a64fbe4 | bellard | uint32_t exceptions; /* exception queue */
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159 | 9a64fbe4 | bellard | uint32_t errors[16];
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160 | 79aceca5 | bellard | int user_mode_only; /* user mode only simulation */ |
161 | 79aceca5 | bellard | struct TranslationBlock *current_tb; /* currently executing TB */ |
162 | 9a64fbe4 | bellard | /* soft mmu support */
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163 | 9a64fbe4 | bellard | /* 0 = kernel, 1 = user */
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164 | 9a64fbe4 | bellard | CPUTLBEntry tlb_read[2][CPU_TLB_SIZE];
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165 | 9a64fbe4 | bellard | CPUTLBEntry tlb_write[2][CPU_TLB_SIZE];
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166 | 79aceca5 | bellard | /* user data */
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167 | 79aceca5 | bellard | void *opaque;
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168 | 79aceca5 | bellard | } CPUPPCState; |
169 | 79aceca5 | bellard | |
170 | 79aceca5 | bellard | CPUPPCState *cpu_ppc_init(void);
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171 | 79aceca5 | bellard | int cpu_ppc_exec(CPUPPCState *s);
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172 | 79aceca5 | bellard | void cpu_ppc_close(CPUPPCState *s);
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173 | 79aceca5 | bellard | /* you can call this signal handler from your SIGBUS and SIGSEGV
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174 | 79aceca5 | bellard | signal handlers to inform the virtual CPU of exceptions. non zero
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175 | 79aceca5 | bellard | is returned if the signal was handled by the virtual CPU. */
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176 | 79aceca5 | bellard | struct siginfo;
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177 | 79aceca5 | bellard | int cpu_ppc_signal_handler(int host_signum, struct siginfo *info, |
178 | 79aceca5 | bellard | void *puc);
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179 | 79aceca5 | bellard | |
180 | 79aceca5 | bellard | void cpu_ppc_dump_state(CPUPPCState *env, FILE *f, int flags); |
181 | 9a64fbe4 | bellard | void cpu_loop_exit(void); |
182 | 9a64fbe4 | bellard | void dump_stack (CPUPPCState *env);
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183 | 9a64fbe4 | bellard | uint32_t _load_xer (void);
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184 | 9a64fbe4 | bellard | void _store_xer (uint32_t value);
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185 | 9a64fbe4 | bellard | uint32_t _load_msr (void);
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186 | 9a64fbe4 | bellard | void _store_msr (uint32_t value);
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187 | 9a64fbe4 | bellard | void do_interrupt (CPUPPCState *env);
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188 | 79aceca5 | bellard | |
189 | 79aceca5 | bellard | #define TARGET_PAGE_BITS 12 |
190 | 79aceca5 | bellard | #include "cpu-all.h" |
191 | 79aceca5 | bellard | |
192 | 79aceca5 | bellard | #define ugpr(n) (env->gpr[n])
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193 | 9a64fbe4 | bellard | #define fprd(n) (env->fpr[n])
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194 | 9a64fbe4 | bellard | #define fprs(n) ((float)env->fpr[n]) |
195 | 9a64fbe4 | bellard | #define fpru(n) ((uint32_t)env->fpr[n])
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196 | 9a64fbe4 | bellard | #define fpri(n) ((int32_t)env->fpr[n])
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197 | 79aceca5 | bellard | |
198 | 79aceca5 | bellard | #define SPR_ENCODE(sprn) \
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199 | 79aceca5 | bellard | (((sprn) >> 5) | (((sprn) & 0x1F) << 5)) |
200 | 79aceca5 | bellard | |
201 | 79aceca5 | bellard | /* User mode SPR */
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202 | 79aceca5 | bellard | #define spr(n) env->spr[n]
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203 | 79aceca5 | bellard | #define XER_SO 31 |
204 | 79aceca5 | bellard | #define XER_OV 30 |
205 | 79aceca5 | bellard | #define XER_CA 29 |
206 | 79aceca5 | bellard | #define XER_BC 0 |
207 | 9a64fbe4 | bellard | #define xer_so env->xer[3] |
208 | 9a64fbe4 | bellard | #define xer_ov env->xer[2] |
209 | 9a64fbe4 | bellard | #define xer_ca env->xer[1] |
210 | 9a64fbe4 | bellard | #define xer_bc env->xer[0] |
211 | 79aceca5 | bellard | |
212 | 9a64fbe4 | bellard | #define XER SPR_ENCODE(1) |
213 | 9a64fbe4 | bellard | #define LR SPR_ENCODE(8) |
214 | 9a64fbe4 | bellard | #define CTR SPR_ENCODE(9) |
215 | 79aceca5 | bellard | /* VEA mode SPR */
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216 | 9a64fbe4 | bellard | #define V_TBL SPR_ENCODE(268) |
217 | 9a64fbe4 | bellard | #define V_TBU SPR_ENCODE(269) |
218 | 79aceca5 | bellard | /* supervisor mode SPR */
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219 | 9a64fbe4 | bellard | #define DSISR SPR_ENCODE(18) |
220 | 9a64fbe4 | bellard | #define DAR SPR_ENCODE(19) |
221 | 9a64fbe4 | bellard | #define DECR SPR_ENCODE(22) |
222 | 9a64fbe4 | bellard | #define SDR1 SPR_ENCODE(25) |
223 | 9a64fbe4 | bellard | #define SRR0 SPR_ENCODE(26) |
224 | 9a64fbe4 | bellard | #define SRR1 SPR_ENCODE(27) |
225 | 9a64fbe4 | bellard | #define SPRG0 SPR_ENCODE(272) |
226 | 9a64fbe4 | bellard | #define SPRG1 SPR_ENCODE(273) |
227 | 9a64fbe4 | bellard | #define SPRG2 SPR_ENCODE(274) |
228 | 9a64fbe4 | bellard | #define SPRG3 SPR_ENCODE(275) |
229 | 9a64fbe4 | bellard | #define SPRG4 SPR_ENCODE(276) |
230 | 9a64fbe4 | bellard | #define SPRG5 SPR_ENCODE(277) |
231 | 9a64fbe4 | bellard | #define SPRG6 SPR_ENCODE(278) |
232 | 9a64fbe4 | bellard | #define SPRG7 SPR_ENCODE(279) |
233 | 9a64fbe4 | bellard | #define ASR SPR_ENCODE(280) |
234 | 9a64fbe4 | bellard | #define EAR SPR_ENCODE(282) |
235 | 9a64fbe4 | bellard | #define O_TBL SPR_ENCODE(284) |
236 | 9a64fbe4 | bellard | #define O_TBU SPR_ENCODE(285) |
237 | 9a64fbe4 | bellard | #define PVR SPR_ENCODE(287) |
238 | 9a64fbe4 | bellard | #define IBAT0U SPR_ENCODE(528) |
239 | 9a64fbe4 | bellard | #define IBAT0L SPR_ENCODE(529) |
240 | 9a64fbe4 | bellard | #define IBAT1U SPR_ENCODE(530) |
241 | 9a64fbe4 | bellard | #define IBAT1L SPR_ENCODE(531) |
242 | 9a64fbe4 | bellard | #define IBAT2U SPR_ENCODE(532) |
243 | 9a64fbe4 | bellard | #define IBAT2L SPR_ENCODE(533) |
244 | 9a64fbe4 | bellard | #define IBAT3U SPR_ENCODE(534) |
245 | 9a64fbe4 | bellard | #define IBAT3L SPR_ENCODE(535) |
246 | 9a64fbe4 | bellard | #define DBAT0U SPR_ENCODE(536) |
247 | 9a64fbe4 | bellard | #define DBAT0L SPR_ENCODE(537) |
248 | 9a64fbe4 | bellard | #define DBAT1U SPR_ENCODE(538) |
249 | 9a64fbe4 | bellard | #define DBAT1L SPR_ENCODE(539) |
250 | 9a64fbe4 | bellard | #define DBAT2U SPR_ENCODE(540) |
251 | 9a64fbe4 | bellard | #define DBAT2L SPR_ENCODE(541) |
252 | 9a64fbe4 | bellard | #define DBAT3U SPR_ENCODE(542) |
253 | 9a64fbe4 | bellard | #define DBAT3L SPR_ENCODE(543) |
254 | 9a64fbe4 | bellard | #define IBAT4U SPR_ENCODE(560) |
255 | 9a64fbe4 | bellard | #define IBAT4L SPR_ENCODE(561) |
256 | 9a64fbe4 | bellard | #define IBAT5U SPR_ENCODE(562) |
257 | 9a64fbe4 | bellard | #define IBAT5L SPR_ENCODE(563) |
258 | 9a64fbe4 | bellard | #define IBAT6U SPR_ENCODE(564) |
259 | 9a64fbe4 | bellard | #define IBAT6L SPR_ENCODE(565) |
260 | 9a64fbe4 | bellard | #define IBAT7U SPR_ENCODE(566) |
261 | 9a64fbe4 | bellard | #define IBAT7L SPR_ENCODE(567) |
262 | 9a64fbe4 | bellard | #define DBAT4U SPR_ENCODE(568) |
263 | 9a64fbe4 | bellard | #define DBAT4L SPR_ENCODE(569) |
264 | 9a64fbe4 | bellard | #define DBAT5U SPR_ENCODE(570) |
265 | 9a64fbe4 | bellard | #define DBAT5L SPR_ENCODE(571) |
266 | 9a64fbe4 | bellard | #define DBAT6U SPR_ENCODE(572) |
267 | 9a64fbe4 | bellard | #define DBAT6L SPR_ENCODE(573) |
268 | 9a64fbe4 | bellard | #define DBAT7U SPR_ENCODE(574) |
269 | 9a64fbe4 | bellard | #define DBAT7L SPR_ENCODE(575) |
270 | 9a64fbe4 | bellard | #define DABR SPR_ENCODE(1013) |
271 | 79aceca5 | bellard | #define DABR_MASK 0xFFFFFFF8 |
272 | 9a64fbe4 | bellard | #define FPECR SPR_ENCODE(1022) |
273 | 9a64fbe4 | bellard | #define PIR SPR_ENCODE(1023) |
274 | 79aceca5 | bellard | |
275 | 79aceca5 | bellard | #define TARGET_PAGE_BITS 12 |
276 | 79aceca5 | bellard | #include "cpu-all.h" |
277 | 79aceca5 | bellard | |
278 | 79aceca5 | bellard | CPUPPCState *cpu_ppc_init(void);
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279 | 79aceca5 | bellard | int cpu_ppc_exec(CPUPPCState *s);
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280 | 79aceca5 | bellard | void cpu_ppc_close(CPUPPCState *s);
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281 | 79aceca5 | bellard | void cpu_ppc_dump_state(CPUPPCState *env, FILE *f, int flags); |
282 | 9a64fbe4 | bellard | void PPC_init_hw (CPUPPCState *env, uint32_t mem_size,
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283 | 9a64fbe4 | bellard | uint32_t kernel_addr, uint32_t kernel_size, |
284 | 9a64fbe4 | bellard | uint32_t stack_addr, int boot_device);
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285 | 79aceca5 | bellard | |
286 | 9a64fbe4 | bellard | /* Memory access type :
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287 | 9a64fbe4 | bellard | * may be needed for precise access rights control and precise exceptions.
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288 | 9a64fbe4 | bellard | */
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289 | 79aceca5 | bellard | enum {
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290 | 9a64fbe4 | bellard | /* 1 bit to define user level / supervisor access */
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291 | 9a64fbe4 | bellard | ACCESS_USER = 0x00,
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292 | 9a64fbe4 | bellard | ACCESS_SUPER = 0x01,
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293 | 9a64fbe4 | bellard | /* Type of instruction that generated the access */
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294 | 9a64fbe4 | bellard | ACCESS_CODE = 0x10, /* Code fetch access */ |
295 | 9a64fbe4 | bellard | ACCESS_INT = 0x20, /* Integer load/store access */ |
296 | 9a64fbe4 | bellard | ACCESS_FLOAT = 0x30, /* floating point load/store access */ |
297 | 9a64fbe4 | bellard | ACCESS_RES = 0x40, /* load/store with reservation */ |
298 | 9a64fbe4 | bellard | ACCESS_EXT = 0x50, /* external access */ |
299 | 9a64fbe4 | bellard | ACCESS_CACHE = 0x60, /* Cache manipulation */ |
300 | 9a64fbe4 | bellard | }; |
301 | 9a64fbe4 | bellard | |
302 | 9a64fbe4 | bellard | /*****************************************************************************/
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303 | 9a64fbe4 | bellard | /* Exceptions */
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304 | 9a64fbe4 | bellard | enum {
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305 | 9a64fbe4 | bellard | EXCP_NONE = -1,
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306 | 79aceca5 | bellard | /* PPC hardware exceptions : exception vector / 0x100 */
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307 | 79aceca5 | bellard | EXCP_RESET = 0x01, /* System reset */ |
308 | 79aceca5 | bellard | EXCP_MACHINE_CHECK = 0x02, /* Machine check exception */ |
309 | 79aceca5 | bellard | EXCP_DSI = 0x03, /* Impossible memory access */ |
310 | 79aceca5 | bellard | EXCP_ISI = 0x04, /* Impossible instruction fetch */ |
311 | 79aceca5 | bellard | EXCP_EXTERNAL = 0x05, /* External interruption */ |
312 | 79aceca5 | bellard | EXCP_ALIGN = 0x06, /* Alignment exception */ |
313 | 79aceca5 | bellard | EXCP_PROGRAM = 0x07, /* Program exception */ |
314 | 79aceca5 | bellard | EXCP_NO_FP = 0x08, /* No floating point */ |
315 | 79aceca5 | bellard | EXCP_DECR = 0x09, /* Decrementer exception */ |
316 | 79aceca5 | bellard | EXCP_RESA = 0x0A, /* Implementation specific */ |
317 | 79aceca5 | bellard | EXCP_RESB = 0x0B, /* Implementation specific */ |
318 | 79aceca5 | bellard | EXCP_SYSCALL = 0x0C, /* System call */ |
319 | 79aceca5 | bellard | EXCP_TRACE = 0x0D, /* Trace exception (optional) */ |
320 | 79aceca5 | bellard | EXCP_FP_ASSIST = 0x0E, /* Floating-point assist (optional) */ |
321 | 9a64fbe4 | bellard | /* MPC740/745/750 & IBM 750 */
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322 | 9a64fbe4 | bellard | EXCP_PERF = 0x0F, /* Performance monitor */ |
323 | 9a64fbe4 | bellard | EXCP_IABR = 0x13, /* Instruction address breakpoint */ |
324 | 9a64fbe4 | bellard | EXCP_SMI = 0x14, /* System management interrupt */ |
325 | 9a64fbe4 | bellard | EXCP_THRM = 0x15, /* Thermal management interrupt */ |
326 | 9a64fbe4 | bellard | /* MPC755 */
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327 | 9a64fbe4 | bellard | EXCP_TLBMISS = 0x10, /* Instruction TLB miss */ |
328 | 9a64fbe4 | bellard | EXCP_TLBMISS_DL = 0x11, /* Data TLB miss for load */ |
329 | 9a64fbe4 | bellard | EXCP_TLBMISS_DS = 0x12, /* Data TLB miss for store */ |
330 | 9a64fbe4 | bellard | EXCP_PPC_MAX = 0x16,
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331 | 9a64fbe4 | bellard | /* Qemu exception */
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332 | 9a64fbe4 | bellard | EXCP_OFCALL = 0x20, /* Call open-firmware emulator */ |
333 | 9a64fbe4 | bellard | EXCP_RTASCALL = 0x21, /* Call RTAS emulator */ |
334 | 9a64fbe4 | bellard | /* Special cases where we want to stop translation */
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335 | 9a64fbe4 | bellard | EXCP_MTMSR = 0x104, /* mtmsr instruction: */ |
336 | 9a64fbe4 | bellard | /* may change privilege level */
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337 | 9a64fbe4 | bellard | EXCP_BRANCH = 0x108, /* branch instruction */ |
338 | 9a64fbe4 | bellard | EXCP_RFI = 0x10C, /* return from interrupt */ |
339 | 9a64fbe4 | bellard | EXCP_SYSCALL_USER = 0x110, /* System call in user mode only */ |
340 | 9a64fbe4 | bellard | }; |
341 | 9a64fbe4 | bellard | /* Error codes */
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342 | 9a64fbe4 | bellard | enum {
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343 | 9a64fbe4 | bellard | /* Exception subtypes for EXCP_DSI */
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344 | 9a64fbe4 | bellard | EXCP_DSI_TRANSLATE = 0x01, /* Data address can't be translated */ |
345 | 9a64fbe4 | bellard | EXCP_DSI_NOTSUP = 0x02, /* Access type not supported */ |
346 | 9a64fbe4 | bellard | EXCP_DSI_PROT = 0x03, /* Memory protection violation */ |
347 | 9a64fbe4 | bellard | EXCP_DSI_EXTERNAL = 0x04, /* External access disabled */ |
348 | 9a64fbe4 | bellard | EXCP_DSI_DABR = 0x05, /* Data address breakpoint */ |
349 | 9a64fbe4 | bellard | /* flags for EXCP_DSI */
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350 | 9a64fbe4 | bellard | EXCP_DSI_DIRECT = 0x10,
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351 | 9a64fbe4 | bellard | EXCP_DSI_STORE = 0x20,
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352 | 9a64fbe4 | bellard | EXCP_ECXW = 0x40,
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353 | 9a64fbe4 | bellard | /* Exception subtypes for EXCP_ISI */
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354 | 9a64fbe4 | bellard | EXCP_ISI_TRANSLATE = 0x01, /* Code address can't be translated */ |
355 | 9a64fbe4 | bellard | EXCP_ISI_NOEXEC = 0x02, /* Try to fetch from a data segment */ |
356 | 9a64fbe4 | bellard | EXCP_ISI_GUARD = 0x03, /* Fetch from guarded memory */ |
357 | 9a64fbe4 | bellard | EXCP_ISI_PROT = 0x04, /* Memory protection violation */ |
358 | 9a64fbe4 | bellard | /* Exception subtypes for EXCP_ALIGN */
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359 | 9a64fbe4 | bellard | EXCP_ALIGN_FP = 0x01, /* FP alignment exception */ |
360 | 9a64fbe4 | bellard | EXCP_ALIGN_LST = 0x02, /* Unaligned mult/extern load/store */ |
361 | 9a64fbe4 | bellard | EXCP_ALIGN_LE = 0x03, /* Multiple little-endian access */ |
362 | 9a64fbe4 | bellard | EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */ |
363 | 9a64fbe4 | bellard | EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */ |
364 | 9a64fbe4 | bellard | EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */ |
365 | 9a64fbe4 | bellard | /* Exception subtypes for EXCP_PROGRAM */
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366 | 79aceca5 | bellard | /* FP exceptions */
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367 | 9a64fbe4 | bellard | EXCP_FP = 0x10,
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368 | 9a64fbe4 | bellard | EXCP_FP_OX = 0x01, /* FP overflow */ |
369 | 9a64fbe4 | bellard | EXCP_FP_UX = 0x02, /* FP underflow */ |
370 | 9a64fbe4 | bellard | EXCP_FP_ZX = 0x03, /* FP divide by zero */ |
371 | 9a64fbe4 | bellard | EXCP_FP_XX = 0x04, /* FP inexact */ |
372 | 9a64fbe4 | bellard | EXCP_FP_VXNAN = 0x05, /* FP invalid SNaN op */ |
373 | 9a64fbe4 | bellard | EXCP_FP_VXISI = 0x06, /* FP invalid infinite substraction */ |
374 | 9a64fbe4 | bellard | EXCP_FP_VXIDI = 0x07, /* FP invalid infinite divide */ |
375 | 9a64fbe4 | bellard | EXCP_FP_VXZDZ = 0x08, /* FP invalid zero divide */ |
376 | 9a64fbe4 | bellard | EXCP_FP_VXIMZ = 0x09, /* FP invalid infinite * zero */ |
377 | 9a64fbe4 | bellard | EXCP_FP_VXVC = 0x0A, /* FP invalid compare */ |
378 | 9a64fbe4 | bellard | EXCP_FP_VXSOFT = 0x0B, /* FP invalid operation */ |
379 | 9a64fbe4 | bellard | EXCP_FP_VXSQRT = 0x0C, /* FP invalid square root */ |
380 | 9a64fbe4 | bellard | EXCP_FP_VXCVI = 0x0D, /* FP invalid integer conversion */ |
381 | 79aceca5 | bellard | /* Invalid instruction */
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382 | 9a64fbe4 | bellard | EXCP_INVAL = 0x20,
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383 | 9a64fbe4 | bellard | EXCP_INVAL_INVAL = 0x01, /* Invalid instruction */ |
384 | 9a64fbe4 | bellard | EXCP_INVAL_LSWX = 0x02, /* Invalid lswx instruction */ |
385 | 9a64fbe4 | bellard | EXCP_INVAL_SPR = 0x03, /* Invalid SPR access */ |
386 | 9a64fbe4 | bellard | EXCP_INVAL_FP = 0x04, /* Unimplemented mandatory fp instr */ |
387 | 79aceca5 | bellard | /* Privileged instruction */
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388 | 9a64fbe4 | bellard | EXCP_PRIV = 0x30,
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389 | 9a64fbe4 | bellard | EXCP_PRIV_OPC = 0x01,
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390 | 9a64fbe4 | bellard | EXCP_PRIV_REG = 0x02,
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391 | 79aceca5 | bellard | /* Trap */
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392 | 9a64fbe4 | bellard | EXCP_TRAP = 0x40,
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393 | 79aceca5 | bellard | }; |
394 | 79aceca5 | bellard | |
395 | 9a64fbe4 | bellard | /*****************************************************************************/
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396 | 9a64fbe4 | bellard | |
397 | 79aceca5 | bellard | #endif /* !defined (__CPU_PPC_H__) */ |