Revision 98cec4a2 hw/sun4u.c
| b/hw/sun4u.c | ||
|---|---|---|
| 243 | 243 |
return kernel_size; |
| 244 | 244 |
} |
| 245 | 245 |
|
| 246 |
void cpu_check_irqs(CPUState *env) |
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| 246 |
void cpu_check_irqs(CPUSPARCState *env)
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{
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uint32_t pil = env->pil_in | |
| 249 | 249 |
(env->softint & ~(SOFTINT_TIMER | SOFTINT_STIMER)); |
| ... | ... | |
| 297 | 297 |
} |
| 298 | 298 |
} |
| 299 | 299 |
|
| 300 |
static void cpu_kick_irq(CPUState *env) |
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| 300 |
static void cpu_kick_irq(CPUSPARCState *env)
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{
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env->halted = 0; |
| 303 | 303 |
cpu_check_irqs(env); |
| ... | ... | |
| 306 | 306 |
|
| 307 | 307 |
static void cpu_set_irq(void *opaque, int irq, int level) |
| 308 | 308 |
{
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CPUState *env = opaque; |
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CPUSPARCState *env = opaque;
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if (level) {
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CPUIRQ_DPRINTF("Raise CPU IRQ %d\n", irq);
|
| ... | ... | |
| 320 | 320 |
} |
| 321 | 321 |
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typedef struct ResetData {
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CPUState *env; |
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CPUSPARCState *env;
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uint64_t prom_addr; |
| 325 | 325 |
} ResetData; |
| 326 | 326 |
|
| ... | ... | |
| 344 | 344 |
qemu_get_timer(f, s->qtimer); |
| 345 | 345 |
} |
| 346 | 346 |
|
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static CPUTimer* cpu_timer_create(const char* name, CPUState *env, |
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static CPUTimer* cpu_timer_create(const char* name, CPUSPARCState *env,
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QEMUBHFunc *cb, uint32_t frequency, |
| 349 | 349 |
uint64_t disabled_mask) |
| 350 | 350 |
{
|
| ... | ... | |
| 373 | 373 |
static void main_cpu_reset(void *opaque) |
| 374 | 374 |
{
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| 375 | 375 |
ResetData *s = (ResetData *)opaque; |
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CPUState *env = s->env; |
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CPUSPARCState *env = s->env;
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| 377 | 377 |
static unsigned int nr_resets; |
| 378 | 378 |
|
| 379 | 379 |
cpu_state_reset(env); |
| ... | ... | |
| 396 | 396 |
|
| 397 | 397 |
static void tick_irq(void *opaque) |
| 398 | 398 |
{
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CPUState *env = opaque; |
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CPUSPARCState *env = opaque;
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CPUTimer* timer = env->tick; |
| 402 | 402 |
|
| ... | ... | |
| 413 | 413 |
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static void stick_irq(void *opaque) |
| 415 | 415 |
{
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CPUState *env = opaque; |
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CPUSPARCState *env = opaque;
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CPUTimer* timer = env->stick; |
| 419 | 419 |
|
| ... | ... | |
| 430 | 430 |
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static void hstick_irq(void *opaque) |
| 432 | 432 |
{
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CPUState *env = opaque; |
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CPUSPARCState *env = opaque;
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CPUTimer* timer = env->hstick; |
| 436 | 436 |
|
| ... | ... | |
| 714 | 714 |
.class_init = ram_class_init, |
| 715 | 715 |
}; |
| 716 | 716 |
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static CPUState *cpu_devinit(const char *cpu_model, const struct hwdef *hwdef) |
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static CPUSPARCState *cpu_devinit(const char *cpu_model, const struct hwdef *hwdef)
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{
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CPUState *env; |
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CPUSPARCState *env;
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ResetData *reset_info; |
| 721 | 721 |
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uint32_t tick_frequency = 100*1000000; |
| ... | ... | |
| 755 | 755 |
const char *initrd_filename, const char *cpu_model, |
| 756 | 756 |
const struct hwdef *hwdef) |
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{
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CPUState *env; |
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CPUSPARCState *env;
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| 759 | 759 |
M48t59State *nvram; |
| 760 | 760 |
unsigned int i; |
| 761 | 761 |
long initrd_size, kernel_size; |
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