Revision 9940a96b
| b/tcg/arm/tcg-target.h | ||
|---|---|---|
| 68 | 68 |
#define TCG_TARGET_HAS_andc_i32 |
| 69 | 69 |
// #define TCG_TARGET_HAS_orc_i32 |
| 70 | 70 |
// #define TCG_TARGET_HAS_eqv_i32 |
| 71 |
// #define TCG_TARGET_HAS_nand_i32 |
|
| 71 | 72 |
|
| 72 | 73 |
#define TCG_TARGET_HAS_GUEST_BASE |
| 73 | 74 |
|
| b/tcg/i386/tcg-target.h | ||
|---|---|---|
| 58 | 58 |
// #define TCG_TARGET_HAS_andc_i32 |
| 59 | 59 |
// #define TCG_TARGET_HAS_orc_i32 |
| 60 | 60 |
// #define TCG_TARGET_HAS_eqv_i32 |
| 61 |
// #define TCG_TARGET_HAS_nand_i32 |
|
| 61 | 62 |
|
| 62 | 63 |
#define TCG_TARGET_HAS_GUEST_BASE |
| 63 | 64 |
|
| b/tcg/mips/tcg-target.h | ||
|---|---|---|
| 88 | 88 |
#undef TCG_TARGET_HAS_andc_i32 |
| 89 | 89 |
#undef TCG_TARGET_HAS_orc_i32 |
| 90 | 90 |
#undef TCG_TARGET_HAS_eqv_i32 |
| 91 |
#undef TCG_TARGET_HAS_nand_i32 |
|
| 91 | 92 |
|
| 92 | 93 |
/* optional instructions automatically implemented */ |
| 93 | 94 |
#undef TCG_TARGET_HAS_neg_i32 /* sub rd, zero, rt */ |
| b/tcg/ppc/tcg-target.h | ||
|---|---|---|
| 90 | 90 |
#define TCG_TARGET_HAS_andc_i32 |
| 91 | 91 |
#define TCG_TARGET_HAS_orc_i32 |
| 92 | 92 |
/* #define TCG_TARGET_HAS_eqv_i32 */ |
| 93 |
/* #define TCG_TARGET_HAS_nand_i32 */ |
|
| 93 | 94 |
|
| 94 | 95 |
#define TCG_AREG0 TCG_REG_R27 |
| 95 | 96 |
|
| b/tcg/ppc64/tcg-target.h | ||
|---|---|---|
| 81 | 81 |
/* #define TCG_TARGET_HAS_andc_i32 */ |
| 82 | 82 |
/* #define TCG_TARGET_HAS_orc_i32 */ |
| 83 | 83 |
/* #define TCG_TARGET_HAS_eqv_i32 */ |
| 84 |
/* #define TCG_TARGET_HAS_nand_i32 */ |
|
| 84 | 85 |
|
| 85 | 86 |
#define TCG_TARGET_HAS_div_i64 |
| 86 | 87 |
/* #define TCG_TARGET_HAS_rot_i64 */ |
| ... | ... | |
| 98 | 99 |
/* #define TCG_TARGET_HAS_andc_i64 */ |
| 99 | 100 |
/* #define TCG_TARGET_HAS_orc_i64 */ |
| 100 | 101 |
/* #define TCG_TARGET_HAS_eqv_i64 */ |
| 102 |
/* #define TCG_TARGET_HAS_nand_i64 */ |
|
| 101 | 103 |
|
| 102 | 104 |
#define TCG_AREG0 TCG_REG_R27 |
| 103 | 105 |
|
| b/tcg/s390/tcg-target.h | ||
|---|---|---|
| 60 | 60 |
// #define TCG_TARGET_HAS_andc_i32 |
| 61 | 61 |
// #define TCG_TARGET_HAS_orc_i32 |
| 62 | 62 |
// #define TCG_TARGET_HAS_eqv_i32 |
| 63 |
// #define TCG_TARGET_HAS_nand_i32 |
|
| 63 | 64 |
|
| 64 | 65 |
// #define TCG_TARGET_HAS_div_i64 |
| 65 | 66 |
// #define TCG_TARGET_HAS_rot_i64 |
| ... | ... | |
| 77 | 78 |
// #define TCG_TARGET_HAS_andc_i64 |
| 78 | 79 |
// #define TCG_TARGET_HAS_orc_i64 |
| 79 | 80 |
// #define TCG_TARGET_HAS_eqv_i64 |
| 81 |
// #define TCG_TARGET_HAS_nand_i64 |
|
| 80 | 82 |
|
| 81 | 83 |
/* used for function call generation */ |
| 82 | 84 |
#define TCG_REG_CALL_STACK TCG_REG_R15 |
| b/tcg/sparc/tcg-target.h | ||
|---|---|---|
| 101 | 101 |
#define TCG_TARGET_HAS_andc_i32 |
| 102 | 102 |
#define TCG_TARGET_HAS_orc_i32 |
| 103 | 103 |
// #define TCG_TARGET_HAS_eqv_i32 |
| 104 |
// #define TCG_TARGET_HAS_nand_i32 |
|
| 104 | 105 |
|
| 105 | 106 |
#if TCG_TARGET_REG_BITS == 64 |
| 106 | 107 |
#define TCG_TARGET_HAS_div_i64 |
| ... | ... | |
| 119 | 120 |
#define TCG_TARGET_HAS_andc_i64 |
| 120 | 121 |
#define TCG_TARGET_HAS_orc_i64 |
| 121 | 122 |
// #define TCG_TARGET_HAS_eqv_i64 |
| 123 |
// #define TCG_TARGET_HAS_nand_i64 |
|
| 122 | 124 |
#endif |
| 123 | 125 |
|
| 124 | 126 |
/* Note: must be synced with dyngen-exec.h */ |
| b/tcg/tcg-op.h | ||
|---|---|---|
| 1763 | 1763 |
|
| 1764 | 1764 |
static inline void tcg_gen_nand_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
| 1765 | 1765 |
{
|
| 1766 |
#ifdef TCG_TARGET_HAS_nand_i32 |
|
| 1767 |
tcg_gen_op3_i32(INDEX_op_nand_i32, ret, arg1, arg2); |
|
| 1768 |
#else |
|
| 1766 | 1769 |
tcg_gen_and_i32(ret, arg1, arg2); |
| 1767 | 1770 |
tcg_gen_not_i32(ret, ret); |
| 1771 |
#endif |
|
| 1768 | 1772 |
} |
| 1769 | 1773 |
|
| 1770 | 1774 |
static inline void tcg_gen_nand_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
| 1771 | 1775 |
{
|
| 1776 |
#ifdef TCG_TARGET_HAS_nand_i64 |
|
| 1777 |
tcg_gen_op3_i64(INDEX_op_nand_i64, ret, arg1, arg2); |
|
| 1778 |
#elif defined(TCG_TARGET_HAS_nand_i32) && TCG_TARGET_REG_BITS == 32 |
|
| 1779 |
tcg_gen_nand_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); |
|
| 1780 |
tcg_gen_nand_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); |
|
| 1781 |
#else |
|
| 1772 | 1782 |
tcg_gen_and_i64(ret, arg1, arg2); |
| 1773 | 1783 |
tcg_gen_not_i64(ret, ret); |
| 1784 |
#endif |
|
| 1774 | 1785 |
} |
| 1775 | 1786 |
|
| 1776 | 1787 |
static inline void tcg_gen_nor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
| b/tcg/tcg-opc.h | ||
|---|---|---|
| 119 | 119 |
#ifdef TCG_TARGET_HAS_eqv_i32 |
| 120 | 120 |
DEF2(eqv_i32, 1, 2, 0, 0) |
| 121 | 121 |
#endif |
| 122 |
#ifdef TCG_TARGET_HAS_nand_i32 |
|
| 123 |
DEF2(nand_i32, 1, 2, 0, 0) |
|
| 124 |
#endif |
|
| 122 | 125 |
|
| 123 | 126 |
#if TCG_TARGET_REG_BITS == 64 |
| 124 | 127 |
DEF2(mov_i64, 1, 1, 0, 0) |
| ... | ... | |
| 205 | 208 |
#ifdef TCG_TARGET_HAS_eqv_i64 |
| 206 | 209 |
DEF2(eqv_i64, 1, 2, 0, 0) |
| 207 | 210 |
#endif |
| 211 |
#ifdef TCG_TARGET_HAS_nand_i64 |
|
| 212 |
DEF2(nand_i64, 1, 2, 0, 0) |
|
| 213 |
#endif |
|
| 208 | 214 |
#endif |
| 209 | 215 |
|
| 210 | 216 |
/* QEMU specific */ |
| b/tcg/x86_64/tcg-target.h | ||
|---|---|---|
| 86 | 86 |
// #define TCG_TARGET_HAS_orc_i64 |
| 87 | 87 |
// #define TCG_TARGET_HAS_eqv_i32 |
| 88 | 88 |
// #define TCG_TARGET_HAS_eqv_i64 |
| 89 |
// #define TCG_TARGET_HAS_nand_i32 |
|
| 90 |
// #define TCG_TARGET_HAS_nand_i64 |
|
| 89 | 91 |
|
| 90 | 92 |
#define TCG_TARGET_HAS_GUEST_BASE |
| 91 | 93 |
|
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