root / hw / omap_dma.c @ 99570a40
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1 | b4e3104b | balrog | /*
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2 | b4e3104b | balrog | * TI OMAP DMA gigacell.
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3 | b4e3104b | balrog | *
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4 | b4e3104b | balrog | * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org>
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5 | b4e3104b | balrog | * Copyright (C) 2007-2008 Lauro Ramos Venancio <lauro.venancio@indt.org.br>
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6 | b4e3104b | balrog | *
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7 | b4e3104b | balrog | * This program is free software; you can redistribute it and/or
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8 | b4e3104b | balrog | * modify it under the terms of the GNU General Public License as
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9 | b4e3104b | balrog | * published by the Free Software Foundation; either version 2 of
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10 | b4e3104b | balrog | * the License, or (at your option) any later version.
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11 | b4e3104b | balrog | *
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12 | b4e3104b | balrog | * This program is distributed in the hope that it will be useful,
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13 | b4e3104b | balrog | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 | b4e3104b | balrog | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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15 | b4e3104b | balrog | * GNU General Public License for more details.
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16 | b4e3104b | balrog | *
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17 | b4e3104b | balrog | * You should have received a copy of the GNU General Public License
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18 | b4e3104b | balrog | * along with this program; if not, write to the Free Software
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19 | b4e3104b | balrog | * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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20 | b4e3104b | balrog | * MA 02111-1307 USA
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21 | b4e3104b | balrog | */
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22 | b4e3104b | balrog | #include "qemu-common.h" |
23 | b4e3104b | balrog | #include "qemu-timer.h" |
24 | b4e3104b | balrog | #include "omap.h" |
25 | b4e3104b | balrog | #include "irq.h" |
26 | b4e3104b | balrog | |
27 | b4e3104b | balrog | struct omap_dma_channel_s {
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28 | b4e3104b | balrog | /* transfer data */
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29 | b4e3104b | balrog | int burst[2]; |
30 | b4e3104b | balrog | int pack[2]; |
31 | 827df9f3 | balrog | int endian[2]; |
32 | 827df9f3 | balrog | int endian_lock[2]; |
33 | 827df9f3 | balrog | int translate[2]; |
34 | b4e3104b | balrog | enum omap_dma_port port[2]; |
35 | b4e3104b | balrog | target_phys_addr_t addr[2];
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36 | b4e3104b | balrog | omap_dma_addressing_t mode[2];
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37 | 827df9f3 | balrog | uint32_t elements; |
38 | b4e3104b | balrog | uint16_t frames; |
39 | 827df9f3 | balrog | int32_t frame_index[2];
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40 | b4e3104b | balrog | int16_t element_index[2];
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41 | b4e3104b | balrog | int data_type;
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42 | b4e3104b | balrog | |
43 | b4e3104b | balrog | /* transfer type */
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44 | b4e3104b | balrog | int transparent_copy;
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45 | b4e3104b | balrog | int constant_fill;
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46 | b4e3104b | balrog | uint32_t color; |
47 | 827df9f3 | balrog | int prefetch;
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48 | b4e3104b | balrog | |
49 | b4e3104b | balrog | /* auto init and linked channel data */
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50 | b4e3104b | balrog | int end_prog;
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51 | b4e3104b | balrog | int repeat;
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52 | b4e3104b | balrog | int auto_init;
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53 | b4e3104b | balrog | int link_enabled;
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54 | b4e3104b | balrog | int link_next_ch;
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55 | b4e3104b | balrog | |
56 | b4e3104b | balrog | /* interruption data */
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57 | b4e3104b | balrog | int interrupts;
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58 | b4e3104b | balrog | int status;
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59 | 827df9f3 | balrog | int cstatus;
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60 | b4e3104b | balrog | |
61 | b4e3104b | balrog | /* state data */
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62 | b4e3104b | balrog | int active;
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63 | b4e3104b | balrog | int enable;
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64 | b4e3104b | balrog | int sync;
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65 | 827df9f3 | balrog | int src_sync;
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66 | b4e3104b | balrog | int pending_request;
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67 | b4e3104b | balrog | int waiting_end_prog;
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68 | b4e3104b | balrog | uint16_t cpc; |
69 | b4e3104b | balrog | |
70 | b4e3104b | balrog | /* sync type */
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71 | b4e3104b | balrog | int fs;
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72 | b4e3104b | balrog | int bs;
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73 | b4e3104b | balrog | |
74 | b4e3104b | balrog | /* compatibility */
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75 | b4e3104b | balrog | int omap_3_1_compatible_disable;
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76 | b4e3104b | balrog | |
77 | b4e3104b | balrog | qemu_irq irq; |
78 | b4e3104b | balrog | struct omap_dma_channel_s *sibling;
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79 | b4e3104b | balrog | |
80 | b4e3104b | balrog | struct omap_dma_reg_set_s {
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81 | b4e3104b | balrog | target_phys_addr_t src, dest; |
82 | b4e3104b | balrog | int frame;
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83 | b4e3104b | balrog | int element;
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84 | 827df9f3 | balrog | int pck_element;
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85 | b4e3104b | balrog | int frame_delta[2]; |
86 | b4e3104b | balrog | int elem_delta[2]; |
87 | b4e3104b | balrog | int frames;
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88 | b4e3104b | balrog | int elements;
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89 | 827df9f3 | balrog | int pck_elements;
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90 | b4e3104b | balrog | } active_set; |
91 | b4e3104b | balrog | |
92 | b4e3104b | balrog | /* unused parameters */
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93 | 827df9f3 | balrog | int write_mode;
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94 | b4e3104b | balrog | int priority;
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95 | b4e3104b | balrog | int interleave_disabled;
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96 | b4e3104b | balrog | int type;
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97 | 827df9f3 | balrog | int suspend;
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98 | 827df9f3 | balrog | int buf_disable;
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99 | b4e3104b | balrog | }; |
100 | b4e3104b | balrog | |
101 | b4e3104b | balrog | struct omap_dma_s {
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102 | b4e3104b | balrog | QEMUTimer *tm; |
103 | b4e3104b | balrog | struct omap_mpu_state_s *mpu;
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104 | b4e3104b | balrog | target_phys_addr_t base; |
105 | b4e3104b | balrog | omap_clk clk; |
106 | b4e3104b | balrog | int64_t delay; |
107 | 827df9f3 | balrog | uint64_t drq; |
108 | 827df9f3 | balrog | qemu_irq irq[4];
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109 | 827df9f3 | balrog | void (*intr_update)(struct omap_dma_s *s); |
110 | b4e3104b | balrog | enum omap_dma_model model;
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111 | b4e3104b | balrog | int omap_3_1_mapping_disabled;
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112 | b4e3104b | balrog | |
113 | 827df9f3 | balrog | uint32_t gcr; |
114 | 827df9f3 | balrog | uint32_t ocp; |
115 | 827df9f3 | balrog | uint32_t caps[5];
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116 | 827df9f3 | balrog | uint32_t irqen[4];
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117 | 827df9f3 | balrog | uint32_t irqstat[4];
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118 | b4e3104b | balrog | int run_count;
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119 | b4e3104b | balrog | |
120 | b4e3104b | balrog | int chans;
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121 | 827df9f3 | balrog | struct omap_dma_channel_s ch[32]; |
122 | b4e3104b | balrog | struct omap_dma_lcd_channel_s lcd_ch;
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123 | b4e3104b | balrog | }; |
124 | b4e3104b | balrog | |
125 | b4e3104b | balrog | /* Interrupts */
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126 | b4e3104b | balrog | #define TIMEOUT_INTR (1 << 0) |
127 | b4e3104b | balrog | #define EVENT_DROP_INTR (1 << 1) |
128 | b4e3104b | balrog | #define HALF_FRAME_INTR (1 << 2) |
129 | b4e3104b | balrog | #define END_FRAME_INTR (1 << 3) |
130 | b4e3104b | balrog | #define LAST_FRAME_INTR (1 << 4) |
131 | b4e3104b | balrog | #define END_BLOCK_INTR (1 << 5) |
132 | b4e3104b | balrog | #define SYNC (1 << 6) |
133 | 827df9f3 | balrog | #define END_PKT_INTR (1 << 7) |
134 | 827df9f3 | balrog | #define TRANS_ERR_INTR (1 << 8) |
135 | 827df9f3 | balrog | #define MISALIGN_INTR (1 << 11) |
136 | b4e3104b | balrog | |
137 | 827df9f3 | balrog | static inline void omap_dma_interrupts_update(struct omap_dma_s *s) |
138 | b4e3104b | balrog | { |
139 | 827df9f3 | balrog | return s->intr_update(s);
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140 | b4e3104b | balrog | } |
141 | b4e3104b | balrog | |
142 | b4e3104b | balrog | static void omap_dma_channel_load(struct omap_dma_s *s, |
143 | b4e3104b | balrog | struct omap_dma_channel_s *ch)
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144 | b4e3104b | balrog | { |
145 | b4e3104b | balrog | struct omap_dma_reg_set_s *a = &ch->active_set;
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146 | b4e3104b | balrog | int i;
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147 | b4e3104b | balrog | int omap_3_1 = !ch->omap_3_1_compatible_disable;
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148 | b4e3104b | balrog | |
149 | b4e3104b | balrog | /*
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150 | b4e3104b | balrog | * TODO: verify address ranges and alignment
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151 | b4e3104b | balrog | * TODO: port endianness
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152 | b4e3104b | balrog | */
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153 | b4e3104b | balrog | |
154 | b4e3104b | balrog | a->src = ch->addr[0];
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155 | b4e3104b | balrog | a->dest = ch->addr[1];
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156 | b4e3104b | balrog | a->frames = ch->frames; |
157 | b4e3104b | balrog | a->elements = ch->elements; |
158 | 827df9f3 | balrog | a->pck_elements = ch->frame_index[!ch->src_sync]; |
159 | b4e3104b | balrog | a->frame = 0;
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160 | b4e3104b | balrog | a->element = 0;
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161 | 827df9f3 | balrog | a->pck_element = 0;
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162 | b4e3104b | balrog | |
163 | b4e3104b | balrog | if (unlikely(!ch->elements || !ch->frames)) {
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164 | b4e3104b | balrog | printf("%s: bad DMA request\n", __FUNCTION__);
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165 | b4e3104b | balrog | return;
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166 | b4e3104b | balrog | } |
167 | b4e3104b | balrog | |
168 | b4e3104b | balrog | for (i = 0; i < 2; i ++) |
169 | b4e3104b | balrog | switch (ch->mode[i]) {
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170 | b4e3104b | balrog | case constant:
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171 | b4e3104b | balrog | a->elem_delta[i] = 0;
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172 | b4e3104b | balrog | a->frame_delta[i] = 0;
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173 | b4e3104b | balrog | break;
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174 | b4e3104b | balrog | case post_incremented:
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175 | b4e3104b | balrog | a->elem_delta[i] = ch->data_type; |
176 | b4e3104b | balrog | a->frame_delta[i] = 0;
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177 | b4e3104b | balrog | break;
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178 | b4e3104b | balrog | case single_index:
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179 | b4e3104b | balrog | a->elem_delta[i] = ch->data_type + |
180 | b4e3104b | balrog | ch->element_index[omap_3_1 ? 0 : i] - 1; |
181 | b4e3104b | balrog | a->frame_delta[i] = 0;
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182 | b4e3104b | balrog | break;
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183 | b4e3104b | balrog | case double_index:
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184 | b4e3104b | balrog | a->elem_delta[i] = ch->data_type + |
185 | b4e3104b | balrog | ch->element_index[omap_3_1 ? 0 : i] - 1; |
186 | b4e3104b | balrog | a->frame_delta[i] = ch->frame_index[omap_3_1 ? 0 : i] -
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187 | b4e3104b | balrog | ch->element_index[omap_3_1 ? 0 : i];
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188 | b4e3104b | balrog | break;
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189 | b4e3104b | balrog | default:
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190 | b4e3104b | balrog | break;
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191 | b4e3104b | balrog | } |
192 | b4e3104b | balrog | } |
193 | b4e3104b | balrog | |
194 | b4e3104b | balrog | static void omap_dma_activate_channel(struct omap_dma_s *s, |
195 | b4e3104b | balrog | struct omap_dma_channel_s *ch)
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196 | b4e3104b | balrog | { |
197 | b4e3104b | balrog | if (!ch->active) {
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198 | b4e3104b | balrog | ch->active = 1;
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199 | b4e3104b | balrog | if (ch->sync)
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200 | b4e3104b | balrog | ch->status |= SYNC; |
201 | b4e3104b | balrog | s->run_count ++; |
202 | b4e3104b | balrog | } |
203 | b4e3104b | balrog | |
204 | b4e3104b | balrog | if (s->delay && !qemu_timer_pending(s->tm))
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205 | b4e3104b | balrog | qemu_mod_timer(s->tm, qemu_get_clock(vm_clock) + s->delay); |
206 | b4e3104b | balrog | } |
207 | b4e3104b | balrog | |
208 | b4e3104b | balrog | static void omap_dma_deactivate_channel(struct omap_dma_s *s, |
209 | b4e3104b | balrog | struct omap_dma_channel_s *ch)
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210 | b4e3104b | balrog | { |
211 | b4e3104b | balrog | /* Update cpc */
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212 | b4e3104b | balrog | ch->cpc = ch->active_set.dest & 0xffff;
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213 | b4e3104b | balrog | |
214 | 827df9f3 | balrog | if (ch->pending_request && !ch->waiting_end_prog && ch->enable) {
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215 | b4e3104b | balrog | /* Don't deactivate the channel */
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216 | b4e3104b | balrog | ch->pending_request = 0;
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217 | 827df9f3 | balrog | return;
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218 | b4e3104b | balrog | } |
219 | b4e3104b | balrog | |
220 | b4e3104b | balrog | /* Don't deactive the channel if it is synchronized and the DMA request is
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221 | b4e3104b | balrog | active */
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222 | 827df9f3 | balrog | if (ch->sync && ch->enable && (s->drq & (1 << ch->sync))) |
223 | b4e3104b | balrog | return;
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224 | b4e3104b | balrog | |
225 | b4e3104b | balrog | if (ch->active) {
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226 | b4e3104b | balrog | ch->active = 0;
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227 | b4e3104b | balrog | ch->status &= ~SYNC; |
228 | b4e3104b | balrog | s->run_count --; |
229 | b4e3104b | balrog | } |
230 | b4e3104b | balrog | |
231 | b4e3104b | balrog | if (!s->run_count)
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232 | b4e3104b | balrog | qemu_del_timer(s->tm); |
233 | b4e3104b | balrog | } |
234 | b4e3104b | balrog | |
235 | b4e3104b | balrog | static void omap_dma_enable_channel(struct omap_dma_s *s, |
236 | b4e3104b | balrog | struct omap_dma_channel_s *ch)
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237 | b4e3104b | balrog | { |
238 | b4e3104b | balrog | if (!ch->enable) {
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239 | b4e3104b | balrog | ch->enable = 1;
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240 | b4e3104b | balrog | ch->waiting_end_prog = 0;
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241 | b4e3104b | balrog | omap_dma_channel_load(s, ch); |
242 | 827df9f3 | balrog | /* TODO: theoretically if ch->sync && ch->prefetch &&
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243 | 827df9f3 | balrog | * !s->drq[ch->sync], we should also activate and fetch from source
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244 | 827df9f3 | balrog | * and then stall until signalled. */
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245 | b4e3104b | balrog | if ((!ch->sync) || (s->drq & (1 << ch->sync))) |
246 | b4e3104b | balrog | omap_dma_activate_channel(s, ch); |
247 | b4e3104b | balrog | } |
248 | b4e3104b | balrog | } |
249 | b4e3104b | balrog | |
250 | b4e3104b | balrog | static void omap_dma_disable_channel(struct omap_dma_s *s, |
251 | b4e3104b | balrog | struct omap_dma_channel_s *ch)
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252 | b4e3104b | balrog | { |
253 | b4e3104b | balrog | if (ch->enable) {
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254 | b4e3104b | balrog | ch->enable = 0;
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255 | b4e3104b | balrog | /* Discard any pending request */
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256 | b4e3104b | balrog | ch->pending_request = 0;
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257 | b4e3104b | balrog | omap_dma_deactivate_channel(s, ch); |
258 | b4e3104b | balrog | } |
259 | b4e3104b | balrog | } |
260 | b4e3104b | balrog | |
261 | b4e3104b | balrog | static void omap_dma_channel_end_prog(struct omap_dma_s *s, |
262 | b4e3104b | balrog | struct omap_dma_channel_s *ch)
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263 | b4e3104b | balrog | { |
264 | b4e3104b | balrog | if (ch->waiting_end_prog) {
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265 | b4e3104b | balrog | ch->waiting_end_prog = 0;
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266 | b4e3104b | balrog | if (!ch->sync || ch->pending_request) {
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267 | b4e3104b | balrog | ch->pending_request = 0;
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268 | b4e3104b | balrog | omap_dma_activate_channel(s, ch); |
269 | b4e3104b | balrog | } |
270 | b4e3104b | balrog | } |
271 | b4e3104b | balrog | } |
272 | b4e3104b | balrog | |
273 | 827df9f3 | balrog | static void omap_dma_interrupts_3_1_update(struct omap_dma_s *s) |
274 | 827df9f3 | balrog | { |
275 | 827df9f3 | balrog | struct omap_dma_channel_s *ch = s->ch;
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276 | 827df9f3 | balrog | |
277 | 827df9f3 | balrog | /* First three interrupts are shared between two channels each. */
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278 | 827df9f3 | balrog | if (ch[0].status | ch[6].status) |
279 | 827df9f3 | balrog | qemu_irq_raise(ch[0].irq);
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280 | 827df9f3 | balrog | if (ch[1].status | ch[7].status) |
281 | 827df9f3 | balrog | qemu_irq_raise(ch[1].irq);
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282 | 827df9f3 | balrog | if (ch[2].status | ch[8].status) |
283 | 827df9f3 | balrog | qemu_irq_raise(ch[2].irq);
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284 | 827df9f3 | balrog | if (ch[3].status) |
285 | 827df9f3 | balrog | qemu_irq_raise(ch[3].irq);
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286 | 827df9f3 | balrog | if (ch[4].status) |
287 | 827df9f3 | balrog | qemu_irq_raise(ch[4].irq);
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288 | 827df9f3 | balrog | if (ch[5].status) |
289 | 827df9f3 | balrog | qemu_irq_raise(ch[5].irq);
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290 | 827df9f3 | balrog | } |
291 | 827df9f3 | balrog | |
292 | 827df9f3 | balrog | static void omap_dma_interrupts_3_2_update(struct omap_dma_s *s) |
293 | 827df9f3 | balrog | { |
294 | 827df9f3 | balrog | struct omap_dma_channel_s *ch = s->ch;
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295 | 827df9f3 | balrog | int i;
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296 | 827df9f3 | balrog | |
297 | 827df9f3 | balrog | for (i = s->chans; i; ch ++, i --)
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298 | 827df9f3 | balrog | if (ch->status)
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299 | 827df9f3 | balrog | qemu_irq_raise(ch->irq); |
300 | 827df9f3 | balrog | } |
301 | 827df9f3 | balrog | |
302 | b4e3104b | balrog | static void omap_dma_enable_3_1_mapping(struct omap_dma_s *s) |
303 | b4e3104b | balrog | { |
304 | b4e3104b | balrog | s->omap_3_1_mapping_disabled = 0;
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305 | b4e3104b | balrog | s->chans = 9;
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306 | 827df9f3 | balrog | s->intr_update = omap_dma_interrupts_3_1_update; |
307 | b4e3104b | balrog | } |
308 | b4e3104b | balrog | |
309 | b4e3104b | balrog | static void omap_dma_disable_3_1_mapping(struct omap_dma_s *s) |
310 | b4e3104b | balrog | { |
311 | b4e3104b | balrog | s->omap_3_1_mapping_disabled = 1;
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312 | b4e3104b | balrog | s->chans = 16;
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313 | 827df9f3 | balrog | s->intr_update = omap_dma_interrupts_3_2_update; |
314 | b4e3104b | balrog | } |
315 | b4e3104b | balrog | |
316 | b4e3104b | balrog | static void omap_dma_process_request(struct omap_dma_s *s, int request) |
317 | b4e3104b | balrog | { |
318 | b4e3104b | balrog | int channel;
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319 | b4e3104b | balrog | int drop_event = 0; |
320 | b4e3104b | balrog | struct omap_dma_channel_s *ch = s->ch;
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321 | b4e3104b | balrog | |
322 | b4e3104b | balrog | for (channel = 0; channel < s->chans; channel ++, ch ++) { |
323 | b4e3104b | balrog | if (ch->enable && ch->sync == request) {
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324 | b4e3104b | balrog | if (!ch->active)
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325 | b4e3104b | balrog | omap_dma_activate_channel(s, ch); |
326 | b4e3104b | balrog | else if (!ch->pending_request) |
327 | b4e3104b | balrog | ch->pending_request = 1;
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328 | b4e3104b | balrog | else {
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329 | b4e3104b | balrog | /* Request collision */
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330 | b4e3104b | balrog | /* Second request received while processing other request */
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331 | b4e3104b | balrog | ch->status |= EVENT_DROP_INTR; |
332 | b4e3104b | balrog | drop_event = 1;
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333 | b4e3104b | balrog | } |
334 | b4e3104b | balrog | } |
335 | b4e3104b | balrog | } |
336 | b4e3104b | balrog | |
337 | b4e3104b | balrog | if (drop_event)
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338 | b4e3104b | balrog | omap_dma_interrupts_update(s); |
339 | b4e3104b | balrog | } |
340 | b4e3104b | balrog | |
341 | b4e3104b | balrog | static void omap_dma_channel_run(struct omap_dma_s *s) |
342 | b4e3104b | balrog | { |
343 | b4e3104b | balrog | int n = s->chans;
|
344 | b4e3104b | balrog | uint16_t status; |
345 | b4e3104b | balrog | uint8_t value[4];
|
346 | b4e3104b | balrog | struct omap_dma_port_if_s *src_p, *dest_p;
|
347 | b4e3104b | balrog | struct omap_dma_reg_set_s *a;
|
348 | b4e3104b | balrog | struct omap_dma_channel_s *ch;
|
349 | b4e3104b | balrog | |
350 | b4e3104b | balrog | for (ch = s->ch; n; n --, ch ++) {
|
351 | b4e3104b | balrog | if (!ch->active)
|
352 | b4e3104b | balrog | continue;
|
353 | b4e3104b | balrog | |
354 | b4e3104b | balrog | a = &ch->active_set; |
355 | b4e3104b | balrog | |
356 | b4e3104b | balrog | src_p = &s->mpu->port[ch->port[0]];
|
357 | b4e3104b | balrog | dest_p = &s->mpu->port[ch->port[1]];
|
358 | b4e3104b | balrog | if ((!ch->constant_fill && !src_p->addr_valid(s->mpu, a->src)) ||
|
359 | b4e3104b | balrog | (!dest_p->addr_valid(s->mpu, a->dest))) { |
360 | b4e3104b | balrog | #if 0
|
361 | b4e3104b | balrog | /* Bus time-out */
|
362 | b4e3104b | balrog | if (ch->interrupts & TIMEOUT_INTR)
|
363 | b4e3104b | balrog | ch->status |= TIMEOUT_INTR;
|
364 | b4e3104b | balrog | omap_dma_deactivate_channel(s, ch);
|
365 | b4e3104b | balrog | continue;
|
366 | b4e3104b | balrog | #endif
|
367 | b4e3104b | balrog | printf("%s: Bus time-out in DMA%i operation\n",
|
368 | b4e3104b | balrog | __FUNCTION__, s->chans - n); |
369 | b4e3104b | balrog | } |
370 | b4e3104b | balrog | |
371 | b4e3104b | balrog | status = ch->status; |
372 | b4e3104b | balrog | while (status == ch->status && ch->active) {
|
373 | b4e3104b | balrog | /* Transfer a single element */
|
374 | b4e3104b | balrog | /* FIXME: check the endianness */
|
375 | b4e3104b | balrog | if (!ch->constant_fill)
|
376 | b4e3104b | balrog | cpu_physical_memory_read(a->src, value, ch->data_type); |
377 | b4e3104b | balrog | else
|
378 | b4e3104b | balrog | *(uint32_t *) value = ch->color; |
379 | b4e3104b | balrog | |
380 | b4e3104b | balrog | if (!ch->transparent_copy ||
|
381 | b4e3104b | balrog | *(uint32_t *) value != ch->color) |
382 | b4e3104b | balrog | cpu_physical_memory_write(a->dest, value, ch->data_type); |
383 | b4e3104b | balrog | |
384 | b4e3104b | balrog | a->src += a->elem_delta[0];
|
385 | b4e3104b | balrog | a->dest += a->elem_delta[1];
|
386 | b4e3104b | balrog | a->element ++; |
387 | b4e3104b | balrog | |
388 | b4e3104b | balrog | /* If the channel is element synchronized, deactivate it */
|
389 | b4e3104b | balrog | if (ch->sync && !ch->fs && !ch->bs)
|
390 | b4e3104b | balrog | omap_dma_deactivate_channel(s, ch); |
391 | b4e3104b | balrog | |
392 | b4e3104b | balrog | /* If it is the last frame, set the LAST_FRAME interrupt */
|
393 | b4e3104b | balrog | if (a->element == 1 && a->frame == a->frames - 1) |
394 | b4e3104b | balrog | if (ch->interrupts & LAST_FRAME_INTR)
|
395 | b4e3104b | balrog | ch->status |= LAST_FRAME_INTR; |
396 | b4e3104b | balrog | |
397 | b4e3104b | balrog | /* If the half of the frame was reached, set the HALF_FRAME
|
398 | b4e3104b | balrog | interrupt */
|
399 | b4e3104b | balrog | if (a->element == (a->elements >> 1)) |
400 | b4e3104b | balrog | if (ch->interrupts & HALF_FRAME_INTR)
|
401 | b4e3104b | balrog | ch->status |= HALF_FRAME_INTR; |
402 | b4e3104b | balrog | |
403 | 827df9f3 | balrog | if (ch->fs && ch->bs) {
|
404 | 827df9f3 | balrog | a->pck_element ++; |
405 | 827df9f3 | balrog | /* Check if a full packet has beed transferred. */
|
406 | 827df9f3 | balrog | if (a->pck_element == a->pck_elements) {
|
407 | 827df9f3 | balrog | a->pck_element = 0;
|
408 | 827df9f3 | balrog | |
409 | 827df9f3 | balrog | /* Set the END_PKT interrupt */
|
410 | 827df9f3 | balrog | if ((ch->interrupts & END_PKT_INTR) && !ch->src_sync)
|
411 | 827df9f3 | balrog | ch->status |= END_PKT_INTR; |
412 | 827df9f3 | balrog | |
413 | 827df9f3 | balrog | /* If the channel is packet-synchronized, deactivate it */
|
414 | 827df9f3 | balrog | if (ch->sync)
|
415 | 827df9f3 | balrog | omap_dma_deactivate_channel(s, ch); |
416 | 827df9f3 | balrog | } |
417 | 827df9f3 | balrog | } |
418 | 827df9f3 | balrog | |
419 | b4e3104b | balrog | if (a->element == a->elements) {
|
420 | b4e3104b | balrog | /* End of Frame */
|
421 | b4e3104b | balrog | a->element = 0;
|
422 | b4e3104b | balrog | a->src += a->frame_delta[0];
|
423 | b4e3104b | balrog | a->dest += a->frame_delta[1];
|
424 | b4e3104b | balrog | a->frame ++; |
425 | b4e3104b | balrog | |
426 | b4e3104b | balrog | /* If the channel is frame synchronized, deactivate it */
|
427 | 827df9f3 | balrog | if (ch->sync && ch->fs && !ch->bs)
|
428 | b4e3104b | balrog | omap_dma_deactivate_channel(s, ch); |
429 | b4e3104b | balrog | |
430 | b4e3104b | balrog | /* If the channel is async, update cpc */
|
431 | b4e3104b | balrog | if (!ch->sync)
|
432 | b4e3104b | balrog | ch->cpc = a->dest & 0xffff;
|
433 | b4e3104b | balrog | |
434 | b4e3104b | balrog | /* Set the END_FRAME interrupt */
|
435 | b4e3104b | balrog | if (ch->interrupts & END_FRAME_INTR)
|
436 | b4e3104b | balrog | ch->status |= END_FRAME_INTR; |
437 | b4e3104b | balrog | |
438 | b4e3104b | balrog | if (a->frame == a->frames) {
|
439 | b4e3104b | balrog | /* End of Block */
|
440 | b4e3104b | balrog | /* Disable the channel */
|
441 | b4e3104b | balrog | |
442 | b4e3104b | balrog | if (ch->omap_3_1_compatible_disable) {
|
443 | b4e3104b | balrog | omap_dma_disable_channel(s, ch); |
444 | b4e3104b | balrog | if (ch->link_enabled)
|
445 | b4e3104b | balrog | omap_dma_enable_channel(s, |
446 | b4e3104b | balrog | &s->ch[ch->link_next_ch]); |
447 | b4e3104b | balrog | } else {
|
448 | b4e3104b | balrog | if (!ch->auto_init)
|
449 | b4e3104b | balrog | omap_dma_disable_channel(s, ch); |
450 | b4e3104b | balrog | else if (ch->repeat || ch->end_prog) |
451 | b4e3104b | balrog | omap_dma_channel_load(s, ch); |
452 | b4e3104b | balrog | else {
|
453 | b4e3104b | balrog | ch->waiting_end_prog = 1;
|
454 | b4e3104b | balrog | omap_dma_deactivate_channel(s, ch); |
455 | b4e3104b | balrog | } |
456 | b4e3104b | balrog | } |
457 | b4e3104b | balrog | |
458 | b4e3104b | balrog | if (ch->interrupts & END_BLOCK_INTR)
|
459 | b4e3104b | balrog | ch->status |= END_BLOCK_INTR; |
460 | b4e3104b | balrog | } |
461 | b4e3104b | balrog | } |
462 | b4e3104b | balrog | } |
463 | b4e3104b | balrog | } |
464 | b4e3104b | balrog | |
465 | b4e3104b | balrog | omap_dma_interrupts_update(s); |
466 | b4e3104b | balrog | if (s->run_count && s->delay)
|
467 | b4e3104b | balrog | qemu_mod_timer(s->tm, qemu_get_clock(vm_clock) + s->delay); |
468 | b4e3104b | balrog | } |
469 | b4e3104b | balrog | |
470 | b4e3104b | balrog | void omap_dma_reset(struct omap_dma_s *s) |
471 | b4e3104b | balrog | { |
472 | b4e3104b | balrog | int i;
|
473 | b4e3104b | balrog | |
474 | b4e3104b | balrog | qemu_del_timer(s->tm); |
475 | 827df9f3 | balrog | if (s->model < omap_dma_4)
|
476 | 827df9f3 | balrog | s->gcr = 0x0004;
|
477 | 827df9f3 | balrog | else
|
478 | 827df9f3 | balrog | s->gcr = 0x00010010;
|
479 | 827df9f3 | balrog | s->ocp = 0x00000000;
|
480 | 827df9f3 | balrog | memset(&s->irqstat, 0, sizeof(s->irqstat)); |
481 | 827df9f3 | balrog | memset(&s->irqen, 0, sizeof(s->irqen)); |
482 | b4e3104b | balrog | s->drq = 0x00000000;
|
483 | b4e3104b | balrog | s->run_count = 0;
|
484 | b4e3104b | balrog | s->lcd_ch.src = emiff; |
485 | b4e3104b | balrog | s->lcd_ch.condition = 0;
|
486 | b4e3104b | balrog | s->lcd_ch.interrupts = 0;
|
487 | b4e3104b | balrog | s->lcd_ch.dual = 0;
|
488 | 827df9f3 | balrog | if (s->model < omap_dma_4)
|
489 | 827df9f3 | balrog | omap_dma_enable_3_1_mapping(s); |
490 | b4e3104b | balrog | for (i = 0; i < s->chans; i ++) { |
491 | 827df9f3 | balrog | s->ch[i].suspend = 0;
|
492 | 827df9f3 | balrog | s->ch[i].prefetch = 0;
|
493 | 827df9f3 | balrog | s->ch[i].buf_disable = 0;
|
494 | 827df9f3 | balrog | s->ch[i].src_sync = 0;
|
495 | b4e3104b | balrog | memset(&s->ch[i].burst, 0, sizeof(s->ch[i].burst)); |
496 | b4e3104b | balrog | memset(&s->ch[i].port, 0, sizeof(s->ch[i].port)); |
497 | b4e3104b | balrog | memset(&s->ch[i].mode, 0, sizeof(s->ch[i].mode)); |
498 | b4e3104b | balrog | memset(&s->ch[i].frame_index, 0, sizeof(s->ch[i].frame_index)); |
499 | b4e3104b | balrog | memset(&s->ch[i].element_index, 0, sizeof(s->ch[i].element_index)); |
500 | 827df9f3 | balrog | memset(&s->ch[i].endian, 0, sizeof(s->ch[i].endian)); |
501 | 827df9f3 | balrog | memset(&s->ch[i].endian_lock, 0, sizeof(s->ch[i].endian_lock)); |
502 | 827df9f3 | balrog | memset(&s->ch[i].translate, 0, sizeof(s->ch[i].translate)); |
503 | 827df9f3 | balrog | s->ch[i].write_mode = 0;
|
504 | 827df9f3 | balrog | s->ch[i].data_type = 0;
|
505 | 827df9f3 | balrog | s->ch[i].transparent_copy = 0;
|
506 | 827df9f3 | balrog | s->ch[i].constant_fill = 0;
|
507 | 827df9f3 | balrog | s->ch[i].color = 0x00000000;
|
508 | 827df9f3 | balrog | s->ch[i].end_prog = 0;
|
509 | 827df9f3 | balrog | s->ch[i].repeat = 0;
|
510 | 827df9f3 | balrog | s->ch[i].auto_init = 0;
|
511 | 827df9f3 | balrog | s->ch[i].link_enabled = 0;
|
512 | 827df9f3 | balrog | if (s->model < omap_dma_4)
|
513 | 827df9f3 | balrog | s->ch[i].interrupts = 0x0003;
|
514 | 827df9f3 | balrog | else
|
515 | 827df9f3 | balrog | s->ch[i].interrupts = 0x0000;
|
516 | 827df9f3 | balrog | s->ch[i].status = 0;
|
517 | 827df9f3 | balrog | s->ch[i].cstatus = 0;
|
518 | 827df9f3 | balrog | s->ch[i].active = 0;
|
519 | 827df9f3 | balrog | s->ch[i].enable = 0;
|
520 | 827df9f3 | balrog | s->ch[i].sync = 0;
|
521 | 827df9f3 | balrog | s->ch[i].pending_request = 0;
|
522 | 827df9f3 | balrog | s->ch[i].waiting_end_prog = 0;
|
523 | 827df9f3 | balrog | s->ch[i].cpc = 0x0000;
|
524 | 827df9f3 | balrog | s->ch[i].fs = 0;
|
525 | 827df9f3 | balrog | s->ch[i].bs = 0;
|
526 | 827df9f3 | balrog | s->ch[i].omap_3_1_compatible_disable = 0;
|
527 | b4e3104b | balrog | memset(&s->ch[i].active_set, 0, sizeof(s->ch[i].active_set)); |
528 | 827df9f3 | balrog | s->ch[i].priority = 0;
|
529 | 827df9f3 | balrog | s->ch[i].interleave_disabled = 0;
|
530 | 827df9f3 | balrog | s->ch[i].type = 0;
|
531 | b4e3104b | balrog | } |
532 | b4e3104b | balrog | } |
533 | b4e3104b | balrog | |
534 | b4e3104b | balrog | static int omap_dma_ch_reg_read(struct omap_dma_s *s, |
535 | b4e3104b | balrog | struct omap_dma_channel_s *ch, int reg, uint16_t *value) |
536 | b4e3104b | balrog | { |
537 | b4e3104b | balrog | switch (reg) {
|
538 | b4e3104b | balrog | case 0x00: /* SYS_DMA_CSDP_CH0 */ |
539 | b4e3104b | balrog | *value = (ch->burst[1] << 14) | |
540 | b4e3104b | balrog | (ch->pack[1] << 13) | |
541 | b4e3104b | balrog | (ch->port[1] << 9) | |
542 | b4e3104b | balrog | (ch->burst[0] << 7) | |
543 | b4e3104b | balrog | (ch->pack[0] << 6) | |
544 | b4e3104b | balrog | (ch->port[0] << 2) | |
545 | b4e3104b | balrog | (ch->data_type >> 1);
|
546 | b4e3104b | balrog | break;
|
547 | b4e3104b | balrog | |
548 | b4e3104b | balrog | case 0x02: /* SYS_DMA_CCR_CH0 */ |
549 | 827df9f3 | balrog | if (s->model <= omap_dma_3_1)
|
550 | b4e3104b | balrog | *value = 0 << 10; /* FIFO_FLUSH reads as 0 */ |
551 | b4e3104b | balrog | else
|
552 | b4e3104b | balrog | *value = ch->omap_3_1_compatible_disable << 10;
|
553 | b4e3104b | balrog | *value |= (ch->mode[1] << 14) | |
554 | b4e3104b | balrog | (ch->mode[0] << 12) | |
555 | b4e3104b | balrog | (ch->end_prog << 11) |
|
556 | b4e3104b | balrog | (ch->repeat << 9) |
|
557 | b4e3104b | balrog | (ch->auto_init << 8) |
|
558 | b4e3104b | balrog | (ch->enable << 7) |
|
559 | b4e3104b | balrog | (ch->priority << 6) |
|
560 | b4e3104b | balrog | (ch->fs << 5) | ch->sync;
|
561 | b4e3104b | balrog | break;
|
562 | b4e3104b | balrog | |
563 | b4e3104b | balrog | case 0x04: /* SYS_DMA_CICR_CH0 */ |
564 | b4e3104b | balrog | *value = ch->interrupts; |
565 | b4e3104b | balrog | break;
|
566 | b4e3104b | balrog | |
567 | b4e3104b | balrog | case 0x06: /* SYS_DMA_CSR_CH0 */ |
568 | b4e3104b | balrog | *value = ch->status; |
569 | b4e3104b | balrog | ch->status &= SYNC; |
570 | b4e3104b | balrog | if (!ch->omap_3_1_compatible_disable && ch->sibling) {
|
571 | b4e3104b | balrog | *value |= (ch->sibling->status & 0x3f) << 6; |
572 | b4e3104b | balrog | ch->sibling->status &= SYNC; |
573 | b4e3104b | balrog | } |
574 | b4e3104b | balrog | qemu_irq_lower(ch->irq); |
575 | b4e3104b | balrog | break;
|
576 | b4e3104b | balrog | |
577 | b4e3104b | balrog | case 0x08: /* SYS_DMA_CSSA_L_CH0 */ |
578 | b4e3104b | balrog | *value = ch->addr[0] & 0x0000ffff; |
579 | b4e3104b | balrog | break;
|
580 | b4e3104b | balrog | |
581 | b4e3104b | balrog | case 0x0a: /* SYS_DMA_CSSA_U_CH0 */ |
582 | b4e3104b | balrog | *value = ch->addr[0] >> 16; |
583 | b4e3104b | balrog | break;
|
584 | b4e3104b | balrog | |
585 | b4e3104b | balrog | case 0x0c: /* SYS_DMA_CDSA_L_CH0 */ |
586 | b4e3104b | balrog | *value = ch->addr[1] & 0x0000ffff; |
587 | b4e3104b | balrog | break;
|
588 | b4e3104b | balrog | |
589 | b4e3104b | balrog | case 0x0e: /* SYS_DMA_CDSA_U_CH0 */ |
590 | b4e3104b | balrog | *value = ch->addr[1] >> 16; |
591 | b4e3104b | balrog | break;
|
592 | b4e3104b | balrog | |
593 | b4e3104b | balrog | case 0x10: /* SYS_DMA_CEN_CH0 */ |
594 | b4e3104b | balrog | *value = ch->elements; |
595 | b4e3104b | balrog | break;
|
596 | b4e3104b | balrog | |
597 | b4e3104b | balrog | case 0x12: /* SYS_DMA_CFN_CH0 */ |
598 | b4e3104b | balrog | *value = ch->frames; |
599 | b4e3104b | balrog | break;
|
600 | b4e3104b | balrog | |
601 | b4e3104b | balrog | case 0x14: /* SYS_DMA_CFI_CH0 */ |
602 | b4e3104b | balrog | *value = ch->frame_index[0];
|
603 | b4e3104b | balrog | break;
|
604 | b4e3104b | balrog | |
605 | b4e3104b | balrog | case 0x16: /* SYS_DMA_CEI_CH0 */ |
606 | b4e3104b | balrog | *value = ch->element_index[0];
|
607 | b4e3104b | balrog | break;
|
608 | b4e3104b | balrog | |
609 | b4e3104b | balrog | case 0x18: /* SYS_DMA_CPC_CH0 or DMA_CSAC */ |
610 | b4e3104b | balrog | if (ch->omap_3_1_compatible_disable)
|
611 | b4e3104b | balrog | *value = ch->active_set.src & 0xffff; /* CSAC */ |
612 | b4e3104b | balrog | else
|
613 | b4e3104b | balrog | *value = ch->cpc; |
614 | b4e3104b | balrog | break;
|
615 | b4e3104b | balrog | |
616 | b4e3104b | balrog | case 0x1a: /* DMA_CDAC */ |
617 | b4e3104b | balrog | *value = ch->active_set.dest & 0xffff; /* CDAC */ |
618 | b4e3104b | balrog | break;
|
619 | b4e3104b | balrog | |
620 | b4e3104b | balrog | case 0x1c: /* DMA_CDEI */ |
621 | b4e3104b | balrog | *value = ch->element_index[1];
|
622 | b4e3104b | balrog | break;
|
623 | b4e3104b | balrog | |
624 | b4e3104b | balrog | case 0x1e: /* DMA_CDFI */ |
625 | b4e3104b | balrog | *value = ch->frame_index[1];
|
626 | b4e3104b | balrog | break;
|
627 | b4e3104b | balrog | |
628 | b4e3104b | balrog | case 0x20: /* DMA_COLOR_L */ |
629 | b4e3104b | balrog | *value = ch->color & 0xffff;
|
630 | b4e3104b | balrog | break;
|
631 | b4e3104b | balrog | |
632 | b4e3104b | balrog | case 0x22: /* DMA_COLOR_U */ |
633 | b4e3104b | balrog | *value = ch->color >> 16;
|
634 | b4e3104b | balrog | break;
|
635 | b4e3104b | balrog | |
636 | b4e3104b | balrog | case 0x24: /* DMA_CCR2 */ |
637 | b4e3104b | balrog | *value = (ch->bs << 2) |
|
638 | b4e3104b | balrog | (ch->transparent_copy << 1) |
|
639 | b4e3104b | balrog | ch->constant_fill; |
640 | b4e3104b | balrog | break;
|
641 | b4e3104b | balrog | |
642 | b4e3104b | balrog | case 0x28: /* DMA_CLNK_CTRL */ |
643 | b4e3104b | balrog | *value = (ch->link_enabled << 15) |
|
644 | b4e3104b | balrog | (ch->link_next_ch & 0xf);
|
645 | b4e3104b | balrog | break;
|
646 | b4e3104b | balrog | |
647 | b4e3104b | balrog | case 0x2a: /* DMA_LCH_CTRL */ |
648 | b4e3104b | balrog | *value = (ch->interleave_disabled << 15) |
|
649 | b4e3104b | balrog | ch->type; |
650 | b4e3104b | balrog | break;
|
651 | b4e3104b | balrog | |
652 | b4e3104b | balrog | default:
|
653 | b4e3104b | balrog | return 1; |
654 | b4e3104b | balrog | } |
655 | b4e3104b | balrog | return 0; |
656 | b4e3104b | balrog | } |
657 | b4e3104b | balrog | |
658 | b4e3104b | balrog | static int omap_dma_ch_reg_write(struct omap_dma_s *s, |
659 | b4e3104b | balrog | struct omap_dma_channel_s *ch, int reg, uint16_t value) |
660 | b4e3104b | balrog | { |
661 | b4e3104b | balrog | switch (reg) {
|
662 | b4e3104b | balrog | case 0x00: /* SYS_DMA_CSDP_CH0 */ |
663 | b4e3104b | balrog | ch->burst[1] = (value & 0xc000) >> 14; |
664 | b4e3104b | balrog | ch->pack[1] = (value & 0x2000) >> 13; |
665 | b4e3104b | balrog | ch->port[1] = (enum omap_dma_port) ((value & 0x1e00) >> 9); |
666 | b4e3104b | balrog | ch->burst[0] = (value & 0x0180) >> 7; |
667 | b4e3104b | balrog | ch->pack[0] = (value & 0x0040) >> 6; |
668 | b4e3104b | balrog | ch->port[0] = (enum omap_dma_port) ((value & 0x003c) >> 2); |
669 | 827df9f3 | balrog | ch->data_type = 1 << (value & 3); |
670 | 827df9f3 | balrog | if (ch->port[0] >= __omap_dma_port_last) |
671 | b4e3104b | balrog | printf("%s: invalid DMA port %i\n", __FUNCTION__,
|
672 | b4e3104b | balrog | ch->port[0]);
|
673 | 827df9f3 | balrog | if (ch->port[1] >= __omap_dma_port_last) |
674 | b4e3104b | balrog | printf("%s: invalid DMA port %i\n", __FUNCTION__,
|
675 | b4e3104b | balrog | ch->port[1]);
|
676 | b4e3104b | balrog | if ((value & 3) == 3) |
677 | b4e3104b | balrog | printf("%s: bad data_type for DMA channel\n", __FUNCTION__);
|
678 | b4e3104b | balrog | break;
|
679 | b4e3104b | balrog | |
680 | b4e3104b | balrog | case 0x02: /* SYS_DMA_CCR_CH0 */ |
681 | b4e3104b | balrog | ch->mode[1] = (omap_dma_addressing_t) ((value & 0xc000) >> 14); |
682 | b4e3104b | balrog | ch->mode[0] = (omap_dma_addressing_t) ((value & 0x3000) >> 12); |
683 | b4e3104b | balrog | ch->end_prog = (value & 0x0800) >> 11; |
684 | 827df9f3 | balrog | if (s->model >= omap_dma_3_2)
|
685 | b4e3104b | balrog | ch->omap_3_1_compatible_disable = (value >> 10) & 0x1; |
686 | b4e3104b | balrog | ch->repeat = (value & 0x0200) >> 9; |
687 | b4e3104b | balrog | ch->auto_init = (value & 0x0100) >> 8; |
688 | b4e3104b | balrog | ch->priority = (value & 0x0040) >> 6; |
689 | b4e3104b | balrog | ch->fs = (value & 0x0020) >> 5; |
690 | b4e3104b | balrog | ch->sync = value & 0x001f;
|
691 | b4e3104b | balrog | |
692 | b4e3104b | balrog | if (value & 0x0080) |
693 | b4e3104b | balrog | omap_dma_enable_channel(s, ch); |
694 | b4e3104b | balrog | else
|
695 | b4e3104b | balrog | omap_dma_disable_channel(s, ch); |
696 | b4e3104b | balrog | |
697 | b4e3104b | balrog | if (ch->end_prog)
|
698 | b4e3104b | balrog | omap_dma_channel_end_prog(s, ch); |
699 | b4e3104b | balrog | |
700 | b4e3104b | balrog | break;
|
701 | b4e3104b | balrog | |
702 | b4e3104b | balrog | case 0x04: /* SYS_DMA_CICR_CH0 */ |
703 | 827df9f3 | balrog | ch->interrupts = value & 0x3f;
|
704 | b4e3104b | balrog | break;
|
705 | b4e3104b | balrog | |
706 | b4e3104b | balrog | case 0x06: /* SYS_DMA_CSR_CH0 */ |
707 | b4e3104b | balrog | OMAP_RO_REG((target_phys_addr_t) reg); |
708 | b4e3104b | balrog | break;
|
709 | b4e3104b | balrog | |
710 | b4e3104b | balrog | case 0x08: /* SYS_DMA_CSSA_L_CH0 */ |
711 | b4e3104b | balrog | ch->addr[0] &= 0xffff0000; |
712 | b4e3104b | balrog | ch->addr[0] |= value;
|
713 | b4e3104b | balrog | break;
|
714 | b4e3104b | balrog | |
715 | b4e3104b | balrog | case 0x0a: /* SYS_DMA_CSSA_U_CH0 */ |
716 | b4e3104b | balrog | ch->addr[0] &= 0x0000ffff; |
717 | b4e3104b | balrog | ch->addr[0] |= (uint32_t) value << 16; |
718 | b4e3104b | balrog | break;
|
719 | b4e3104b | balrog | |
720 | b4e3104b | balrog | case 0x0c: /* SYS_DMA_CDSA_L_CH0 */ |
721 | b4e3104b | balrog | ch->addr[1] &= 0xffff0000; |
722 | b4e3104b | balrog | ch->addr[1] |= value;
|
723 | b4e3104b | balrog | break;
|
724 | b4e3104b | balrog | |
725 | b4e3104b | balrog | case 0x0e: /* SYS_DMA_CDSA_U_CH0 */ |
726 | b4e3104b | balrog | ch->addr[1] &= 0x0000ffff; |
727 | b4e3104b | balrog | ch->addr[1] |= (uint32_t) value << 16; |
728 | b4e3104b | balrog | break;
|
729 | b4e3104b | balrog | |
730 | b4e3104b | balrog | case 0x10: /* SYS_DMA_CEN_CH0 */ |
731 | b4e3104b | balrog | ch->elements = value; |
732 | b4e3104b | balrog | break;
|
733 | b4e3104b | balrog | |
734 | b4e3104b | balrog | case 0x12: /* SYS_DMA_CFN_CH0 */ |
735 | b4e3104b | balrog | ch->frames = value; |
736 | b4e3104b | balrog | break;
|
737 | b4e3104b | balrog | |
738 | b4e3104b | balrog | case 0x14: /* SYS_DMA_CFI_CH0 */ |
739 | b4e3104b | balrog | ch->frame_index[0] = (int16_t) value;
|
740 | b4e3104b | balrog | break;
|
741 | b4e3104b | balrog | |
742 | b4e3104b | balrog | case 0x16: /* SYS_DMA_CEI_CH0 */ |
743 | b4e3104b | balrog | ch->element_index[0] = (int16_t) value;
|
744 | b4e3104b | balrog | break;
|
745 | b4e3104b | balrog | |
746 | b4e3104b | balrog | case 0x18: /* SYS_DMA_CPC_CH0 or DMA_CSAC */ |
747 | b4e3104b | balrog | OMAP_RO_REG((target_phys_addr_t) reg); |
748 | b4e3104b | balrog | break;
|
749 | b4e3104b | balrog | |
750 | b4e3104b | balrog | case 0x1c: /* DMA_CDEI */ |
751 | b4e3104b | balrog | ch->element_index[1] = (int16_t) value;
|
752 | b4e3104b | balrog | break;
|
753 | b4e3104b | balrog | |
754 | b4e3104b | balrog | case 0x1e: /* DMA_CDFI */ |
755 | b4e3104b | balrog | ch->frame_index[1] = (int16_t) value;
|
756 | b4e3104b | balrog | break;
|
757 | b4e3104b | balrog | |
758 | b4e3104b | balrog | case 0x20: /* DMA_COLOR_L */ |
759 | b4e3104b | balrog | ch->color &= 0xffff0000;
|
760 | b4e3104b | balrog | ch->color |= value; |
761 | b4e3104b | balrog | break;
|
762 | b4e3104b | balrog | |
763 | b4e3104b | balrog | case 0x22: /* DMA_COLOR_U */ |
764 | b4e3104b | balrog | ch->color &= 0xffff;
|
765 | b4e3104b | balrog | ch->color |= value << 16;
|
766 | b4e3104b | balrog | break;
|
767 | b4e3104b | balrog | |
768 | b4e3104b | balrog | case 0x24: /* DMA_CCR2 */ |
769 | 827df9f3 | balrog | ch->bs = (value >> 2) & 0x1; |
770 | b4e3104b | balrog | ch->transparent_copy = (value >> 1) & 0x1; |
771 | b4e3104b | balrog | ch->constant_fill = value & 0x1;
|
772 | b4e3104b | balrog | break;
|
773 | b4e3104b | balrog | |
774 | b4e3104b | balrog | case 0x28: /* DMA_CLNK_CTRL */ |
775 | b4e3104b | balrog | ch->link_enabled = (value >> 15) & 0x1; |
776 | b4e3104b | balrog | if (value & (1 << 14)) { /* Stop_Lnk */ |
777 | b4e3104b | balrog | ch->link_enabled = 0;
|
778 | b4e3104b | balrog | omap_dma_disable_channel(s, ch); |
779 | b4e3104b | balrog | } |
780 | b4e3104b | balrog | ch->link_next_ch = value & 0x1f;
|
781 | b4e3104b | balrog | break;
|
782 | b4e3104b | balrog | |
783 | b4e3104b | balrog | case 0x2a: /* DMA_LCH_CTRL */ |
784 | b4e3104b | balrog | ch->interleave_disabled = (value >> 15) & 0x1; |
785 | b4e3104b | balrog | ch->type = value & 0xf;
|
786 | b4e3104b | balrog | break;
|
787 | b4e3104b | balrog | |
788 | b4e3104b | balrog | default:
|
789 | b4e3104b | balrog | return 1; |
790 | b4e3104b | balrog | } |
791 | b4e3104b | balrog | return 0; |
792 | b4e3104b | balrog | } |
793 | b4e3104b | balrog | |
794 | b4e3104b | balrog | static int omap_dma_3_2_lcd_write(struct omap_dma_lcd_channel_s *s, int offset, |
795 | b4e3104b | balrog | uint16_t value) |
796 | b4e3104b | balrog | { |
797 | b4e3104b | balrog | switch (offset) {
|
798 | b4e3104b | balrog | case 0xbc0: /* DMA_LCD_CSDP */ |
799 | b4e3104b | balrog | s->brust_f2 = (value >> 14) & 0x3; |
800 | b4e3104b | balrog | s->pack_f2 = (value >> 13) & 0x1; |
801 | b4e3104b | balrog | s->data_type_f2 = (1 << ((value >> 11) & 0x3)); |
802 | b4e3104b | balrog | s->brust_f1 = (value >> 7) & 0x3; |
803 | b4e3104b | balrog | s->pack_f1 = (value >> 6) & 0x1; |
804 | b4e3104b | balrog | s->data_type_f1 = (1 << ((value >> 0) & 0x3)); |
805 | b4e3104b | balrog | break;
|
806 | b4e3104b | balrog | |
807 | b4e3104b | balrog | case 0xbc2: /* DMA_LCD_CCR */ |
808 | b4e3104b | balrog | s->mode_f2 = (value >> 14) & 0x3; |
809 | b4e3104b | balrog | s->mode_f1 = (value >> 12) & 0x3; |
810 | b4e3104b | balrog | s->end_prog = (value >> 11) & 0x1; |
811 | b4e3104b | balrog | s->omap_3_1_compatible_disable = (value >> 10) & 0x1; |
812 | b4e3104b | balrog | s->repeat = (value >> 9) & 0x1; |
813 | b4e3104b | balrog | s->auto_init = (value >> 8) & 0x1; |
814 | b4e3104b | balrog | s->running = (value >> 7) & 0x1; |
815 | b4e3104b | balrog | s->priority = (value >> 6) & 0x1; |
816 | b4e3104b | balrog | s->bs = (value >> 4) & 0x1; |
817 | b4e3104b | balrog | break;
|
818 | b4e3104b | balrog | |
819 | b4e3104b | balrog | case 0xbc4: /* DMA_LCD_CTRL */ |
820 | b4e3104b | balrog | s->dst = (value >> 8) & 0x1; |
821 | b4e3104b | balrog | s->src = ((value >> 6) & 0x3) << 1; |
822 | b4e3104b | balrog | s->condition = 0;
|
823 | b4e3104b | balrog | /* Assume no bus errors and thus no BUS_ERROR irq bits. */
|
824 | b4e3104b | balrog | s->interrupts = (value >> 1) & 1; |
825 | b4e3104b | balrog | s->dual = value & 1;
|
826 | b4e3104b | balrog | break;
|
827 | b4e3104b | balrog | |
828 | b4e3104b | balrog | case 0xbc8: /* TOP_B1_L */ |
829 | b4e3104b | balrog | s->src_f1_top &= 0xffff0000;
|
830 | b4e3104b | balrog | s->src_f1_top |= 0x0000ffff & value;
|
831 | b4e3104b | balrog | break;
|
832 | b4e3104b | balrog | |
833 | b4e3104b | balrog | case 0xbca: /* TOP_B1_U */ |
834 | b4e3104b | balrog | s->src_f1_top &= 0x0000ffff;
|
835 | b4e3104b | balrog | s->src_f1_top |= value << 16;
|
836 | b4e3104b | balrog | break;
|
837 | b4e3104b | balrog | |
838 | b4e3104b | balrog | case 0xbcc: /* BOT_B1_L */ |
839 | b4e3104b | balrog | s->src_f1_bottom &= 0xffff0000;
|
840 | b4e3104b | balrog | s->src_f1_bottom |= 0x0000ffff & value;
|
841 | b4e3104b | balrog | break;
|
842 | b4e3104b | balrog | |
843 | b4e3104b | balrog | case 0xbce: /* BOT_B1_U */ |
844 | b4e3104b | balrog | s->src_f1_bottom &= 0x0000ffff;
|
845 | b4e3104b | balrog | s->src_f1_bottom |= (uint32_t) value << 16;
|
846 | b4e3104b | balrog | break;
|
847 | b4e3104b | balrog | |
848 | b4e3104b | balrog | case 0xbd0: /* TOP_B2_L */ |
849 | b4e3104b | balrog | s->src_f2_top &= 0xffff0000;
|
850 | b4e3104b | balrog | s->src_f2_top |= 0x0000ffff & value;
|
851 | b4e3104b | balrog | break;
|
852 | b4e3104b | balrog | |
853 | b4e3104b | balrog | case 0xbd2: /* TOP_B2_U */ |
854 | b4e3104b | balrog | s->src_f2_top &= 0x0000ffff;
|
855 | b4e3104b | balrog | s->src_f2_top |= (uint32_t) value << 16;
|
856 | b4e3104b | balrog | break;
|
857 | b4e3104b | balrog | |
858 | b4e3104b | balrog | case 0xbd4: /* BOT_B2_L */ |
859 | b4e3104b | balrog | s->src_f2_bottom &= 0xffff0000;
|
860 | b4e3104b | balrog | s->src_f2_bottom |= 0x0000ffff & value;
|
861 | b4e3104b | balrog | break;
|
862 | b4e3104b | balrog | |
863 | b4e3104b | balrog | case 0xbd6: /* BOT_B2_U */ |
864 | b4e3104b | balrog | s->src_f2_bottom &= 0x0000ffff;
|
865 | b4e3104b | balrog | s->src_f2_bottom |= (uint32_t) value << 16;
|
866 | b4e3104b | balrog | break;
|
867 | b4e3104b | balrog | |
868 | b4e3104b | balrog | case 0xbd8: /* DMA_LCD_SRC_EI_B1 */ |
869 | b4e3104b | balrog | s->element_index_f1 = value; |
870 | b4e3104b | balrog | break;
|
871 | b4e3104b | balrog | |
872 | b4e3104b | balrog | case 0xbda: /* DMA_LCD_SRC_FI_B1_L */ |
873 | b4e3104b | balrog | s->frame_index_f1 &= 0xffff0000;
|
874 | b4e3104b | balrog | s->frame_index_f1 |= 0x0000ffff & value;
|
875 | b4e3104b | balrog | break;
|
876 | b4e3104b | balrog | |
877 | b4e3104b | balrog | case 0xbf4: /* DMA_LCD_SRC_FI_B1_U */ |
878 | b4e3104b | balrog | s->frame_index_f1 &= 0x0000ffff;
|
879 | b4e3104b | balrog | s->frame_index_f1 |= (uint32_t) value << 16;
|
880 | b4e3104b | balrog | break;
|
881 | b4e3104b | balrog | |
882 | b4e3104b | balrog | case 0xbdc: /* DMA_LCD_SRC_EI_B2 */ |
883 | b4e3104b | balrog | s->element_index_f2 = value; |
884 | b4e3104b | balrog | break;
|
885 | b4e3104b | balrog | |
886 | b4e3104b | balrog | case 0xbde: /* DMA_LCD_SRC_FI_B2_L */ |
887 | b4e3104b | balrog | s->frame_index_f2 &= 0xffff0000;
|
888 | b4e3104b | balrog | s->frame_index_f2 |= 0x0000ffff & value;
|
889 | b4e3104b | balrog | break;
|
890 | b4e3104b | balrog | |
891 | b4e3104b | balrog | case 0xbf6: /* DMA_LCD_SRC_FI_B2_U */ |
892 | b4e3104b | balrog | s->frame_index_f2 &= 0x0000ffff;
|
893 | b4e3104b | balrog | s->frame_index_f2 |= (uint32_t) value << 16;
|
894 | b4e3104b | balrog | break;
|
895 | b4e3104b | balrog | |
896 | b4e3104b | balrog | case 0xbe0: /* DMA_LCD_SRC_EN_B1 */ |
897 | b4e3104b | balrog | s->elements_f1 = value; |
898 | b4e3104b | balrog | break;
|
899 | b4e3104b | balrog | |
900 | b4e3104b | balrog | case 0xbe4: /* DMA_LCD_SRC_FN_B1 */ |
901 | b4e3104b | balrog | s->frames_f1 = value; |
902 | b4e3104b | balrog | break;
|
903 | b4e3104b | balrog | |
904 | b4e3104b | balrog | case 0xbe2: /* DMA_LCD_SRC_EN_B2 */ |
905 | b4e3104b | balrog | s->elements_f2 = value; |
906 | b4e3104b | balrog | break;
|
907 | b4e3104b | balrog | |
908 | b4e3104b | balrog | case 0xbe6: /* DMA_LCD_SRC_FN_B2 */ |
909 | b4e3104b | balrog | s->frames_f2 = value; |
910 | b4e3104b | balrog | break;
|
911 | b4e3104b | balrog | |
912 | b4e3104b | balrog | case 0xbea: /* DMA_LCD_LCH_CTRL */ |
913 | b4e3104b | balrog | s->lch_type = value & 0xf;
|
914 | b4e3104b | balrog | break;
|
915 | b4e3104b | balrog | |
916 | b4e3104b | balrog | default:
|
917 | b4e3104b | balrog | return 1; |
918 | b4e3104b | balrog | } |
919 | b4e3104b | balrog | return 0; |
920 | b4e3104b | balrog | } |
921 | b4e3104b | balrog | |
922 | b4e3104b | balrog | static int omap_dma_3_2_lcd_read(struct omap_dma_lcd_channel_s *s, int offset, |
923 | b4e3104b | balrog | uint16_t *ret) |
924 | b4e3104b | balrog | { |
925 | b4e3104b | balrog | switch (offset) {
|
926 | b4e3104b | balrog | case 0xbc0: /* DMA_LCD_CSDP */ |
927 | b4e3104b | balrog | *ret = (s->brust_f2 << 14) |
|
928 | b4e3104b | balrog | (s->pack_f2 << 13) |
|
929 | b4e3104b | balrog | ((s->data_type_f2 >> 1) << 11) | |
930 | b4e3104b | balrog | (s->brust_f1 << 7) |
|
931 | b4e3104b | balrog | (s->pack_f1 << 6) |
|
932 | b4e3104b | balrog | ((s->data_type_f1 >> 1) << 0); |
933 | b4e3104b | balrog | break;
|
934 | b4e3104b | balrog | |
935 | b4e3104b | balrog | case 0xbc2: /* DMA_LCD_CCR */ |
936 | b4e3104b | balrog | *ret = (s->mode_f2 << 14) |
|
937 | b4e3104b | balrog | (s->mode_f1 << 12) |
|
938 | b4e3104b | balrog | (s->end_prog << 11) |
|
939 | b4e3104b | balrog | (s->omap_3_1_compatible_disable << 10) |
|
940 | b4e3104b | balrog | (s->repeat << 9) |
|
941 | b4e3104b | balrog | (s->auto_init << 8) |
|
942 | b4e3104b | balrog | (s->running << 7) |
|
943 | b4e3104b | balrog | (s->priority << 6) |
|
944 | b4e3104b | balrog | (s->bs << 4);
|
945 | b4e3104b | balrog | break;
|
946 | b4e3104b | balrog | |
947 | b4e3104b | balrog | case 0xbc4: /* DMA_LCD_CTRL */ |
948 | b4e3104b | balrog | qemu_irq_lower(s->irq); |
949 | b4e3104b | balrog | *ret = (s->dst << 8) |
|
950 | b4e3104b | balrog | ((s->src & 0x6) << 5) | |
951 | b4e3104b | balrog | (s->condition << 3) |
|
952 | b4e3104b | balrog | (s->interrupts << 1) |
|
953 | b4e3104b | balrog | s->dual; |
954 | b4e3104b | balrog | break;
|
955 | b4e3104b | balrog | |
956 | b4e3104b | balrog | case 0xbc8: /* TOP_B1_L */ |
957 | b4e3104b | balrog | *ret = s->src_f1_top & 0xffff;
|
958 | b4e3104b | balrog | break;
|
959 | b4e3104b | balrog | |
960 | b4e3104b | balrog | case 0xbca: /* TOP_B1_U */ |
961 | b4e3104b | balrog | *ret = s->src_f1_top >> 16;
|
962 | b4e3104b | balrog | break;
|
963 | b4e3104b | balrog | |
964 | b4e3104b | balrog | case 0xbcc: /* BOT_B1_L */ |
965 | b4e3104b | balrog | *ret = s->src_f1_bottom & 0xffff;
|
966 | b4e3104b | balrog | break;
|
967 | b4e3104b | balrog | |
968 | b4e3104b | balrog | case 0xbce: /* BOT_B1_U */ |
969 | b4e3104b | balrog | *ret = s->src_f1_bottom >> 16;
|
970 | b4e3104b | balrog | break;
|
971 | b4e3104b | balrog | |
972 | b4e3104b | balrog | case 0xbd0: /* TOP_B2_L */ |
973 | b4e3104b | balrog | *ret = s->src_f2_top & 0xffff;
|
974 | b4e3104b | balrog | break;
|
975 | b4e3104b | balrog | |
976 | b4e3104b | balrog | case 0xbd2: /* TOP_B2_U */ |
977 | b4e3104b | balrog | *ret = s->src_f2_top >> 16;
|
978 | b4e3104b | balrog | break;
|
979 | b4e3104b | balrog | |
980 | b4e3104b | balrog | case 0xbd4: /* BOT_B2_L */ |
981 | b4e3104b | balrog | *ret = s->src_f2_bottom & 0xffff;
|
982 | b4e3104b | balrog | break;
|
983 | b4e3104b | balrog | |
984 | b4e3104b | balrog | case 0xbd6: /* BOT_B2_U */ |
985 | b4e3104b | balrog | *ret = s->src_f2_bottom >> 16;
|
986 | b4e3104b | balrog | break;
|
987 | b4e3104b | balrog | |
988 | b4e3104b | balrog | case 0xbd8: /* DMA_LCD_SRC_EI_B1 */ |
989 | b4e3104b | balrog | *ret = s->element_index_f1; |
990 | b4e3104b | balrog | break;
|
991 | b4e3104b | balrog | |
992 | b4e3104b | balrog | case 0xbda: /* DMA_LCD_SRC_FI_B1_L */ |
993 | b4e3104b | balrog | *ret = s->frame_index_f1 & 0xffff;
|
994 | b4e3104b | balrog | break;
|
995 | b4e3104b | balrog | |
996 | b4e3104b | balrog | case 0xbf4: /* DMA_LCD_SRC_FI_B1_U */ |
997 | b4e3104b | balrog | *ret = s->frame_index_f1 >> 16;
|
998 | b4e3104b | balrog | break;
|
999 | b4e3104b | balrog | |
1000 | b4e3104b | balrog | case 0xbdc: /* DMA_LCD_SRC_EI_B2 */ |
1001 | b4e3104b | balrog | *ret = s->element_index_f2; |
1002 | b4e3104b | balrog | break;
|
1003 | b4e3104b | balrog | |
1004 | b4e3104b | balrog | case 0xbde: /* DMA_LCD_SRC_FI_B2_L */ |
1005 | b4e3104b | balrog | *ret = s->frame_index_f2 & 0xffff;
|
1006 | b4e3104b | balrog | break;
|
1007 | b4e3104b | balrog | |
1008 | b4e3104b | balrog | case 0xbf6: /* DMA_LCD_SRC_FI_B2_U */ |
1009 | b4e3104b | balrog | *ret = s->frame_index_f2 >> 16;
|
1010 | b4e3104b | balrog | break;
|
1011 | b4e3104b | balrog | |
1012 | b4e3104b | balrog | case 0xbe0: /* DMA_LCD_SRC_EN_B1 */ |
1013 | b4e3104b | balrog | *ret = s->elements_f1; |
1014 | b4e3104b | balrog | break;
|
1015 | b4e3104b | balrog | |
1016 | b4e3104b | balrog | case 0xbe4: /* DMA_LCD_SRC_FN_B1 */ |
1017 | b4e3104b | balrog | *ret = s->frames_f1; |
1018 | b4e3104b | balrog | break;
|
1019 | b4e3104b | balrog | |
1020 | b4e3104b | balrog | case 0xbe2: /* DMA_LCD_SRC_EN_B2 */ |
1021 | b4e3104b | balrog | *ret = s->elements_f2; |
1022 | b4e3104b | balrog | break;
|
1023 | b4e3104b | balrog | |
1024 | b4e3104b | balrog | case 0xbe6: /* DMA_LCD_SRC_FN_B2 */ |
1025 | b4e3104b | balrog | *ret = s->frames_f2; |
1026 | b4e3104b | balrog | break;
|
1027 | b4e3104b | balrog | |
1028 | b4e3104b | balrog | case 0xbea: /* DMA_LCD_LCH_CTRL */ |
1029 | b4e3104b | balrog | *ret = s->lch_type; |
1030 | b4e3104b | balrog | break;
|
1031 | b4e3104b | balrog | |
1032 | b4e3104b | balrog | default:
|
1033 | b4e3104b | balrog | return 1; |
1034 | b4e3104b | balrog | } |
1035 | b4e3104b | balrog | return 0; |
1036 | b4e3104b | balrog | } |
1037 | b4e3104b | balrog | |
1038 | b4e3104b | balrog | static int omap_dma_3_1_lcd_write(struct omap_dma_lcd_channel_s *s, int offset, |
1039 | b4e3104b | balrog | uint16_t value) |
1040 | b4e3104b | balrog | { |
1041 | b4e3104b | balrog | switch (offset) {
|
1042 | b4e3104b | balrog | case 0x300: /* SYS_DMA_LCD_CTRL */ |
1043 | b4e3104b | balrog | s->src = (value & 0x40) ? imif : emiff;
|
1044 | b4e3104b | balrog | s->condition = 0;
|
1045 | b4e3104b | balrog | /* Assume no bus errors and thus no BUS_ERROR irq bits. */
|
1046 | b4e3104b | balrog | s->interrupts = (value >> 1) & 1; |
1047 | b4e3104b | balrog | s->dual = value & 1;
|
1048 | b4e3104b | balrog | break;
|
1049 | b4e3104b | balrog | |
1050 | b4e3104b | balrog | case 0x302: /* SYS_DMA_LCD_TOP_F1_L */ |
1051 | b4e3104b | balrog | s->src_f1_top &= 0xffff0000;
|
1052 | b4e3104b | balrog | s->src_f1_top |= 0x0000ffff & value;
|
1053 | b4e3104b | balrog | break;
|
1054 | b4e3104b | balrog | |
1055 | b4e3104b | balrog | case 0x304: /* SYS_DMA_LCD_TOP_F1_U */ |
1056 | b4e3104b | balrog | s->src_f1_top &= 0x0000ffff;
|
1057 | b4e3104b | balrog | s->src_f1_top |= value << 16;
|
1058 | b4e3104b | balrog | break;
|
1059 | b4e3104b | balrog | |
1060 | b4e3104b | balrog | case 0x306: /* SYS_DMA_LCD_BOT_F1_L */ |
1061 | b4e3104b | balrog | s->src_f1_bottom &= 0xffff0000;
|
1062 | b4e3104b | balrog | s->src_f1_bottom |= 0x0000ffff & value;
|
1063 | b4e3104b | balrog | break;
|
1064 | b4e3104b | balrog | |
1065 | b4e3104b | balrog | case 0x308: /* SYS_DMA_LCD_BOT_F1_U */ |
1066 | b4e3104b | balrog | s->src_f1_bottom &= 0x0000ffff;
|
1067 | b4e3104b | balrog | s->src_f1_bottom |= value << 16;
|
1068 | b4e3104b | balrog | break;
|
1069 | b4e3104b | balrog | |
1070 | b4e3104b | balrog | case 0x30a: /* SYS_DMA_LCD_TOP_F2_L */ |
1071 | b4e3104b | balrog | s->src_f2_top &= 0xffff0000;
|
1072 | b4e3104b | balrog | s->src_f2_top |= 0x0000ffff & value;
|
1073 | b4e3104b | balrog | break;
|
1074 | b4e3104b | balrog | |
1075 | b4e3104b | balrog | case 0x30c: /* SYS_DMA_LCD_TOP_F2_U */ |
1076 | b4e3104b | balrog | s->src_f2_top &= 0x0000ffff;
|
1077 | b4e3104b | balrog | s->src_f2_top |= value << 16;
|
1078 | b4e3104b | balrog | break;
|
1079 | b4e3104b | balrog | |
1080 | b4e3104b | balrog | case 0x30e: /* SYS_DMA_LCD_BOT_F2_L */ |
1081 | b4e3104b | balrog | s->src_f2_bottom &= 0xffff0000;
|
1082 | b4e3104b | balrog | s->src_f2_bottom |= 0x0000ffff & value;
|
1083 | b4e3104b | balrog | break;
|
1084 | b4e3104b | balrog | |
1085 | b4e3104b | balrog | case 0x310: /* SYS_DMA_LCD_BOT_F2_U */ |
1086 | b4e3104b | balrog | s->src_f2_bottom &= 0x0000ffff;
|
1087 | b4e3104b | balrog | s->src_f2_bottom |= value << 16;
|
1088 | b4e3104b | balrog | break;
|
1089 | b4e3104b | balrog | |
1090 | b4e3104b | balrog | default:
|
1091 | b4e3104b | balrog | return 1; |
1092 | b4e3104b | balrog | } |
1093 | b4e3104b | balrog | return 0; |
1094 | b4e3104b | balrog | } |
1095 | b4e3104b | balrog | |
1096 | b4e3104b | balrog | static int omap_dma_3_1_lcd_read(struct omap_dma_lcd_channel_s *s, int offset, |
1097 | b4e3104b | balrog | uint16_t *ret) |
1098 | b4e3104b | balrog | { |
1099 | b4e3104b | balrog | int i;
|
1100 | b4e3104b | balrog | |
1101 | b4e3104b | balrog | switch (offset) {
|
1102 | b4e3104b | balrog | case 0x300: /* SYS_DMA_LCD_CTRL */ |
1103 | b4e3104b | balrog | i = s->condition; |
1104 | b4e3104b | balrog | s->condition = 0;
|
1105 | b4e3104b | balrog | qemu_irq_lower(s->irq); |
1106 | b4e3104b | balrog | *ret = ((s->src == imif) << 6) | (i << 3) | |
1107 | b4e3104b | balrog | (s->interrupts << 1) | s->dual;
|
1108 | b4e3104b | balrog | break;
|
1109 | b4e3104b | balrog | |
1110 | b4e3104b | balrog | case 0x302: /* SYS_DMA_LCD_TOP_F1_L */ |
1111 | b4e3104b | balrog | *ret = s->src_f1_top & 0xffff;
|
1112 | b4e3104b | balrog | break;
|
1113 | b4e3104b | balrog | |
1114 | b4e3104b | balrog | case 0x304: /* SYS_DMA_LCD_TOP_F1_U */ |
1115 | b4e3104b | balrog | *ret = s->src_f1_top >> 16;
|
1116 | b4e3104b | balrog | break;
|
1117 | b4e3104b | balrog | |
1118 | b4e3104b | balrog | case 0x306: /* SYS_DMA_LCD_BOT_F1_L */ |
1119 | b4e3104b | balrog | *ret = s->src_f1_bottom & 0xffff;
|
1120 | b4e3104b | balrog | break;
|
1121 | b4e3104b | balrog | |
1122 | b4e3104b | balrog | case 0x308: /* SYS_DMA_LCD_BOT_F1_U */ |
1123 | b4e3104b | balrog | *ret = s->src_f1_bottom >> 16;
|
1124 | b4e3104b | balrog | break;
|
1125 | b4e3104b | balrog | |
1126 | b4e3104b | balrog | case 0x30a: /* SYS_DMA_LCD_TOP_F2_L */ |
1127 | b4e3104b | balrog | *ret = s->src_f2_top & 0xffff;
|
1128 | b4e3104b | balrog | break;
|
1129 | b4e3104b | balrog | |
1130 | b4e3104b | balrog | case 0x30c: /* SYS_DMA_LCD_TOP_F2_U */ |
1131 | b4e3104b | balrog | *ret = s->src_f2_top >> 16;
|
1132 | b4e3104b | balrog | break;
|
1133 | b4e3104b | balrog | |
1134 | b4e3104b | balrog | case 0x30e: /* SYS_DMA_LCD_BOT_F2_L */ |
1135 | b4e3104b | balrog | *ret = s->src_f2_bottom & 0xffff;
|
1136 | b4e3104b | balrog | break;
|
1137 | b4e3104b | balrog | |
1138 | b4e3104b | balrog | case 0x310: /* SYS_DMA_LCD_BOT_F2_U */ |
1139 | b4e3104b | balrog | *ret = s->src_f2_bottom >> 16;
|
1140 | b4e3104b | balrog | break;
|
1141 | b4e3104b | balrog | |
1142 | b4e3104b | balrog | default:
|
1143 | b4e3104b | balrog | return 1; |
1144 | b4e3104b | balrog | } |
1145 | b4e3104b | balrog | return 0; |
1146 | b4e3104b | balrog | } |
1147 | b4e3104b | balrog | |
1148 | b4e3104b | balrog | static int omap_dma_sys_write(struct omap_dma_s *s, int offset, uint16_t value) |
1149 | b4e3104b | balrog | { |
1150 | b4e3104b | balrog | switch (offset) {
|
1151 | b4e3104b | balrog | case 0x400: /* SYS_DMA_GCR */ |
1152 | b4e3104b | balrog | s->gcr = value; |
1153 | b4e3104b | balrog | break;
|
1154 | b4e3104b | balrog | |
1155 | b4e3104b | balrog | case 0x404: /* DMA_GSCR */ |
1156 | b4e3104b | balrog | if (value & 0x8) |
1157 | b4e3104b | balrog | omap_dma_disable_3_1_mapping(s); |
1158 | b4e3104b | balrog | else
|
1159 | b4e3104b | balrog | omap_dma_enable_3_1_mapping(s); |
1160 | b4e3104b | balrog | break;
|
1161 | b4e3104b | balrog | |
1162 | b4e3104b | balrog | case 0x408: /* DMA_GRST */ |
1163 | b4e3104b | balrog | if (value & 0x1) |
1164 | b4e3104b | balrog | omap_dma_reset(s); |
1165 | b4e3104b | balrog | break;
|
1166 | b4e3104b | balrog | |
1167 | b4e3104b | balrog | default:
|
1168 | b4e3104b | balrog | return 1; |
1169 | b4e3104b | balrog | } |
1170 | b4e3104b | balrog | return 0; |
1171 | b4e3104b | balrog | } |
1172 | b4e3104b | balrog | |
1173 | b4e3104b | balrog | static int omap_dma_sys_read(struct omap_dma_s *s, int offset, |
1174 | b4e3104b | balrog | uint16_t *ret) |
1175 | b4e3104b | balrog | { |
1176 | b4e3104b | balrog | switch (offset) {
|
1177 | b4e3104b | balrog | case 0x400: /* SYS_DMA_GCR */ |
1178 | b4e3104b | balrog | *ret = s->gcr; |
1179 | b4e3104b | balrog | break;
|
1180 | b4e3104b | balrog | |
1181 | b4e3104b | balrog | case 0x404: /* DMA_GSCR */ |
1182 | b4e3104b | balrog | *ret = s->omap_3_1_mapping_disabled << 3;
|
1183 | b4e3104b | balrog | break;
|
1184 | b4e3104b | balrog | |
1185 | b4e3104b | balrog | case 0x408: /* DMA_GRST */ |
1186 | b4e3104b | balrog | *ret = 0;
|
1187 | b4e3104b | balrog | break;
|
1188 | b4e3104b | balrog | |
1189 | b4e3104b | balrog | case 0x442: /* DMA_HW_ID */ |
1190 | b4e3104b | balrog | case 0x444: /* DMA_PCh2_ID */ |
1191 | b4e3104b | balrog | case 0x446: /* DMA_PCh0_ID */ |
1192 | b4e3104b | balrog | case 0x448: /* DMA_PCh1_ID */ |
1193 | b4e3104b | balrog | case 0x44a: /* DMA_PChG_ID */ |
1194 | b4e3104b | balrog | case 0x44c: /* DMA_PChD_ID */ |
1195 | b4e3104b | balrog | *ret = 1;
|
1196 | b4e3104b | balrog | break;
|
1197 | b4e3104b | balrog | |
1198 | b4e3104b | balrog | case 0x44e: /* DMA_CAPS_0_U */ |
1199 | 827df9f3 | balrog | *ret = (s->caps[0] >> 16) & 0xffff; |
1200 | b4e3104b | balrog | break;
|
1201 | b4e3104b | balrog | case 0x450: /* DMA_CAPS_0_L */ |
1202 | 827df9f3 | balrog | *ret = (s->caps[0] >> 0) & 0xffff; |
1203 | b4e3104b | balrog | break;
|
1204 | b4e3104b | balrog | |
1205 | 827df9f3 | balrog | case 0x452: /* DMA_CAPS_1_U */ |
1206 | 827df9f3 | balrog | *ret = (s->caps[1] >> 16) & 0xffff; |
1207 | 827df9f3 | balrog | break;
|
1208 | b4e3104b | balrog | case 0x454: /* DMA_CAPS_1_L */ |
1209 | 827df9f3 | balrog | *ret = (s->caps[1] >> 0) & 0xffff; |
1210 | b4e3104b | balrog | break;
|
1211 | b4e3104b | balrog | |
1212 | b4e3104b | balrog | case 0x456: /* DMA_CAPS_2 */ |
1213 | 827df9f3 | balrog | *ret = s->caps[2];
|
1214 | b4e3104b | balrog | break;
|
1215 | b4e3104b | balrog | |
1216 | b4e3104b | balrog | case 0x458: /* DMA_CAPS_3 */ |
1217 | 827df9f3 | balrog | *ret = s->caps[3];
|
1218 | b4e3104b | balrog | break;
|
1219 | b4e3104b | balrog | |
1220 | b4e3104b | balrog | case 0x45a: /* DMA_CAPS_4 */ |
1221 | 827df9f3 | balrog | *ret = s->caps[4];
|
1222 | b4e3104b | balrog | break;
|
1223 | b4e3104b | balrog | |
1224 | b4e3104b | balrog | case 0x460: /* DMA_PCh2_SR */ |
1225 | b4e3104b | balrog | case 0x480: /* DMA_PCh0_SR */ |
1226 | b4e3104b | balrog | case 0x482: /* DMA_PCh1_SR */ |
1227 | b4e3104b | balrog | case 0x4c0: /* DMA_PChD_SR_0 */ |
1228 | b4e3104b | balrog | printf("%s: Physical Channel Status Registers not implemented.\n",
|
1229 | b4e3104b | balrog | __FUNCTION__); |
1230 | b4e3104b | balrog | *ret = 0xff;
|
1231 | b4e3104b | balrog | break;
|
1232 | b4e3104b | balrog | |
1233 | b4e3104b | balrog | default:
|
1234 | b4e3104b | balrog | return 1; |
1235 | b4e3104b | balrog | } |
1236 | b4e3104b | balrog | return 0; |
1237 | b4e3104b | balrog | } |
1238 | b4e3104b | balrog | |
1239 | b4e3104b | balrog | static uint32_t omap_dma_read(void *opaque, target_phys_addr_t addr) |
1240 | b4e3104b | balrog | { |
1241 | b4e3104b | balrog | struct omap_dma_s *s = (struct omap_dma_s *) opaque; |
1242 | b4e3104b | balrog | int reg, ch, offset = addr - s->base;
|
1243 | b4e3104b | balrog | uint16_t ret; |
1244 | b4e3104b | balrog | |
1245 | b4e3104b | balrog | switch (offset) {
|
1246 | b4e3104b | balrog | case 0x300 ... 0x3fe: |
1247 | 827df9f3 | balrog | if (s->model <= omap_dma_3_1 || !s->omap_3_1_mapping_disabled) {
|
1248 | b4e3104b | balrog | if (omap_dma_3_1_lcd_read(&s->lcd_ch, offset, &ret))
|
1249 | b4e3104b | balrog | break;
|
1250 | b4e3104b | balrog | return ret;
|
1251 | b4e3104b | balrog | } |
1252 | b4e3104b | balrog | /* Fall through. */
|
1253 | b4e3104b | balrog | case 0x000 ... 0x2fe: |
1254 | b4e3104b | balrog | reg = offset & 0x3f;
|
1255 | b4e3104b | balrog | ch = (offset >> 6) & 0x0f; |
1256 | b4e3104b | balrog | if (omap_dma_ch_reg_read(s, &s->ch[ch], reg, &ret))
|
1257 | b4e3104b | balrog | break;
|
1258 | b4e3104b | balrog | return ret;
|
1259 | b4e3104b | balrog | |
1260 | b4e3104b | balrog | case 0x404 ... 0x4fe: |
1261 | 827df9f3 | balrog | if (s->model <= omap_dma_3_1)
|
1262 | b4e3104b | balrog | break;
|
1263 | b4e3104b | balrog | /* Fall through. */
|
1264 | b4e3104b | balrog | case 0x400: |
1265 | b4e3104b | balrog | if (omap_dma_sys_read(s, offset, &ret))
|
1266 | b4e3104b | balrog | break;
|
1267 | b4e3104b | balrog | return ret;
|
1268 | b4e3104b | balrog | |
1269 | b4e3104b | balrog | case 0xb00 ... 0xbfe: |
1270 | b4e3104b | balrog | if (s->model == omap_dma_3_2 && s->omap_3_1_mapping_disabled) {
|
1271 | b4e3104b | balrog | if (omap_dma_3_2_lcd_read(&s->lcd_ch, offset, &ret))
|
1272 | b4e3104b | balrog | break;
|
1273 | b4e3104b | balrog | return ret;
|
1274 | b4e3104b | balrog | } |
1275 | b4e3104b | balrog | break;
|
1276 | b4e3104b | balrog | } |
1277 | b4e3104b | balrog | |
1278 | b4e3104b | balrog | OMAP_BAD_REG(addr); |
1279 | b4e3104b | balrog | return 0; |
1280 | b4e3104b | balrog | } |
1281 | b4e3104b | balrog | |
1282 | b4e3104b | balrog | static void omap_dma_write(void *opaque, target_phys_addr_t addr, |
1283 | b4e3104b | balrog | uint32_t value) |
1284 | b4e3104b | balrog | { |
1285 | b4e3104b | balrog | struct omap_dma_s *s = (struct omap_dma_s *) opaque; |
1286 | b4e3104b | balrog | int reg, ch, offset = addr - s->base;
|
1287 | b4e3104b | balrog | |
1288 | b4e3104b | balrog | switch (offset) {
|
1289 | b4e3104b | balrog | case 0x300 ... 0x3fe: |
1290 | 827df9f3 | balrog | if (s->model <= omap_dma_3_1 || !s->omap_3_1_mapping_disabled) {
|
1291 | b4e3104b | balrog | if (omap_dma_3_1_lcd_write(&s->lcd_ch, offset, value))
|
1292 | b4e3104b | balrog | break;
|
1293 | b4e3104b | balrog | return;
|
1294 | b4e3104b | balrog | } |
1295 | b4e3104b | balrog | /* Fall through. */
|
1296 | b4e3104b | balrog | case 0x000 ... 0x2fe: |
1297 | b4e3104b | balrog | reg = offset & 0x3f;
|
1298 | b4e3104b | balrog | ch = (offset >> 6) & 0x0f; |
1299 | b4e3104b | balrog | if (omap_dma_ch_reg_write(s, &s->ch[ch], reg, value))
|
1300 | b4e3104b | balrog | break;
|
1301 | b4e3104b | balrog | return;
|
1302 | b4e3104b | balrog | |
1303 | b4e3104b | balrog | case 0x404 ... 0x4fe: |
1304 | 827df9f3 | balrog | if (s->model <= omap_dma_3_1)
|
1305 | b4e3104b | balrog | break;
|
1306 | b4e3104b | balrog | case 0x400: |
1307 | b4e3104b | balrog | /* Fall through. */
|
1308 | b4e3104b | balrog | if (omap_dma_sys_write(s, offset, value))
|
1309 | b4e3104b | balrog | break;
|
1310 | b4e3104b | balrog | return;
|
1311 | b4e3104b | balrog | |
1312 | b4e3104b | balrog | case 0xb00 ... 0xbfe: |
1313 | b4e3104b | balrog | if (s->model == omap_dma_3_2 && s->omap_3_1_mapping_disabled) {
|
1314 | b4e3104b | balrog | if (omap_dma_3_2_lcd_write(&s->lcd_ch, offset, value))
|
1315 | b4e3104b | balrog | break;
|
1316 | b4e3104b | balrog | return;
|
1317 | b4e3104b | balrog | } |
1318 | b4e3104b | balrog | break;
|
1319 | b4e3104b | balrog | } |
1320 | b4e3104b | balrog | |
1321 | b4e3104b | balrog | OMAP_BAD_REG(addr); |
1322 | b4e3104b | balrog | } |
1323 | b4e3104b | balrog | |
1324 | b4e3104b | balrog | static CPUReadMemoryFunc *omap_dma_readfn[] = {
|
1325 | b4e3104b | balrog | omap_badwidth_read16, |
1326 | b4e3104b | balrog | omap_dma_read, |
1327 | b4e3104b | balrog | omap_badwidth_read16, |
1328 | b4e3104b | balrog | }; |
1329 | b4e3104b | balrog | |
1330 | b4e3104b | balrog | static CPUWriteMemoryFunc *omap_dma_writefn[] = {
|
1331 | b4e3104b | balrog | omap_badwidth_write16, |
1332 | b4e3104b | balrog | omap_dma_write, |
1333 | b4e3104b | balrog | omap_badwidth_write16, |
1334 | b4e3104b | balrog | }; |
1335 | b4e3104b | balrog | |
1336 | b4e3104b | balrog | static void omap_dma_request(void *opaque, int drq, int req) |
1337 | b4e3104b | balrog | { |
1338 | b4e3104b | balrog | struct omap_dma_s *s = (struct omap_dma_s *) opaque; |
1339 | 827df9f3 | balrog | /* The request pins are level triggered in QEMU. */
|
1340 | b4e3104b | balrog | if (req) {
|
1341 | b4e3104b | balrog | if (~s->drq & (1 << drq)) { |
1342 | b4e3104b | balrog | s->drq |= 1 << drq;
|
1343 | b4e3104b | balrog | omap_dma_process_request(s, drq); |
1344 | b4e3104b | balrog | } |
1345 | b4e3104b | balrog | } else
|
1346 | b4e3104b | balrog | s->drq &= ~(1 << drq);
|
1347 | b4e3104b | balrog | } |
1348 | b4e3104b | balrog | |
1349 | b4e3104b | balrog | static void omap_dma_clk_update(void *opaque, int line, int on) |
1350 | b4e3104b | balrog | { |
1351 | b4e3104b | balrog | struct omap_dma_s *s = (struct omap_dma_s *) opaque; |
1352 | b4e3104b | balrog | |
1353 | b4e3104b | balrog | if (on) {
|
1354 | b4e3104b | balrog | /* TODO: make a clever calculation */
|
1355 | b4e3104b | balrog | s->delay = ticks_per_sec >> 8;
|
1356 | b4e3104b | balrog | if (s->run_count)
|
1357 | b4e3104b | balrog | qemu_mod_timer(s->tm, qemu_get_clock(vm_clock) + s->delay); |
1358 | b4e3104b | balrog | } else {
|
1359 | b4e3104b | balrog | s->delay = 0;
|
1360 | b4e3104b | balrog | qemu_del_timer(s->tm); |
1361 | b4e3104b | balrog | } |
1362 | b4e3104b | balrog | } |
1363 | b4e3104b | balrog | |
1364 | 827df9f3 | balrog | static void omap_dma_setcaps(struct omap_dma_s *s) |
1365 | 827df9f3 | balrog | { |
1366 | 827df9f3 | balrog | switch (s->model) {
|
1367 | 827df9f3 | balrog | default:
|
1368 | 827df9f3 | balrog | case omap_dma_3_1:
|
1369 | 827df9f3 | balrog | break;
|
1370 | 827df9f3 | balrog | case omap_dma_3_2:
|
1371 | 827df9f3 | balrog | case omap_dma_4:
|
1372 | 827df9f3 | balrog | /* XXX Only available for sDMA */
|
1373 | 827df9f3 | balrog | s->caps[0] =
|
1374 | 827df9f3 | balrog | (1 << 19) | /* Constant Fill Capability */ |
1375 | 827df9f3 | balrog | (1 << 18); /* Transparent BLT Capability */ |
1376 | 827df9f3 | balrog | s->caps[1] =
|
1377 | 827df9f3 | balrog | (1 << 1); /* 1-bit palettized capability (DMA 3.2 only) */ |
1378 | 827df9f3 | balrog | s->caps[2] =
|
1379 | 827df9f3 | balrog | (1 << 8) | /* SEPARATE_SRC_AND_DST_INDEX_CPBLTY */ |
1380 | 827df9f3 | balrog | (1 << 7) | /* DST_DOUBLE_INDEX_ADRS_CPBLTY */ |
1381 | 827df9f3 | balrog | (1 << 6) | /* DST_SINGLE_INDEX_ADRS_CPBLTY */ |
1382 | 827df9f3 | balrog | (1 << 5) | /* DST_POST_INCRMNT_ADRS_CPBLTY */ |
1383 | 827df9f3 | balrog | (1 << 4) | /* DST_CONST_ADRS_CPBLTY */ |
1384 | 827df9f3 | balrog | (1 << 3) | /* SRC_DOUBLE_INDEX_ADRS_CPBLTY */ |
1385 | 827df9f3 | balrog | (1 << 2) | /* SRC_SINGLE_INDEX_ADRS_CPBLTY */ |
1386 | 827df9f3 | balrog | (1 << 1) | /* SRC_POST_INCRMNT_ADRS_CPBLTY */ |
1387 | 827df9f3 | balrog | (1 << 0); /* SRC_CONST_ADRS_CPBLTY */ |
1388 | 827df9f3 | balrog | s->caps[3] =
|
1389 | 827df9f3 | balrog | (1 << 6) | /* BLOCK_SYNCHR_CPBLTY (DMA 4 only) */ |
1390 | 827df9f3 | balrog | (1 << 7) | /* PKT_SYNCHR_CPBLTY (DMA 4 only) */ |
1391 | 827df9f3 | balrog | (1 << 5) | /* CHANNEL_CHAINING_CPBLTY */ |
1392 | 827df9f3 | balrog | (1 << 4) | /* LCh_INTERLEAVE_CPBLTY */ |
1393 | 827df9f3 | balrog | (1 << 3) | /* AUTOINIT_REPEAT_CPBLTY (DMA 3.2 only) */ |
1394 | 827df9f3 | balrog | (1 << 2) | /* AUTOINIT_ENDPROG_CPBLTY (DMA 3.2 only) */ |
1395 | 827df9f3 | balrog | (1 << 1) | /* FRAME_SYNCHR_CPBLTY */ |
1396 | 827df9f3 | balrog | (1 << 0); /* ELMNT_SYNCHR_CPBLTY */ |
1397 | 827df9f3 | balrog | s->caps[4] =
|
1398 | 827df9f3 | balrog | (1 << 7) | /* PKT_INTERRUPT_CPBLTY (DMA 4 only) */ |
1399 | 827df9f3 | balrog | (1 << 6) | /* SYNC_STATUS_CPBLTY */ |
1400 | 827df9f3 | balrog | (1 << 5) | /* BLOCK_INTERRUPT_CPBLTY */ |
1401 | 827df9f3 | balrog | (1 << 4) | /* LAST_FRAME_INTERRUPT_CPBLTY */ |
1402 | 827df9f3 | balrog | (1 << 3) | /* FRAME_INTERRUPT_CPBLTY */ |
1403 | 827df9f3 | balrog | (1 << 2) | /* HALF_FRAME_INTERRUPT_CPBLTY */ |
1404 | 827df9f3 | balrog | (1 << 1) | /* EVENT_DROP_INTERRUPT_CPBLTY */ |
1405 | 827df9f3 | balrog | (1 << 0); /* TIMEOUT_INTERRUPT_CPBLTY (DMA 3.2 only) */ |
1406 | 827df9f3 | balrog | break;
|
1407 | 827df9f3 | balrog | } |
1408 | 827df9f3 | balrog | } |
1409 | 827df9f3 | balrog | |
1410 | b4e3104b | balrog | struct omap_dma_s *omap_dma_init(target_phys_addr_t base, qemu_irq *irqs,
|
1411 | b4e3104b | balrog | qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk,
|
1412 | b4e3104b | balrog | enum omap_dma_model model)
|
1413 | b4e3104b | balrog | { |
1414 | b4e3104b | balrog | int iomemtype, num_irqs, memsize, i;
|
1415 | b4e3104b | balrog | struct omap_dma_s *s = (struct omap_dma_s *) |
1416 | b4e3104b | balrog | qemu_mallocz(sizeof(struct omap_dma_s)); |
1417 | b4e3104b | balrog | |
1418 | 827df9f3 | balrog | if (model <= omap_dma_3_1) {
|
1419 | b4e3104b | balrog | num_irqs = 6;
|
1420 | b4e3104b | balrog | memsize = 0x800;
|
1421 | b4e3104b | balrog | } else {
|
1422 | b4e3104b | balrog | num_irqs = 16;
|
1423 | b4e3104b | balrog | memsize = 0xc00;
|
1424 | b4e3104b | balrog | } |
1425 | b4e3104b | balrog | s->base = base; |
1426 | b4e3104b | balrog | s->model = model; |
1427 | b4e3104b | balrog | s->mpu = mpu; |
1428 | b4e3104b | balrog | s->clk = clk; |
1429 | b4e3104b | balrog | s->lcd_ch.irq = lcd_irq; |
1430 | b4e3104b | balrog | s->lcd_ch.mpu = mpu; |
1431 | 827df9f3 | balrog | omap_dma_setcaps(s); |
1432 | b4e3104b | balrog | while (num_irqs --)
|
1433 | b4e3104b | balrog | s->ch[num_irqs].irq = irqs[num_irqs]; |
1434 | b4e3104b | balrog | for (i = 0; i < 3; i ++) { |
1435 | b4e3104b | balrog | s->ch[i].sibling = &s->ch[i + 6];
|
1436 | b4e3104b | balrog | s->ch[i + 6].sibling = &s->ch[i];
|
1437 | b4e3104b | balrog | } |
1438 | b4e3104b | balrog | s->tm = qemu_new_timer(vm_clock, (QEMUTimerCB *) omap_dma_channel_run, s); |
1439 | b4e3104b | balrog | omap_clk_adduser(s->clk, qemu_allocate_irqs(omap_dma_clk_update, s, 1)[0]); |
1440 | b4e3104b | balrog | mpu->drq = qemu_allocate_irqs(omap_dma_request, s, 32);
|
1441 | b4e3104b | balrog | omap_dma_reset(s); |
1442 | b4e3104b | balrog | omap_dma_clk_update(s, 0, 1); |
1443 | b4e3104b | balrog | |
1444 | b4e3104b | balrog | iomemtype = cpu_register_io_memory(0, omap_dma_readfn,
|
1445 | b4e3104b | balrog | omap_dma_writefn, s); |
1446 | b4e3104b | balrog | cpu_register_physical_memory(s->base, memsize, iomemtype); |
1447 | b4e3104b | balrog | |
1448 | b4e3104b | balrog | return s;
|
1449 | b4e3104b | balrog | } |
1450 | b4e3104b | balrog | |
1451 | 827df9f3 | balrog | static void omap_dma_interrupts_4_update(struct omap_dma_s *s) |
1452 | 827df9f3 | balrog | { |
1453 | 827df9f3 | balrog | struct omap_dma_channel_s *ch = s->ch;
|
1454 | 827df9f3 | balrog | uint32_t bmp, bit; |
1455 | 827df9f3 | balrog | |
1456 | 827df9f3 | balrog | for (bmp = 0, bit = 1; bit; ch ++, bit <<= 1) |
1457 | 827df9f3 | balrog | if (ch->status) {
|
1458 | 827df9f3 | balrog | bmp |= bit; |
1459 | 827df9f3 | balrog | ch->cstatus |= ch->status; |
1460 | 827df9f3 | balrog | ch->status = 0;
|
1461 | 827df9f3 | balrog | } |
1462 | 827df9f3 | balrog | if ((s->irqstat[0] |= s->irqen[0] & bmp)) |
1463 | 827df9f3 | balrog | qemu_irq_raise(s->irq[0]);
|
1464 | 827df9f3 | balrog | if ((s->irqstat[1] |= s->irqen[1] & bmp)) |
1465 | 827df9f3 | balrog | qemu_irq_raise(s->irq[1]);
|
1466 | 827df9f3 | balrog | if ((s->irqstat[2] |= s->irqen[2] & bmp)) |
1467 | 827df9f3 | balrog | qemu_irq_raise(s->irq[2]);
|
1468 | 827df9f3 | balrog | if ((s->irqstat[3] |= s->irqen[3] & bmp)) |
1469 | 827df9f3 | balrog | qemu_irq_raise(s->irq[3]);
|
1470 | 827df9f3 | balrog | } |
1471 | 827df9f3 | balrog | |
1472 | 827df9f3 | balrog | static uint32_t omap_dma4_read(void *opaque, target_phys_addr_t addr) |
1473 | 827df9f3 | balrog | { |
1474 | 827df9f3 | balrog | struct omap_dma_s *s = (struct omap_dma_s *) opaque; |
1475 | 827df9f3 | balrog | int irqn = 0, chnum, offset = addr - s->base; |
1476 | 827df9f3 | balrog | struct omap_dma_channel_s *ch;
|
1477 | 827df9f3 | balrog | |
1478 | 827df9f3 | balrog | switch (offset) {
|
1479 | 827df9f3 | balrog | case 0x00: /* DMA4_REVISION */ |
1480 | 827df9f3 | balrog | return 0x40; |
1481 | 827df9f3 | balrog | |
1482 | 827df9f3 | balrog | case 0x14: /* DMA4_IRQSTATUS_L3 */ |
1483 | 827df9f3 | balrog | irqn ++; |
1484 | 827df9f3 | balrog | case 0x10: /* DMA4_IRQSTATUS_L2 */ |
1485 | 827df9f3 | balrog | irqn ++; |
1486 | 827df9f3 | balrog | case 0x0c: /* DMA4_IRQSTATUS_L1 */ |
1487 | 827df9f3 | balrog | irqn ++; |
1488 | 827df9f3 | balrog | case 0x08: /* DMA4_IRQSTATUS_L0 */ |
1489 | 827df9f3 | balrog | return s->irqstat[irqn];
|
1490 | 827df9f3 | balrog | |
1491 | 827df9f3 | balrog | case 0x24: /* DMA4_IRQENABLE_L3 */ |
1492 | 827df9f3 | balrog | irqn ++; |
1493 | 827df9f3 | balrog | case 0x20: /* DMA4_IRQENABLE_L2 */ |
1494 | 827df9f3 | balrog | irqn ++; |
1495 | 827df9f3 | balrog | case 0x1c: /* DMA4_IRQENABLE_L1 */ |
1496 | 827df9f3 | balrog | irqn ++; |
1497 | 827df9f3 | balrog | case 0x18: /* DMA4_IRQENABLE_L0 */ |
1498 | 827df9f3 | balrog | return s->irqen[irqn];
|
1499 | 827df9f3 | balrog | |
1500 | 827df9f3 | balrog | case 0x28: /* DMA4_SYSSTATUS */ |
1501 | 827df9f3 | balrog | return 1; /* RESETDONE */ |
1502 | 827df9f3 | balrog | |
1503 | 827df9f3 | balrog | case 0x2c: /* DMA4_OCP_SYSCONFIG */ |
1504 | 827df9f3 | balrog | return s->ocp;
|
1505 | 827df9f3 | balrog | |
1506 | 827df9f3 | balrog | case 0x64: /* DMA4_CAPS_0 */ |
1507 | 827df9f3 | balrog | return s->caps[0]; |
1508 | 827df9f3 | balrog | case 0x6c: /* DMA4_CAPS_2 */ |
1509 | 827df9f3 | balrog | return s->caps[2]; |
1510 | 827df9f3 | balrog | case 0x70: /* DMA4_CAPS_3 */ |
1511 | 827df9f3 | balrog | return s->caps[3]; |
1512 | 827df9f3 | balrog | case 0x74: /* DMA4_CAPS_4 */ |
1513 | 827df9f3 | balrog | return s->caps[4]; |
1514 | 827df9f3 | balrog | |
1515 | 827df9f3 | balrog | case 0x78: /* DMA4_GCR */ |
1516 | 827df9f3 | balrog | return s->gcr;
|
1517 | 827df9f3 | balrog | |
1518 | 827df9f3 | balrog | case 0x80 ... 0xfff: |
1519 | 827df9f3 | balrog | offset -= 0x80;
|
1520 | 827df9f3 | balrog | chnum = offset / 0x60;
|
1521 | 827df9f3 | balrog | ch = s->ch + chnum; |
1522 | 827df9f3 | balrog | offset -= chnum * 0x60;
|
1523 | 827df9f3 | balrog | break;
|
1524 | 827df9f3 | balrog | |
1525 | 827df9f3 | balrog | default:
|
1526 | 827df9f3 | balrog | OMAP_BAD_REG(addr); |
1527 | 827df9f3 | balrog | return 0; |
1528 | 827df9f3 | balrog | } |
1529 | 827df9f3 | balrog | |
1530 | 827df9f3 | balrog | /* Per-channel registers */
|
1531 | 827df9f3 | balrog | switch (offset) {
|
1532 | 827df9f3 | balrog | case 0x00: /* DMA4_CCR */ |
1533 | 827df9f3 | balrog | return (ch->buf_disable << 25) | |
1534 | 827df9f3 | balrog | (ch->src_sync << 24) |
|
1535 | 827df9f3 | balrog | (ch->prefetch << 23) |
|
1536 | 827df9f3 | balrog | ((ch->sync & 0x60) << 14) | |
1537 | 827df9f3 | balrog | (ch->bs << 18) |
|
1538 | 827df9f3 | balrog | (ch->transparent_copy << 17) |
|
1539 | 827df9f3 | balrog | (ch->constant_fill << 16) |
|
1540 | 827df9f3 | balrog | (ch->mode[1] << 14) | |
1541 | 827df9f3 | balrog | (ch->mode[0] << 12) | |
1542 | 827df9f3 | balrog | (0 << 10) | (0 << 9) | |
1543 | 827df9f3 | balrog | (ch->suspend << 8) |
|
1544 | 827df9f3 | balrog | (ch->enable << 7) |
|
1545 | 827df9f3 | balrog | (ch->priority << 6) |
|
1546 | 827df9f3 | balrog | (ch->fs << 5) | (ch->sync & 0x1f); |
1547 | 827df9f3 | balrog | |
1548 | 827df9f3 | balrog | case 0x04: /* DMA4_CLNK_CTRL */ |
1549 | 827df9f3 | balrog | return (ch->link_enabled << 15) | ch->link_next_ch; |
1550 | 827df9f3 | balrog | |
1551 | 827df9f3 | balrog | case 0x08: /* DMA4_CICR */ |
1552 | 827df9f3 | balrog | return ch->interrupts;
|
1553 | 827df9f3 | balrog | |
1554 | 827df9f3 | balrog | case 0x0c: /* DMA4_CSR */ |
1555 | 827df9f3 | balrog | return ch->cstatus;
|
1556 | 827df9f3 | balrog | |
1557 | 827df9f3 | balrog | case 0x10: /* DMA4_CSDP */ |
1558 | 827df9f3 | balrog | return (ch->endian[0] << 21) | |
1559 | 827df9f3 | balrog | (ch->endian_lock[0] << 20) | |
1560 | 827df9f3 | balrog | (ch->endian[1] << 19) | |
1561 | 827df9f3 | balrog | (ch->endian_lock[1] << 18) | |
1562 | 827df9f3 | balrog | (ch->write_mode << 16) |
|
1563 | 827df9f3 | balrog | (ch->burst[1] << 14) | |
1564 | 827df9f3 | balrog | (ch->pack[1] << 13) | |
1565 | 827df9f3 | balrog | (ch->translate[1] << 9) | |
1566 | 827df9f3 | balrog | (ch->burst[0] << 7) | |
1567 | 827df9f3 | balrog | (ch->pack[0] << 6) | |
1568 | 827df9f3 | balrog | (ch->translate[0] << 2) | |
1569 | 827df9f3 | balrog | (ch->data_type >> 1);
|
1570 | 827df9f3 | balrog | |
1571 | 827df9f3 | balrog | case 0x14: /* DMA4_CEN */ |
1572 | 827df9f3 | balrog | return ch->elements;
|
1573 | 827df9f3 | balrog | |
1574 | 827df9f3 | balrog | case 0x18: /* DMA4_CFN */ |
1575 | 827df9f3 | balrog | return ch->frames;
|
1576 | 827df9f3 | balrog | |
1577 | 827df9f3 | balrog | case 0x1c: /* DMA4_CSSA */ |
1578 | 827df9f3 | balrog | return ch->addr[0]; |
1579 | 827df9f3 | balrog | |
1580 | 827df9f3 | balrog | case 0x20: /* DMA4_CDSA */ |
1581 | 827df9f3 | balrog | return ch->addr[1]; |
1582 | 827df9f3 | balrog | |
1583 | 827df9f3 | balrog | case 0x24: /* DMA4_CSEI */ |
1584 | 827df9f3 | balrog | return ch->element_index[0]; |
1585 | 827df9f3 | balrog | |
1586 | 827df9f3 | balrog | case 0x28: /* DMA4_CSFI */ |
1587 | 827df9f3 | balrog | return ch->frame_index[0]; |
1588 | 827df9f3 | balrog | |
1589 | 827df9f3 | balrog | case 0x2c: /* DMA4_CDEI */ |
1590 | 827df9f3 | balrog | return ch->element_index[1]; |
1591 | 827df9f3 | balrog | |
1592 | 827df9f3 | balrog | case 0x30: /* DMA4_CDFI */ |
1593 | 827df9f3 | balrog | return ch->frame_index[1]; |
1594 | 827df9f3 | balrog | |
1595 | 827df9f3 | balrog | case 0x34: /* DMA4_CSAC */ |
1596 | 827df9f3 | balrog | return ch->active_set.src & 0xffff; |
1597 | 827df9f3 | balrog | |
1598 | 827df9f3 | balrog | case 0x38: /* DMA4_CDAC */ |
1599 | 827df9f3 | balrog | return ch->active_set.dest & 0xffff; |
1600 | 827df9f3 | balrog | |
1601 | 827df9f3 | balrog | case 0x3c: /* DMA4_CCEN */ |
1602 | 827df9f3 | balrog | return ch->active_set.element;
|
1603 | 827df9f3 | balrog | |
1604 | 827df9f3 | balrog | case 0x40: /* DMA4_CCFN */ |
1605 | 827df9f3 | balrog | return ch->active_set.frame;
|
1606 | 827df9f3 | balrog | |
1607 | 827df9f3 | balrog | case 0x44: /* DMA4_COLOR */ |
1608 | 827df9f3 | balrog | /* XXX only in sDMA */
|
1609 | 827df9f3 | balrog | return ch->color;
|
1610 | 827df9f3 | balrog | |
1611 | 827df9f3 | balrog | default:
|
1612 | 827df9f3 | balrog | OMAP_BAD_REG(addr); |
1613 | 827df9f3 | balrog | return 0; |
1614 | 827df9f3 | balrog | } |
1615 | 827df9f3 | balrog | } |
1616 | 827df9f3 | balrog | |
1617 | 827df9f3 | balrog | static void omap_dma4_write(void *opaque, target_phys_addr_t addr, |
1618 | 827df9f3 | balrog | uint32_t value) |
1619 | 827df9f3 | balrog | { |
1620 | 827df9f3 | balrog | struct omap_dma_s *s = (struct omap_dma_s *) opaque; |
1621 | 827df9f3 | balrog | int chnum, irqn = 0, offset = addr - s->base; |
1622 | 827df9f3 | balrog | struct omap_dma_channel_s *ch;
|
1623 | 827df9f3 | balrog | |
1624 | 827df9f3 | balrog | switch (offset) {
|
1625 | 827df9f3 | balrog | case 0x14: /* DMA4_IRQSTATUS_L3 */ |
1626 | 827df9f3 | balrog | irqn ++; |
1627 | 827df9f3 | balrog | case 0x10: /* DMA4_IRQSTATUS_L2 */ |
1628 | 827df9f3 | balrog | irqn ++; |
1629 | 827df9f3 | balrog | case 0x0c: /* DMA4_IRQSTATUS_L1 */ |
1630 | 827df9f3 | balrog | irqn ++; |
1631 | 827df9f3 | balrog | case 0x08: /* DMA4_IRQSTATUS_L0 */ |
1632 | 827df9f3 | balrog | s->irqstat[irqn] &= ~value; |
1633 | 827df9f3 | balrog | if (!s->irqstat[irqn])
|
1634 | 827df9f3 | balrog | qemu_irq_lower(s->irq[irqn]); |
1635 | 827df9f3 | balrog | return;
|
1636 | 827df9f3 | balrog | |
1637 | 827df9f3 | balrog | case 0x24: /* DMA4_IRQENABLE_L3 */ |
1638 | 827df9f3 | balrog | irqn ++; |
1639 | 827df9f3 | balrog | case 0x20: /* DMA4_IRQENABLE_L2 */ |
1640 | 827df9f3 | balrog | irqn ++; |
1641 | 827df9f3 | balrog | case 0x1c: /* DMA4_IRQENABLE_L1 */ |
1642 | 827df9f3 | balrog | irqn ++; |
1643 | 827df9f3 | balrog | case 0x18: /* DMA4_IRQENABLE_L0 */ |
1644 | 827df9f3 | balrog | s->irqen[irqn] = value; |
1645 | 827df9f3 | balrog | return;
|
1646 | 827df9f3 | balrog | |
1647 | 827df9f3 | balrog | case 0x2c: /* DMA4_OCP_SYSCONFIG */ |
1648 | 827df9f3 | balrog | if (value & 2) /* SOFTRESET */ |
1649 | 827df9f3 | balrog | omap_dma_reset(s); |
1650 | 827df9f3 | balrog | s->ocp = value & 0x3321;
|
1651 | 827df9f3 | balrog | if (((s->ocp >> 12) & 3) == 3) /* MIDLEMODE */ |
1652 | 827df9f3 | balrog | fprintf(stderr, "%s: invalid DMA power mode\n", __FUNCTION__);
|
1653 | 827df9f3 | balrog | return;
|
1654 | 827df9f3 | balrog | |
1655 | 827df9f3 | balrog | case 0x78: /* DMA4_GCR */ |
1656 | 827df9f3 | balrog | s->gcr = value & 0x00ff00ff;
|
1657 | 827df9f3 | balrog | if ((value & 0xff) == 0x00) /* MAX_CHANNEL_FIFO_DEPTH */ |
1658 | 827df9f3 | balrog | fprintf(stderr, "%s: wrong FIFO depth in GCR\n", __FUNCTION__);
|
1659 | 827df9f3 | balrog | return;
|
1660 | 827df9f3 | balrog | |
1661 | 827df9f3 | balrog | case 0x80 ... 0xfff: |
1662 | 827df9f3 | balrog | offset -= 0x80;
|
1663 | 827df9f3 | balrog | chnum = offset / 0x60;
|
1664 | 827df9f3 | balrog | ch = s->ch + chnum; |
1665 | 827df9f3 | balrog | offset -= chnum * 0x60;
|
1666 | 827df9f3 | balrog | break;
|
1667 | 827df9f3 | balrog | |
1668 | 827df9f3 | balrog | case 0x00: /* DMA4_REVISION */ |
1669 | 827df9f3 | balrog | case 0x28: /* DMA4_SYSSTATUS */ |
1670 | 827df9f3 | balrog | case 0x64: /* DMA4_CAPS_0 */ |
1671 | 827df9f3 | balrog | case 0x6c: /* DMA4_CAPS_2 */ |
1672 | 827df9f3 | balrog | case 0x70: /* DMA4_CAPS_3 */ |
1673 | 827df9f3 | balrog | case 0x74: /* DMA4_CAPS_4 */ |
1674 | 827df9f3 | balrog | OMAP_RO_REG(addr); |
1675 | 827df9f3 | balrog | return;
|
1676 | 827df9f3 | balrog | |
1677 | 827df9f3 | balrog | default:
|
1678 | 827df9f3 | balrog | OMAP_BAD_REG(addr); |
1679 | 827df9f3 | balrog | return;
|
1680 | 827df9f3 | balrog | } |
1681 | 827df9f3 | balrog | |
1682 | 827df9f3 | balrog | /* Per-channel registers */
|
1683 | 827df9f3 | balrog | switch (offset) {
|
1684 | 827df9f3 | balrog | case 0x00: /* DMA4_CCR */ |
1685 | 827df9f3 | balrog | ch->buf_disable = (value >> 25) & 1; |
1686 | 827df9f3 | balrog | ch->src_sync = (value >> 24) & 1; /* XXX For CamDMA must be 1 */ |
1687 | 827df9f3 | balrog | if (ch->buf_disable && !ch->src_sync)
|
1688 | 827df9f3 | balrog | fprintf(stderr, "%s: Buffering disable is not allowed in "
|
1689 | 827df9f3 | balrog | "destination synchronised mode\n", __FUNCTION__);
|
1690 | 827df9f3 | balrog | ch->prefetch = (value >> 23) & 1; |
1691 | 827df9f3 | balrog | ch->bs = (value >> 18) & 1; |
1692 | 827df9f3 | balrog | ch->transparent_copy = (value >> 17) & 1; |
1693 | 827df9f3 | balrog | ch->constant_fill = (value >> 16) & 1; |
1694 | 827df9f3 | balrog | ch->mode[1] = (omap_dma_addressing_t) ((value & 0xc000) >> 14); |
1695 | 827df9f3 | balrog | ch->mode[0] = (omap_dma_addressing_t) ((value & 0x3000) >> 12); |
1696 | 827df9f3 | balrog | ch->suspend = (value & 0x0100) >> 8; |
1697 | 827df9f3 | balrog | ch->priority = (value & 0x0040) >> 6; |
1698 | 827df9f3 | balrog | ch->fs = (value & 0x0020) >> 5; |
1699 | 827df9f3 | balrog | if (ch->fs && ch->bs && ch->mode[0] && ch->mode[1]) |
1700 | 827df9f3 | balrog | fprintf(stderr, "%s: For a packet transfer at least one port "
|
1701 | 827df9f3 | balrog | "must be constant-addressed\n", __FUNCTION__);
|
1702 | 827df9f3 | balrog | ch->sync = (value & 0x001f) | ((value >> 14) & 0x0060); |
1703 | 827df9f3 | balrog | /* XXX must be 0x01 for CamDMA */
|
1704 | 827df9f3 | balrog | |
1705 | 827df9f3 | balrog | if (value & 0x0080) |
1706 | 827df9f3 | balrog | omap_dma_enable_channel(s, ch); |
1707 | 827df9f3 | balrog | else
|
1708 | 827df9f3 | balrog | omap_dma_disable_channel(s, ch); |
1709 | 827df9f3 | balrog | |
1710 | 827df9f3 | balrog | break;
|
1711 | 827df9f3 | balrog | |
1712 | 827df9f3 | balrog | case 0x04: /* DMA4_CLNK_CTRL */ |
1713 | 827df9f3 | balrog | ch->link_enabled = (value >> 15) & 0x1; |
1714 | 827df9f3 | balrog | ch->link_next_ch = value & 0x1f;
|
1715 | 827df9f3 | balrog | break;
|
1716 | 827df9f3 | balrog | |
1717 | 827df9f3 | balrog | case 0x08: /* DMA4_CICR */ |
1718 | 827df9f3 | balrog | ch->interrupts = value & 0x09be;
|
1719 | 827df9f3 | balrog | break;
|
1720 | 827df9f3 | balrog | |
1721 | 827df9f3 | balrog | case 0x0c: /* DMA4_CSR */ |
1722 | 827df9f3 | balrog | ch->cstatus &= ~value; |
1723 | 827df9f3 | balrog | break;
|
1724 | 827df9f3 | balrog | |
1725 | 827df9f3 | balrog | case 0x10: /* DMA4_CSDP */ |
1726 | 827df9f3 | balrog | ch->endian[0] =(value >> 21) & 1; |
1727 | 827df9f3 | balrog | ch->endian_lock[0] =(value >> 20) & 1; |
1728 | 827df9f3 | balrog | ch->endian[1] =(value >> 19) & 1; |
1729 | 827df9f3 | balrog | ch->endian_lock[1] =(value >> 18) & 1; |
1730 | 827df9f3 | balrog | if (ch->endian[0] != ch->endian[1]) |
1731 | 827df9f3 | balrog | fprintf(stderr, "%s: DMA endianned conversion enable attempt\n",
|
1732 | 827df9f3 | balrog | __FUNCTION__); |
1733 | 827df9f3 | balrog | ch->write_mode = (value >> 16) & 3; |
1734 | 827df9f3 | balrog | ch->burst[1] = (value & 0xc000) >> 14; |
1735 | 827df9f3 | balrog | ch->pack[1] = (value & 0x2000) >> 13; |
1736 | 827df9f3 | balrog | ch->translate[1] = (value & 0x1e00) >> 9; |
1737 | 827df9f3 | balrog | ch->burst[0] = (value & 0x0180) >> 7; |
1738 | 827df9f3 | balrog | ch->pack[0] = (value & 0x0040) >> 6; |
1739 | 827df9f3 | balrog | ch->translate[0] = (value & 0x003c) >> 2; |
1740 | 827df9f3 | balrog | if (ch->translate[0] | ch->translate[1]) |
1741 | 827df9f3 | balrog | fprintf(stderr, "%s: bad MReqAddressTranslate sideband signal\n",
|
1742 | 827df9f3 | balrog | __FUNCTION__); |
1743 | 827df9f3 | balrog | ch->data_type = 1 << (value & 3); |
1744 | 827df9f3 | balrog | if ((value & 3) == 3) |
1745 | 827df9f3 | balrog | printf("%s: bad data_type for DMA channel\n", __FUNCTION__);
|
1746 | 827df9f3 | balrog | break;
|
1747 | 827df9f3 | balrog | |
1748 | 827df9f3 | balrog | case 0x14: /* DMA4_CEN */ |
1749 | 827df9f3 | balrog | ch->elements = value & 0xffffff;
|
1750 | 827df9f3 | balrog | break;
|
1751 | 827df9f3 | balrog | |
1752 | 827df9f3 | balrog | case 0x18: /* DMA4_CFN */ |
1753 | 827df9f3 | balrog | ch->frames = value & 0xffff;
|
1754 | 827df9f3 | balrog | break;
|
1755 | 827df9f3 | balrog | |
1756 | 827df9f3 | balrog | case 0x1c: /* DMA4_CSSA */ |
1757 | 827df9f3 | balrog | ch->addr[0] = (target_phys_addr_t) (uint32_t) value;
|
1758 | 827df9f3 | balrog | break;
|
1759 | 827df9f3 | balrog | |
1760 | 827df9f3 | balrog | case 0x20: /* DMA4_CDSA */ |
1761 | 827df9f3 | balrog | ch->addr[1] = (target_phys_addr_t) (uint32_t) value;
|
1762 | 827df9f3 | balrog | break;
|
1763 | 827df9f3 | balrog | |
1764 | 827df9f3 | balrog | case 0x24: /* DMA4_CSEI */ |
1765 | 827df9f3 | balrog | ch->element_index[0] = (int16_t) value;
|
1766 | 827df9f3 | balrog | break;
|
1767 | 827df9f3 | balrog | |
1768 | 827df9f3 | balrog | case 0x28: /* DMA4_CSFI */ |
1769 | 827df9f3 | balrog | ch->frame_index[0] = (int32_t) value;
|
1770 | 827df9f3 | balrog | break;
|
1771 | 827df9f3 | balrog | |
1772 | 827df9f3 | balrog | case 0x2c: /* DMA4_CDEI */ |
1773 | 827df9f3 | balrog | ch->element_index[1] = (int16_t) value;
|
1774 | 827df9f3 | balrog | break;
|
1775 | 827df9f3 | balrog | |
1776 | 827df9f3 | balrog | case 0x30: /* DMA4_CDFI */ |
1777 | 827df9f3 | balrog | ch->frame_index[1] = (int32_t) value;
|
1778 | 827df9f3 | balrog | break;
|
1779 | 827df9f3 | balrog | |
1780 | 827df9f3 | balrog | case 0x44: /* DMA4_COLOR */ |
1781 | 827df9f3 | balrog | /* XXX only in sDMA */
|
1782 | 827df9f3 | balrog | ch->color = value; |
1783 | 827df9f3 | balrog | break;
|
1784 | 827df9f3 | balrog | |
1785 | 827df9f3 | balrog | case 0x34: /* DMA4_CSAC */ |
1786 | 827df9f3 | balrog | case 0x38: /* DMA4_CDAC */ |
1787 | 827df9f3 | balrog | case 0x3c: /* DMA4_CCEN */ |
1788 | 827df9f3 | balrog | case 0x40: /* DMA4_CCFN */ |
1789 | 827df9f3 | balrog | OMAP_RO_REG(addr); |
1790 | 827df9f3 | balrog | break;
|
1791 | 827df9f3 | balrog | |
1792 | 827df9f3 | balrog | default:
|
1793 | 827df9f3 | balrog | OMAP_BAD_REG(addr); |
1794 | 827df9f3 | balrog | } |
1795 | 827df9f3 | balrog | } |
1796 | 827df9f3 | balrog | |
1797 | 827df9f3 | balrog | static CPUReadMemoryFunc *omap_dma4_readfn[] = {
|
1798 | 827df9f3 | balrog | omap_badwidth_read16, |
1799 | 827df9f3 | balrog | omap_dma4_read, |
1800 | 827df9f3 | balrog | omap_dma4_read, |
1801 | 827df9f3 | balrog | }; |
1802 | 827df9f3 | balrog | |
1803 | 827df9f3 | balrog | static CPUWriteMemoryFunc *omap_dma4_writefn[] = {
|
1804 | 827df9f3 | balrog | omap_badwidth_write16, |
1805 | 827df9f3 | balrog | omap_dma4_write, |
1806 | 827df9f3 | balrog | omap_dma4_write, |
1807 | 827df9f3 | balrog | }; |
1808 | 827df9f3 | balrog | |
1809 | 827df9f3 | balrog | struct omap_dma_s *omap_dma4_init(target_phys_addr_t base, qemu_irq *irqs,
|
1810 | 827df9f3 | balrog | struct omap_mpu_state_s *mpu, int fifo, |
1811 | 827df9f3 | balrog | int chans, omap_clk iclk, omap_clk fclk)
|
1812 | 827df9f3 | balrog | { |
1813 | 827df9f3 | balrog | int iomemtype;
|
1814 | 827df9f3 | balrog | struct omap_dma_s *s = (struct omap_dma_s *) |
1815 | 827df9f3 | balrog | qemu_mallocz(sizeof(struct omap_dma_s)); |
1816 | 827df9f3 | balrog | |
1817 | 827df9f3 | balrog | s->base = base; |
1818 | 827df9f3 | balrog | s->model = omap_dma_4; |
1819 | 827df9f3 | balrog | s->chans = chans; |
1820 | 827df9f3 | balrog | s->mpu = mpu; |
1821 | 827df9f3 | balrog | s->clk = fclk; |
1822 | 827df9f3 | balrog | memcpy(&s->irq, irqs, sizeof(s->irq));
|
1823 | 827df9f3 | balrog | s->intr_update = omap_dma_interrupts_4_update; |
1824 | 827df9f3 | balrog | omap_dma_setcaps(s); |
1825 | 827df9f3 | balrog | s->tm = qemu_new_timer(vm_clock, (QEMUTimerCB *) omap_dma_channel_run, s); |
1826 | 827df9f3 | balrog | omap_clk_adduser(s->clk, qemu_allocate_irqs(omap_dma_clk_update, s, 1)[0]); |
1827 | 827df9f3 | balrog | mpu->drq = qemu_allocate_irqs(omap_dma_request, s, 64);
|
1828 | 827df9f3 | balrog | omap_dma_reset(s); |
1829 | 827df9f3 | balrog | omap_dma_clk_update(s, 0, 1); |
1830 | 827df9f3 | balrog | |
1831 | 827df9f3 | balrog | iomemtype = cpu_register_io_memory(0, omap_dma4_readfn,
|
1832 | 827df9f3 | balrog | omap_dma4_writefn, s); |
1833 | 827df9f3 | balrog | cpu_register_physical_memory(s->base, 0x1000, iomemtype);
|
1834 | 827df9f3 | balrog | |
1835 | 827df9f3 | balrog | return s;
|
1836 | 827df9f3 | balrog | } |
1837 | 827df9f3 | balrog | |
1838 | b4e3104b | balrog | struct omap_dma_lcd_channel_s *omap_dma_get_lcdch(struct omap_dma_s *s) |
1839 | b4e3104b | balrog | { |
1840 | b4e3104b | balrog | return &s->lcd_ch;
|
1841 | b4e3104b | balrog | } |