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/*
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 * OMAP clocks.
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 *
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 * Copyright (C) 2006-2008 Andrzej Zaborowski  <balrog@zabor.org>
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 *
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 * Clocks data comes in part from arch/arm/mach-omap1/clock.h in Linux.
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 *
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 * This program is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU General Public License as
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 * published by the Free Software Foundation; either version 2 of
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 * the License, or (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 *
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 * You should have received a copy of the GNU General Public License
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 * along with this program; if not, write to the Free Software
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 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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 * MA 02111-1307 USA
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 */
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#include "hw.h"
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#include "omap.h"
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struct clk {
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    const char *name;
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    const char *alias;
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    struct clk *parent;
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    struct clk *child1;
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    struct clk *sibling;
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#define ALWAYS_ENABLED                (1 << 0)
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#define CLOCK_IN_OMAP310        (1 << 10)
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#define CLOCK_IN_OMAP730        (1 << 11)
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#define CLOCK_IN_OMAP1510        (1 << 12)
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#define CLOCK_IN_OMAP16XX        (1 << 13)
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#define CLOCK_IN_OMAP242X        (1 << 14)
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#define CLOCK_IN_OMAP243X        (1 << 15)
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#define CLOCK_IN_OMAP343X        (1 << 16)
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    uint32_t flags;
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    int id;
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    int running;                /* Is currently ticking */
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    int enabled;                /* Is enabled, regardless of its input clk */
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    unsigned long rate;                /* Current rate (if .running) */
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    unsigned int divisor;        /* Rate relative to input (if .enabled) */
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    unsigned int multiplier;        /* Rate relative to input (if .enabled) */
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    qemu_irq users[16];                /* Who to notify on change */
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    int usecount;                /* Automatically idle when unused */
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};
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static struct clk xtal_osc12m = {
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    .name        = "xtal_osc_12m",
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    .rate        = 12000000,
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    .flags        = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310,
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};
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static struct clk xtal_osc32k = {
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    .name        = "xtal_osc_32k",
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    .rate        = 32768,
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    .flags        = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 |
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            CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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};
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static struct clk ck_ref = {
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    .name        = "ck_ref",
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    .alias        = "clkin",
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    .parent        = &xtal_osc12m,
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    .flags        = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 |
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            ALWAYS_ENABLED,
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};
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/* If a dpll is disabled it becomes a bypass, child clocks don't stop */
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static struct clk dpll1 = {
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    .name        = "dpll1",
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    .parent        = &ck_ref,
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    .flags        = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 |
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            ALWAYS_ENABLED,
79
};
80

    
81
static struct clk dpll2 = {
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    .name        = "dpll2",
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    .parent        = &ck_ref,
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    .flags        = CLOCK_IN_OMAP310 | ALWAYS_ENABLED,
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};
86

    
87
static struct clk dpll3 = {
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    .name        = "dpll3",
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    .parent        = &ck_ref,
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    .flags        = CLOCK_IN_OMAP310 | ALWAYS_ENABLED,
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};
92

    
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static struct clk dpll4 = {
94
    .name        = "dpll4",
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    .parent        = &ck_ref,
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    .multiplier        = 4,
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    .flags        = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310,
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};
99

    
100
static struct clk apll = {
101
    .name        = "apll",
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    .parent        = &ck_ref,
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    .multiplier        = 48,
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    .divisor        = 12,
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    .flags        = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310,
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};
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static struct clk ck_48m = {
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    .name        = "ck_48m",
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    .parent        = &dpll4,        /* either dpll4 or apll */
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    .flags        = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310,
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};
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static struct clk ck_dpll1out = {
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    .name        = "ck_dpll1out",
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    .parent        = &dpll1,
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    .flags        = CLOCK_IN_OMAP16XX,
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};
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static struct clk sossi_ck = {
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    .name        = "ck_sossi",
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    .parent        = &ck_dpll1out,
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    .flags        = CLOCK_IN_OMAP16XX,
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};
125

    
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static struct clk clkm1 = {
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    .name        = "clkm1",
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    .alias        = "ck_gen1",
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    .parent        = &dpll1,
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    .flags        = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 |
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            ALWAYS_ENABLED,
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};
133

    
134
static struct clk clkm2 = {
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    .name        = "clkm2",
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    .alias        = "ck_gen2",
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    .parent        = &dpll1,
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    .flags        = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 |
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            ALWAYS_ENABLED,
140
};
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static struct clk clkm3 = {
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    .name        = "clkm3",
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    .alias        = "ck_gen3",
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    .parent        = &dpll1,        /* either dpll1 or ck_ref */
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    .flags        = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 |
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            ALWAYS_ENABLED,
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};
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static struct clk arm_ck = {
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    .name        = "arm_ck",
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    .alias        = "mpu_ck",
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    .parent        = &clkm1,
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    .flags        = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 |
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            ALWAYS_ENABLED,
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};
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static struct clk armper_ck = {
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    .name        = "armper_ck",
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    .alias        = "mpuper_ck",
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    .parent        = &clkm1,
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    .flags        = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310,
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};
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static struct clk arm_gpio_ck = {
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    .name        = "arm_gpio_ck",
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    .alias        = "mpu_gpio_ck",
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    .parent        = &clkm1,
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    .divisor        = 1,
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    .flags        = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310,
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};
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173
static struct clk armxor_ck = {
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    .name        = "armxor_ck",
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    .alias        = "mpuxor_ck",
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    .parent        = &ck_ref,
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    .flags        = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310,
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};
179

    
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static struct clk armtim_ck = {
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    .name        = "armtim_ck",
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    .alias        = "mputim_ck",
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    .parent        = &ck_ref,        /* either CLKIN or DPLL1 */
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    .flags        = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310,
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};
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static struct clk armwdt_ck = {
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    .name        = "armwdt_ck",
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    .alias        = "mpuwd_ck",
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    .parent        = &clkm1,
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    .divisor        = 14,
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    .flags        = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 |
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            ALWAYS_ENABLED,
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};
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static struct clk arminth_ck16xx = {
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    .name        = "arminth_ck",
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    .parent        = &arm_ck,
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    .flags        = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
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    /* Note: On 16xx the frequency can be divided by 2 by programming
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     * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1
202
     *
203
     * 1510 version is in TC clocks.
204
     */
205
};
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static struct clk dsp_ck = {
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    .name        = "dsp_ck",
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    .parent        = &clkm2,
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    .flags        = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
211
};
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static struct clk dspmmu_ck = {
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    .name        = "dspmmu_ck",
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    .parent        = &clkm2,
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    .flags        = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
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            ALWAYS_ENABLED,
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};
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static struct clk dspper_ck = {
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    .name        = "dspper_ck",
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    .parent        = &clkm2,
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    .flags        = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
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};
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static struct clk dspxor_ck = {
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    .name        = "dspxor_ck",
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    .parent        = &ck_ref,
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    .flags        = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
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};
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static struct clk dsptim_ck = {
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    .name        = "dsptim_ck",
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    .parent        = &ck_ref,
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    .flags        = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
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};
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static struct clk tc_ck = {
239
    .name        = "tc_ck",
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    .parent        = &clkm3,
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    .flags        = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
242
            CLOCK_IN_OMAP730 | CLOCK_IN_OMAP310 |
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            ALWAYS_ENABLED,
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};
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246
static struct clk arminth_ck15xx = {
247
    .name        = "arminth_ck",
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    .parent        = &tc_ck,
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    .flags        = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | ALWAYS_ENABLED,
250
    /* Note: On 1510 the frequency follows TC_CK
251
     *
252
     * 16xx version is in MPU clocks.
253
     */
254
};
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256
static struct clk tipb_ck = {
257
    /* No-idle controlled by "tc_ck" */
258
    .name        = "tipb_ck",
259
    .parent        = &tc_ck,
260
    .flags        = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | ALWAYS_ENABLED,
261
};
262

    
263
static struct clk l3_ocpi_ck = {
264
    /* No-idle controlled by "tc_ck" */
265
    .name        = "l3_ocpi_ck",
266
    .parent        = &tc_ck,
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    .flags        = CLOCK_IN_OMAP16XX,
268
};
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270
static struct clk tc1_ck = {
271
    .name        = "tc1_ck",
272
    .parent        = &tc_ck,
273
    .flags        = CLOCK_IN_OMAP16XX,
274
};
275

    
276
static struct clk tc2_ck = {
277
    .name        = "tc2_ck",
278
    .parent        = &tc_ck,
279
    .flags        = CLOCK_IN_OMAP16XX,
280
};
281

    
282
static struct clk dma_ck = {
283
    /* No-idle controlled by "tc_ck" */
284
    .name        = "dma_ck",
285
    .parent        = &tc_ck,
286
    .flags        = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 |
287
            ALWAYS_ENABLED,
288
};
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290
static struct clk dma_lcdfree_ck = {
291
    .name        = "dma_lcdfree_ck",
292
    .parent        = &tc_ck,
293
    .flags        = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
294
};
295

    
296
static struct clk api_ck = {
297
    .name        = "api_ck",
298
    .alias        = "mpui_ck",
299
    .parent        = &tc_ck,
300
    .flags        = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310,
301
};
302

    
303
static struct clk lb_ck = {
304
    .name        = "lb_ck",
305
    .parent        = &tc_ck,
306
    .flags        = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310,
307
};
308

    
309
static struct clk lbfree_ck = {
310
    .name        = "lbfree_ck",
311
    .parent        = &tc_ck,
312
    .flags        = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310,
313
};
314

    
315
static struct clk hsab_ck = {
316
    .name        = "hsab_ck",
317
    .parent        = &tc_ck,
318
    .flags        = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310,
319
};
320

    
321
static struct clk rhea1_ck = {
322
    .name        = "rhea1_ck",
323
    .parent        = &tc_ck,
324
    .flags        = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
325
};
326

    
327
static struct clk rhea2_ck = {
328
    .name        = "rhea2_ck",
329
    .parent        = &tc_ck,
330
    .flags        = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
331
};
332

    
333
static struct clk lcd_ck_16xx = {
334
    .name        = "lcd_ck",
335
    .parent        = &clkm3,
336
    .flags        = CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP730,
337
};
338

    
339
static struct clk lcd_ck_1510 = {
340
    .name        = "lcd_ck",
341
    .parent        = &clkm3,
342
    .flags        = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310,
343
};
344

    
345
static struct clk uart1_1510 = {
346
    .name        = "uart1_ck",
347
    /* Direct from ULPD, no real parent */
348
    .parent        = &armper_ck,        /* either armper_ck or dpll4 */
349
    .rate        = 12000000,
350
    .flags        = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | ALWAYS_ENABLED,
351
};
352

    
353
static struct clk uart1_16xx = {
354
    .name        = "uart1_ck",
355
    /* Direct from ULPD, no real parent */
356
    .parent        = &armper_ck,
357
    .rate        = 48000000,
358
    .flags        = CLOCK_IN_OMAP16XX,
359
};
360

    
361
static struct clk uart2_ck = {
362
    .name        = "uart2_ck",
363
    /* Direct from ULPD, no real parent */
364
    .parent        = &armper_ck,        /* either armper_ck or dpll4 */
365
    .rate        = 12000000,
366
    .flags        = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 |
367
            ALWAYS_ENABLED,
368
};
369

    
370
static struct clk uart3_1510 = {
371
    .name        = "uart3_ck",
372
    /* Direct from ULPD, no real parent */
373
    .parent        = &armper_ck,        /* either armper_ck or dpll4 */
374
    .rate        = 12000000,
375
    .flags        = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | ALWAYS_ENABLED,
376
};
377

    
378
static struct clk uart3_16xx = {
379
    .name        = "uart3_ck",
380
    /* Direct from ULPD, no real parent */
381
    .parent        = &armper_ck,
382
    .rate        = 48000000,
383
    .flags        = CLOCK_IN_OMAP16XX,
384
};
385

    
386
static struct clk usb_clk0 = {        /* 6 MHz output on W4_USB_CLK0 */
387
    .name        = "usb_clk0",
388
    .alias        = "usb.clko",
389
    /* Direct from ULPD, no parent */
390
    .rate        = 6000000,
391
    .flags        = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310,
392
};
393

    
394
static struct clk usb_hhc_ck1510 = {
395
    .name        = "usb_hhc_ck",
396
    /* Direct from ULPD, no parent */
397
    .rate        = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */
398
    .flags        = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310,
399
};
400

    
401
static struct clk usb_hhc_ck16xx = {
402
    .name        = "usb_hhc_ck",
403
    /* Direct from ULPD, no parent */
404
    .rate        = 48000000,
405
    /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
406
    .flags        = CLOCK_IN_OMAP16XX,
407
};
408

    
409
static struct clk usb_w2fc_mclk = {
410
    .name        = "usb_w2fc_mclk",
411
    .alias        = "usb_w2fc_ck",
412
    .parent        = &ck_48m,
413
    .rate        = 48000000,
414
    .flags        = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
415
};
416

    
417
static struct clk mclk_1510 = {
418
    .name        = "mclk",
419
    /* Direct from ULPD, no parent. May be enabled by ext hardware. */
420
    .rate        = 12000000,
421
    .flags        = CLOCK_IN_OMAP1510,
422
};
423

    
424
static struct clk bclk_310 = {
425
    .name        = "bt_mclk_out",        /* Alias midi_mclk_out? */
426
    .parent        = &armper_ck,
427
    .flags        = CLOCK_IN_OMAP310,
428
};
429

    
430
static struct clk mclk_310 = {
431
    .name        = "com_mclk_out",
432
    .parent        = &armper_ck,
433
    .flags        = CLOCK_IN_OMAP310,
434
};
435

    
436
static struct clk mclk_16xx = {
437
    .name        = "mclk",
438
    /* Direct from ULPD, no parent. May be enabled by ext hardware. */
439
    .flags        = CLOCK_IN_OMAP16XX,
440
};
441

    
442
static struct clk bclk_1510 = {
443
    .name        = "bclk",
444
    /* Direct from ULPD, no parent. May be enabled by ext hardware. */
445
    .rate        = 12000000,
446
    .flags        = CLOCK_IN_OMAP1510,
447
};
448

    
449
static struct clk bclk_16xx = {
450
    .name        = "bclk",
451
    /* Direct from ULPD, no parent. May be enabled by ext hardware. */
452
    .flags        = CLOCK_IN_OMAP16XX,
453
};
454

    
455
static struct clk mmc1_ck = {
456
    .name        = "mmc_ck",
457
    .id                = 1,
458
    /* Functional clock is direct from ULPD, interface clock is ARMPER */
459
    .parent        = &armper_ck,        /* either armper_ck or dpll4 */
460
    .rate        = 48000000,
461
    .flags        = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310,
462
};
463

    
464
static struct clk mmc2_ck = {
465
    .name        = "mmc_ck",
466
    .id                = 2,
467
    /* Functional clock is direct from ULPD, interface clock is ARMPER */
468
    .parent        = &armper_ck,
469
    .rate        = 48000000,
470
    .flags        = CLOCK_IN_OMAP16XX,
471
};
472

    
473
static struct clk cam_mclk = {
474
    .name        = "cam.mclk",
475
    .flags        = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
476
    .rate        = 12000000,
477
};
478

    
479
static struct clk cam_exclk = {
480
    .name        = "cam.exclk",
481
    .flags        = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
482
    /* Either 12M from cam.mclk or 48M from dpll4 */
483
    .parent        = &cam_mclk,
484
};
485

    
486
static struct clk cam_lclk = {
487
    .name        = "cam.lclk",
488
    .flags        = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
489
};
490

    
491
static struct clk i2c_fck = {
492
    .name        = "i2c_fck",
493
    .id                = 1,
494
    .flags        = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
495
            ALWAYS_ENABLED,
496
    .parent        = &armxor_ck,
497
};
498

    
499
static struct clk i2c_ick = {
500
    .name        = "i2c_ick",
501
    .id                = 1,
502
    .flags        = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
503
    .parent        = &armper_ck,
504
};
505

    
506
static struct clk clk32k = {
507
    .name        = "clk32-kHz",
508
    .flags        = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
509
            CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED,
510
    .parent        = &xtal_osc32k,
511
};
512

    
513
static struct clk ref_clk = {
514
    .name        = "ref_clk",
515
    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED,
516
    .rate        = 12000000,        /* 12 MHz or 13 MHz or 19.2 MHz */
517
    /*.parent        = sys.xtalin */
518
};
519

    
520
static struct clk apll_96m = {
521
    .name        = "apll_96m",
522
    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED,
523
    .rate        = 96000000,
524
    /*.parent        = ref_clk */
525
};
526

    
527
static struct clk apll_54m = {
528
    .name        = "apll_54m",
529
    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED,
530
    .rate        = 54000000,
531
    /*.parent        = ref_clk */
532
};
533

    
534
static struct clk sys_clk = {
535
    .name        = "sys_clk",
536
    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED,
537
    .rate        = 32768,
538
    /*.parent        = sys.xtalin */
539
};
540

    
541
static struct clk sleep_clk = {
542
    .name        = "sleep_clk",
543
    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED,
544
    .rate        = 32768,
545
    /*.parent        = sys.xtalin */
546
};
547

    
548
static struct clk dpll_ck = {
549
    .name        = "dpll",
550
    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED,
551
    .parent        = &ref_clk,
552
};
553

    
554
static struct clk dpll_x2_ck = {
555
    .name        = "dpll_x2",
556
    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED,
557
    .parent        = &ref_clk,
558
};
559

    
560
static struct clk wdt1_sys_clk = {
561
    .name        = "wdt1_sys_clk",
562
    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED,
563
    .rate        = 32768,
564
    /*.parent        = sys.xtalin */
565
};
566

    
567
static struct clk func_96m_clk = {
568
    .name        = "func_96m_clk",
569
    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
570
    .divisor        = 1,
571
    .parent        = &apll_96m,
572
};
573

    
574
static struct clk func_48m_clk = {
575
    .name        = "func_48m_clk",
576
    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
577
    .divisor        = 2,
578
    .parent        = &apll_96m,
579
};
580

    
581
static struct clk func_12m_clk = {
582
    .name        = "func_12m_clk",
583
    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
584
    .divisor        = 8,
585
    .parent        = &apll_96m,
586
};
587

    
588
static struct clk func_54m_clk = {
589
    .name        = "func_54m_clk",
590
    .flags        = CLOCK_IN_OMAP242X,
591
    .divisor        = 1,
592
    .parent        = &apll_54m,
593
};
594

    
595
static struct clk sys_clkout = {
596
    .name        = "clkout",
597
    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
598
    .parent        = &sys_clk,
599
};
600

    
601
static struct clk sys_clkout2 = {
602
    .name        = "clkout2",
603
    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
604
    .parent        = &sys_clk,
605
};
606

    
607
static struct clk core_clk = {
608
    .name        = "core_clk",
609
    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
610
    .parent        = &dpll_x2_ck,        /* Switchable between dpll_ck and clk32k */
611
};
612

    
613
static struct clk l3_clk = {
614
    .name        = "l3_clk",
615
    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
616
    .parent        = &core_clk,
617
};
618

    
619
static struct clk core_l4_iclk = {
620
    .name        = "core_l4_iclk",
621
    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
622
    .parent        = &l3_clk,
623
};
624

    
625
static struct clk wu_l4_iclk = {
626
    .name        = "wu_l4_iclk",
627
    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
628
    .parent        = &l3_clk,
629
};
630

    
631
static struct clk core_l3_iclk = {
632
    .name        = "core_l3_iclk",
633
    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
634
    .parent        = &core_clk,
635
};
636

    
637
static struct clk core_l4_usb_clk = {
638
    .name        = "core_l4_usb_clk",
639
    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
640
    .parent        = &l3_clk,
641
};
642

    
643
static struct clk wu_gpt1_clk = {
644
    .name        = "wu_gpt1_clk",
645
    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
646
    .parent        = &sys_clk,
647
};
648

    
649
static struct clk wu_32k_clk = {
650
    .name        = "wu_32k_clk",
651
    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
652
    .parent        = &sys_clk,
653
};
654

    
655
static struct clk uart1_fclk = {
656
    .name        = "uart1_fclk",
657
    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
658
    .parent        = &func_48m_clk,
659
};
660

    
661
static struct clk uart1_iclk = {
662
    .name        = "uart1_iclk",
663
    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
664
    .parent        = &core_l4_iclk,
665
};
666

    
667
static struct clk uart2_fclk = {
668
    .name        = "uart2_fclk",
669
    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
670
    .parent        = &func_48m_clk,
671
};
672

    
673
static struct clk uart2_iclk = {
674
    .name        = "uart2_iclk",
675
    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
676
    .parent        = &core_l4_iclk,
677
};
678

    
679
static struct clk uart3_fclk = {
680
    .name        = "uart3_fclk",
681
    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
682
    .parent        = &func_48m_clk,
683
};
684

    
685
static struct clk uart3_iclk = {
686
    .name        = "uart3_iclk",
687
    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
688
    .parent        = &core_l4_iclk,
689
};
690

    
691
static struct clk mpu_fclk = {
692
    .name        = "mpu_fclk",
693
    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
694
    .parent        = &core_clk,
695
};
696

    
697
static struct clk mpu_iclk = {
698
    .name        = "mpu_iclk",
699
    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
700
    .parent        = &core_clk,
701
};
702

    
703
static struct clk int_m_fclk = {
704
    .name        = "int_m_fclk",
705
    .alias        = "mpu_intc_fclk",
706
    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
707
    .parent        = &core_clk,
708
};
709

    
710
static struct clk int_m_iclk = {
711
    .name        = "int_m_iclk",
712
    .alias        = "mpu_intc_iclk",
713
    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
714
    .parent        = &core_clk,
715
};
716

    
717
static struct clk core_gpt2_clk = {
718
    .name        = "core_gpt2_clk",
719
    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
720
    .parent        = &sys_clk,
721
};
722

    
723
static struct clk core_gpt3_clk = {
724
    .name        = "core_gpt3_clk",
725
    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
726
    .parent        = &sys_clk,
727
};
728

    
729
static struct clk core_gpt4_clk = {
730
    .name        = "core_gpt4_clk",
731
    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
732
    .parent        = &sys_clk,
733
};
734

    
735
static struct clk core_gpt5_clk = {
736
    .name        = "core_gpt5_clk",
737
    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
738
    .parent        = &sys_clk,
739
};
740

    
741
static struct clk core_gpt6_clk = {
742
    .name        = "core_gpt6_clk",
743
    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
744
    .parent        = &sys_clk,
745
};
746

    
747
static struct clk core_gpt7_clk = {
748
    .name        = "core_gpt7_clk",
749
    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
750
    .parent        = &sys_clk,
751
};
752

    
753
static struct clk core_gpt8_clk = {
754
    .name        = "core_gpt8_clk",
755
    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
756
    .parent        = &sys_clk,
757
};
758

    
759
static struct clk core_gpt9_clk = {
760
    .name        = "core_gpt9_clk",
761
    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
762
    .parent        = &sys_clk,
763
};
764

    
765
static struct clk core_gpt10_clk = {
766
    .name        = "core_gpt10_clk",
767
    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
768
    .parent        = &sys_clk,
769
};
770

    
771
static struct clk core_gpt11_clk = {
772
    .name        = "core_gpt11_clk",
773
    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
774
    .parent        = &sys_clk,
775
};
776

    
777
static struct clk core_gpt12_clk = {
778
    .name        = "core_gpt12_clk",
779
    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
780
    .parent        = &sys_clk,
781
};
782

    
783
static struct clk mcbsp1_clk = {
784
    .name        = "mcbsp1_cg",
785
    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
786
    .divisor        = 2,
787
    .parent        = &func_96m_clk,
788
};
789

    
790
static struct clk mcbsp2_clk = {
791
    .name        = "mcbsp2_cg",
792
    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
793
    .divisor        = 2,
794
    .parent        = &func_96m_clk,
795
};
796

    
797
static struct clk emul_clk = {
798
    .name        = "emul_ck",
799
    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
800
    .parent        = &func_54m_clk,
801
};
802

    
803
static struct clk sdma_fclk = {
804
    .name        = "sdma_fclk",
805
    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
806
    .parent        = &l3_clk,
807
};
808

    
809
static struct clk sdma_iclk = {
810
    .name        = "sdma_iclk",
811
    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
812
    .parent        = &core_l3_iclk, /* core_l4_iclk for the configuration port */
813
};
814

    
815
static struct clk i2c1_fclk = {
816
    .name        = "i2c1.fclk",
817
    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
818
    .parent        = &func_12m_clk,
819
    .divisor        = 1,
820
};
821

    
822
static struct clk i2c1_iclk = {
823
    .name        = "i2c1.iclk",
824
    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
825
    .parent        = &core_l4_iclk,
826
};
827

    
828
static struct clk i2c2_fclk = {
829
    .name        = "i2c2.fclk",
830
    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
831
    .parent        = &func_12m_clk,
832
    .divisor        = 1,
833
};
834

    
835
static struct clk i2c2_iclk = {
836
    .name        = "i2c2.iclk",
837
    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
838
    .parent        = &core_l4_iclk,
839
};
840

    
841
static struct clk gpio_dbclk[4] = {
842
    {
843
        .name        = "gpio1_dbclk",
844
        .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
845
        .parent        = &wu_32k_clk,
846
    }, {
847
        .name        = "gpio2_dbclk",
848
        .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
849
        .parent        = &wu_32k_clk,
850
    }, {
851
        .name        = "gpio3_dbclk",
852
        .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
853
        .parent        = &wu_32k_clk,
854
    }, {
855
        .name        = "gpio4_dbclk",
856
        .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
857
        .parent        = &wu_32k_clk,
858
    },
859
};
860

    
861
static struct clk gpio_iclk = {
862
    .name        = "gpio_iclk",
863
    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
864
    .parent        = &wu_l4_iclk,
865
};
866

    
867
static struct clk mmc_fck = {
868
    .name        = "mmc_fclk",
869
    .flags        = CLOCK_IN_OMAP242X,
870
    .parent        = &func_96m_clk,
871
};
872

    
873
static struct clk mmc_ick = {
874
    .name        = "mmc_iclk",
875
    .flags        = CLOCK_IN_OMAP242X,
876
    .parent        = &core_l4_iclk,
877
};
878

    
879
static struct clk spi_fclk[3] = {
880
    {
881
        .name        = "spi1_fclk",
882
        .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
883
        .parent        = &func_48m_clk,
884
    }, {
885
        .name        = "spi2_fclk",
886
        .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
887
        .parent        = &func_48m_clk,
888
    }, {
889
        .name        = "spi3_fclk",
890
        .flags        = CLOCK_IN_OMAP243X,
891
        .parent        = &func_48m_clk,
892
    },
893
};
894

    
895
static struct clk dss_clk[2] = {
896
    {
897
        .name        = "dss_clk1",
898
        .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
899
        .parent        = &core_clk,
900
    }, {
901
        .name        = "dss_clk2",
902
        .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
903
        .parent        = &sys_clk,
904
    },
905
};
906

    
907
static struct clk dss_54m_clk = {
908
    .name        = "dss_54m_clk",
909
    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
910
    .parent        = &func_54m_clk,
911
};
912

    
913
static struct clk dss_l3_iclk = {
914
    .name        = "dss_l3_iclk",
915
    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
916
    .parent        = &core_l3_iclk,
917
};
918

    
919
static struct clk dss_l4_iclk = {
920
    .name        = "dss_l4_iclk",
921
    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
922
    .parent        = &core_l4_iclk,
923
};
924

    
925
static struct clk spi_iclk[3] = {
926
    {
927
        .name        = "spi1_iclk",
928
        .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
929
        .parent        = &core_l4_iclk,
930
    }, {
931
        .name        = "spi2_iclk",
932
        .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
933
        .parent        = &core_l4_iclk,
934
    }, {
935
        .name        = "spi3_iclk",
936
        .flags        = CLOCK_IN_OMAP243X,
937
        .parent        = &core_l4_iclk,
938
    },
939
};
940

    
941
static struct clk omapctrl_clk = {
942
    .name        = "omapctrl_iclk",
943
    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
944
    /* XXX Should be in WKUP domain */
945
    .parent        = &core_l4_iclk,
946
};
947

    
948
static struct clk *onchip_clks[] = {
949
    /* OMAP 1 */
950

    
951
    /* non-ULPD clocks */
952
    &xtal_osc12m,
953
    &xtal_osc32k,
954
    &ck_ref,
955
    &dpll1,
956
    &dpll2,
957
    &dpll3,
958
    &dpll4,
959
    &apll,
960
    &ck_48m,
961
    /* CK_GEN1 clocks */
962
    &clkm1,
963
    &ck_dpll1out,
964
    &sossi_ck,
965
    &arm_ck,
966
    &armper_ck,
967
    &arm_gpio_ck,
968
    &armxor_ck,
969
    &armtim_ck,
970
    &armwdt_ck,
971
    &arminth_ck15xx,  &arminth_ck16xx,
972
    /* CK_GEN2 clocks */
973
    &clkm2,
974
    &dsp_ck,
975
    &dspmmu_ck,
976
    &dspper_ck,
977
    &dspxor_ck,
978
    &dsptim_ck,
979
    /* CK_GEN3 clocks */
980
    &clkm3,
981
    &tc_ck,
982
    &tipb_ck,
983
    &l3_ocpi_ck,
984
    &tc1_ck,
985
    &tc2_ck,
986
    &dma_ck,
987
    &dma_lcdfree_ck,
988
    &api_ck,
989
    &lb_ck,
990
    &lbfree_ck,
991
    &hsab_ck,
992
    &rhea1_ck,
993
    &rhea2_ck,
994
    &lcd_ck_16xx,
995
    &lcd_ck_1510,
996
    /* ULPD clocks */
997
    &uart1_1510,
998
    &uart1_16xx,
999
    &uart2_ck,
1000
    &uart3_1510,
1001
    &uart3_16xx,
1002
    &usb_clk0,
1003
    &usb_hhc_ck1510, &usb_hhc_ck16xx,
1004
    &mclk_1510,  &mclk_16xx, &mclk_310,
1005
    &bclk_1510,  &bclk_16xx, &bclk_310,
1006
    &mmc1_ck,
1007
    &mmc2_ck,
1008
    &cam_mclk,
1009
    &cam_exclk,
1010
    &cam_lclk,
1011
    &clk32k,
1012
    &usb_w2fc_mclk,
1013
    /* Virtual clocks */
1014
    &i2c_fck,
1015
    &i2c_ick,
1016

    
1017
    /* OMAP 2 */
1018

    
1019
    &ref_clk,
1020
    &apll_96m,
1021
    &apll_54m,
1022
    &sys_clk,
1023
    &sleep_clk,
1024
    &dpll_ck,
1025
    &dpll_x2_ck,
1026
    &wdt1_sys_clk,
1027
    &func_96m_clk,
1028
    &func_48m_clk,
1029
    &func_12m_clk,
1030
    &func_54m_clk,
1031
    &sys_clkout,
1032
    &sys_clkout2,
1033
    &core_clk,
1034
    &l3_clk,
1035
    &core_l4_iclk,
1036
    &wu_l4_iclk,
1037
    &core_l3_iclk,
1038
    &core_l4_usb_clk,
1039
    &wu_gpt1_clk,
1040
    &wu_32k_clk,
1041
    &uart1_fclk,
1042
    &uart1_iclk,
1043
    &uart2_fclk,
1044
    &uart2_iclk,
1045
    &uart3_fclk,
1046
    &uart3_iclk,
1047
    &mpu_fclk,
1048
    &mpu_iclk,
1049
    &int_m_fclk,
1050
    &int_m_iclk,
1051
    &core_gpt2_clk,
1052
    &core_gpt3_clk,
1053
    &core_gpt4_clk,
1054
    &core_gpt5_clk,
1055
    &core_gpt6_clk,
1056
    &core_gpt7_clk,
1057
    &core_gpt8_clk,
1058
    &core_gpt9_clk,
1059
    &core_gpt10_clk,
1060
    &core_gpt11_clk,
1061
    &core_gpt12_clk,
1062
    &mcbsp1_clk,
1063
    &mcbsp2_clk,
1064
    &emul_clk,
1065
    &sdma_fclk,
1066
    &sdma_iclk,
1067
    &i2c1_fclk,
1068
    &i2c1_iclk,
1069
    &i2c2_fclk,
1070
    &i2c2_iclk,
1071
    &gpio_dbclk[0],
1072
    &gpio_dbclk[1],
1073
    &gpio_dbclk[2],
1074
    &gpio_dbclk[3],
1075
    &gpio_iclk,
1076
    &mmc_fck,
1077
    &mmc_ick,
1078
    &spi_fclk[0],
1079
    &spi_iclk[0],
1080
    &spi_fclk[1],
1081
    &spi_iclk[1],
1082
    &spi_fclk[2],
1083
    &spi_iclk[2],
1084
    &dss_clk[0],
1085
    &dss_clk[1],
1086
    &dss_54m_clk,
1087
    &dss_l3_iclk,
1088
    &dss_l4_iclk,
1089
    &omapctrl_clk,
1090

    
1091
    0
1092
};
1093

    
1094
void omap_clk_adduser(struct clk *clk, qemu_irq user)
1095
{
1096
    qemu_irq *i;
1097

    
1098
    for (i = clk->users; *i; i ++);
1099
    *i = user;
1100
}
1101

    
1102
/* If a clock is allowed to idle, it is disabled automatically when
1103
 * all of clock domains using it are disabled.  */
1104
static int omap_clk_is_idle(struct clk *clk)
1105
{
1106
    struct clk *chld;
1107

    
1108
    if (!clk->enabled && (!clk->usecount || !(clk->flags && ALWAYS_ENABLED)))
1109
        return 1;
1110
    if (clk->usecount)
1111
        return 0;
1112

    
1113
    for (chld = clk->child1; chld; chld = chld->sibling)
1114
        if (!omap_clk_is_idle(chld))
1115
            return 0;
1116
    return 1;
1117
}
1118

    
1119
struct clk *omap_findclk(struct omap_mpu_state_s *mpu, const char *name)
1120
{
1121
    struct clk *i;
1122

    
1123
    for (i = mpu->clks; i->name; i ++)
1124
        if (!strcmp(i->name, name) || (i->alias && !strcmp(i->alias, name)))
1125
            return i;
1126
    cpu_abort(mpu->env, "%s: %s not found\n", __FUNCTION__, name);
1127
}
1128

    
1129
void omap_clk_get(struct clk *clk)
1130
{
1131
    clk->usecount ++;
1132
}
1133

    
1134
void omap_clk_put(struct clk *clk)
1135
{
1136
    if (!(clk->usecount --))
1137
        cpu_abort(cpu_single_env, "%s: %s is not in use\n",
1138
                        __FUNCTION__, clk->name);
1139
}
1140

    
1141
static void omap_clk_update(struct clk *clk)
1142
{
1143
    int parent, running;
1144
    qemu_irq *user;
1145
    struct clk *i;
1146

    
1147
    if (clk->parent)
1148
        parent = clk->parent->running;
1149
    else
1150
        parent = 1;
1151

    
1152
    running = parent && (clk->enabled ||
1153
                    ((clk->flags & ALWAYS_ENABLED) && clk->usecount));
1154
    if (clk->running != running) {
1155
        clk->running = running;
1156
        for (user = clk->users; *user; user ++)
1157
            qemu_set_irq(*user, running);
1158
        for (i = clk->child1; i; i = i->sibling)
1159
            omap_clk_update(i);
1160
    }
1161
}
1162

    
1163
static void omap_clk_rate_update_full(struct clk *clk, unsigned long int rate,
1164
                unsigned long int div, unsigned long int mult)
1165
{
1166
    struct clk *i;
1167
    qemu_irq *user;
1168

    
1169
    clk->rate = muldiv64(rate, mult, div);
1170
    if (clk->running)
1171
        for (user = clk->users; *user; user ++)
1172
            qemu_irq_raise(*user);
1173
    for (i = clk->child1; i; i = i->sibling)
1174
        omap_clk_rate_update_full(i, rate,
1175
                        div * i->divisor, mult * i->multiplier);
1176
}
1177

    
1178
static void omap_clk_rate_update(struct clk *clk)
1179
{
1180
    struct clk *i;
1181
    unsigned long int div, mult = div = 1;
1182

    
1183
    for (i = clk; i->parent; i = i->parent) {
1184
        div *= i->divisor;
1185
        mult *= i->multiplier;
1186
    }
1187

    
1188
    omap_clk_rate_update_full(clk, i->rate, div, mult);
1189
}
1190

    
1191
void omap_clk_reparent(struct clk *clk, struct clk *parent)
1192
{
1193
    struct clk **p;
1194

    
1195
    if (clk->parent) {
1196
        for (p = &clk->parent->child1; *p != clk; p = &(*p)->sibling);
1197
        *p = clk->sibling;
1198
    }
1199

    
1200
    clk->parent = parent;
1201
    if (parent) {
1202
        clk->sibling = parent->child1;
1203
        parent->child1 = clk;
1204
        omap_clk_update(clk);
1205
        omap_clk_rate_update(clk);
1206
    } else
1207
        clk->sibling = 0;
1208
}
1209

    
1210
void omap_clk_onoff(struct clk *clk, int on)
1211
{
1212
    clk->enabled = on;
1213
    omap_clk_update(clk);
1214
}
1215

    
1216
void omap_clk_canidle(struct clk *clk, int can)
1217
{
1218
    if (can)
1219
        omap_clk_put(clk);
1220
    else
1221
        omap_clk_get(clk);
1222
}
1223

    
1224
void omap_clk_setrate(struct clk *clk, int divide, int multiply)
1225
{
1226
    clk->divisor = divide;
1227
    clk->multiplier = multiply;
1228
    omap_clk_rate_update(clk);
1229
}
1230

    
1231
int64_t omap_clk_getrate(omap_clk clk)
1232
{
1233
    return clk->rate;
1234
}
1235

    
1236
void omap_clk_init(struct omap_mpu_state_s *mpu)
1237
{
1238
    struct clk **i, *j, *k;
1239
    int count;
1240
    int flag;
1241

    
1242
    if (cpu_is_omap310(mpu))
1243
        flag = CLOCK_IN_OMAP310;
1244
    else if (cpu_is_omap1510(mpu))
1245
        flag = CLOCK_IN_OMAP1510;
1246
    else if (cpu_is_omap2410(mpu) || cpu_is_omap2420(mpu))
1247
        flag = CLOCK_IN_OMAP242X;
1248
    else if (cpu_is_omap2430(mpu))
1249
        flag = CLOCK_IN_OMAP243X;
1250
    else if (cpu_is_omap3430(mpu))
1251
        flag = CLOCK_IN_OMAP243X;
1252
    else
1253
        return;
1254

    
1255
    for (i = onchip_clks, count = 0; *i; i ++)
1256
        if ((*i)->flags & flag)
1257
            count ++;
1258
    mpu->clks = (struct clk *) qemu_mallocz(sizeof(struct clk) * (count + 1));
1259
    for (i = onchip_clks, j = mpu->clks; *i; i ++)
1260
        if ((*i)->flags & flag) {
1261
            memcpy(j, *i, sizeof(struct clk));
1262
            for (k = mpu->clks; k < j; k ++)
1263
                if (j->parent && !strcmp(j->parent->name, k->name)) {
1264
                    j->parent = k;
1265
                    j->sibling = k->child1;
1266
                    k->child1 = j;
1267
                } else if (k->parent && !strcmp(k->parent->name, j->name)) {
1268
                    k->parent = j;
1269
                    k->sibling = j->child1;
1270
                    j->child1 = k;
1271
                }
1272
            j->divisor = j->divisor ?: 1;
1273
            j->multiplier = j->multiplier ?: 1;
1274
            j ++;
1275
        }
1276
    for (j = mpu->clks; count --; j ++) {
1277
        omap_clk_update(j);
1278
        omap_clk_rate_update(j);
1279
    }
1280
}