Revision 997ff0d9 target-i386/op_helper.c
| b/target-i386/op_helper.c | ||
|---|---|---|
| 51 | 51 |
} |
| 52 | 52 |
} |
| 53 | 53 |
|
| 54 |
static inline uint32_t compute_eflags(void)
|
|
| 54 |
static inline uint32_t cpu_compute_eflags(CPUX86State *env)
|
|
| 55 | 55 |
{
|
| 56 |
return env->eflags | helper_cc_compute_all(CC_OP) | (DF & DF_MASK);
|
|
| 56 |
return env->eflags | cpu_cc_compute_all(env, CC_OP) | (DF & DF_MASK);
|
|
| 57 | 57 |
} |
| 58 | 58 |
|
| 59 | 59 |
/* NOTE: CC_OP must be modified manually to CC_OP_EFLAGS */ |
| 60 |
static inline void load_eflags(int eflags, int update_mask) |
|
| 60 |
static inline void cpu_load_eflags(CPUX86State *env, int eflags, |
|
| 61 |
int update_mask) |
|
| 61 | 62 |
{
|
| 62 | 63 |
CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
| 63 | 64 |
DF = 1 - (2 * ((eflags >> 10) & 1)); |
| ... | ... | |
| 146 | 147 |
|
| 147 | 148 |
void helper_write_eflags(target_ulong t0, uint32_t update_mask) |
| 148 | 149 |
{
|
| 149 |
load_eflags(t0, update_mask);
|
|
| 150 |
cpu_load_eflags(env, t0, update_mask);
|
|
| 150 | 151 |
} |
| 151 | 152 |
|
| 152 | 153 |
target_ulong helper_read_eflags(void) |
| ... | ... | |
| 435 | 436 |
e2 &= ~DESC_TSS_BUSY_MASK; |
| 436 | 437 |
stl_kernel(ptr + 4, e2); |
| 437 | 438 |
} |
| 438 |
old_eflags = compute_eflags();
|
|
| 439 |
old_eflags = cpu_compute_eflags(env);
|
|
| 439 | 440 |
if (source == SWITCH_TSS_IRET) {
|
| 440 | 441 |
old_eflags &= ~NT_MASK; |
| 441 | 442 |
} |
| ... | ... | |
| 513 | 514 |
if (!(type & 8)) {
|
| 514 | 515 |
eflags_mask &= 0xffff; |
| 515 | 516 |
} |
| 516 |
load_eflags(new_eflags, eflags_mask);
|
|
| 517 |
cpu_load_eflags(env, new_eflags, eflags_mask);
|
|
| 517 | 518 |
/* XXX: what to do in 16 bit case? */ |
| 518 | 519 |
EAX = new_regs[0]; |
| 519 | 520 |
ECX = new_regs[1]; |
| ... | ... | |
| 900 | 901 |
PUSHL(ssp, esp, sp_mask, env->segs[R_SS].selector); |
| 901 | 902 |
PUSHL(ssp, esp, sp_mask, ESP); |
| 902 | 903 |
} |
| 903 |
PUSHL(ssp, esp, sp_mask, compute_eflags());
|
|
| 904 |
PUSHL(ssp, esp, sp_mask, cpu_compute_eflags(env));
|
|
| 904 | 905 |
PUSHL(ssp, esp, sp_mask, env->segs[R_CS].selector); |
| 905 | 906 |
PUSHL(ssp, esp, sp_mask, old_eip); |
| 906 | 907 |
if (has_error_code) {
|
| ... | ... | |
| 917 | 918 |
PUSHW(ssp, esp, sp_mask, env->segs[R_SS].selector); |
| 918 | 919 |
PUSHW(ssp, esp, sp_mask, ESP); |
| 919 | 920 |
} |
| 920 |
PUSHW(ssp, esp, sp_mask, compute_eflags());
|
|
| 921 |
PUSHW(ssp, esp, sp_mask, cpu_compute_eflags(env));
|
|
| 921 | 922 |
PUSHW(ssp, esp, sp_mask, env->segs[R_CS].selector); |
| 922 | 923 |
PUSHW(ssp, esp, sp_mask, old_eip); |
| 923 | 924 |
if (has_error_code) {
|
| ... | ... | |
| 1089 | 1090 |
|
| 1090 | 1091 |
PUSHQ(esp, env->segs[R_SS].selector); |
| 1091 | 1092 |
PUSHQ(esp, ESP); |
| 1092 |
PUSHQ(esp, compute_eflags());
|
|
| 1093 |
PUSHQ(esp, cpu_compute_eflags(env));
|
|
| 1093 | 1094 |
PUSHQ(esp, env->segs[R_CS].selector); |
| 1094 | 1095 |
PUSHQ(esp, old_eip); |
| 1095 | 1096 |
if (has_error_code) {
|
| ... | ... | |
| 1139 | 1140 |
int code64; |
| 1140 | 1141 |
|
| 1141 | 1142 |
ECX = env->eip + next_eip_addend; |
| 1142 |
env->regs[11] = compute_eflags();
|
|
| 1143 |
env->regs[11] = cpu_compute_eflags(env);
|
|
| 1143 | 1144 |
|
| 1144 | 1145 |
code64 = env->hflags & HF_CS64_MASK; |
| 1145 | 1146 |
|
| ... | ... | |
| 1156 | 1157 |
DESC_S_MASK | |
| 1157 | 1158 |
DESC_W_MASK | DESC_A_MASK); |
| 1158 | 1159 |
env->eflags &= ~env->fmask; |
| 1159 |
load_eflags(env->eflags, 0);
|
|
| 1160 |
cpu_load_eflags(env, env->eflags, 0);
|
|
| 1160 | 1161 |
if (code64) {
|
| 1161 | 1162 |
env->eip = env->lstar; |
| 1162 | 1163 |
} else {
|
| ... | ... | |
| 1218 | 1219 |
DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | |
| 1219 | 1220 |
DESC_S_MASK | (3 << DESC_DPL_SHIFT) | |
| 1220 | 1221 |
DESC_W_MASK | DESC_A_MASK); |
| 1221 |
load_eflags((uint32_t)(env->regs[11]), TF_MASK | AC_MASK | ID_MASK | |
|
| 1222 |
IF_MASK | IOPL_MASK | VM_MASK | RF_MASK | NT_MASK); |
|
| 1222 |
cpu_load_eflags(env, (uint32_t)(env->regs[11]), TF_MASK | AC_MASK |
|
| 1223 |
| ID_MASK | IF_MASK | IOPL_MASK | VM_MASK | RF_MASK | |
|
| 1224 |
NT_MASK); |
|
| 1223 | 1225 |
cpu_x86_set_cpl(env, 3); |
| 1224 | 1226 |
} else {
|
| 1225 | 1227 |
cpu_x86_load_seg_cache(env, R_CS, selector | 3, |
| ... | ... | |
| 1266 | 1268 |
} |
| 1267 | 1269 |
old_cs = env->segs[R_CS].selector; |
| 1268 | 1270 |
/* XXX: use SS segment size? */ |
| 1269 |
PUSHW(ssp, esp, 0xffff, compute_eflags());
|
|
| 1271 |
PUSHW(ssp, esp, 0xffff, cpu_compute_eflags(env));
|
|
| 1270 | 1272 |
PUSHW(ssp, esp, 0xffff, old_cs); |
| 1271 | 1273 |
PUSHW(ssp, esp, 0xffff, old_eip); |
| 1272 | 1274 |
|
| ... | ... | |
| 1536 | 1538 |
stq_phys(sm_state + 0x7ff8 - i * 8, env->regs[i]); |
| 1537 | 1539 |
} |
| 1538 | 1540 |
stq_phys(sm_state + 0x7f78, env->eip); |
| 1539 |
stl_phys(sm_state + 0x7f70, compute_eflags());
|
|
| 1541 |
stl_phys(sm_state + 0x7f70, cpu_compute_eflags(env));
|
|
| 1540 | 1542 |
stl_phys(sm_state + 0x7f68, env->dr[6]); |
| 1541 | 1543 |
stl_phys(sm_state + 0x7f60, env->dr[7]); |
| 1542 | 1544 |
|
| ... | ... | |
| 1549 | 1551 |
#else |
| 1550 | 1552 |
stl_phys(sm_state + 0x7ffc, env->cr[0]); |
| 1551 | 1553 |
stl_phys(sm_state + 0x7ff8, env->cr[3]); |
| 1552 |
stl_phys(sm_state + 0x7ff4, compute_eflags());
|
|
| 1554 |
stl_phys(sm_state + 0x7ff4, cpu_compute_eflags(env));
|
|
| 1553 | 1555 |
stl_phys(sm_state + 0x7ff0, env->eip); |
| 1554 | 1556 |
stl_phys(sm_state + 0x7fec, EDI); |
| 1555 | 1557 |
stl_phys(sm_state + 0x7fe8, ESI); |
| ... | ... | |
| 1600 | 1602 |
#ifdef TARGET_X86_64 |
| 1601 | 1603 |
cpu_load_efer(env, 0); |
| 1602 | 1604 |
#endif |
| 1603 |
load_eflags(0, ~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK)); |
|
| 1605 |
cpu_load_eflags(env, 0, ~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | |
|
| 1606 |
DF_MASK)); |
|
| 1604 | 1607 |
env->eip = 0x00008000; |
| 1605 | 1608 |
cpu_x86_load_seg_cache(env, R_CS, (env->smbase >> 4) & 0xffff, env->smbase, |
| 1606 | 1609 |
0xffffffff, 0); |
| ... | ... | |
| 1667 | 1670 |
env->regs[i] = ldq_phys(sm_state + 0x7ff8 - i * 8); |
| 1668 | 1671 |
} |
| 1669 | 1672 |
env->eip = ldq_phys(sm_state + 0x7f78); |
| 1670 |
load_eflags(ldl_phys(sm_state + 0x7f70),
|
|
| 1671 |
~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK)); |
|
| 1673 |
cpu_load_eflags(env, ldl_phys(sm_state + 0x7f70),
|
|
| 1674 |
~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK));
|
|
| 1672 | 1675 |
env->dr[6] = ldl_phys(sm_state + 0x7f68); |
| 1673 | 1676 |
env->dr[7] = ldl_phys(sm_state + 0x7f60); |
| 1674 | 1677 |
|
| ... | ... | |
| 1683 | 1686 |
#else |
| 1684 | 1687 |
cpu_x86_update_cr0(env, ldl_phys(sm_state + 0x7ffc)); |
| 1685 | 1688 |
cpu_x86_update_cr3(env, ldl_phys(sm_state + 0x7ff8)); |
| 1686 |
load_eflags(ldl_phys(sm_state + 0x7ff4),
|
|
| 1687 |
~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK)); |
|
| 1689 |
cpu_load_eflags(env, ldl_phys(sm_state + 0x7ff4),
|
|
| 1690 |
~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK));
|
|
| 1688 | 1691 |
env->eip = ldl_phys(sm_state + 0x7ff0); |
| 1689 | 1692 |
EDI = ldl_phys(sm_state + 0x7fec); |
| 1690 | 1693 |
ESI = ldl_phys(sm_state + 0x7fe8); |
| ... | ... | |
| 2731 | 2734 |
if (shift == 0) {
|
| 2732 | 2735 |
eflags_mask &= 0xffff; |
| 2733 | 2736 |
} |
| 2734 |
load_eflags(new_eflags, eflags_mask);
|
|
| 2737 |
cpu_load_eflags(env, new_eflags, eflags_mask);
|
|
| 2735 | 2738 |
env->hflags2 &= ~HF2_NMI_MASK; |
| 2736 | 2739 |
} |
| 2737 | 2740 |
|
| ... | ... | |
| 2951 | 2954 |
if (shift == 0) {
|
| 2952 | 2955 |
eflags_mask &= 0xffff; |
| 2953 | 2956 |
} |
| 2954 |
load_eflags(new_eflags, eflags_mask);
|
|
| 2957 |
cpu_load_eflags(env, new_eflags, eflags_mask);
|
|
| 2955 | 2958 |
} |
| 2956 | 2959 |
return; |
| 2957 | 2960 |
|
| ... | ... | |
| 2964 | 2967 |
POPL(ssp, sp, sp_mask, new_gs); |
| 2965 | 2968 |
|
| 2966 | 2969 |
/* modify processor state */ |
| 2967 |
load_eflags(new_eflags, TF_MASK | AC_MASK | ID_MASK | |
|
| 2968 |
IF_MASK | IOPL_MASK | VM_MASK | NT_MASK | VIF_MASK | VIP_MASK); |
|
| 2970 |
cpu_load_eflags(env, new_eflags, TF_MASK | AC_MASK | ID_MASK | |
|
| 2971 |
IF_MASK | IOPL_MASK | VM_MASK | NT_MASK | VIF_MASK | |
|
| 2972 |
VIP_MASK); |
|
| 2969 | 2973 |
load_seg_vm(R_CS, new_cs & 0xffff); |
| 2970 | 2974 |
cpu_x86_set_cpl(env, 3); |
| 2971 | 2975 |
load_seg_vm(R_SS, new_ss & 0xffff); |
| ... | ... | |
| 4153 | 4157 |
|
| 4154 | 4158 |
stq_phys(env->vm_hsave + offsetof(struct vmcb, save.efer), env->efer); |
| 4155 | 4159 |
stq_phys(env->vm_hsave + offsetof(struct vmcb, save.rflags), |
| 4156 |
compute_eflags());
|
|
| 4160 |
cpu_compute_eflags(env));
|
|
| 4157 | 4161 |
|
| 4158 | 4162 |
svm_save_seg(env->vm_hsave + offsetof(struct vmcb, save.es), |
| 4159 | 4163 |
&env->segs[R_ES]); |
| ... | ... | |
| 4229 | 4233 |
cpu_load_efer(env, |
| 4230 | 4234 |
ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.efer))); |
| 4231 | 4235 |
env->eflags = 0; |
| 4232 |
load_eflags(ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.rflags)), |
|
| 4233 |
~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK)); |
|
| 4236 |
cpu_load_eflags(env, ldq_phys(env->vm_vmcb + offsetof(struct vmcb, |
|
| 4237 |
save.rflags)), |
|
| 4238 |
~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK)); |
|
| 4234 | 4239 |
CC_OP = CC_OP_EFLAGS; |
| 4235 | 4240 |
|
| 4236 | 4241 |
svm_load_seg_cache(env->vm_vmcb + offsetof(struct vmcb, save.es), |
| ... | ... | |
| 4601 | 4606 |
stl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_ctl), int_ctl); |
| 4602 | 4607 |
|
| 4603 | 4608 |
stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.rflags), |
| 4604 |
compute_eflags());
|
|
| 4609 |
cpu_compute_eflags(env));
|
|
| 4605 | 4610 |
stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.rip), env->eip); |
| 4606 | 4611 |
stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.rsp), ESP); |
| 4607 | 4612 |
stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.rax), EAX); |
| ... | ... | |
| 4640 | 4645 |
cpu_load_efer(env, ldq_phys(env->vm_hsave + offsetof(struct vmcb, |
| 4641 | 4646 |
save.efer))); |
| 4642 | 4647 |
env->eflags = 0; |
| 4643 |
load_eflags(ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.rflags)), |
|
| 4644 |
~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK)); |
|
| 4648 |
cpu_load_eflags(env, ldq_phys(env->vm_hsave + offsetof(struct vmcb, |
|
| 4649 |
save.rflags)), |
|
| 4650 |
~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK)); |
|
| 4645 | 4651 |
CC_OP = CC_OP_EFLAGS; |
| 4646 | 4652 |
|
| 4647 | 4653 |
svm_load_seg_cache(env->vm_hsave + offsetof(struct vmcb, save.es), |
Also available in: Unified diff