Revision 99a0949b hw/eepro100.c
| b/hw/eepro100.c | ||
|---|---|---|
| 144 | 144 |
//~ int32_t tx_buf_size0; /* Length of Tx hdr. */ |
| 145 | 145 |
//~ uint32_t tx_buf_addr1; /* void *, data to be transmitted. */ |
| 146 | 146 |
//~ int32_t tx_buf_size1; /* Length of Tx data. */ |
| 147 |
} eepro100_tx_t;
|
|
| 147 |
} a_eepro100_tx;
|
|
| 148 | 148 |
|
| 149 | 149 |
/* Receive frame descriptor. */ |
| 150 | 150 |
typedef struct {
|
| ... | ... | |
| 155 | 155 |
uint16_t count; |
| 156 | 156 |
uint16_t size; |
| 157 | 157 |
char packet[MAX_ETH_FRAME_SIZE + 4]; |
| 158 |
} eepro100_rx_t;
|
|
| 158 |
} a_eepro100_rx;
|
|
| 159 | 159 |
|
| 160 | 160 |
typedef struct {
|
| 161 | 161 |
uint32_t tx_good_frames, tx_max_collisions, tx_late_collisions, |
| ... | ... | |
| 167 | 167 |
uint32_t fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported; |
| 168 | 168 |
uint16_t xmt_tco_frames, rcv_tco_frames; |
| 169 | 169 |
uint32_t complete; |
| 170 |
} eepro100_stats_t;
|
|
| 170 |
} a_eepro100_stats;
|
|
| 171 | 171 |
|
| 172 | 172 |
typedef enum {
|
| 173 | 173 |
cu_idle = 0, |
| ... | ... | |
| 175 | 175 |
cu_active = 2, |
| 176 | 176 |
cu_lpq_active = 2, |
| 177 | 177 |
cu_hqp_active = 3 |
| 178 |
} cu_state_t;
|
|
| 178 |
} a_cu_state;
|
|
| 179 | 179 |
|
| 180 | 180 |
typedef enum {
|
| 181 | 181 |
ru_idle = 0, |
| 182 | 182 |
ru_suspended = 1, |
| 183 | 183 |
ru_no_resources = 2, |
| 184 | 184 |
ru_ready = 4 |
| 185 |
} ru_state_t;
|
|
| 185 |
} a_ru_state;
|
|
| 186 | 186 |
|
| 187 | 187 |
typedef struct {
|
| 188 | 188 |
PCIDevice dev; |
| ... | ... | |
| 213 | 213 |
uint8_t macaddr[6]; |
| 214 | 214 |
uint32_t statcounter[19]; |
| 215 | 215 |
uint16_t mdimem[32]; |
| 216 |
eeprom_t *eeprom;
|
|
| 216 |
a_eeprom *eeprom;
|
|
| 217 | 217 |
uint32_t device; /* device variant */ |
| 218 | 218 |
uint32_t pointer; |
| 219 | 219 |
/* (cu_base + cu_offset) address the next command block in the command block list. */ |
| ... | ... | |
| 222 | 222 |
/* (ru_base + ru_offset) address the RFD in the Receive Frame Area. */ |
| 223 | 223 |
uint32_t ru_base; /* RU base address */ |
| 224 | 224 |
uint32_t ru_offset; /* RU address offset */ |
| 225 |
uint32_t statsaddr; /* pointer to eepro100_stats_t */
|
|
| 226 |
eepro100_stats_t statistics; /* statistical counters */
|
|
| 225 |
uint32_t statsaddr; /* pointer to a_eepro100_stats */
|
|
| 226 |
a_eepro100_stats statistics; /* statistical counters */
|
|
| 227 | 227 |
#if 0 |
| 228 | 228 |
uint16_t status; |
| 229 | 229 |
#endif |
| ... | ... | |
| 600 | 600 |
CmdTxFlex = 0x0008, /* Use "Flexible mode" for CmdTx command. */ |
| 601 | 601 |
}; |
| 602 | 602 |
|
| 603 |
static cu_state_t get_cu_state(EEPRO100State * s)
|
|
| 603 |
static a_cu_state get_cu_state(EEPRO100State * s)
|
|
| 604 | 604 |
{
|
| 605 | 605 |
return ((s->mem[SCBStatus] >> 6) & 0x03); |
| 606 | 606 |
} |
| 607 | 607 |
|
| 608 |
static void set_cu_state(EEPRO100State * s, cu_state_t state)
|
|
| 608 |
static void set_cu_state(EEPRO100State * s, a_cu_state state)
|
|
| 609 | 609 |
{
|
| 610 | 610 |
s->mem[SCBStatus] = (s->mem[SCBStatus] & 0x3f) + (state << 6); |
| 611 | 611 |
} |
| 612 | 612 |
|
| 613 |
static ru_state_t get_ru_state(EEPRO100State * s)
|
|
| 613 |
static a_ru_state get_ru_state(EEPRO100State * s)
|
|
| 614 | 614 |
{
|
| 615 | 615 |
return ((s->mem[SCBStatus] >> 2) & 0x0f); |
| 616 | 616 |
} |
| 617 | 617 |
|
| 618 |
static void set_ru_state(EEPRO100State * s, ru_state_t state)
|
|
| 618 |
static void set_ru_state(EEPRO100State * s, a_ru_state state)
|
|
| 619 | 619 |
{
|
| 620 | 620 |
s->mem[SCBStatus] = (s->mem[SCBStatus] & 0xc3) + (state << 2); |
| 621 | 621 |
} |
| ... | ... | |
| 639 | 639 |
|
| 640 | 640 |
static void eepro100_cu_command(EEPRO100State * s, uint8_t val) |
| 641 | 641 |
{
|
| 642 |
eepro100_tx_t tx;
|
|
| 642 |
a_eepro100_tx tx;
|
|
| 643 | 643 |
uint32_t cb_address; |
| 644 | 644 |
switch (val) {
|
| 645 | 645 |
case CU_NOP: |
| ... | ... | |
| 915 | 915 |
return val; |
| 916 | 916 |
} |
| 917 | 917 |
|
| 918 |
static void eepro100_write_eeprom(eeprom_t * eeprom, uint8_t val)
|
|
| 918 |
static void eepro100_write_eeprom(a_eeprom * eeprom, uint8_t val)
|
|
| 919 | 919 |
{
|
| 920 | 920 |
TRACE(EEPROM, logout("val=0x%02x\n", val));
|
| 921 | 921 |
|
| ... | ... | |
| 1099 | 1099 |
typedef struct {
|
| 1100 | 1100 |
uint32_t st_sign; /* Self Test Signature */ |
| 1101 | 1101 |
uint32_t st_result; /* Self Test Results */ |
| 1102 |
} eepro100_selftest_t;
|
|
| 1102 |
} a_eepro100_selftest;
|
|
| 1103 | 1103 |
|
| 1104 | 1104 |
static uint32_t eepro100_read_port(EEPRO100State * s) |
| 1105 | 1105 |
{
|
| ... | ... | |
| 1117 | 1117 |
break; |
| 1118 | 1118 |
case PORT_SELFTEST: |
| 1119 | 1119 |
TRACE(OTHER, logout("selftest address=0x%08x\n", address));
|
| 1120 |
eepro100_selftest_t data;
|
|
| 1120 |
a_eepro100_selftest data;
|
|
| 1121 | 1121 |
cpu_physical_memory_read(address, (uint8_t *) & data, sizeof(data)); |
| 1122 | 1122 |
data.st_sign = 0xffffffff; |
| 1123 | 1123 |
data.st_result = 0; |
| ... | ... | |
| 1398 | 1398 |
* |
| 1399 | 1399 |
****************************************************************************/ |
| 1400 | 1400 |
|
| 1401 |
static void pci_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
|
|
| 1401 |
static void pci_mmio_writeb(void *opaque, a_target_phys_addr addr, uint32_t val)
|
|
| 1402 | 1402 |
{
|
| 1403 | 1403 |
EEPRO100State *s = opaque; |
| 1404 | 1404 |
//~ logout("addr=%s val=0x%02x\n", regname(addr), val);
|
| 1405 | 1405 |
eepro100_write1(s, addr, val); |
| 1406 | 1406 |
} |
| 1407 | 1407 |
|
| 1408 |
static void pci_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
|
|
| 1408 |
static void pci_mmio_writew(void *opaque, a_target_phys_addr addr, uint32_t val)
|
|
| 1409 | 1409 |
{
|
| 1410 | 1410 |
EEPRO100State *s = opaque; |
| 1411 | 1411 |
//~ logout("addr=%s val=0x%02x\n", regname(addr), val);
|
| 1412 | 1412 |
eepro100_write2(s, addr, val); |
| 1413 | 1413 |
} |
| 1414 | 1414 |
|
| 1415 |
static void pci_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
|
|
| 1415 |
static void pci_mmio_writel(void *opaque, a_target_phys_addr addr, uint32_t val)
|
|
| 1416 | 1416 |
{
|
| 1417 | 1417 |
EEPRO100State *s = opaque; |
| 1418 | 1418 |
//~ logout("addr=%s val=0x%02x\n", regname(addr), val);
|
| 1419 | 1419 |
eepro100_write4(s, addr, val); |
| 1420 | 1420 |
} |
| 1421 | 1421 |
|
| 1422 |
static uint32_t pci_mmio_readb(void *opaque, target_phys_addr_t addr)
|
|
| 1422 |
static uint32_t pci_mmio_readb(void *opaque, a_target_phys_addr addr)
|
|
| 1423 | 1423 |
{
|
| 1424 | 1424 |
EEPRO100State *s = opaque; |
| 1425 | 1425 |
//~ logout("addr=%s\n", regname(addr));
|
| 1426 | 1426 |
return eepro100_read1(s, addr); |
| 1427 | 1427 |
} |
| 1428 | 1428 |
|
| 1429 |
static uint32_t pci_mmio_readw(void *opaque, target_phys_addr_t addr)
|
|
| 1429 |
static uint32_t pci_mmio_readw(void *opaque, a_target_phys_addr addr)
|
|
| 1430 | 1430 |
{
|
| 1431 | 1431 |
EEPRO100State *s = opaque; |
| 1432 | 1432 |
//~ logout("addr=%s\n", regname(addr));
|
| 1433 | 1433 |
return eepro100_read2(s, addr); |
| 1434 | 1434 |
} |
| 1435 | 1435 |
|
| 1436 |
static uint32_t pci_mmio_readl(void *opaque, target_phys_addr_t addr)
|
|
| 1436 |
static uint32_t pci_mmio_readl(void *opaque, a_target_phys_addr addr)
|
|
| 1437 | 1437 |
{
|
| 1438 | 1438 |
EEPRO100State *s = opaque; |
| 1439 | 1439 |
//~ logout("addr=%s\n", regname(addr));
|
| ... | ... | |
| 1541 | 1541 |
} |
| 1542 | 1542 |
//~ !!! |
| 1543 | 1543 |
//~ $3 = {status = 0x0, command = 0xc000, link = 0x2d220, rx_buf_addr = 0x207dc, count = 0x0, size = 0x5f8, packet = {0x0 <repeats 1518 times>}}
|
| 1544 |
eepro100_rx_t rx;
|
|
| 1544 |
a_eepro100_rx rx;
|
|
| 1545 | 1545 |
cpu_physical_memory_read(s->ru_base + s->ru_offset, (uint8_t *) & rx, |
| 1546 |
offsetof(eepro100_rx_t, packet));
|
|
| 1546 |
offsetof(a_eepro100_rx, packet));
|
|
| 1547 | 1547 |
uint16_t rfd_command = le16_to_cpu(rx.command); |
| 1548 | 1548 |
uint16_t rfd_size = le16_to_cpu(rx.size); |
| 1549 | 1549 |
assert(size <= rfd_size); |
| ... | ... | |
| 1552 | 1552 |
} |
| 1553 | 1553 |
TRACE(OTHER, logout("command 0x%04x, link 0x%08x, addr 0x%08x, size %u\n",
|
| 1554 | 1554 |
rfd_command, rx.link, rx.rx_buf_addr, rfd_size)); |
| 1555 |
stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, status),
|
|
| 1555 |
stw_phys(s->ru_base + s->ru_offset + offsetof(a_eepro100_rx, status),
|
|
| 1556 | 1556 |
rfd_status); |
| 1557 |
stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, count), size);
|
|
| 1557 |
stw_phys(s->ru_base + s->ru_offset + offsetof(a_eepro100_rx, count), size);
|
|
| 1558 | 1558 |
/* Early receive interrupt not supported. */ |
| 1559 | 1559 |
//~ eepro100_er_interrupt(s); |
| 1560 | 1560 |
/* Receive CRC Transfer not supported. */ |
| ... | ... | |
| 1562 | 1562 |
/* TODO: check stripping enable bit. */ |
| 1563 | 1563 |
//~ assert(!(s->configuration[17] & 1)); |
| 1564 | 1564 |
cpu_physical_memory_write(s->ru_base + s->ru_offset + |
| 1565 |
offsetof(eepro100_rx_t, packet), buf, size);
|
|
| 1565 |
offsetof(a_eepro100_rx, packet), buf, size);
|
|
| 1566 | 1566 |
s->statistics.rx_good_frames++; |
| 1567 | 1567 |
eepro100_fr_interrupt(s); |
| 1568 | 1568 |
s->ru_offset = le32_to_cpu(rx.link); |
Also available in: Unified diff