Revision 99a0949b hw/ppc.c
| b/hw/ppc.c | ||
|---|---|---|
| 377 | 377 |
} |
| 378 | 378 |
/*****************************************************************************/ |
| 379 | 379 |
/* PowerPC time base and decrementer emulation */ |
| 380 |
struct ppc_tb_t {
|
|
| 380 |
struct ppc_tb {
|
|
| 381 | 381 |
/* Time base management */ |
| 382 | 382 |
int64_t tb_offset; /* Compensation */ |
| 383 | 383 |
int64_t atb_offset; /* Compensation */ |
| ... | ... | |
| 394 | 394 |
void *opaque; |
| 395 | 395 |
}; |
| 396 | 396 |
|
| 397 |
static inline uint64_t cpu_ppc_get_tb(ppc_tb_t *tb_env, uint64_t vmclk,
|
|
| 397 |
static inline uint64_t cpu_ppc_get_tb(a_ppc_tb *tb_env, uint64_t vmclk,
|
|
| 398 | 398 |
int64_t tb_offset) |
| 399 | 399 |
{
|
| 400 | 400 |
/* TB time in tb periods */ |
| ... | ... | |
| 403 | 403 |
|
| 404 | 404 |
uint32_t cpu_ppc_load_tbl (CPUState *env) |
| 405 | 405 |
{
|
| 406 |
ppc_tb_t *tb_env = env->tb_env;
|
|
| 406 |
a_ppc_tb *tb_env = env->tb_env;
|
|
| 407 | 407 |
uint64_t tb; |
| 408 | 408 |
|
| 409 | 409 |
tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->tb_offset); |
| ... | ... | |
| 414 | 414 |
|
| 415 | 415 |
static inline uint32_t _cpu_ppc_load_tbu(CPUState *env) |
| 416 | 416 |
{
|
| 417 |
ppc_tb_t *tb_env = env->tb_env;
|
|
| 417 |
a_ppc_tb *tb_env = env->tb_env;
|
|
| 418 | 418 |
uint64_t tb; |
| 419 | 419 |
|
| 420 | 420 |
tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->tb_offset); |
| ... | ... | |
| 428 | 428 |
return _cpu_ppc_load_tbu(env); |
| 429 | 429 |
} |
| 430 | 430 |
|
| 431 |
static inline void cpu_ppc_store_tb(ppc_tb_t *tb_env, uint64_t vmclk,
|
|
| 431 |
static inline void cpu_ppc_store_tb(a_ppc_tb *tb_env, uint64_t vmclk,
|
|
| 432 | 432 |
int64_t *tb_offsetp, uint64_t value) |
| 433 | 433 |
{
|
| 434 | 434 |
*tb_offsetp = value - muldiv64(vmclk, tb_env->tb_freq, get_ticks_per_sec()); |
| ... | ... | |
| 438 | 438 |
|
| 439 | 439 |
void cpu_ppc_store_tbl (CPUState *env, uint32_t value) |
| 440 | 440 |
{
|
| 441 |
ppc_tb_t *tb_env = env->tb_env;
|
|
| 441 |
a_ppc_tb *tb_env = env->tb_env;
|
|
| 442 | 442 |
uint64_t tb; |
| 443 | 443 |
|
| 444 | 444 |
tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->tb_offset); |
| ... | ... | |
| 449 | 449 |
|
| 450 | 450 |
static inline void _cpu_ppc_store_tbu(CPUState *env, uint32_t value) |
| 451 | 451 |
{
|
| 452 |
ppc_tb_t *tb_env = env->tb_env;
|
|
| 452 |
a_ppc_tb *tb_env = env->tb_env;
|
|
| 453 | 453 |
uint64_t tb; |
| 454 | 454 |
|
| 455 | 455 |
tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->tb_offset); |
| ... | ... | |
| 465 | 465 |
|
| 466 | 466 |
uint32_t cpu_ppc_load_atbl (CPUState *env) |
| 467 | 467 |
{
|
| 468 |
ppc_tb_t *tb_env = env->tb_env;
|
|
| 468 |
a_ppc_tb *tb_env = env->tb_env;
|
|
| 469 | 469 |
uint64_t tb; |
| 470 | 470 |
|
| 471 | 471 |
tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->atb_offset); |
| ... | ... | |
| 476 | 476 |
|
| 477 | 477 |
uint32_t cpu_ppc_load_atbu (CPUState *env) |
| 478 | 478 |
{
|
| 479 |
ppc_tb_t *tb_env = env->tb_env;
|
|
| 479 |
a_ppc_tb *tb_env = env->tb_env;
|
|
| 480 | 480 |
uint64_t tb; |
| 481 | 481 |
|
| 482 | 482 |
tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->atb_offset); |
| ... | ... | |
| 487 | 487 |
|
| 488 | 488 |
void cpu_ppc_store_atbl (CPUState *env, uint32_t value) |
| 489 | 489 |
{
|
| 490 |
ppc_tb_t *tb_env = env->tb_env;
|
|
| 490 |
a_ppc_tb *tb_env = env->tb_env;
|
|
| 491 | 491 |
uint64_t tb; |
| 492 | 492 |
|
| 493 | 493 |
tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->atb_offset); |
| ... | ... | |
| 498 | 498 |
|
| 499 | 499 |
void cpu_ppc_store_atbu (CPUState *env, uint32_t value) |
| 500 | 500 |
{
|
| 501 |
ppc_tb_t *tb_env = env->tb_env;
|
|
| 501 |
a_ppc_tb *tb_env = env->tb_env;
|
|
| 502 | 502 |
uint64_t tb; |
| 503 | 503 |
|
| 504 | 504 |
tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->atb_offset); |
| ... | ... | |
| 509 | 509 |
|
| 510 | 510 |
static void cpu_ppc_tb_stop (CPUState *env) |
| 511 | 511 |
{
|
| 512 |
ppc_tb_t *tb_env = env->tb_env;
|
|
| 512 |
a_ppc_tb *tb_env = env->tb_env;
|
|
| 513 | 513 |
uint64_t tb, atb, vmclk; |
| 514 | 514 |
|
| 515 | 515 |
/* If the time base is already frozen, do nothing */ |
| ... | ... | |
| 531 | 531 |
|
| 532 | 532 |
static void cpu_ppc_tb_start (CPUState *env) |
| 533 | 533 |
{
|
| 534 |
ppc_tb_t *tb_env = env->tb_env;
|
|
| 534 |
a_ppc_tb *tb_env = env->tb_env;
|
|
| 535 | 535 |
uint64_t tb, atb, vmclk; |
| 536 | 536 |
|
| 537 | 537 |
/* If the time base is not frozen, do nothing */ |
| ... | ... | |
| 552 | 552 |
|
| 553 | 553 |
static inline uint32_t _cpu_ppc_load_decr(CPUState *env, uint64_t next) |
| 554 | 554 |
{
|
| 555 |
ppc_tb_t *tb_env = env->tb_env;
|
|
| 555 |
a_ppc_tb *tb_env = env->tb_env;
|
|
| 556 | 556 |
uint32_t decr; |
| 557 | 557 |
int64_t diff; |
| 558 | 558 |
|
| ... | ... | |
| 568 | 568 |
|
| 569 | 569 |
uint32_t cpu_ppc_load_decr (CPUState *env) |
| 570 | 570 |
{
|
| 571 |
ppc_tb_t *tb_env = env->tb_env;
|
|
| 571 |
a_ppc_tb *tb_env = env->tb_env;
|
|
| 572 | 572 |
|
| 573 | 573 |
return _cpu_ppc_load_decr(env, tb_env->decr_next); |
| 574 | 574 |
} |
| 575 | 575 |
|
| 576 | 576 |
uint32_t cpu_ppc_load_hdecr (CPUState *env) |
| 577 | 577 |
{
|
| 578 |
ppc_tb_t *tb_env = env->tb_env;
|
|
| 578 |
a_ppc_tb *tb_env = env->tb_env;
|
|
| 579 | 579 |
|
| 580 | 580 |
return _cpu_ppc_load_decr(env, tb_env->hdecr_next); |
| 581 | 581 |
} |
| 582 | 582 |
|
| 583 | 583 |
uint64_t cpu_ppc_load_purr (CPUState *env) |
| 584 | 584 |
{
|
| 585 |
ppc_tb_t *tb_env = env->tb_env;
|
|
| 585 |
a_ppc_tb *tb_env = env->tb_env;
|
|
| 586 | 586 |
uint64_t diff; |
| 587 | 587 |
|
| 588 | 588 |
diff = qemu_get_clock(vm_clock) - tb_env->purr_start; |
| ... | ... | |
| 613 | 613 |
uint32_t decr, uint32_t value, |
| 614 | 614 |
int is_excp) |
| 615 | 615 |
{
|
| 616 |
ppc_tb_t *tb_env = env->tb_env;
|
|
| 616 |
a_ppc_tb *tb_env = env->tb_env;
|
|
| 617 | 617 |
uint64_t now, next; |
| 618 | 618 |
|
| 619 | 619 |
LOG_TB("%s: %08" PRIx32 " => %08" PRIx32 "\n", __func__,
|
| ... | ... | |
| 637 | 637 |
static inline void _cpu_ppc_store_decr(CPUState *env, uint32_t decr, |
| 638 | 638 |
uint32_t value, int is_excp) |
| 639 | 639 |
{
|
| 640 |
ppc_tb_t *tb_env = env->tb_env;
|
|
| 640 |
a_ppc_tb *tb_env = env->tb_env;
|
|
| 641 | 641 |
|
| 642 | 642 |
__cpu_ppc_store_decr(env, &tb_env->decr_next, tb_env->decr_timer, |
| 643 | 643 |
&cpu_ppc_decr_excp, decr, value, is_excp); |
| ... | ... | |
| 656 | 656 |
static inline void _cpu_ppc_store_hdecr(CPUState *env, uint32_t hdecr, |
| 657 | 657 |
uint32_t value, int is_excp) |
| 658 | 658 |
{
|
| 659 |
ppc_tb_t *tb_env = env->tb_env;
|
|
| 659 |
a_ppc_tb *tb_env = env->tb_env;
|
|
| 660 | 660 |
|
| 661 | 661 |
if (tb_env->hdecr_timer != NULL) {
|
| 662 | 662 |
__cpu_ppc_store_decr(env, &tb_env->hdecr_next, tb_env->hdecr_timer, |
| ... | ... | |
| 676 | 676 |
|
| 677 | 677 |
void cpu_ppc_store_purr (CPUState *env, uint64_t value) |
| 678 | 678 |
{
|
| 679 |
ppc_tb_t *tb_env = env->tb_env;
|
|
| 679 |
a_ppc_tb *tb_env = env->tb_env;
|
|
| 680 | 680 |
|
| 681 | 681 |
tb_env->purr_load = value; |
| 682 | 682 |
tb_env->purr_start = qemu_get_clock(vm_clock); |
| ... | ... | |
| 685 | 685 |
static void cpu_ppc_set_tb_clk (void *opaque, uint32_t freq) |
| 686 | 686 |
{
|
| 687 | 687 |
CPUState *env = opaque; |
| 688 |
ppc_tb_t *tb_env = env->tb_env;
|
|
| 688 |
a_ppc_tb *tb_env = env->tb_env;
|
|
| 689 | 689 |
|
| 690 | 690 |
tb_env->tb_freq = freq; |
| 691 | 691 |
tb_env->decr_freq = freq; |
| ... | ... | |
| 701 | 701 |
/* Set up (once) timebase frequency (in Hz) */ |
| 702 | 702 |
clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq) |
| 703 | 703 |
{
|
| 704 |
ppc_tb_t *tb_env;
|
|
| 704 |
a_ppc_tb *tb_env;
|
|
| 705 | 705 |
|
| 706 |
tb_env = qemu_mallocz(sizeof(ppc_tb_t));
|
|
| 706 |
tb_env = qemu_mallocz(sizeof(a_ppc_tb));
|
|
| 707 | 707 |
env->tb_env = tb_env; |
| 708 | 708 |
/* Create new timer */ |
| 709 | 709 |
tb_env->decr_timer = qemu_new_timer(vm_clock, &cpu_ppc_decr_cb, env); |
| ... | ... | |
| 751 | 751 |
/* Embedded PowerPC timers */ |
| 752 | 752 |
|
| 753 | 753 |
/* PIT, FIT & WDT */ |
| 754 |
typedef struct ppcemb_timer_t ppcemb_timer_t;
|
|
| 755 |
struct ppcemb_timer_t {
|
|
| 754 |
typedef struct ppcemb_timer a_ppcemb_timer;
|
|
| 755 |
struct ppcemb_timer {
|
|
| 756 | 756 |
uint64_t pit_reload; /* PIT auto-reload value */ |
| 757 | 757 |
uint64_t fit_next; /* Tick for next FIT interrupt */ |
| 758 | 758 |
struct QEMUTimer *fit_timer; |
| ... | ... | |
| 764 | 764 |
static void cpu_4xx_fit_cb (void *opaque) |
| 765 | 765 |
{
|
| 766 | 766 |
CPUState *env; |
| 767 |
ppc_tb_t *tb_env;
|
|
| 768 |
ppcemb_timer_t *ppcemb_timer;
|
|
| 767 |
a_ppc_tb *tb_env;
|
|
| 768 |
a_ppcemb_timer *ppcemb_timer;
|
|
| 769 | 769 |
uint64_t now, next; |
| 770 | 770 |
|
| 771 | 771 |
env = opaque; |
| ... | ... | |
| 802 | 802 |
} |
| 803 | 803 |
|
| 804 | 804 |
/* Programmable interval timer */ |
| 805 |
static void start_stop_pit (CPUState *env, ppc_tb_t *tb_env, int is_excp)
|
|
| 805 |
static void start_stop_pit (CPUState *env, a_ppc_tb *tb_env, int is_excp)
|
|
| 806 | 806 |
{
|
| 807 |
ppcemb_timer_t *ppcemb_timer;
|
|
| 807 |
a_ppcemb_timer *ppcemb_timer;
|
|
| 808 | 808 |
uint64_t now, next; |
| 809 | 809 |
|
| 810 | 810 |
ppcemb_timer = tb_env->opaque; |
| ... | ... | |
| 832 | 832 |
static void cpu_4xx_pit_cb (void *opaque) |
| 833 | 833 |
{
|
| 834 | 834 |
CPUState *env; |
| 835 |
ppc_tb_t *tb_env;
|
|
| 836 |
ppcemb_timer_t *ppcemb_timer;
|
|
| 835 |
a_ppc_tb *tb_env;
|
|
| 836 |
a_ppcemb_timer *ppcemb_timer;
|
|
| 837 | 837 |
|
| 838 | 838 |
env = opaque; |
| 839 | 839 |
tb_env = env->tb_env; |
| ... | ... | |
| 854 | 854 |
static void cpu_4xx_wdt_cb (void *opaque) |
| 855 | 855 |
{
|
| 856 | 856 |
CPUState *env; |
| 857 |
ppc_tb_t *tb_env;
|
|
| 858 |
ppcemb_timer_t *ppcemb_timer;
|
|
| 857 |
a_ppc_tb *tb_env;
|
|
| 858 |
a_ppcemb_timer *ppcemb_timer;
|
|
| 859 | 859 |
uint64_t now, next; |
| 860 | 860 |
|
| 861 | 861 |
env = opaque; |
| ... | ... | |
| 920 | 920 |
|
| 921 | 921 |
void store_40x_pit (CPUState *env, target_ulong val) |
| 922 | 922 |
{
|
| 923 |
ppc_tb_t *tb_env;
|
|
| 924 |
ppcemb_timer_t *ppcemb_timer;
|
|
| 923 |
a_ppc_tb *tb_env;
|
|
| 924 |
a_ppcemb_timer *ppcemb_timer;
|
|
| 925 | 925 |
|
| 926 | 926 |
tb_env = env->tb_env; |
| 927 | 927 |
ppcemb_timer = tb_env->opaque; |
| ... | ... | |
| 945 | 945 |
|
| 946 | 946 |
void store_booke_tcr (CPUState *env, target_ulong val) |
| 947 | 947 |
{
|
| 948 |
ppc_tb_t *tb_env;
|
|
| 948 |
a_ppc_tb *tb_env;
|
|
| 949 | 949 |
|
| 950 | 950 |
tb_env = env->tb_env; |
| 951 | 951 |
LOG_TB("%s: val " TARGET_FMT_lx "\n", __func__, val);
|
| ... | ... | |
| 957 | 957 |
static void ppc_emb_set_tb_clk (void *opaque, uint32_t freq) |
| 958 | 958 |
{
|
| 959 | 959 |
CPUState *env = opaque; |
| 960 |
ppc_tb_t *tb_env = env->tb_env;
|
|
| 960 |
a_ppc_tb *tb_env = env->tb_env;
|
|
| 961 | 961 |
|
| 962 | 962 |
LOG_TB("%s set new frequency to %" PRIu32 "\n", __func__,
|
| 963 | 963 |
freq); |
| ... | ... | |
| 968 | 968 |
|
| 969 | 969 |
clk_setup_cb ppc_emb_timers_init (CPUState *env, uint32_t freq) |
| 970 | 970 |
{
|
| 971 |
ppc_tb_t *tb_env;
|
|
| 972 |
ppcemb_timer_t *ppcemb_timer;
|
|
| 971 |
a_ppc_tb *tb_env;
|
|
| 972 |
a_ppcemb_timer *ppcemb_timer;
|
|
| 973 | 973 |
|
| 974 |
tb_env = qemu_mallocz(sizeof(ppc_tb_t));
|
|
| 974 |
tb_env = qemu_mallocz(sizeof(a_ppc_tb));
|
|
| 975 | 975 |
env->tb_env = tb_env; |
| 976 |
ppcemb_timer = qemu_mallocz(sizeof(ppcemb_timer_t));
|
|
| 976 |
ppcemb_timer = qemu_mallocz(sizeof(a_ppcemb_timer));
|
|
| 977 | 977 |
tb_env->tb_freq = freq; |
| 978 | 978 |
tb_env->decr_freq = freq; |
| 979 | 979 |
tb_env->opaque = ppcemb_timer; |
| ... | ... | |
| 992 | 992 |
|
| 993 | 993 |
/*****************************************************************************/ |
| 994 | 994 |
/* Embedded PowerPC Device Control Registers */ |
| 995 |
typedef struct ppc_dcrn_t ppc_dcrn_t;
|
|
| 996 |
struct ppc_dcrn_t {
|
|
| 995 |
typedef struct ppc_dcrn a_ppc_dcrn;
|
|
| 996 |
struct ppc_dcrn {
|
|
| 997 | 997 |
dcr_read_cb dcr_read; |
| 998 | 998 |
dcr_write_cb dcr_write; |
| 999 | 999 |
void *opaque; |
| ... | ... | |
| 1003 | 1003 |
* using DCRIPR to get the 22 upper bits of the DCR address |
| 1004 | 1004 |
*/ |
| 1005 | 1005 |
#define DCRN_NB 1024 |
| 1006 |
struct ppc_dcr_t {
|
|
| 1007 |
ppc_dcrn_t dcrn[DCRN_NB];
|
|
| 1006 |
struct ppc_dcr {
|
|
| 1007 |
a_ppc_dcrn dcrn[DCRN_NB];
|
|
| 1008 | 1008 |
int (*read_error)(int dcrn); |
| 1009 | 1009 |
int (*write_error)(int dcrn); |
| 1010 | 1010 |
}; |
| 1011 | 1011 |
|
| 1012 |
int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp)
|
|
| 1012 |
int ppc_dcr_read (a_ppc_dcr *dcr_env, int dcrn, target_ulong *valp)
|
|
| 1013 | 1013 |
{
|
| 1014 |
ppc_dcrn_t *dcr;
|
|
| 1014 |
a_ppc_dcrn *dcr;
|
|
| 1015 | 1015 |
|
| 1016 | 1016 |
if (dcrn < 0 || dcrn >= DCRN_NB) |
| 1017 | 1017 |
goto error; |
| ... | ... | |
| 1029 | 1029 |
return -1; |
| 1030 | 1030 |
} |
| 1031 | 1031 |
|
| 1032 |
int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val)
|
|
| 1032 |
int ppc_dcr_write (a_ppc_dcr *dcr_env, int dcrn, target_ulong val)
|
|
| 1033 | 1033 |
{
|
| 1034 |
ppc_dcrn_t *dcr;
|
|
| 1034 |
a_ppc_dcrn *dcr;
|
|
| 1035 | 1035 |
|
| 1036 | 1036 |
if (dcrn < 0 || dcrn >= DCRN_NB) |
| 1037 | 1037 |
goto error; |
| ... | ... | |
| 1052 | 1052 |
int ppc_dcr_register (CPUState *env, int dcrn, void *opaque, |
| 1053 | 1053 |
dcr_read_cb dcr_read, dcr_write_cb dcr_write) |
| 1054 | 1054 |
{
|
| 1055 |
ppc_dcr_t *dcr_env;
|
|
| 1056 |
ppc_dcrn_t *dcr;
|
|
| 1055 |
a_ppc_dcr *dcr_env;
|
|
| 1056 |
a_ppc_dcrn *dcr;
|
|
| 1057 | 1057 |
|
| 1058 | 1058 |
dcr_env = env->dcr_env; |
| 1059 | 1059 |
if (dcr_env == NULL) |
| ... | ... | |
| 1075 | 1075 |
int ppc_dcr_init (CPUState *env, int (*read_error)(int dcrn), |
| 1076 | 1076 |
int (*write_error)(int dcrn)) |
| 1077 | 1077 |
{
|
| 1078 |
ppc_dcr_t *dcr_env;
|
|
| 1078 |
a_ppc_dcr *dcr_env;
|
|
| 1079 | 1079 |
|
| 1080 |
dcr_env = qemu_mallocz(sizeof(ppc_dcr_t));
|
|
| 1080 |
dcr_env = qemu_mallocz(sizeof(a_ppc_dcr));
|
|
| 1081 | 1081 |
dcr_env->read_error = read_error; |
| 1082 | 1082 |
dcr_env->write_error = write_error; |
| 1083 | 1083 |
env->dcr_env = dcr_env; |
| ... | ... | |
| 1117 | 1117 |
|
| 1118 | 1118 |
/*****************************************************************************/ |
| 1119 | 1119 |
/* NVRAM helpers */ |
| 1120 |
static inline uint32_t nvram_read (nvram_t *nvram, uint32_t addr)
|
|
| 1120 |
static inline uint32_t nvram_read (a_nvram *nvram, uint32_t addr)
|
|
| 1121 | 1121 |
{
|
| 1122 | 1122 |
return (*nvram->read_fn)(nvram->opaque, addr);; |
| 1123 | 1123 |
} |
| 1124 | 1124 |
|
| 1125 |
static inline void nvram_write (nvram_t *nvram, uint32_t addr, uint32_t val)
|
|
| 1125 |
static inline void nvram_write (a_nvram *nvram, uint32_t addr, uint32_t val)
|
|
| 1126 | 1126 |
{
|
| 1127 | 1127 |
(*nvram->write_fn)(nvram->opaque, addr, val); |
| 1128 | 1128 |
} |
| 1129 | 1129 |
|
| 1130 |
void NVRAM_set_byte (nvram_t *nvram, uint32_t addr, uint8_t value)
|
|
| 1130 |
void NVRAM_set_byte (a_nvram *nvram, uint32_t addr, uint8_t value)
|
|
| 1131 | 1131 |
{
|
| 1132 | 1132 |
nvram_write(nvram, addr, value); |
| 1133 | 1133 |
} |
| 1134 | 1134 |
|
| 1135 |
uint8_t NVRAM_get_byte (nvram_t *nvram, uint32_t addr)
|
|
| 1135 |
uint8_t NVRAM_get_byte (a_nvram *nvram, uint32_t addr)
|
|
| 1136 | 1136 |
{
|
| 1137 | 1137 |
return nvram_read(nvram, addr); |
| 1138 | 1138 |
} |
| 1139 | 1139 |
|
| 1140 |
void NVRAM_set_word (nvram_t *nvram, uint32_t addr, uint16_t value)
|
|
| 1140 |
void NVRAM_set_word (a_nvram *nvram, uint32_t addr, uint16_t value)
|
|
| 1141 | 1141 |
{
|
| 1142 | 1142 |
nvram_write(nvram, addr, value >> 8); |
| 1143 | 1143 |
nvram_write(nvram, addr + 1, value & 0xFF); |
| 1144 | 1144 |
} |
| 1145 | 1145 |
|
| 1146 |
uint16_t NVRAM_get_word (nvram_t *nvram, uint32_t addr)
|
|
| 1146 |
uint16_t NVRAM_get_word (a_nvram *nvram, uint32_t addr)
|
|
| 1147 | 1147 |
{
|
| 1148 | 1148 |
uint16_t tmp; |
| 1149 | 1149 |
|
| ... | ... | |
| 1153 | 1153 |
return tmp; |
| 1154 | 1154 |
} |
| 1155 | 1155 |
|
| 1156 |
void NVRAM_set_lword (nvram_t *nvram, uint32_t addr, uint32_t value)
|
|
| 1156 |
void NVRAM_set_lword (a_nvram *nvram, uint32_t addr, uint32_t value)
|
|
| 1157 | 1157 |
{
|
| 1158 | 1158 |
nvram_write(nvram, addr, value >> 24); |
| 1159 | 1159 |
nvram_write(nvram, addr + 1, (value >> 16) & 0xFF); |
| ... | ... | |
| 1161 | 1161 |
nvram_write(nvram, addr + 3, value & 0xFF); |
| 1162 | 1162 |
} |
| 1163 | 1163 |
|
| 1164 |
uint32_t NVRAM_get_lword (nvram_t *nvram, uint32_t addr)
|
|
| 1164 |
uint32_t NVRAM_get_lword (a_nvram *nvram, uint32_t addr)
|
|
| 1165 | 1165 |
{
|
| 1166 | 1166 |
uint32_t tmp; |
| 1167 | 1167 |
|
| ... | ... | |
| 1173 | 1173 |
return tmp; |
| 1174 | 1174 |
} |
| 1175 | 1175 |
|
| 1176 |
void NVRAM_set_string (nvram_t *nvram, uint32_t addr,
|
|
| 1176 |
void NVRAM_set_string (a_nvram *nvram, uint32_t addr,
|
|
| 1177 | 1177 |
const char *str, uint32_t max) |
| 1178 | 1178 |
{
|
| 1179 | 1179 |
int i; |
| ... | ... | |
| 1185 | 1185 |
nvram_write(nvram, addr + max - 1, '\0'); |
| 1186 | 1186 |
} |
| 1187 | 1187 |
|
| 1188 |
int NVRAM_get_string (nvram_t *nvram, uint8_t *dst, uint16_t addr, int max)
|
|
| 1188 |
int NVRAM_get_string (a_nvram *nvram, uint8_t *dst, uint16_t addr, int max)
|
|
| 1189 | 1189 |
{
|
| 1190 | 1190 |
int i; |
| 1191 | 1191 |
|
| ... | ... | |
| 1214 | 1214 |
return tmp; |
| 1215 | 1215 |
} |
| 1216 | 1216 |
|
| 1217 |
static uint16_t NVRAM_compute_crc (nvram_t *nvram, uint32_t start, uint32_t count)
|
|
| 1217 |
static uint16_t NVRAM_compute_crc (a_nvram *nvram, uint32_t start, uint32_t count)
|
|
| 1218 | 1218 |
{
|
| 1219 | 1219 |
uint32_t i; |
| 1220 | 1220 |
uint16_t crc = 0xFFFF; |
| ... | ... | |
| 1234 | 1234 |
|
| 1235 | 1235 |
#define CMDLINE_ADDR 0x017ff000 |
| 1236 | 1236 |
|
| 1237 |
int PPC_NVRAM_set_params (nvram_t *nvram, uint16_t NVRAM_size,
|
|
| 1237 |
int PPC_NVRAM_set_params (a_nvram *nvram, uint16_t NVRAM_size,
|
|
| 1238 | 1238 |
const char *arch, |
| 1239 | 1239 |
uint32_t RAM_size, int boot_device, |
| 1240 | 1240 |
uint32_t kernel_image, uint32_t kernel_size, |
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