Revision 9a152519 tcg/mips/tcg-target.c
b/tcg/mips/tcg-target.c | ||
---|---|---|
300 | 300 |
OPC_SPECIAL = 0x00 << 26, |
301 | 301 |
OPC_SLL = OPC_SPECIAL | 0x00, |
302 | 302 |
OPC_SRL = OPC_SPECIAL | 0x02, |
303 |
OPC_ROTR = OPC_SPECIAL | (0x01 << 21) | 0x02, |
|
303 | 304 |
OPC_SRA = OPC_SPECIAL | 0x03, |
304 | 305 |
OPC_SLLV = OPC_SPECIAL | 0x04, |
305 | 306 |
OPC_SRLV = OPC_SPECIAL | 0x06, |
307 |
OPC_ROTRV = OPC_SPECIAL | (0x01 << 6) | 0x06, |
|
306 | 308 |
OPC_SRAV = OPC_SPECIAL | 0x07, |
307 | 309 |
OPC_JR = OPC_SPECIAL | 0x08, |
308 | 310 |
OPC_JALR = OPC_SPECIAL | 0x09, |
... | ... | |
1420 | 1422 |
tcg_out_opc_reg(s, OPC_SRLV, args[0], args[2], args[1]); |
1421 | 1423 |
} |
1422 | 1424 |
break; |
1425 |
case INDEX_op_rotl_i32: |
|
1426 |
if (const_args[2]) { |
|
1427 |
tcg_out_opc_sa(s, OPC_ROTR, args[0], args[1], 0x20 - args[2]); |
|
1428 |
} else { |
|
1429 |
tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_AT, 32); |
|
1430 |
tcg_out_opc_reg(s, OPC_SUBU, TCG_REG_AT, TCG_REG_AT, args[2]); |
|
1431 |
tcg_out_opc_reg(s, OPC_ROTRV, args[0], TCG_REG_AT, args[1]); |
|
1432 |
} |
|
1433 |
break; |
|
1434 |
case INDEX_op_rotr_i32: |
|
1435 |
if (const_args[2]) { |
|
1436 |
tcg_out_opc_sa(s, OPC_ROTR, args[0], args[1], args[2]); |
|
1437 |
} else { |
|
1438 |
tcg_out_opc_reg(s, OPC_ROTRV, args[0], args[2], args[1]); |
|
1439 |
} |
|
1440 |
break; |
|
1423 | 1441 |
|
1424 | 1442 |
/* The bswap routines do not work on non-R2 CPU. In that case |
1425 | 1443 |
we let TCG generating the corresponding code. */ |
... | ... | |
1523 | 1541 |
{ INDEX_op_shl_i32, { "r", "rZ", "ri" } }, |
1524 | 1542 |
{ INDEX_op_shr_i32, { "r", "rZ", "ri" } }, |
1525 | 1543 |
{ INDEX_op_sar_i32, { "r", "rZ", "ri" } }, |
1544 |
{ INDEX_op_rotr_i32, { "r", "rZ", "ri" } }, |
|
1545 |
{ INDEX_op_rotl_i32, { "r", "rZ", "ri" } }, |
|
1526 | 1546 |
|
1527 | 1547 |
{ INDEX_op_bswap16_i32, { "r", "r" } }, |
1528 | 1548 |
{ INDEX_op_bswap32_i32, { "r", "r" } }, |
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