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1 | 3475187d | bellard | /*
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2 | 3475187d | bellard | * QEMU Sun4u System Emulator
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3 | 5fafdf24 | ths | *
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4 | 3475187d | bellard | * Copyright (c) 2005 Fabrice Bellard
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5 | 5fafdf24 | ths | *
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6 | 3475187d | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 3475187d | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 3475187d | bellard | * in the Software without restriction, including without limitation the rights
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9 | 3475187d | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 3475187d | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 3475187d | bellard | * furnished to do so, subject to the following conditions:
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12 | 3475187d | bellard | *
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13 | 3475187d | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 3475187d | bellard | * all copies or substantial portions of the Software.
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15 | 3475187d | bellard | *
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16 | 3475187d | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 3475187d | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 3475187d | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 3475187d | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 3475187d | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 3475187d | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 3475187d | bellard | * THE SOFTWARE.
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23 | 3475187d | bellard | */
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24 | 87ecb68b | pbrook | #include "hw.h" |
25 | 87ecb68b | pbrook | #include "pci.h" |
26 | 87ecb68b | pbrook | #include "pc.h" |
27 | 87ecb68b | pbrook | #include "nvram.h" |
28 | 87ecb68b | pbrook | #include "fdc.h" |
29 | 87ecb68b | pbrook | #include "net.h" |
30 | 87ecb68b | pbrook | #include "qemu-timer.h" |
31 | 87ecb68b | pbrook | #include "sysemu.h" |
32 | 87ecb68b | pbrook | #include "boards.h" |
33 | d2c63fc1 | blueswir1 | #include "firmware_abi.h" |
34 | 3475187d | bellard | |
35 | 83469015 | bellard | #define KERNEL_LOAD_ADDR 0x00404000 |
36 | 83469015 | bellard | #define CMDLINE_ADDR 0x003ff000 |
37 | 83469015 | bellard | #define INITRD_LOAD_ADDR 0x00300000 |
38 | 75956cf0 | pbrook | #define PROM_SIZE_MAX (512 * 1024) |
39 | f930d07e | blueswir1 | #define PROM_ADDR 0x1fff0000000ULL |
40 | f930d07e | blueswir1 | #define PROM_VADDR 0x000ffd00000ULL |
41 | 83469015 | bellard | #define APB_SPECIAL_BASE 0x1fe00000000ULL |
42 | f930d07e | blueswir1 | #define APB_MEM_BASE 0x1ff00000000ULL |
43 | f930d07e | blueswir1 | #define VGA_BASE (APB_MEM_BASE + 0x400000ULL) |
44 | f930d07e | blueswir1 | #define PROM_FILENAME "openbios-sparc64" |
45 | 83469015 | bellard | #define NVRAM_SIZE 0x2000 |
46 | e4bcb14c | ths | #define MAX_IDE_BUS 2 |
47 | 3475187d | bellard | |
48 | 3475187d | bellard | /* TSC handling */
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49 | 3475187d | bellard | |
50 | 3475187d | bellard | uint64_t cpu_get_tsc() |
51 | 3475187d | bellard | { |
52 | 3475187d | bellard | return qemu_get_clock(vm_clock);
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53 | 3475187d | bellard | } |
54 | 3475187d | bellard | |
55 | 3475187d | bellard | int DMA_get_channel_mode (int nchan) |
56 | 3475187d | bellard | { |
57 | 3475187d | bellard | return 0; |
58 | 3475187d | bellard | } |
59 | 3475187d | bellard | int DMA_read_memory (int nchan, void *buf, int pos, int size) |
60 | 3475187d | bellard | { |
61 | 3475187d | bellard | return 0; |
62 | 3475187d | bellard | } |
63 | 3475187d | bellard | int DMA_write_memory (int nchan, void *buf, int pos, int size) |
64 | 3475187d | bellard | { |
65 | 3475187d | bellard | return 0; |
66 | 3475187d | bellard | } |
67 | 3475187d | bellard | void DMA_hold_DREQ (int nchan) {} |
68 | 3475187d | bellard | void DMA_release_DREQ (int nchan) {} |
69 | 3475187d | bellard | void DMA_schedule(int nchan) {} |
70 | 3475187d | bellard | void DMA_run (void) {} |
71 | 3475187d | bellard | void DMA_init (int high_page_enable) {} |
72 | 3475187d | bellard | void DMA_register_channel (int nchan, |
73 | 3475187d | bellard | DMA_transfer_handler transfer_handler, |
74 | 3475187d | bellard | void *opaque)
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75 | 3475187d | bellard | { |
76 | 3475187d | bellard | } |
77 | 3475187d | bellard | |
78 | 3475187d | bellard | extern int nographic; |
79 | 3475187d | bellard | |
80 | d2c63fc1 | blueswir1 | static int sun4u_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size, |
81 | d2c63fc1 | blueswir1 | const unsigned char *arch, |
82 | d2c63fc1 | blueswir1 | uint32_t RAM_size, const char *boot_devices, |
83 | d2c63fc1 | blueswir1 | uint32_t kernel_image, uint32_t kernel_size, |
84 | d2c63fc1 | blueswir1 | const char *cmdline, |
85 | d2c63fc1 | blueswir1 | uint32_t initrd_image, uint32_t initrd_size, |
86 | d2c63fc1 | blueswir1 | uint32_t NVRAM_image, |
87 | d2c63fc1 | blueswir1 | int width, int height, int depth) |
88 | 83469015 | bellard | { |
89 | 66508601 | blueswir1 | unsigned int i; |
90 | 66508601 | blueswir1 | uint32_t start, end; |
91 | d2c63fc1 | blueswir1 | uint8_t image[0x1ff0];
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92 | d2c63fc1 | blueswir1 | ohwcfg_v3_t *header = (ohwcfg_v3_t *)ℑ |
93 | d2c63fc1 | blueswir1 | struct sparc_arch_cfg *sparc_header;
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94 | d2c63fc1 | blueswir1 | struct OpenBIOS_nvpart_v1 *part_header;
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95 | d2c63fc1 | blueswir1 | |
96 | d2c63fc1 | blueswir1 | memset(image, '\0', sizeof(image)); |
97 | d2c63fc1 | blueswir1 | |
98 | d2c63fc1 | blueswir1 | // Try to match PPC NVRAM
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99 | d2c63fc1 | blueswir1 | strcpy(header->struct_ident, "QEMU_BIOS");
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100 | d2c63fc1 | blueswir1 | header->struct_version = cpu_to_be32(3); /* structure v3 */ |
101 | d2c63fc1 | blueswir1 | |
102 | d2c63fc1 | blueswir1 | header->nvram_size = cpu_to_be16(NVRAM_size); |
103 | d2c63fc1 | blueswir1 | header->nvram_arch_ptr = cpu_to_be16(sizeof(ohwcfg_v3_t));
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104 | d2c63fc1 | blueswir1 | header->nvram_arch_size = cpu_to_be16(sizeof(struct sparc_arch_cfg)); |
105 | d2c63fc1 | blueswir1 | strcpy(header->arch, arch); |
106 | d2c63fc1 | blueswir1 | header->nb_cpus = smp_cpus & 0xff;
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107 | d2c63fc1 | blueswir1 | header->RAM0_base = 0;
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108 | d2c63fc1 | blueswir1 | header->RAM0_size = cpu_to_be64((uint64_t)RAM_size); |
109 | d2c63fc1 | blueswir1 | strcpy(header->boot_devices, boot_devices); |
110 | d2c63fc1 | blueswir1 | header->nboot_devices = strlen(boot_devices) & 0xff;
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111 | d2c63fc1 | blueswir1 | header->kernel_image = cpu_to_be64((uint64_t)kernel_image); |
112 | d2c63fc1 | blueswir1 | header->kernel_size = cpu_to_be64((uint64_t)kernel_size); |
113 | 3475187d | bellard | if (cmdline) {
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114 | 83469015 | bellard | strcpy(phys_ram_base + CMDLINE_ADDR, cmdline); |
115 | d2c63fc1 | blueswir1 | header->cmdline = cpu_to_be64((uint64_t)CMDLINE_ADDR); |
116 | d2c63fc1 | blueswir1 | header->cmdline_size = cpu_to_be64((uint64_t)strlen(cmdline)); |
117 | 3475187d | bellard | } |
118 | d2c63fc1 | blueswir1 | header->initrd_image = cpu_to_be64((uint64_t)initrd_image); |
119 | d2c63fc1 | blueswir1 | header->initrd_size = cpu_to_be64((uint64_t)initrd_size); |
120 | d2c63fc1 | blueswir1 | header->NVRAM_image = cpu_to_be64((uint64_t)NVRAM_image); |
121 | d2c63fc1 | blueswir1 | |
122 | d2c63fc1 | blueswir1 | header->width = cpu_to_be16(width); |
123 | d2c63fc1 | blueswir1 | header->height = cpu_to_be16(height); |
124 | d2c63fc1 | blueswir1 | header->depth = cpu_to_be16(depth); |
125 | d2c63fc1 | blueswir1 | if (nographic)
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126 | d2c63fc1 | blueswir1 | header->graphic_flags = cpu_to_be16(OHW_GF_NOGRAPHICS); |
127 | 83469015 | bellard | |
128 | d2c63fc1 | blueswir1 | header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8)); |
129 | d2c63fc1 | blueswir1 | |
130 | d2c63fc1 | blueswir1 | // Architecture specific header
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131 | d2c63fc1 | blueswir1 | start = sizeof(ohwcfg_v3_t);
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132 | d2c63fc1 | blueswir1 | sparc_header = (struct sparc_arch_cfg *)&image[start];
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133 | d2c63fc1 | blueswir1 | sparc_header->valid = 0;
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134 | d2c63fc1 | blueswir1 | start += sizeof(struct sparc_arch_cfg); |
135 | 83469015 | bellard | |
136 | 66508601 | blueswir1 | // OpenBIOS nvram variables
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137 | 66508601 | blueswir1 | // Variable partition
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138 | d2c63fc1 | blueswir1 | part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
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139 | d2c63fc1 | blueswir1 | part_header->signature = OPENBIOS_PART_SYSTEM; |
140 | d2c63fc1 | blueswir1 | strcpy(part_header->name, "system");
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141 | 66508601 | blueswir1 | |
142 | d2c63fc1 | blueswir1 | end = start + sizeof(struct OpenBIOS_nvpart_v1); |
143 | 66508601 | blueswir1 | for (i = 0; i < nb_prom_envs; i++) |
144 | d2c63fc1 | blueswir1 | end = OpenBIOS_set_var(image, end, prom_envs[i]); |
145 | d2c63fc1 | blueswir1 | |
146 | d2c63fc1 | blueswir1 | // End marker
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147 | d2c63fc1 | blueswir1 | image[end++] = '\0';
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148 | 66508601 | blueswir1 | |
149 | 66508601 | blueswir1 | end = start + ((end - start + 15) & ~15); |
150 | d2c63fc1 | blueswir1 | OpenBIOS_finish_partition(part_header, end - start); |
151 | 66508601 | blueswir1 | |
152 | 66508601 | blueswir1 | // free partition
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153 | 66508601 | blueswir1 | start = end; |
154 | d2c63fc1 | blueswir1 | part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
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155 | d2c63fc1 | blueswir1 | part_header->signature = OPENBIOS_PART_FREE; |
156 | d2c63fc1 | blueswir1 | strcpy(part_header->name, "free");
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157 | 66508601 | blueswir1 | |
158 | 66508601 | blueswir1 | end = 0x1fd0;
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159 | d2c63fc1 | blueswir1 | OpenBIOS_finish_partition(part_header, end - start); |
160 | d2c63fc1 | blueswir1 | |
161 | d2c63fc1 | blueswir1 | for (i = 0; i < sizeof(image); i++) |
162 | d2c63fc1 | blueswir1 | m48t59_write(nvram, i, image[i]); |
163 | 66508601 | blueswir1 | |
164 | 83469015 | bellard | return 0; |
165 | 3475187d | bellard | } |
166 | 3475187d | bellard | |
167 | 3475187d | bellard | void pic_info()
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168 | 3475187d | bellard | { |
169 | 3475187d | bellard | } |
170 | 3475187d | bellard | |
171 | 3475187d | bellard | void irq_info()
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172 | 3475187d | bellard | { |
173 | 3475187d | bellard | } |
174 | 3475187d | bellard | |
175 | 83469015 | bellard | void qemu_system_powerdown(void) |
176 | 3475187d | bellard | { |
177 | 3475187d | bellard | } |
178 | 3475187d | bellard | |
179 | c68ea704 | bellard | static void main_cpu_reset(void *opaque) |
180 | c68ea704 | bellard | { |
181 | c68ea704 | bellard | CPUState *env = opaque; |
182 | 20c9f095 | blueswir1 | |
183 | c68ea704 | bellard | cpu_reset(env); |
184 | 20c9f095 | blueswir1 | ptimer_set_limit(env->tick, 0x7fffffffffffffffULL, 1); |
185 | 20c9f095 | blueswir1 | ptimer_run(env->tick, 0);
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186 | 20c9f095 | blueswir1 | ptimer_set_limit(env->stick, 0x7fffffffffffffffULL, 1); |
187 | 20c9f095 | blueswir1 | ptimer_run(env->stick, 0);
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188 | 20c9f095 | blueswir1 | ptimer_set_limit(env->hstick, 0x7fffffffffffffffULL, 1); |
189 | 20c9f095 | blueswir1 | ptimer_run(env->hstick, 0);
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190 | 20c9f095 | blueswir1 | } |
191 | 20c9f095 | blueswir1 | |
192 | 20c9f095 | blueswir1 | void tick_irq(void *opaque) |
193 | 20c9f095 | blueswir1 | { |
194 | 20c9f095 | blueswir1 | CPUState *env = opaque; |
195 | 20c9f095 | blueswir1 | |
196 | 20c9f095 | blueswir1 | cpu_interrupt(env, CPU_INTERRUPT_TIMER); |
197 | 20c9f095 | blueswir1 | } |
198 | 20c9f095 | blueswir1 | |
199 | 20c9f095 | blueswir1 | void stick_irq(void *opaque) |
200 | 20c9f095 | blueswir1 | { |
201 | 20c9f095 | blueswir1 | CPUState *env = opaque; |
202 | 20c9f095 | blueswir1 | |
203 | 20c9f095 | blueswir1 | cpu_interrupt(env, CPU_INTERRUPT_TIMER); |
204 | 20c9f095 | blueswir1 | } |
205 | 20c9f095 | blueswir1 | |
206 | 20c9f095 | blueswir1 | void hstick_irq(void *opaque) |
207 | 20c9f095 | blueswir1 | { |
208 | 20c9f095 | blueswir1 | CPUState *env = opaque; |
209 | 20c9f095 | blueswir1 | |
210 | 20c9f095 | blueswir1 | cpu_interrupt(env, CPU_INTERRUPT_TIMER); |
211 | c68ea704 | bellard | } |
212 | c68ea704 | bellard | |
213 | f19e918d | blueswir1 | static void dummy_cpu_set_irq(void *opaque, int irq, int level) |
214 | f19e918d | blueswir1 | { |
215 | f19e918d | blueswir1 | } |
216 | f19e918d | blueswir1 | |
217 | 83469015 | bellard | static const int ide_iobase[2] = { 0x1f0, 0x170 }; |
218 | 83469015 | bellard | static const int ide_iobase2[2] = { 0x3f6, 0x376 }; |
219 | 83469015 | bellard | static const int ide_irq[2] = { 14, 15 }; |
220 | 3475187d | bellard | |
221 | 83469015 | bellard | static const int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 }; |
222 | 83469015 | bellard | static const int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 }; |
223 | 83469015 | bellard | |
224 | 83469015 | bellard | static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc }; |
225 | 83469015 | bellard | static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 }; |
226 | 83469015 | bellard | |
227 | 83469015 | bellard | static fdctrl_t *floppy_controller;
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228 | 3475187d | bellard | |
229 | 3475187d | bellard | /* Sun4u hardware initialisation */
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230 | b881c2c6 | blueswir1 | static void sun4u_init(int ram_size, int vga_ram_size, |
231 | b881c2c6 | blueswir1 | const char *boot_devices, DisplayState *ds, |
232 | b881c2c6 | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
233 | b881c2c6 | blueswir1 | const char *initrd_filename, const char *cpu_model) |
234 | 3475187d | bellard | { |
235 | c68ea704 | bellard | CPUState *env; |
236 | 3475187d | bellard | char buf[1024]; |
237 | 83469015 | bellard | m48t59_t *nvram; |
238 | 3475187d | bellard | int ret, linux_boot;
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239 | 3475187d | bellard | unsigned int i; |
240 | 83469015 | bellard | long prom_offset, initrd_size, kernel_size;
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241 | 83469015 | bellard | PCIBus *pci_bus; |
242 | 20c9f095 | blueswir1 | QEMUBH *bh; |
243 | f19e918d | blueswir1 | qemu_irq *irq; |
244 | e4bcb14c | ths | int index;
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245 | e4bcb14c | ths | BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; |
246 | e4bcb14c | ths | BlockDriverState *fd[MAX_FD]; |
247 | 3475187d | bellard | |
248 | 3475187d | bellard | linux_boot = (kernel_filename != NULL);
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249 | 3475187d | bellard | |
250 | 62724a37 | blueswir1 | /* init CPUs */
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251 | 62724a37 | blueswir1 | if (cpu_model == NULL) |
252 | 62724a37 | blueswir1 | cpu_model = "TI UltraSparc II";
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253 | aaed909a | bellard | env = cpu_init(cpu_model); |
254 | aaed909a | bellard | if (!env) {
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255 | 62724a37 | blueswir1 | fprintf(stderr, "Unable to find Sparc CPU definition\n");
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256 | 62724a37 | blueswir1 | exit(1);
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257 | 62724a37 | blueswir1 | } |
258 | 20c9f095 | blueswir1 | bh = qemu_bh_new(tick_irq, env); |
259 | 20c9f095 | blueswir1 | env->tick = ptimer_init(bh); |
260 | 20c9f095 | blueswir1 | ptimer_set_period(env->tick, 1ULL);
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261 | 20c9f095 | blueswir1 | |
262 | 20c9f095 | blueswir1 | bh = qemu_bh_new(stick_irq, env); |
263 | 20c9f095 | blueswir1 | env->stick = ptimer_init(bh); |
264 | 20c9f095 | blueswir1 | ptimer_set_period(env->stick, 1ULL);
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265 | 20c9f095 | blueswir1 | |
266 | 20c9f095 | blueswir1 | bh = qemu_bh_new(hstick_irq, env); |
267 | 20c9f095 | blueswir1 | env->hstick = ptimer_init(bh); |
268 | 20c9f095 | blueswir1 | ptimer_set_period(env->hstick, 1ULL);
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269 | c68ea704 | bellard | register_savevm("cpu", 0, 3, cpu_save, cpu_load, env); |
270 | c68ea704 | bellard | qemu_register_reset(main_cpu_reset, env); |
271 | 20c9f095 | blueswir1 | main_cpu_reset(env); |
272 | c68ea704 | bellard | |
273 | 3475187d | bellard | /* allocate RAM */
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274 | 3475187d | bellard | cpu_register_physical_memory(0, ram_size, 0); |
275 | 3475187d | bellard | |
276 | 83469015 | bellard | prom_offset = ram_size + vga_ram_size; |
277 | 5fafdf24 | ths | cpu_register_physical_memory(PROM_ADDR, |
278 | 5fafdf24 | ths | (PROM_SIZE_MAX + TARGET_PAGE_SIZE) & TARGET_PAGE_MASK, |
279 | b3783731 | bellard | prom_offset | IO_MEM_ROM); |
280 | 3475187d | bellard | |
281 | 1192dad8 | j_mayer | if (bios_name == NULL) |
282 | 1192dad8 | j_mayer | bios_name = PROM_FILENAME; |
283 | 1192dad8 | j_mayer | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name); |
284 | f19e918d | blueswir1 | ret = load_elf(buf, PROM_ADDR - PROM_VADDR, NULL, NULL, NULL); |
285 | 3475187d | bellard | if (ret < 0) { |
286 | f930d07e | blueswir1 | fprintf(stderr, "qemu: could not load prom '%s'\n",
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287 | f930d07e | blueswir1 | buf); |
288 | f930d07e | blueswir1 | exit(1);
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289 | 3475187d | bellard | } |
290 | 3475187d | bellard | |
291 | 3475187d | bellard | kernel_size = 0;
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292 | 83469015 | bellard | initrd_size = 0;
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293 | 3475187d | bellard | if (linux_boot) {
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294 | b3783731 | bellard | /* XXX: put correct offset */
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295 | 74287114 | ths | kernel_size = load_elf(kernel_filename, 0, NULL, NULL, NULL); |
296 | 3475187d | bellard | if (kernel_size < 0) |
297 | f930d07e | blueswir1 | kernel_size = load_aout(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR); |
298 | f930d07e | blueswir1 | if (kernel_size < 0) |
299 | f930d07e | blueswir1 | kernel_size = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR); |
300 | 3475187d | bellard | if (kernel_size < 0) { |
301 | 5fafdf24 | ths | fprintf(stderr, "qemu: could not load kernel '%s'\n",
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302 | 3475187d | bellard | kernel_filename); |
303 | f930d07e | blueswir1 | exit(1);
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304 | 3475187d | bellard | } |
305 | 3475187d | bellard | |
306 | 3475187d | bellard | /* load initrd */
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307 | 3475187d | bellard | if (initrd_filename) {
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308 | 3475187d | bellard | initrd_size = load_image(initrd_filename, phys_ram_base + INITRD_LOAD_ADDR); |
309 | 3475187d | bellard | if (initrd_size < 0) { |
310 | 5fafdf24 | ths | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
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311 | 3475187d | bellard | initrd_filename); |
312 | 3475187d | bellard | exit(1);
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313 | 3475187d | bellard | } |
314 | 3475187d | bellard | } |
315 | 3475187d | bellard | if (initrd_size > 0) { |
316 | f930d07e | blueswir1 | for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { |
317 | f930d07e | blueswir1 | if (ldl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i)
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318 | f930d07e | blueswir1 | == 0x48647253) { // HdrS |
319 | f930d07e | blueswir1 | stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
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320 | f930d07e | blueswir1 | stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 20, initrd_size);
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321 | f930d07e | blueswir1 | break;
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322 | f930d07e | blueswir1 | } |
323 | f930d07e | blueswir1 | } |
324 | 3475187d | bellard | } |
325 | 3475187d | bellard | } |
326 | 502a5395 | pbrook | pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, NULL);
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327 | 83469015 | bellard | isa_mem_base = VGA_BASE; |
328 | 75956cf0 | pbrook | pci_cirrus_vga_init(pci_bus, ds, phys_ram_base + ram_size, ram_size, vga_ram_size); |
329 | 83469015 | bellard | |
330 | 83469015 | bellard | for(i = 0; i < MAX_SERIAL_PORTS; i++) { |
331 | 83469015 | bellard | if (serial_hds[i]) {
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332 | d537cf6c | pbrook | serial_init(serial_io[i], NULL/*serial_irq[i]*/, serial_hds[i]); |
333 | 83469015 | bellard | } |
334 | 83469015 | bellard | } |
335 | 83469015 | bellard | |
336 | 83469015 | bellard | for(i = 0; i < MAX_PARALLEL_PORTS; i++) { |
337 | 83469015 | bellard | if (parallel_hds[i]) {
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338 | d537cf6c | pbrook | parallel_init(parallel_io[i], NULL/*parallel_irq[i]*/, parallel_hds[i]); |
339 | 83469015 | bellard | } |
340 | 83469015 | bellard | } |
341 | 83469015 | bellard | |
342 | 83469015 | bellard | for(i = 0; i < nb_nics; i++) { |
343 | a41b2ff2 | pbrook | if (!nd_table[i].model)
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344 | a41b2ff2 | pbrook | nd_table[i].model = "ne2k_pci";
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345 | f930d07e | blueswir1 | pci_nic_init(pci_bus, &nd_table[i], -1);
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346 | 83469015 | bellard | } |
347 | 83469015 | bellard | |
348 | f19e918d | blueswir1 | irq = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, 32); |
349 | e4bcb14c | ths | if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
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350 | e4bcb14c | ths | fprintf(stderr, "qemu: too many IDE bus\n");
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351 | e4bcb14c | ths | exit(1);
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352 | e4bcb14c | ths | } |
353 | e4bcb14c | ths | for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) { |
354 | e4bcb14c | ths | index = drive_get_index(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS); |
355 | e4bcb14c | ths | if (index != -1) |
356 | e4bcb14c | ths | hd[i] = drives_table[index].bdrv; |
357 | e4bcb14c | ths | else
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358 | e4bcb14c | ths | hd[i] = NULL;
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359 | e4bcb14c | ths | } |
360 | e4bcb14c | ths | |
361 | e4bcb14c | ths | // XXX pci_cmd646_ide_init(pci_bus, hd, 1);
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362 | e4bcb14c | ths | pci_piix3_ide_init(pci_bus, hd, -1, irq);
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363 | d537cf6c | pbrook | /* FIXME: wire up interrupts. */
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364 | d537cf6c | pbrook | i8042_init(NULL/*1*/, NULL/*12*/, 0x60); |
365 | e4bcb14c | ths | for(i = 0; i < MAX_FD; i++) { |
366 | e4bcb14c | ths | index = drive_get_index(IF_FLOPPY, 0, i);
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367 | e4bcb14c | ths | if (index != -1) |
368 | e4bcb14c | ths | fd[i] = drives_table[index].bdrv; |
369 | e4bcb14c | ths | else
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370 | e4bcb14c | ths | fd[i] = NULL;
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371 | e4bcb14c | ths | } |
372 | e4bcb14c | ths | floppy_controller = fdctrl_init(NULL/*6*/, 2, 0, 0x3f0, fd); |
373 | d537cf6c | pbrook | nvram = m48t59_init(NULL/*8*/, 0, 0x0074, NVRAM_SIZE, 59); |
374 | d2c63fc1 | blueswir1 | sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", ram_size, boot_devices,
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375 | 83469015 | bellard | KERNEL_LOAD_ADDR, kernel_size, |
376 | 83469015 | bellard | kernel_cmdline, |
377 | 83469015 | bellard | INITRD_LOAD_ADDR, initrd_size, |
378 | 83469015 | bellard | /* XXX: need an option to load a NVRAM image */
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379 | 83469015 | bellard | 0,
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380 | 83469015 | bellard | graphic_width, graphic_height, graphic_depth); |
381 | 83469015 | bellard | |
382 | 3475187d | bellard | } |
383 | 3475187d | bellard | |
384 | 3475187d | bellard | QEMUMachine sun4u_machine = { |
385 | 3475187d | bellard | "sun4u",
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386 | 3475187d | bellard | "Sun4u platform",
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387 | 3475187d | bellard | sun4u_init, |
388 | 3475187d | bellard | }; |