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1 | 7e1543c2 | pbrook | /*
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2 | 7e1543c2 | pbrook | * ARM AMBA PrimeCell PL031 RTC
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3 | 7e1543c2 | pbrook | *
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4 | 7e1543c2 | pbrook | * Copyright (c) 2007 CodeSourcery
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5 | 7e1543c2 | pbrook | *
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6 | 7e1543c2 | pbrook | * This file is free software; you can redistribute it and/or modify
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7 | 7e1543c2 | pbrook | * it under the terms of the GNU General Public License version 2 as
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8 | 7e1543c2 | pbrook | * published by the Free Software Foundation.
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9 | 7e1543c2 | pbrook | *
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10 | 6b620ca3 | Paolo Bonzini | * Contributions after 2012-01-13 are licensed under the terms of the
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11 | 6b620ca3 | Paolo Bonzini | * GNU GPL, version 2 or (at your option) any later version.
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12 | 7e1543c2 | pbrook | */
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13 | 7e1543c2 | pbrook | |
14 | a63bdb31 | Paul Brook | #include "sysbus.h" |
15 | 87ecb68b | pbrook | #include "qemu-timer.h" |
16 | b0f26631 | Paolo Bonzini | #include "sysemu.h" |
17 | 7e1543c2 | pbrook | |
18 | 7e1543c2 | pbrook | //#define DEBUG_PL031
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19 | 7e1543c2 | pbrook | |
20 | 7e1543c2 | pbrook | #ifdef DEBUG_PL031
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21 | 001faf32 | Blue Swirl | #define DPRINTF(fmt, ...) \
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22 | 001faf32 | Blue Swirl | do { printf("pl031: " fmt , ## __VA_ARGS__); } while (0) |
23 | 7e1543c2 | pbrook | #else
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24 | 001faf32 | Blue Swirl | #define DPRINTF(fmt, ...) do {} while(0) |
25 | 7e1543c2 | pbrook | #endif
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26 | 7e1543c2 | pbrook | |
27 | 7e1543c2 | pbrook | #define RTC_DR 0x00 /* Data read register */ |
28 | 7e1543c2 | pbrook | #define RTC_MR 0x04 /* Match register */ |
29 | 7e1543c2 | pbrook | #define RTC_LR 0x08 /* Data load register */ |
30 | 7e1543c2 | pbrook | #define RTC_CR 0x0c /* Control register */ |
31 | 7e1543c2 | pbrook | #define RTC_IMSC 0x10 /* Interrupt mask and set register */ |
32 | 7e1543c2 | pbrook | #define RTC_RIS 0x14 /* Raw interrupt status register */ |
33 | 7e1543c2 | pbrook | #define RTC_MIS 0x18 /* Masked interrupt status register */ |
34 | 7e1543c2 | pbrook | #define RTC_ICR 0x1c /* Interrupt clear register */ |
35 | 7e1543c2 | pbrook | |
36 | 7e1543c2 | pbrook | typedef struct { |
37 | a63bdb31 | Paul Brook | SysBusDevice busdev; |
38 | 9edbe481 | Avi Kivity | MemoryRegion iomem; |
39 | 7e1543c2 | pbrook | QEMUTimer *timer; |
40 | 7e1543c2 | pbrook | qemu_irq irq; |
41 | 7e1543c2 | pbrook | |
42 | b0f26631 | Paolo Bonzini | /* Needed to preserve the tick_count across migration, even if the
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43 | b0f26631 | Paolo Bonzini | * absolute value of the rtc_clock is different on the source and
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44 | b0f26631 | Paolo Bonzini | * destination.
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45 | b0f26631 | Paolo Bonzini | */
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46 | b0f26631 | Paolo Bonzini | uint32_t tick_offset_vmstate; |
47 | 7e1543c2 | pbrook | uint32_t tick_offset; |
48 | 7e1543c2 | pbrook | |
49 | 7e1543c2 | pbrook | uint32_t mr; |
50 | 7e1543c2 | pbrook | uint32_t lr; |
51 | 7e1543c2 | pbrook | uint32_t cr; |
52 | 7e1543c2 | pbrook | uint32_t im; |
53 | 7e1543c2 | pbrook | uint32_t is; |
54 | 7e1543c2 | pbrook | } pl031_state; |
55 | 7e1543c2 | pbrook | |
56 | 7e1543c2 | pbrook | static const unsigned char pl031_id[] = { |
57 | 7e1543c2 | pbrook | 0x31, 0x10, 0x14, 0x00, /* Device ID */ |
58 | 7e1543c2 | pbrook | 0x0d, 0xf0, 0x05, 0xb1 /* Cell ID */ |
59 | 7e1543c2 | pbrook | }; |
60 | 7e1543c2 | pbrook | |
61 | 7e1543c2 | pbrook | static void pl031_update(pl031_state *s) |
62 | 7e1543c2 | pbrook | { |
63 | 7e1543c2 | pbrook | qemu_set_irq(s->irq, s->is & s->im); |
64 | 7e1543c2 | pbrook | } |
65 | 7e1543c2 | pbrook | |
66 | 7e1543c2 | pbrook | static void pl031_interrupt(void * opaque) |
67 | 7e1543c2 | pbrook | { |
68 | 7e1543c2 | pbrook | pl031_state *s = (pl031_state *)opaque; |
69 | 7e1543c2 | pbrook | |
70 | 13a16f1d | Peter Maydell | s->is = 1;
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71 | 7e1543c2 | pbrook | DPRINTF("Alarm raised\n");
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72 | 7e1543c2 | pbrook | pl031_update(s); |
73 | 7e1543c2 | pbrook | } |
74 | 7e1543c2 | pbrook | |
75 | 7e1543c2 | pbrook | static uint32_t pl031_get_count(pl031_state *s)
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76 | 7e1543c2 | pbrook | { |
77 | b0f26631 | Paolo Bonzini | int64_t now = qemu_get_clock_ns(rtc_clock); |
78 | b0f26631 | Paolo Bonzini | return s->tick_offset + now / get_ticks_per_sec();
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79 | 7e1543c2 | pbrook | } |
80 | 7e1543c2 | pbrook | |
81 | 7e1543c2 | pbrook | static void pl031_set_alarm(pl031_state *s) |
82 | 7e1543c2 | pbrook | { |
83 | 7e1543c2 | pbrook | uint32_t ticks; |
84 | 7e1543c2 | pbrook | |
85 | 7e1543c2 | pbrook | /* The timer wraps around. This subtraction also wraps in the same way,
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86 | 7e1543c2 | pbrook | and gives correct results when alarm < now_ticks. */
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87 | b0f26631 | Paolo Bonzini | ticks = s->mr - pl031_get_count(s); |
88 | 7e1543c2 | pbrook | DPRINTF("Alarm set in %ud ticks\n", ticks);
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89 | 7e1543c2 | pbrook | if (ticks == 0) { |
90 | 7e1543c2 | pbrook | qemu_del_timer(s->timer); |
91 | 7e1543c2 | pbrook | pl031_interrupt(s); |
92 | 7e1543c2 | pbrook | } else {
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93 | b0f26631 | Paolo Bonzini | int64_t now = qemu_get_clock_ns(rtc_clock); |
94 | 6ee093c9 | Juan Quintela | qemu_mod_timer(s->timer, now + (int64_t)ticks * get_ticks_per_sec()); |
95 | 7e1543c2 | pbrook | } |
96 | 7e1543c2 | pbrook | } |
97 | 7e1543c2 | pbrook | |
98 | 9edbe481 | Avi Kivity | static uint64_t pl031_read(void *opaque, target_phys_addr_t offset, |
99 | 9edbe481 | Avi Kivity | unsigned size)
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100 | 7e1543c2 | pbrook | { |
101 | 7e1543c2 | pbrook | pl031_state *s = (pl031_state *)opaque; |
102 | 7e1543c2 | pbrook | |
103 | 7e1543c2 | pbrook | if (offset >= 0xfe0 && offset < 0x1000) |
104 | 7e1543c2 | pbrook | return pl031_id[(offset - 0xfe0) >> 2]; |
105 | 7e1543c2 | pbrook | |
106 | 7e1543c2 | pbrook | switch (offset) {
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107 | 7e1543c2 | pbrook | case RTC_DR:
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108 | 7e1543c2 | pbrook | return pl031_get_count(s);
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109 | 7e1543c2 | pbrook | case RTC_MR:
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110 | 7e1543c2 | pbrook | return s->mr;
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111 | 7e1543c2 | pbrook | case RTC_IMSC:
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112 | 7e1543c2 | pbrook | return s->im;
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113 | 7e1543c2 | pbrook | case RTC_RIS:
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114 | 7e1543c2 | pbrook | return s->is;
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115 | 7e1543c2 | pbrook | case RTC_LR:
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116 | 7e1543c2 | pbrook | return s->lr;
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117 | 7e1543c2 | pbrook | case RTC_CR:
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118 | 7e1543c2 | pbrook | /* RTC is permanently enabled. */
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119 | 7e1543c2 | pbrook | return 1; |
120 | 7e1543c2 | pbrook | case RTC_MIS:
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121 | 7e1543c2 | pbrook | return s->is & s->im;
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122 | 7e1543c2 | pbrook | case RTC_ICR:
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123 | 7e1543c2 | pbrook | fprintf(stderr, "qemu: pl031_read: Unexpected offset 0x%x\n",
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124 | 7e1543c2 | pbrook | (int)offset);
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125 | 7e1543c2 | pbrook | break;
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126 | 7e1543c2 | pbrook | default:
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127 | 2ac71179 | Paul Brook | hw_error("pl031_read: Bad offset 0x%x\n", (int)offset); |
128 | 7e1543c2 | pbrook | break;
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129 | 7e1543c2 | pbrook | } |
130 | 7e1543c2 | pbrook | |
131 | 7e1543c2 | pbrook | return 0; |
132 | 7e1543c2 | pbrook | } |
133 | 7e1543c2 | pbrook | |
134 | c227f099 | Anthony Liguori | static void pl031_write(void * opaque, target_phys_addr_t offset, |
135 | 9edbe481 | Avi Kivity | uint64_t value, unsigned size)
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136 | 7e1543c2 | pbrook | { |
137 | 7e1543c2 | pbrook | pl031_state *s = (pl031_state *)opaque; |
138 | 7e1543c2 | pbrook | |
139 | 7e1543c2 | pbrook | |
140 | 7e1543c2 | pbrook | switch (offset) {
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141 | 7e1543c2 | pbrook | case RTC_LR:
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142 | 7e1543c2 | pbrook | s->tick_offset += value - pl031_get_count(s); |
143 | 7e1543c2 | pbrook | pl031_set_alarm(s); |
144 | 7e1543c2 | pbrook | break;
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145 | 7e1543c2 | pbrook | case RTC_MR:
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146 | 7e1543c2 | pbrook | s->mr = value; |
147 | 7e1543c2 | pbrook | pl031_set_alarm(s); |
148 | 7e1543c2 | pbrook | break;
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149 | 7e1543c2 | pbrook | case RTC_IMSC:
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150 | 7e1543c2 | pbrook | s->im = value & 1;
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151 | 7e1543c2 | pbrook | DPRINTF("Interrupt mask %d\n", s->im);
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152 | 7e1543c2 | pbrook | pl031_update(s); |
153 | 7e1543c2 | pbrook | break;
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154 | 7e1543c2 | pbrook | case RTC_ICR:
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155 | ff2712ba | Stefan Weil | /* The PL031 documentation (DDI0224B) states that the interrupt is
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156 | 7e1543c2 | pbrook | cleared when bit 0 of the written value is set. However the
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157 | 7e1543c2 | pbrook | arm926e documentation (DDI0287B) states that the interrupt is
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158 | 7e1543c2 | pbrook | cleared when any value is written. */
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159 | 7e1543c2 | pbrook | DPRINTF("Interrupt cleared");
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160 | 7e1543c2 | pbrook | s->is = 0;
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161 | 7e1543c2 | pbrook | pl031_update(s); |
162 | 7e1543c2 | pbrook | break;
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163 | 7e1543c2 | pbrook | case RTC_CR:
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164 | 7e1543c2 | pbrook | /* Written value is ignored. */
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165 | 7e1543c2 | pbrook | break;
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166 | 7e1543c2 | pbrook | |
167 | 7e1543c2 | pbrook | case RTC_DR:
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168 | 7e1543c2 | pbrook | case RTC_MIS:
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169 | 7e1543c2 | pbrook | case RTC_RIS:
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170 | 7e1543c2 | pbrook | fprintf(stderr, "qemu: pl031_write: Unexpected offset 0x%x\n",
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171 | 7e1543c2 | pbrook | (int)offset);
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172 | 7e1543c2 | pbrook | break;
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173 | 7e1543c2 | pbrook | |
174 | 7e1543c2 | pbrook | default:
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175 | 2ac71179 | Paul Brook | hw_error("pl031_write: Bad offset 0x%x\n", (int)offset); |
176 | 7e1543c2 | pbrook | break;
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177 | 7e1543c2 | pbrook | } |
178 | 7e1543c2 | pbrook | } |
179 | 7e1543c2 | pbrook | |
180 | 9edbe481 | Avi Kivity | static const MemoryRegionOps pl031_ops = { |
181 | 9edbe481 | Avi Kivity | .read = pl031_read, |
182 | 9edbe481 | Avi Kivity | .write = pl031_write, |
183 | 9edbe481 | Avi Kivity | .endianness = DEVICE_NATIVE_ENDIAN, |
184 | 7e1543c2 | pbrook | }; |
185 | 7e1543c2 | pbrook | |
186 | 81a322d4 | Gerd Hoffmann | static int pl031_init(SysBusDevice *dev) |
187 | 7e1543c2 | pbrook | { |
188 | a63bdb31 | Paul Brook | pl031_state *s = FROM_SYSBUS(pl031_state, dev); |
189 | f6503059 | balrog | struct tm tm;
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190 | 7e1543c2 | pbrook | |
191 | 9edbe481 | Avi Kivity | memory_region_init_io(&s->iomem, &pl031_ops, s, "pl031", 0x1000); |
192 | 750ecd44 | Avi Kivity | sysbus_init_mmio(dev, &s->iomem); |
193 | 7e1543c2 | pbrook | |
194 | a63bdb31 | Paul Brook | sysbus_init_irq(dev, &s->irq); |
195 | f6503059 | balrog | qemu_get_timedate(&tm, 0);
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196 | b0f26631 | Paolo Bonzini | s->tick_offset = mktimegm(&tm) - qemu_get_clock_ns(rtc_clock) / get_ticks_per_sec(); |
197 | 7e1543c2 | pbrook | |
198 | b0f26631 | Paolo Bonzini | s->timer = qemu_new_timer_ns(rtc_clock, pl031_interrupt, s); |
199 | 81a322d4 | Gerd Hoffmann | return 0; |
200 | 7e1543c2 | pbrook | } |
201 | a63bdb31 | Paul Brook | |
202 | b0f26631 | Paolo Bonzini | static void pl031_pre_save(void *opaque) |
203 | b0f26631 | Paolo Bonzini | { |
204 | b0f26631 | Paolo Bonzini | pl031_state *s = opaque; |
205 | b0f26631 | Paolo Bonzini | |
206 | b0f26631 | Paolo Bonzini | /* tick_offset is base_time - rtc_clock base time. Instead, we want to
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207 | b0f26631 | Paolo Bonzini | * store the base time relative to the vm_clock for backwards-compatibility. */
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208 | b0f26631 | Paolo Bonzini | int64_t delta = qemu_get_clock_ns(rtc_clock) - qemu_get_clock_ns(vm_clock); |
209 | b0f26631 | Paolo Bonzini | s->tick_offset_vmstate = s->tick_offset + delta / get_ticks_per_sec(); |
210 | b0f26631 | Paolo Bonzini | } |
211 | b0f26631 | Paolo Bonzini | |
212 | ac204b8f | Paolo Bonzini | static int pl031_post_load(void *opaque, int version_id) |
213 | ac204b8f | Paolo Bonzini | { |
214 | ac204b8f | Paolo Bonzini | pl031_state *s = opaque; |
215 | ac204b8f | Paolo Bonzini | |
216 | b0f26631 | Paolo Bonzini | int64_t delta = qemu_get_clock_ns(rtc_clock) - qemu_get_clock_ns(vm_clock); |
217 | b0f26631 | Paolo Bonzini | s->tick_offset = s->tick_offset_vmstate - delta / get_ticks_per_sec(); |
218 | ac204b8f | Paolo Bonzini | pl031_set_alarm(s); |
219 | ac204b8f | Paolo Bonzini | return 0; |
220 | ac204b8f | Paolo Bonzini | } |
221 | ac204b8f | Paolo Bonzini | |
222 | ac204b8f | Paolo Bonzini | static const VMStateDescription vmstate_pl031 = { |
223 | ac204b8f | Paolo Bonzini | .name = "pl031",
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224 | ac204b8f | Paolo Bonzini | .version_id = 1,
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225 | ac204b8f | Paolo Bonzini | .minimum_version_id = 1,
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226 | b0f26631 | Paolo Bonzini | .pre_save = pl031_pre_save, |
227 | ac204b8f | Paolo Bonzini | .post_load = pl031_post_load, |
228 | ac204b8f | Paolo Bonzini | .fields = (VMStateField[]) { |
229 | b0f26631 | Paolo Bonzini | VMSTATE_UINT32(tick_offset_vmstate, pl031_state), |
230 | ac204b8f | Paolo Bonzini | VMSTATE_UINT32(mr, pl031_state), |
231 | ac204b8f | Paolo Bonzini | VMSTATE_UINT32(lr, pl031_state), |
232 | ac204b8f | Paolo Bonzini | VMSTATE_UINT32(cr, pl031_state), |
233 | ac204b8f | Paolo Bonzini | VMSTATE_UINT32(im, pl031_state), |
234 | ac204b8f | Paolo Bonzini | VMSTATE_UINT32(is, pl031_state), |
235 | ac204b8f | Paolo Bonzini | VMSTATE_END_OF_LIST() |
236 | ac204b8f | Paolo Bonzini | } |
237 | ac204b8f | Paolo Bonzini | }; |
238 | ac204b8f | Paolo Bonzini | |
239 | 999e12bb | Anthony Liguori | static void pl031_class_init(ObjectClass *klass, void *data) |
240 | 999e12bb | Anthony Liguori | { |
241 | 39bffca2 | Anthony Liguori | DeviceClass *dc = DEVICE_CLASS(klass); |
242 | 999e12bb | Anthony Liguori | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
243 | 999e12bb | Anthony Liguori | |
244 | 999e12bb | Anthony Liguori | k->init = pl031_init; |
245 | 39bffca2 | Anthony Liguori | dc->no_user = 1;
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246 | 39bffca2 | Anthony Liguori | dc->vmsd = &vmstate_pl031; |
247 | 999e12bb | Anthony Liguori | } |
248 | 999e12bb | Anthony Liguori | |
249 | 39bffca2 | Anthony Liguori | static TypeInfo pl031_info = {
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250 | 39bffca2 | Anthony Liguori | .name = "pl031",
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251 | 39bffca2 | Anthony Liguori | .parent = TYPE_SYS_BUS_DEVICE, |
252 | 39bffca2 | Anthony Liguori | .instance_size = sizeof(pl031_state),
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253 | 39bffca2 | Anthony Liguori | .class_init = pl031_class_init, |
254 | 0dc5595c | Peter Maydell | }; |
255 | 0dc5595c | Peter Maydell | |
256 | 83f7d43a | Andreas Färber | static void pl031_register_types(void) |
257 | a63bdb31 | Paul Brook | { |
258 | 39bffca2 | Anthony Liguori | type_register_static(&pl031_info); |
259 | a63bdb31 | Paul Brook | } |
260 | a63bdb31 | Paul Brook | |
261 | 83f7d43a | Andreas Färber | type_init(pl031_register_types) |