root / hw / mc146818rtc.c @ 9a3a8895
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/*
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* QEMU MC146818 RTC emulation
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*
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* Copyright (c) 2003-2004 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h" |
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#include "qemu-timer.h" |
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#include "sysemu.h" |
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#include "mc146818rtc.h" |
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|
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#ifdef TARGET_I386
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#include "apic.h" |
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#endif
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//#define DEBUG_CMOS
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//#define DEBUG_COALESCED
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|
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#ifdef DEBUG_CMOS
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# define CMOS_DPRINTF(format, ...) printf(format, ## __VA_ARGS__) |
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#else
|
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# define CMOS_DPRINTF(format, ...) do { } while (0) |
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#endif
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|
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#ifdef DEBUG_COALESCED
|
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# define DPRINTF_C(format, ...) printf(format, ## __VA_ARGS__) |
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#else
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# define DPRINTF_C(format, ...) do { } while (0) |
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#endif
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|
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#define NSEC_PER_SEC 1000000000LL |
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#define SEC_PER_MIN 60 |
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#define MIN_PER_HOUR 60 |
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#define SEC_PER_HOUR 3600 |
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#define HOUR_PER_DAY 24 |
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#define SEC_PER_DAY 86400 |
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|
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#define RTC_REINJECT_ON_ACK_COUNT 20 |
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#define RTC_CLOCK_RATE 32768 |
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#define UIP_HOLD_LENGTH (8 * NSEC_PER_SEC / 32768) |
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|
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typedef struct RTCState { |
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ISADevice dev; |
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MemoryRegion io; |
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uint8_t cmos_data[128];
|
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uint8_t cmos_index; |
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int32_t base_year; |
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uint64_t base_rtc; |
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uint64_t last_update; |
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int64_t offset; |
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qemu_irq irq; |
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qemu_irq sqw_irq; |
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int it_shift;
|
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/* periodic timer */
|
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QEMUTimer *periodic_timer; |
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int64_t next_periodic_time; |
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/* update-ended timer */
|
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QEMUTimer *update_timer; |
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uint64_t next_alarm_time; |
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uint16_t irq_reinject_on_ack_count; |
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uint32_t irq_coalesced; |
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uint32_t period; |
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QEMUTimer *coalesced_timer; |
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Notifier clock_reset_notifier; |
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LostTickPolicy lost_tick_policy; |
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Notifier suspend_notifier; |
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} RTCState; |
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|
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static void rtc_set_time(RTCState *s); |
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static void rtc_update_time(RTCState *s); |
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static void rtc_set_cmos(RTCState *s, const struct tm *tm); |
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static inline int rtc_from_bcd(RTCState *s, int a); |
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static uint64_t get_next_alarm(RTCState *s);
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|
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static inline bool rtc_running(RTCState *s) |
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{
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return (!(s->cmos_data[RTC_REG_B] & REG_B_SET) &&
|
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(s->cmos_data[RTC_REG_A] & 0x70) <= 0x20); |
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} |
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|
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static uint64_t get_guest_rtc_ns(RTCState *s)
|
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{
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uint64_t guest_rtc; |
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uint64_t guest_clock = qemu_get_clock_ns(rtc_clock); |
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|
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guest_rtc = s->base_rtc * NSEC_PER_SEC |
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+ guest_clock - s->last_update + s->offset; |
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return guest_rtc;
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} |
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|
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#ifdef TARGET_I386
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static void rtc_coalesced_timer_update(RTCState *s) |
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{
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if (s->irq_coalesced == 0) { |
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qemu_del_timer(s->coalesced_timer); |
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} else {
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/* divide each RTC interval to 2 - 8 smaller intervals */
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int c = MIN(s->irq_coalesced, 7) + 1; |
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int64_t next_clock = qemu_get_clock_ns(rtc_clock) + |
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muldiv64(s->period / c, get_ticks_per_sec(), RTC_CLOCK_RATE); |
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qemu_mod_timer(s->coalesced_timer, next_clock); |
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} |
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} |
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|
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static void rtc_coalesced_timer(void *opaque) |
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{
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RTCState *s = opaque; |
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|
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if (s->irq_coalesced != 0) { |
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apic_reset_irq_delivered(); |
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s->cmos_data[RTC_REG_C] |= 0xc0;
|
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DPRINTF_C("cmos: injecting from timer\n");
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qemu_irq_raise(s->irq); |
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if (apic_get_irq_delivered()) {
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s->irq_coalesced--; |
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DPRINTF_C("cmos: coalesced irqs decreased to %d\n",
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s->irq_coalesced); |
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} |
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} |
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|
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rtc_coalesced_timer_update(s); |
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} |
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#endif
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|
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/* handle periodic timer */
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static void periodic_timer_update(RTCState *s, int64_t current_time) |
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{
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int period_code, period;
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int64_t cur_clock, next_irq_clock; |
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|
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period_code = s->cmos_data[RTC_REG_A] & 0x0f;
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if (period_code != 0 |
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&& ((s->cmos_data[RTC_REG_B] & REG_B_PIE) |
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|| ((s->cmos_data[RTC_REG_B] & REG_B_SQWE) && s->sqw_irq))) {
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if (period_code <= 2) |
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period_code += 7;
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/* period in 32 Khz cycles */
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period = 1 << (period_code - 1); |
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#ifdef TARGET_I386
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if (period != s->period) {
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s->irq_coalesced = (s->irq_coalesced * s->period) / period; |
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DPRINTF_C("cmos: coalesced irqs scaled to %d\n", s->irq_coalesced);
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} |
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s->period = period; |
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#endif
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/* compute 32 khz clock */
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cur_clock = muldiv64(current_time, RTC_CLOCK_RATE, get_ticks_per_sec()); |
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next_irq_clock = (cur_clock & ~(period - 1)) + period;
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s->next_periodic_time = |
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muldiv64(next_irq_clock, get_ticks_per_sec(), RTC_CLOCK_RATE) + 1;
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qemu_mod_timer(s->periodic_timer, s->next_periodic_time); |
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} else {
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#ifdef TARGET_I386
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s->irq_coalesced = 0;
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#endif
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qemu_del_timer(s->periodic_timer); |
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} |
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} |
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|
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static void rtc_periodic_timer(void *opaque) |
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{
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RTCState *s = opaque; |
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|
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periodic_timer_update(s, s->next_periodic_time); |
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s->cmos_data[RTC_REG_C] |= REG_C_PF; |
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if (s->cmos_data[RTC_REG_B] & REG_B_PIE) {
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s->cmos_data[RTC_REG_C] |= REG_C_IRQF; |
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#ifdef TARGET_I386
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if (s->lost_tick_policy == LOST_TICK_SLEW) {
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if (s->irq_reinject_on_ack_count >= RTC_REINJECT_ON_ACK_COUNT)
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s->irq_reinject_on_ack_count = 0;
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apic_reset_irq_delivered(); |
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qemu_irq_raise(s->irq); |
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if (!apic_get_irq_delivered()) {
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s->irq_coalesced++; |
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rtc_coalesced_timer_update(s); |
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DPRINTF_C("cmos: coalesced irqs increased to %d\n",
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s->irq_coalesced); |
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} |
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} else
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#endif
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qemu_irq_raise(s->irq); |
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} |
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if (s->cmos_data[RTC_REG_B] & REG_B_SQWE) {
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/* Not square wave at all but we don't want 2048Hz interrupts!
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Must be seen as a pulse. */
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qemu_irq_raise(s->sqw_irq); |
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} |
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} |
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|
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/* handle update-ended timer */
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static void check_update_timer(RTCState *s) |
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{
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uint64_t next_update_time; |
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uint64_t guest_nsec; |
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int next_alarm_sec;
|
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|
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/* From the data sheet: "Holding the dividers in reset prevents
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* interrupts from operating, while setting the SET bit allows"
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* them to occur. However, it will prevent an alarm interrupt
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* from occurring, because the time of day is not updated.
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*/
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if ((s->cmos_data[RTC_REG_A] & 0x60) == 0x60) { |
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qemu_del_timer(s->update_timer); |
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return;
|
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} |
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if ((s->cmos_data[RTC_REG_C] & REG_C_UF) &&
|
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(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
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qemu_del_timer(s->update_timer); |
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return;
|
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} |
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if ((s->cmos_data[RTC_REG_C] & REG_C_UF) &&
|
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(s->cmos_data[RTC_REG_C] & REG_C_AF)) {
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qemu_del_timer(s->update_timer); |
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return;
|
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} |
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|
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guest_nsec = get_guest_rtc_ns(s) % NSEC_PER_SEC; |
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/* if UF is clear, reprogram to next second */
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next_update_time = qemu_get_clock_ns(rtc_clock) |
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+ NSEC_PER_SEC - guest_nsec; |
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|
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/* Compute time of next alarm. One second is already accounted
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* for in next_update_time.
|
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*/
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next_alarm_sec = get_next_alarm(s); |
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s->next_alarm_time = next_update_time + (next_alarm_sec - 1) * NSEC_PER_SEC;
|
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|
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if (s->cmos_data[RTC_REG_C] & REG_C_UF) {
|
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/* UF is set, but AF is clear. Program the timer to target
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* the alarm time. */
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next_update_time = s->next_alarm_time; |
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} |
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if (next_update_time != qemu_timer_expire_time_ns(s->update_timer)) {
|
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qemu_mod_timer(s->update_timer, next_update_time); |
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} |
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} |
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|
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static inline uint8_t convert_hour(RTCState *s, uint8_t hour) |
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{
|
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if (!(s->cmos_data[RTC_REG_B] & REG_B_24H)) {
|
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hour %= 12;
|
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if (s->cmos_data[RTC_HOURS] & 0x80) { |
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hour += 12;
|
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} |
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} |
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return hour;
|
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} |
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|
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static uint64_t get_next_alarm(RTCState *s)
|
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{
|
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int32_t alarm_sec, alarm_min, alarm_hour, cur_hour, cur_min, cur_sec; |
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int32_t hour, min, sec; |
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|
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rtc_update_time(s); |
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|
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alarm_sec = rtc_from_bcd(s, s->cmos_data[RTC_SECONDS_ALARM]); |
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alarm_min = rtc_from_bcd(s, s->cmos_data[RTC_MINUTES_ALARM]); |
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alarm_hour = rtc_from_bcd(s, s->cmos_data[RTC_HOURS_ALARM]); |
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alarm_hour = alarm_hour == -1 ? -1 : convert_hour(s, alarm_hour); |
| 278 |
|
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cur_sec = rtc_from_bcd(s, s->cmos_data[RTC_SECONDS]); |
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cur_min = rtc_from_bcd(s, s->cmos_data[RTC_MINUTES]); |
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cur_hour = rtc_from_bcd(s, s->cmos_data[RTC_HOURS]); |
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cur_hour = convert_hour(s, cur_hour); |
| 283 |
|
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if (alarm_hour == -1) { |
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alarm_hour = cur_hour; |
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if (alarm_min == -1) { |
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alarm_min = cur_min; |
| 288 |
if (alarm_sec == -1) { |
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alarm_sec = cur_sec + 1;
|
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} else if (cur_sec > alarm_sec) { |
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alarm_min++; |
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} |
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} else if (cur_min == alarm_min) { |
| 294 |
if (alarm_sec == -1) { |
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alarm_sec = cur_sec + 1;
|
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} else {
|
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if (cur_sec > alarm_sec) {
|
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alarm_hour++; |
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} |
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} |
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if (alarm_sec == SEC_PER_MIN) {
|
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/* wrap to next hour, minutes is not in don't care mode */
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alarm_sec = 0;
|
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alarm_hour++; |
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} |
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} else if (cur_min > alarm_min) { |
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alarm_hour++; |
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} |
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} else if (cur_hour == alarm_hour) { |
| 310 |
if (alarm_min == -1) { |
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alarm_min = cur_min; |
| 312 |
if (alarm_sec == -1) { |
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alarm_sec = cur_sec + 1;
|
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} else if (cur_sec > alarm_sec) { |
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alarm_min++; |
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} |
| 317 |
|
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if (alarm_sec == SEC_PER_MIN) {
|
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alarm_sec = 0;
|
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alarm_min++; |
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} |
| 322 |
/* wrap to next day, hour is not in don't care mode */
|
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alarm_min %= MIN_PER_HOUR; |
| 324 |
} else if (cur_min == alarm_min) { |
| 325 |
if (alarm_sec == -1) { |
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alarm_sec = cur_sec + 1;
|
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} |
| 328 |
/* wrap to next day, hours+minutes not in don't care mode */
|
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alarm_sec %= SEC_PER_MIN; |
| 330 |
} |
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} |
| 332 |
|
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/* values that are still don't care fire at the next min/sec */
|
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if (alarm_min == -1) { |
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alarm_min = 0;
|
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} |
| 337 |
if (alarm_sec == -1) { |
| 338 |
alarm_sec = 0;
|
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} |
| 340 |
|
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/* keep values in range */
|
| 342 |
if (alarm_sec == SEC_PER_MIN) {
|
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alarm_sec = 0;
|
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alarm_min++; |
| 345 |
} |
| 346 |
if (alarm_min == MIN_PER_HOUR) {
|
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alarm_min = 0;
|
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alarm_hour++; |
| 349 |
} |
| 350 |
alarm_hour %= HOUR_PER_DAY; |
| 351 |
|
| 352 |
hour = alarm_hour - cur_hour; |
| 353 |
min = hour * MIN_PER_HOUR + alarm_min - cur_min; |
| 354 |
sec = min * SEC_PER_MIN + alarm_sec - cur_sec; |
| 355 |
return sec <= 0 ? sec + SEC_PER_DAY : sec; |
| 356 |
} |
| 357 |
|
| 358 |
static void rtc_update_timer(void *opaque) |
| 359 |
{
|
| 360 |
RTCState *s = opaque; |
| 361 |
int32_t irqs = REG_C_UF; |
| 362 |
int32_t new_irqs; |
| 363 |
|
| 364 |
assert((s->cmos_data[RTC_REG_A] & 0x60) != 0x60); |
| 365 |
|
| 366 |
/* UIP might have been latched, update time and clear it. */
|
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rtc_update_time(s); |
| 368 |
s->cmos_data[RTC_REG_A] &= ~REG_A_UIP; |
| 369 |
|
| 370 |
if (qemu_get_clock_ns(rtc_clock) >= s->next_alarm_time) {
|
| 371 |
irqs |= REG_C_AF; |
| 372 |
if (s->cmos_data[RTC_REG_B] & REG_B_AIE) {
|
| 373 |
qemu_system_wakeup_request(QEMU_WAKEUP_REASON_RTC); |
| 374 |
} |
| 375 |
} |
| 376 |
|
| 377 |
new_irqs = irqs & ~s->cmos_data[RTC_REG_C]; |
| 378 |
s->cmos_data[RTC_REG_C] |= irqs; |
| 379 |
if ((new_irqs & s->cmos_data[RTC_REG_B]) != 0) { |
| 380 |
s->cmos_data[RTC_REG_C] |= REG_C_IRQF; |
| 381 |
qemu_irq_raise(s->irq); |
| 382 |
} |
| 383 |
check_update_timer(s); |
| 384 |
} |
| 385 |
|
| 386 |
static void cmos_ioport_write(void *opaque, uint32_t addr, uint32_t data) |
| 387 |
{
|
| 388 |
RTCState *s = opaque; |
| 389 |
|
| 390 |
if ((addr & 1) == 0) { |
| 391 |
s->cmos_index = data & 0x7f;
|
| 392 |
} else {
|
| 393 |
CMOS_DPRINTF("cmos: write index=0x%02x val=0x%02x\n",
|
| 394 |
s->cmos_index, data); |
| 395 |
switch(s->cmos_index) {
|
| 396 |
case RTC_SECONDS_ALARM:
|
| 397 |
case RTC_MINUTES_ALARM:
|
| 398 |
case RTC_HOURS_ALARM:
|
| 399 |
s->cmos_data[s->cmos_index] = data; |
| 400 |
check_update_timer(s); |
| 401 |
break;
|
| 402 |
case RTC_SECONDS:
|
| 403 |
case RTC_MINUTES:
|
| 404 |
case RTC_HOURS:
|
| 405 |
case RTC_DAY_OF_WEEK:
|
| 406 |
case RTC_DAY_OF_MONTH:
|
| 407 |
case RTC_MONTH:
|
| 408 |
case RTC_YEAR:
|
| 409 |
s->cmos_data[s->cmos_index] = data; |
| 410 |
/* if in set mode, do not update the time */
|
| 411 |
if (rtc_running(s)) {
|
| 412 |
rtc_set_time(s); |
| 413 |
check_update_timer(s); |
| 414 |
} |
| 415 |
break;
|
| 416 |
case RTC_REG_A:
|
| 417 |
if ((data & 0x60) == 0x60) { |
| 418 |
if (rtc_running(s)) {
|
| 419 |
rtc_update_time(s); |
| 420 |
} |
| 421 |
/* What happens to UIP when divider reset is enabled is
|
| 422 |
* unclear from the datasheet. Shouldn't matter much
|
| 423 |
* though.
|
| 424 |
*/
|
| 425 |
s->cmos_data[RTC_REG_A] &= ~REG_A_UIP; |
| 426 |
} else if (((s->cmos_data[RTC_REG_A] & 0x60) == 0x60) && |
| 427 |
(data & 0x70) <= 0x20) { |
| 428 |
/* when the divider reset is removed, the first update cycle
|
| 429 |
* begins one-half second later*/
|
| 430 |
if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
|
| 431 |
s->offset = 500000000;
|
| 432 |
rtc_set_time(s); |
| 433 |
} |
| 434 |
s->cmos_data[RTC_REG_A] &= ~REG_A_UIP; |
| 435 |
} |
| 436 |
/* UIP bit is read only */
|
| 437 |
s->cmos_data[RTC_REG_A] = (data & ~REG_A_UIP) | |
| 438 |
(s->cmos_data[RTC_REG_A] & REG_A_UIP); |
| 439 |
periodic_timer_update(s, qemu_get_clock_ns(rtc_clock)); |
| 440 |
check_update_timer(s); |
| 441 |
break;
|
| 442 |
case RTC_REG_B:
|
| 443 |
if (data & REG_B_SET) {
|
| 444 |
/* update cmos to when the rtc was stopping */
|
| 445 |
if (rtc_running(s)) {
|
| 446 |
rtc_update_time(s); |
| 447 |
} |
| 448 |
/* set mode: reset UIP mode */
|
| 449 |
s->cmos_data[RTC_REG_A] &= ~REG_A_UIP; |
| 450 |
data &= ~REG_B_UIE; |
| 451 |
} else {
|
| 452 |
/* if disabling set mode, update the time */
|
| 453 |
if ((s->cmos_data[RTC_REG_B] & REG_B_SET) &&
|
| 454 |
(s->cmos_data[RTC_REG_A] & 0x70) <= 0x20) { |
| 455 |
s->offset = get_guest_rtc_ns(s) % NSEC_PER_SEC; |
| 456 |
rtc_set_time(s); |
| 457 |
} |
| 458 |
} |
| 459 |
/* if an interrupt flag is already set when the interrupt
|
| 460 |
* becomes enabled, raise an interrupt immediately. */
|
| 461 |
if (data & s->cmos_data[RTC_REG_C] & REG_C_MASK) {
|
| 462 |
s->cmos_data[RTC_REG_C] |= REG_C_IRQF; |
| 463 |
qemu_irq_raise(s->irq); |
| 464 |
} else {
|
| 465 |
s->cmos_data[RTC_REG_C] &= ~REG_C_IRQF; |
| 466 |
qemu_irq_lower(s->irq); |
| 467 |
} |
| 468 |
s->cmos_data[RTC_REG_B] = data; |
| 469 |
periodic_timer_update(s, qemu_get_clock_ns(rtc_clock)); |
| 470 |
check_update_timer(s); |
| 471 |
break;
|
| 472 |
case RTC_REG_C:
|
| 473 |
case RTC_REG_D:
|
| 474 |
/* cannot write to them */
|
| 475 |
break;
|
| 476 |
default:
|
| 477 |
s->cmos_data[s->cmos_index] = data; |
| 478 |
break;
|
| 479 |
} |
| 480 |
} |
| 481 |
} |
| 482 |
|
| 483 |
static inline int rtc_to_bcd(RTCState *s, int a) |
| 484 |
{
|
| 485 |
if (s->cmos_data[RTC_REG_B] & REG_B_DM) {
|
| 486 |
return a;
|
| 487 |
} else {
|
| 488 |
return ((a / 10) << 4) | (a % 10); |
| 489 |
} |
| 490 |
} |
| 491 |
|
| 492 |
static inline int rtc_from_bcd(RTCState *s, int a) |
| 493 |
{
|
| 494 |
if ((a & 0xc0) == 0xc0) { |
| 495 |
return -1; |
| 496 |
} |
| 497 |
if (s->cmos_data[RTC_REG_B] & REG_B_DM) {
|
| 498 |
return a;
|
| 499 |
} else {
|
| 500 |
return ((a >> 4) * 10) + (a & 0x0f); |
| 501 |
} |
| 502 |
} |
| 503 |
|
| 504 |
static void rtc_get_time(RTCState *s, struct tm *tm) |
| 505 |
{
|
| 506 |
tm->tm_sec = rtc_from_bcd(s, s->cmos_data[RTC_SECONDS]); |
| 507 |
tm->tm_min = rtc_from_bcd(s, s->cmos_data[RTC_MINUTES]); |
| 508 |
tm->tm_hour = rtc_from_bcd(s, s->cmos_data[RTC_HOURS] & 0x7f);
|
| 509 |
if (!(s->cmos_data[RTC_REG_B] & REG_B_24H)) {
|
| 510 |
tm->tm_hour %= 12;
|
| 511 |
if (s->cmos_data[RTC_HOURS] & 0x80) { |
| 512 |
tm->tm_hour += 12;
|
| 513 |
} |
| 514 |
} |
| 515 |
tm->tm_wday = rtc_from_bcd(s, s->cmos_data[RTC_DAY_OF_WEEK]) - 1;
|
| 516 |
tm->tm_mday = rtc_from_bcd(s, s->cmos_data[RTC_DAY_OF_MONTH]); |
| 517 |
tm->tm_mon = rtc_from_bcd(s, s->cmos_data[RTC_MONTH]) - 1;
|
| 518 |
tm->tm_year = rtc_from_bcd(s, s->cmos_data[RTC_YEAR]) + s->base_year - 1900;
|
| 519 |
} |
| 520 |
|
| 521 |
static void rtc_set_time(RTCState *s) |
| 522 |
{
|
| 523 |
struct tm tm;
|
| 524 |
|
| 525 |
rtc_get_time(s, &tm); |
| 526 |
s->base_rtc = mktimegm(&tm); |
| 527 |
s->last_update = qemu_get_clock_ns(rtc_clock); |
| 528 |
|
| 529 |
rtc_change_mon_event(&tm); |
| 530 |
} |
| 531 |
|
| 532 |
static void rtc_set_cmos(RTCState *s, const struct tm *tm) |
| 533 |
{
|
| 534 |
int year;
|
| 535 |
|
| 536 |
s->cmos_data[RTC_SECONDS] = rtc_to_bcd(s, tm->tm_sec); |
| 537 |
s->cmos_data[RTC_MINUTES] = rtc_to_bcd(s, tm->tm_min); |
| 538 |
if (s->cmos_data[RTC_REG_B] & REG_B_24H) {
|
| 539 |
/* 24 hour format */
|
| 540 |
s->cmos_data[RTC_HOURS] = rtc_to_bcd(s, tm->tm_hour); |
| 541 |
} else {
|
| 542 |
/* 12 hour format */
|
| 543 |
int h = (tm->tm_hour % 12) ? tm->tm_hour % 12 : 12; |
| 544 |
s->cmos_data[RTC_HOURS] = rtc_to_bcd(s, h); |
| 545 |
if (tm->tm_hour >= 12) |
| 546 |
s->cmos_data[RTC_HOURS] |= 0x80;
|
| 547 |
} |
| 548 |
s->cmos_data[RTC_DAY_OF_WEEK] = rtc_to_bcd(s, tm->tm_wday + 1);
|
| 549 |
s->cmos_data[RTC_DAY_OF_MONTH] = rtc_to_bcd(s, tm->tm_mday); |
| 550 |
s->cmos_data[RTC_MONTH] = rtc_to_bcd(s, tm->tm_mon + 1);
|
| 551 |
year = (tm->tm_year - s->base_year) % 100;
|
| 552 |
if (year < 0) |
| 553 |
year += 100;
|
| 554 |
s->cmos_data[RTC_YEAR] = rtc_to_bcd(s, year); |
| 555 |
} |
| 556 |
|
| 557 |
static void rtc_update_time(RTCState *s) |
| 558 |
{
|
| 559 |
struct tm ret;
|
| 560 |
time_t guest_sec; |
| 561 |
int64_t guest_nsec; |
| 562 |
|
| 563 |
guest_nsec = get_guest_rtc_ns(s); |
| 564 |
guest_sec = guest_nsec / NSEC_PER_SEC; |
| 565 |
gmtime_r(&guest_sec, &ret); |
| 566 |
rtc_set_cmos(s, &ret); |
| 567 |
} |
| 568 |
|
| 569 |
static int update_in_progress(RTCState *s) |
| 570 |
{
|
| 571 |
int64_t guest_nsec; |
| 572 |
|
| 573 |
if (!rtc_running(s)) {
|
| 574 |
return 0; |
| 575 |
} |
| 576 |
if (qemu_timer_pending(s->update_timer)) {
|
| 577 |
int64_t next_update_time = qemu_timer_expire_time_ns(s->update_timer); |
| 578 |
/* Latch UIP until the timer expires. */
|
| 579 |
if (qemu_get_clock_ns(rtc_clock) >= (next_update_time - UIP_HOLD_LENGTH)) {
|
| 580 |
s->cmos_data[RTC_REG_A] |= REG_A_UIP; |
| 581 |
return 1; |
| 582 |
} |
| 583 |
} |
| 584 |
|
| 585 |
guest_nsec = get_guest_rtc_ns(s); |
| 586 |
/* UIP bit will be set at last 244us of every second. */
|
| 587 |
if ((guest_nsec % NSEC_PER_SEC) >= (NSEC_PER_SEC - UIP_HOLD_LENGTH)) {
|
| 588 |
return 1; |
| 589 |
} |
| 590 |
return 0; |
| 591 |
} |
| 592 |
|
| 593 |
static uint32_t cmos_ioport_read(void *opaque, uint32_t addr) |
| 594 |
{
|
| 595 |
RTCState *s = opaque; |
| 596 |
int ret;
|
| 597 |
if ((addr & 1) == 0) { |
| 598 |
return 0xff; |
| 599 |
} else {
|
| 600 |
switch(s->cmos_index) {
|
| 601 |
case RTC_SECONDS:
|
| 602 |
case RTC_MINUTES:
|
| 603 |
case RTC_HOURS:
|
| 604 |
case RTC_DAY_OF_WEEK:
|
| 605 |
case RTC_DAY_OF_MONTH:
|
| 606 |
case RTC_MONTH:
|
| 607 |
case RTC_YEAR:
|
| 608 |
/* if not in set mode, calibrate cmos before
|
| 609 |
* reading*/
|
| 610 |
if (rtc_running(s)) {
|
| 611 |
rtc_update_time(s); |
| 612 |
} |
| 613 |
ret = s->cmos_data[s->cmos_index]; |
| 614 |
break;
|
| 615 |
case RTC_REG_A:
|
| 616 |
if (update_in_progress(s)) {
|
| 617 |
s->cmos_data[s->cmos_index] |= REG_A_UIP; |
| 618 |
} else {
|
| 619 |
s->cmos_data[s->cmos_index] &= ~REG_A_UIP; |
| 620 |
} |
| 621 |
ret = s->cmos_data[s->cmos_index]; |
| 622 |
break;
|
| 623 |
case RTC_REG_C:
|
| 624 |
ret = s->cmos_data[s->cmos_index]; |
| 625 |
qemu_irq_lower(s->irq); |
| 626 |
s->cmos_data[RTC_REG_C] = 0x00;
|
| 627 |
if (ret & (REG_C_UF | REG_C_AF)) {
|
| 628 |
check_update_timer(s); |
| 629 |
} |
| 630 |
#ifdef TARGET_I386
|
| 631 |
if(s->irq_coalesced &&
|
| 632 |
(s->cmos_data[RTC_REG_B] & REG_B_PIE) && |
| 633 |
s->irq_reinject_on_ack_count < RTC_REINJECT_ON_ACK_COUNT) {
|
| 634 |
s->irq_reinject_on_ack_count++; |
| 635 |
s->cmos_data[RTC_REG_C] |= REG_C_IRQF | REG_C_PF; |
| 636 |
apic_reset_irq_delivered(); |
| 637 |
DPRINTF_C("cmos: injecting on ack\n");
|
| 638 |
qemu_irq_raise(s->irq); |
| 639 |
if (apic_get_irq_delivered()) {
|
| 640 |
s->irq_coalesced--; |
| 641 |
DPRINTF_C("cmos: coalesced irqs decreased to %d\n",
|
| 642 |
s->irq_coalesced); |
| 643 |
} |
| 644 |
} |
| 645 |
#endif
|
| 646 |
break;
|
| 647 |
default:
|
| 648 |
ret = s->cmos_data[s->cmos_index]; |
| 649 |
break;
|
| 650 |
} |
| 651 |
CMOS_DPRINTF("cmos: read index=0x%02x val=0x%02x\n",
|
| 652 |
s->cmos_index, ret); |
| 653 |
return ret;
|
| 654 |
} |
| 655 |
} |
| 656 |
|
| 657 |
void rtc_set_memory(ISADevice *dev, int addr, int val) |
| 658 |
{
|
| 659 |
RTCState *s = DO_UPCAST(RTCState, dev, dev); |
| 660 |
if (addr >= 0 && addr <= 127) |
| 661 |
s->cmos_data[addr] = val; |
| 662 |
} |
| 663 |
|
| 664 |
/* PC cmos mappings */
|
| 665 |
#define REG_IBM_CENTURY_BYTE 0x32 |
| 666 |
#define REG_IBM_PS2_CENTURY_BYTE 0x37 |
| 667 |
|
| 668 |
static void rtc_set_date_from_host(ISADevice *dev) |
| 669 |
{
|
| 670 |
RTCState *s = DO_UPCAST(RTCState, dev, dev); |
| 671 |
struct tm tm;
|
| 672 |
int val;
|
| 673 |
|
| 674 |
qemu_get_timedate(&tm, 0);
|
| 675 |
|
| 676 |
s->base_rtc = mktimegm(&tm); |
| 677 |
s->last_update = qemu_get_clock_ns(rtc_clock); |
| 678 |
s->offset = 0;
|
| 679 |
|
| 680 |
/* set the CMOS date */
|
| 681 |
rtc_set_cmos(s, &tm); |
| 682 |
|
| 683 |
val = rtc_to_bcd(s, (tm.tm_year / 100) + 19); |
| 684 |
rtc_set_memory(dev, REG_IBM_CENTURY_BYTE, val); |
| 685 |
rtc_set_memory(dev, REG_IBM_PS2_CENTURY_BYTE, val); |
| 686 |
} |
| 687 |
|
| 688 |
static int rtc_post_load(void *opaque, int version_id) |
| 689 |
{
|
| 690 |
RTCState *s = opaque; |
| 691 |
|
| 692 |
if (version_id <= 2) { |
| 693 |
rtc_set_time(s); |
| 694 |
s->offset = 0;
|
| 695 |
check_update_timer(s); |
| 696 |
} |
| 697 |
|
| 698 |
#ifdef TARGET_I386
|
| 699 |
if (version_id >= 2) { |
| 700 |
if (s->lost_tick_policy == LOST_TICK_SLEW) {
|
| 701 |
rtc_coalesced_timer_update(s); |
| 702 |
} |
| 703 |
} |
| 704 |
#endif
|
| 705 |
return 0; |
| 706 |
} |
| 707 |
|
| 708 |
static const VMStateDescription vmstate_rtc = { |
| 709 |
.name = "mc146818rtc",
|
| 710 |
.version_id = 3,
|
| 711 |
.minimum_version_id = 1,
|
| 712 |
.minimum_version_id_old = 1,
|
| 713 |
.post_load = rtc_post_load, |
| 714 |
.fields = (VMStateField []) {
|
| 715 |
VMSTATE_BUFFER(cmos_data, RTCState), |
| 716 |
VMSTATE_UINT8(cmos_index, RTCState), |
| 717 |
VMSTATE_UNUSED(7*4), |
| 718 |
VMSTATE_TIMER(periodic_timer, RTCState), |
| 719 |
VMSTATE_INT64(next_periodic_time, RTCState), |
| 720 |
VMSTATE_UNUSED(3*8), |
| 721 |
VMSTATE_UINT32_V(irq_coalesced, RTCState, 2),
|
| 722 |
VMSTATE_UINT32_V(period, RTCState, 2),
|
| 723 |
VMSTATE_UINT64_V(base_rtc, RTCState, 3),
|
| 724 |
VMSTATE_UINT64_V(last_update, RTCState, 3),
|
| 725 |
VMSTATE_INT64_V(offset, RTCState, 3),
|
| 726 |
VMSTATE_TIMER_V(update_timer, RTCState, 3),
|
| 727 |
VMSTATE_UINT64_V(next_alarm_time, RTCState, 3),
|
| 728 |
VMSTATE_END_OF_LIST() |
| 729 |
} |
| 730 |
}; |
| 731 |
|
| 732 |
static void rtc_notify_clock_reset(Notifier *notifier, void *data) |
| 733 |
{
|
| 734 |
RTCState *s = container_of(notifier, RTCState, clock_reset_notifier); |
| 735 |
int64_t now = *(int64_t *)data; |
| 736 |
|
| 737 |
rtc_set_date_from_host(&s->dev); |
| 738 |
periodic_timer_update(s, now); |
| 739 |
check_update_timer(s); |
| 740 |
#ifdef TARGET_I386
|
| 741 |
if (s->lost_tick_policy == LOST_TICK_SLEW) {
|
| 742 |
rtc_coalesced_timer_update(s); |
| 743 |
} |
| 744 |
#endif
|
| 745 |
} |
| 746 |
|
| 747 |
/* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE)
|
| 748 |
BIOS will read it and start S3 resume at POST Entry */
|
| 749 |
static void rtc_notify_suspend(Notifier *notifier, void *data) |
| 750 |
{
|
| 751 |
RTCState *s = container_of(notifier, RTCState, suspend_notifier); |
| 752 |
rtc_set_memory(&s->dev, 0xF, 0xFE); |
| 753 |
} |
| 754 |
|
| 755 |
static void rtc_reset(void *opaque) |
| 756 |
{
|
| 757 |
RTCState *s = opaque; |
| 758 |
|
| 759 |
s->cmos_data[RTC_REG_B] &= ~(REG_B_PIE | REG_B_AIE | REG_B_SQWE); |
| 760 |
s->cmos_data[RTC_REG_C] &= ~(REG_C_UF | REG_C_IRQF | REG_C_PF | REG_C_AF); |
| 761 |
check_update_timer(s); |
| 762 |
|
| 763 |
qemu_irq_lower(s->irq); |
| 764 |
|
| 765 |
#ifdef TARGET_I386
|
| 766 |
if (s->lost_tick_policy == LOST_TICK_SLEW) {
|
| 767 |
s->irq_coalesced = 0;
|
| 768 |
} |
| 769 |
#endif
|
| 770 |
} |
| 771 |
|
| 772 |
static const MemoryRegionPortio cmos_portio[] = { |
| 773 |
{0, 2, 1, .read = cmos_ioport_read, .write = cmos_ioport_write },
|
| 774 |
PORTIO_END_OF_LIST(), |
| 775 |
}; |
| 776 |
|
| 777 |
static const MemoryRegionOps cmos_ops = { |
| 778 |
.old_portio = cmos_portio |
| 779 |
}; |
| 780 |
|
| 781 |
static void rtc_get_date(Object *obj, Visitor *v, void *opaque, |
| 782 |
const char *name, Error **errp) |
| 783 |
{
|
| 784 |
ISADevice *isa = ISA_DEVICE(obj); |
| 785 |
RTCState *s = DO_UPCAST(RTCState, dev, isa); |
| 786 |
struct tm current_tm;
|
| 787 |
|
| 788 |
rtc_update_time(s); |
| 789 |
rtc_get_time(s, ¤t_tm); |
| 790 |
visit_start_struct(v, NULL, "struct tm", name, 0, errp); |
| 791 |
visit_type_int32(v, ¤t_tm.tm_year, "tm_year", errp);
|
| 792 |
visit_type_int32(v, ¤t_tm.tm_mon, "tm_mon", errp);
|
| 793 |
visit_type_int32(v, ¤t_tm.tm_mday, "tm_mday", errp);
|
| 794 |
visit_type_int32(v, ¤t_tm.tm_hour, "tm_hour", errp);
|
| 795 |
visit_type_int32(v, ¤t_tm.tm_min, "tm_min", errp);
|
| 796 |
visit_type_int32(v, ¤t_tm.tm_sec, "tm_sec", errp);
|
| 797 |
visit_end_struct(v, errp); |
| 798 |
} |
| 799 |
|
| 800 |
static int rtc_initfn(ISADevice *dev) |
| 801 |
{
|
| 802 |
RTCState *s = DO_UPCAST(RTCState, dev, dev); |
| 803 |
int base = 0x70; |
| 804 |
|
| 805 |
s->cmos_data[RTC_REG_A] = 0x26;
|
| 806 |
s->cmos_data[RTC_REG_B] = 0x02;
|
| 807 |
s->cmos_data[RTC_REG_C] = 0x00;
|
| 808 |
s->cmos_data[RTC_REG_D] = 0x80;
|
| 809 |
|
| 810 |
rtc_set_date_from_host(dev); |
| 811 |
|
| 812 |
#ifdef TARGET_I386
|
| 813 |
switch (s->lost_tick_policy) {
|
| 814 |
case LOST_TICK_SLEW:
|
| 815 |
s->coalesced_timer = |
| 816 |
qemu_new_timer_ns(rtc_clock, rtc_coalesced_timer, s); |
| 817 |
break;
|
| 818 |
case LOST_TICK_DISCARD:
|
| 819 |
break;
|
| 820 |
default:
|
| 821 |
return -EINVAL;
|
| 822 |
} |
| 823 |
#endif
|
| 824 |
|
| 825 |
s->periodic_timer = qemu_new_timer_ns(rtc_clock, rtc_periodic_timer, s); |
| 826 |
s->update_timer = qemu_new_timer_ns(rtc_clock, rtc_update_timer, s); |
| 827 |
check_update_timer(s); |
| 828 |
|
| 829 |
s->clock_reset_notifier.notify = rtc_notify_clock_reset; |
| 830 |
qemu_register_clock_reset_notifier(rtc_clock, &s->clock_reset_notifier); |
| 831 |
|
| 832 |
s->suspend_notifier.notify = rtc_notify_suspend; |
| 833 |
qemu_register_suspend_notifier(&s->suspend_notifier); |
| 834 |
|
| 835 |
memory_region_init_io(&s->io, &cmos_ops, s, "rtc", 2); |
| 836 |
isa_register_ioport(dev, &s->io, base); |
| 837 |
|
| 838 |
qdev_set_legacy_instance_id(&dev->qdev, base, 3);
|
| 839 |
qemu_register_reset(rtc_reset, s); |
| 840 |
|
| 841 |
object_property_add(OBJECT(s), "date", "struct tm", |
| 842 |
rtc_get_date, NULL, NULL, s, NULL); |
| 843 |
|
| 844 |
return 0; |
| 845 |
} |
| 846 |
|
| 847 |
ISADevice *rtc_init(ISABus *bus, int base_year, qemu_irq intercept_irq)
|
| 848 |
{
|
| 849 |
ISADevice *dev; |
| 850 |
RTCState *s; |
| 851 |
|
| 852 |
dev = isa_create(bus, "mc146818rtc");
|
| 853 |
s = DO_UPCAST(RTCState, dev, dev); |
| 854 |
qdev_prop_set_int32(&dev->qdev, "base_year", base_year);
|
| 855 |
qdev_init_nofail(&dev->qdev); |
| 856 |
if (intercept_irq) {
|
| 857 |
s->irq = intercept_irq; |
| 858 |
} else {
|
| 859 |
isa_init_irq(dev, &s->irq, RTC_ISA_IRQ); |
| 860 |
} |
| 861 |
return dev;
|
| 862 |
} |
| 863 |
|
| 864 |
static Property mc146818rtc_properties[] = {
|
| 865 |
DEFINE_PROP_INT32("base_year", RTCState, base_year, 1980), |
| 866 |
DEFINE_PROP_LOSTTICKPOLICY("lost_tick_policy", RTCState,
|
| 867 |
lost_tick_policy, LOST_TICK_DISCARD), |
| 868 |
DEFINE_PROP_END_OF_LIST(), |
| 869 |
}; |
| 870 |
|
| 871 |
static void rtc_class_initfn(ObjectClass *klass, void *data) |
| 872 |
{
|
| 873 |
DeviceClass *dc = DEVICE_CLASS(klass); |
| 874 |
ISADeviceClass *ic = ISA_DEVICE_CLASS(klass); |
| 875 |
ic->init = rtc_initfn; |
| 876 |
dc->no_user = 1;
|
| 877 |
dc->vmsd = &vmstate_rtc; |
| 878 |
dc->props = mc146818rtc_properties; |
| 879 |
} |
| 880 |
|
| 881 |
static TypeInfo mc146818rtc_info = {
|
| 882 |
.name = "mc146818rtc",
|
| 883 |
.parent = TYPE_ISA_DEVICE, |
| 884 |
.instance_size = sizeof(RTCState),
|
| 885 |
.class_init = rtc_class_initfn, |
| 886 |
}; |
| 887 |
|
| 888 |
static void mc146818rtc_register_types(void) |
| 889 |
{
|
| 890 |
type_register_static(&mc146818rtc_info); |
| 891 |
} |
| 892 |
|
| 893 |
type_init(mc146818rtc_register_types) |