root / hw / mainstone.h @ 9a3e12c8
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1 | 7233b355 | ths | /*
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2 | 7233b355 | ths | * PXA270-based Intel Mainstone platforms.
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3 | 7233b355 | ths | *
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4 | 7233b355 | ths | * Copyright (c) 2007 by Armin Kuster <akuster@kama-aina.net> or
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5 | 7233b355 | ths | * <akuster@mvista.com>
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6 | 7233b355 | ths | *
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7 | 7233b355 | ths | * This code is licensed under the GNU GPL v2.
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8 | 7233b355 | ths | */
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9 | 7233b355 | ths | |
10 | 7233b355 | ths | #ifndef __MAINSTONE_H__
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11 | 7233b355 | ths | #define __MAINSTONE_H__
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12 | 7233b355 | ths | |
13 | 7233b355 | ths | /* Device addresses */
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14 | 7233b355 | ths | #define MST_FPGA_PHYS 0x08000000 |
15 | 7233b355 | ths | #define MST_ETH_PHYS 0x10000300 |
16 | 7233b355 | ths | #define MST_FLASH_0 0x00000000 |
17 | 7233b355 | ths | #define MST_FLASH_1 0x04000000 |
18 | 7233b355 | ths | |
19 | 7233b355 | ths | /* IRQ definitions */
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20 | f1de1334 | ths | #define MMC_IRQ 0 |
21 | f1de1334 | ths | #define USIM_IRQ 1 |
22 | f1de1334 | ths | #define USBC_IRQ 2 |
23 | f1de1334 | ths | #define ETHERNET_IRQ 3 |
24 | f1de1334 | ths | #define AC97_IRQ 4 |
25 | f1de1334 | ths | #define PEN_IRQ 5 |
26 | f1de1334 | ths | #define MSINS_IRQ 6 |
27 | f1de1334 | ths | #define EXBRD_IRQ 7 |
28 | f1de1334 | ths | #define S0_CD_IRQ 9 |
29 | f1de1334 | ths | #define S0_STSCHG_IRQ 10 |
30 | f1de1334 | ths | #define S0_IRQ 11 |
31 | f1de1334 | ths | #define S1_CD_IRQ 13 |
32 | f1de1334 | ths | #define S1_STSCHG_IRQ 14 |
33 | f1de1334 | ths | #define S1_IRQ 15 |
34 | 7233b355 | ths | |
35 | 7233b355 | ths | extern qemu_irq
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36 | bc24a225 | Paul Brook | *mst_irq_init(PXA2xxState *cpu, uint32_t base, int irq);
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37 | 7233b355 | ths | |
38 | 7233b355 | ths | #endif /* __MAINSTONE_H__ */ |