root / hw / sbi.c @ 9a3e12c8
History | View | Annotate | Download (3.9 kB)
1 | 7d85892b | blueswir1 | /*
|
---|---|---|---|
2 | 7d85892b | blueswir1 | * QEMU Sparc SBI interrupt controller emulation
|
3 | 7d85892b | blueswir1 | *
|
4 | 7d85892b | blueswir1 | * Based on slavio_intctl, copyright (c) 2003-2005 Fabrice Bellard
|
5 | 7d85892b | blueswir1 | *
|
6 | 7d85892b | blueswir1 | * Permission is hereby granted, free of charge, to any person obtaining a copy
|
7 | 7d85892b | blueswir1 | * of this software and associated documentation files (the "Software"), to deal
|
8 | 7d85892b | blueswir1 | * in the Software without restriction, including without limitation the rights
|
9 | 7d85892b | blueswir1 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
10 | 7d85892b | blueswir1 | * copies of the Software, and to permit persons to whom the Software is
|
11 | 7d85892b | blueswir1 | * furnished to do so, subject to the following conditions:
|
12 | 7d85892b | blueswir1 | *
|
13 | 7d85892b | blueswir1 | * The above copyright notice and this permission notice shall be included in
|
14 | 7d85892b | blueswir1 | * all copies or substantial portions of the Software.
|
15 | 7d85892b | blueswir1 | *
|
16 | 7d85892b | blueswir1 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
17 | 7d85892b | blueswir1 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
18 | 7d85892b | blueswir1 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
19 | 7d85892b | blueswir1 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
20 | 7d85892b | blueswir1 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
21 | 7d85892b | blueswir1 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
22 | 7d85892b | blueswir1 | * THE SOFTWARE.
|
23 | 7d85892b | blueswir1 | */
|
24 | 7d85892b | blueswir1 | #include "hw.h" |
25 | 7d85892b | blueswir1 | #include "sun4m.h" |
26 | 7d85892b | blueswir1 | #include "console.h" |
27 | 7d85892b | blueswir1 | |
28 | 7d85892b | blueswir1 | //#define DEBUG_IRQ
|
29 | 7d85892b | blueswir1 | |
30 | 7d85892b | blueswir1 | #ifdef DEBUG_IRQ
|
31 | 001faf32 | Blue Swirl | #define DPRINTF(fmt, ...) \
|
32 | 001faf32 | Blue Swirl | do { printf("IRQ: " fmt , ## __VA_ARGS__); } while (0) |
33 | 7d85892b | blueswir1 | #else
|
34 | 001faf32 | Blue Swirl | #define DPRINTF(fmt, ...)
|
35 | 7d85892b | blueswir1 | #endif
|
36 | 7d85892b | blueswir1 | |
37 | 7d85892b | blueswir1 | #define MAX_CPUS 16 |
38 | 7d85892b | blueswir1 | |
39 | 7d85892b | blueswir1 | #define SBI_NREGS 16 |
40 | 7d85892b | blueswir1 | |
41 | 7d85892b | blueswir1 | typedef struct SBIState { |
42 | 7d85892b | blueswir1 | uint32_t regs[SBI_NREGS]; |
43 | 7d85892b | blueswir1 | uint32_t intreg_pending[MAX_CPUS]; |
44 | 7d85892b | blueswir1 | qemu_irq *cpu_irqs[MAX_CPUS]; |
45 | 7d85892b | blueswir1 | uint32_t pil_out[MAX_CPUS]; |
46 | 7d85892b | blueswir1 | } SBIState; |
47 | 7d85892b | blueswir1 | |
48 | 7d85892b | blueswir1 | #define SBI_SIZE (SBI_NREGS * 4) |
49 | 7d85892b | blueswir1 | |
50 | 7d85892b | blueswir1 | static void sbi_set_irq(void *opaque, int irq, int level) |
51 | 7d85892b | blueswir1 | { |
52 | 7d85892b | blueswir1 | } |
53 | 7d85892b | blueswir1 | |
54 | 7d85892b | blueswir1 | static void sbi_set_timer_irq_cpu(void *opaque, int cpu, int level) |
55 | 7d85892b | blueswir1 | { |
56 | 7d85892b | blueswir1 | } |
57 | 7d85892b | blueswir1 | |
58 | 7d85892b | blueswir1 | static uint32_t sbi_mem_readl(void *opaque, target_phys_addr_t addr) |
59 | 7d85892b | blueswir1 | { |
60 | 7d85892b | blueswir1 | SBIState *s = opaque; |
61 | 7d85892b | blueswir1 | uint32_t saddr, ret; |
62 | 7d85892b | blueswir1 | |
63 | e64d7d59 | blueswir1 | saddr = addr >> 2;
|
64 | 7d85892b | blueswir1 | switch (saddr) {
|
65 | 7d85892b | blueswir1 | default:
|
66 | 7d85892b | blueswir1 | ret = s->regs[saddr]; |
67 | 7d85892b | blueswir1 | break;
|
68 | 7d85892b | blueswir1 | } |
69 | 7d85892b | blueswir1 | DPRINTF("read system reg 0x" TARGET_FMT_plx " = %x\n", addr, ret); |
70 | 7d85892b | blueswir1 | |
71 | 7d85892b | blueswir1 | return ret;
|
72 | 7d85892b | blueswir1 | } |
73 | 7d85892b | blueswir1 | |
74 | 7d85892b | blueswir1 | static void sbi_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
75 | 7d85892b | blueswir1 | { |
76 | 7d85892b | blueswir1 | SBIState *s = opaque; |
77 | 7d85892b | blueswir1 | uint32_t saddr; |
78 | 7d85892b | blueswir1 | |
79 | e64d7d59 | blueswir1 | saddr = addr >> 2;
|
80 | 7d85892b | blueswir1 | DPRINTF("write system reg 0x" TARGET_FMT_plx " = %x\n", addr, val); |
81 | 7d85892b | blueswir1 | switch (saddr) {
|
82 | 7d85892b | blueswir1 | default:
|
83 | 7d85892b | blueswir1 | s->regs[saddr] = val; |
84 | 7d85892b | blueswir1 | break;
|
85 | 7d85892b | blueswir1 | } |
86 | 7d85892b | blueswir1 | } |
87 | 7d85892b | blueswir1 | |
88 | 7d85892b | blueswir1 | static CPUReadMemoryFunc *sbi_mem_read[3] = { |
89 | 7c560456 | blueswir1 | NULL,
|
90 | 7c560456 | blueswir1 | NULL,
|
91 | 7d85892b | blueswir1 | sbi_mem_readl, |
92 | 7d85892b | blueswir1 | }; |
93 | 7d85892b | blueswir1 | |
94 | 7d85892b | blueswir1 | static CPUWriteMemoryFunc *sbi_mem_write[3] = { |
95 | 7c560456 | blueswir1 | NULL,
|
96 | 7c560456 | blueswir1 | NULL,
|
97 | 7d85892b | blueswir1 | sbi_mem_writel, |
98 | 7d85892b | blueswir1 | }; |
99 | 7d85892b | blueswir1 | |
100 | 7d85892b | blueswir1 | static void sbi_save(QEMUFile *f, void *opaque) |
101 | 7d85892b | blueswir1 | { |
102 | 7d85892b | blueswir1 | SBIState *s = opaque; |
103 | 7d85892b | blueswir1 | unsigned int i; |
104 | 7d85892b | blueswir1 | |
105 | 7d85892b | blueswir1 | for (i = 0; i < MAX_CPUS; i++) { |
106 | 7d85892b | blueswir1 | qemu_put_be32s(f, &s->intreg_pending[i]); |
107 | 7d85892b | blueswir1 | } |
108 | 7d85892b | blueswir1 | } |
109 | 7d85892b | blueswir1 | |
110 | 7d85892b | blueswir1 | static int sbi_load(QEMUFile *f, void *opaque, int version_id) |
111 | 7d85892b | blueswir1 | { |
112 | 7d85892b | blueswir1 | SBIState *s = opaque; |
113 | 7d85892b | blueswir1 | unsigned int i; |
114 | 7d85892b | blueswir1 | |
115 | 7d85892b | blueswir1 | if (version_id != 1) |
116 | 7d85892b | blueswir1 | return -EINVAL;
|
117 | 7d85892b | blueswir1 | |
118 | 7d85892b | blueswir1 | for (i = 0; i < MAX_CPUS; i++) { |
119 | 7d85892b | blueswir1 | qemu_get_be32s(f, &s->intreg_pending[i]); |
120 | 7d85892b | blueswir1 | } |
121 | 7d85892b | blueswir1 | |
122 | 7d85892b | blueswir1 | return 0; |
123 | 7d85892b | blueswir1 | } |
124 | 7d85892b | blueswir1 | |
125 | 7d85892b | blueswir1 | static void sbi_reset(void *opaque) |
126 | 7d85892b | blueswir1 | { |
127 | 7d85892b | blueswir1 | SBIState *s = opaque; |
128 | 7d85892b | blueswir1 | unsigned int i; |
129 | 7d85892b | blueswir1 | |
130 | 7d85892b | blueswir1 | for (i = 0; i < MAX_CPUS; i++) { |
131 | 7d85892b | blueswir1 | s->intreg_pending[i] = 0;
|
132 | 7d85892b | blueswir1 | } |
133 | 7d85892b | blueswir1 | } |
134 | 7d85892b | blueswir1 | |
135 | 7d85892b | blueswir1 | void *sbi_init(target_phys_addr_t addr, qemu_irq **irq, qemu_irq **cpu_irq,
|
136 | 7d85892b | blueswir1 | qemu_irq **parent_irq) |
137 | 7d85892b | blueswir1 | { |
138 | 7d85892b | blueswir1 | unsigned int i; |
139 | 7d85892b | blueswir1 | int sbi_io_memory;
|
140 | 7d85892b | blueswir1 | SBIState *s; |
141 | 7d85892b | blueswir1 | |
142 | 7d85892b | blueswir1 | s = qemu_mallocz(sizeof(SBIState));
|
143 | 7d85892b | blueswir1 | |
144 | 7d85892b | blueswir1 | for (i = 0; i < MAX_CPUS; i++) { |
145 | 7d85892b | blueswir1 | s->cpu_irqs[i] = parent_irq[i]; |
146 | 7d85892b | blueswir1 | } |
147 | 7d85892b | blueswir1 | |
148 | 1eed09cb | Avi Kivity | sbi_io_memory = cpu_register_io_memory(sbi_mem_read, sbi_mem_write, s); |
149 | 7d85892b | blueswir1 | cpu_register_physical_memory(addr, SBI_SIZE, sbi_io_memory); |
150 | 7d85892b | blueswir1 | |
151 | 7d85892b | blueswir1 | register_savevm("sbi", addr, 1, sbi_save, sbi_load, s); |
152 | a08d4367 | Jan Kiszka | qemu_register_reset(sbi_reset, s); |
153 | 7d85892b | blueswir1 | *irq = qemu_allocate_irqs(sbi_set_irq, s, 32);
|
154 | 7d85892b | blueswir1 | *cpu_irq = qemu_allocate_irqs(sbi_set_timer_irq_cpu, s, MAX_CPUS); |
155 | 7d85892b | blueswir1 | sbi_reset(s); |
156 | 7d85892b | blueswir1 | |
157 | 7d85892b | blueswir1 | return s;
|
158 | 7d85892b | blueswir1 | } |