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/*
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* Virtio PCI Bindings
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*
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* Copyright IBM, Corp. 2007
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* Copyright (c) 2009 CodeSourcery
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*
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* Authors:
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* Anthony Liguori <aliguori@us.ibm.com>
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* Paul Brook <paul@codesourcery.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2. See
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* the COPYING file in the top-level directory.
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*
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*/
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#include <inttypes.h> |
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#include "virtio.h" |
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#include "pci.h" |
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//#include "sysemu.h"
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#include "msix.h" |
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/* from Linux's linux/virtio_pci.h */
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/* A 32-bit r/o bitmask of the features supported by the host */
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#define VIRTIO_PCI_HOST_FEATURES 0 |
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/* A 32-bit r/w bitmask of features activated by the guest */
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#define VIRTIO_PCI_GUEST_FEATURES 4 |
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/* A 32-bit r/w PFN for the currently selected queue */
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#define VIRTIO_PCI_QUEUE_PFN 8 |
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/* A 16-bit r/o queue size for the currently selected queue */
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#define VIRTIO_PCI_QUEUE_NUM 12 |
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/* A 16-bit r/w queue selector */
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#define VIRTIO_PCI_QUEUE_SEL 14 |
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/* A 16-bit r/w queue notifier */
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#define VIRTIO_PCI_QUEUE_NOTIFY 16 |
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/* An 8-bit device status register. */
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#define VIRTIO_PCI_STATUS 18 |
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/* An 8-bit r/o interrupt status register. Reading the value will return the
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* current contents of the ISR and will also clear it. This is effectively
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* a read-and-acknowledge. */
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#define VIRTIO_PCI_ISR 19 |
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/* MSI-X registers: only enabled if MSI-X is enabled. */
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/* A 16-bit vector for configuration changes. */
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#define VIRTIO_MSI_CONFIG_VECTOR 20 |
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/* A 16-bit vector for selected queue notifications. */
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#define VIRTIO_MSI_QUEUE_VECTOR 22 |
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/* Config space size */
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#define VIRTIO_PCI_CONFIG_NOMSI 20 |
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#define VIRTIO_PCI_CONFIG_MSI 24 |
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#define VIRTIO_PCI_REGION_SIZE(dev) (msix_present(dev) ? \
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VIRTIO_PCI_CONFIG_MSI : \ |
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VIRTIO_PCI_CONFIG_NOMSI) |
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/* The remaining space is defined by each driver as the per-driver
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* configuration space */
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#define VIRTIO_PCI_CONFIG(dev) (msix_enabled(dev) ? \
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VIRTIO_PCI_CONFIG_MSI : \ |
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VIRTIO_PCI_CONFIG_NOMSI) |
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/* Virtio ABI version, if we increment this, we break the guest driver. */
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#define VIRTIO_PCI_ABI_VERSION 0 |
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/* How many bits to shift physical queue address written to QUEUE_PFN.
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* 12 is historical, and due to x86 page size. */
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#define VIRTIO_PCI_QUEUE_ADDR_SHIFT 12 |
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/* QEMU doesn't strictly need write barriers since everything runs in
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* lock-step. We'll leave the calls to wmb() in though to make it obvious for
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* KVM or if kqemu gets SMP support.
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*/
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#define wmb() do { } while (0) |
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/* PCI bindings. */
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typedef struct { |
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PCIDevice pci_dev; |
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VirtIODevice *vdev; |
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uint32_t addr; |
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uint16_t vendor; |
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uint16_t device; |
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uint16_t subvendor; |
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uint16_t class_code; |
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uint8_t pif; |
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} VirtIOPCIProxy; |
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/* virtio device */
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static void virtio_pci_notify(void *opaque, uint16_t vector) |
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{ |
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VirtIOPCIProxy *proxy = opaque; |
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if (msix_enabled(&proxy->pci_dev))
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msix_notify(&proxy->pci_dev, vector); |
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else
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qemu_set_irq(proxy->pci_dev.irq[0], proxy->vdev->isr & 1); |
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} |
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static void virtio_pci_save_config(void * opaque, QEMUFile *f) |
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{ |
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VirtIOPCIProxy *proxy = opaque; |
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pci_device_save(&proxy->pci_dev, f); |
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msix_save(&proxy->pci_dev, f); |
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if (msix_present(&proxy->pci_dev))
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qemu_put_be16(f, proxy->vdev->config_vector); |
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} |
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static void virtio_pci_save_queue(void * opaque, int n, QEMUFile *f) |
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{ |
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VirtIOPCIProxy *proxy = opaque; |
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if (msix_present(&proxy->pci_dev))
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qemu_put_be16(f, virtio_queue_vector(proxy->vdev, n)); |
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} |
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static int virtio_pci_load_config(void * opaque, QEMUFile *f) |
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{ |
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VirtIOPCIProxy *proxy = opaque; |
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int ret;
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ret = pci_device_load(&proxy->pci_dev, f); |
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if (ret)
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return ret;
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msix_load(&proxy->pci_dev, f); |
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if (msix_present(&proxy->pci_dev))
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qemu_get_be16s(f, &proxy->vdev->config_vector); |
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return 0; |
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} |
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static int virtio_pci_load_queue(void * opaque, int n, QEMUFile *f) |
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{ |
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VirtIOPCIProxy *proxy = opaque; |
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uint16_t vector; |
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if (!msix_present(&proxy->pci_dev))
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return 0; |
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qemu_get_be16s(f, &vector); |
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virtio_queue_set_vector(proxy->vdev, n, vector); |
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return 0; |
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} |
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static void virtio_pci_reset(void *opaque) |
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{ |
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VirtIOPCIProxy *proxy = opaque; |
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virtio_reset(proxy->vdev); |
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msix_reset(&proxy->pci_dev); |
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} |
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static void virtio_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
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{ |
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VirtIOPCIProxy *proxy = opaque; |
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VirtIODevice *vdev = proxy->vdev; |
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target_phys_addr_t pa; |
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switch (addr) {
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case VIRTIO_PCI_GUEST_FEATURES:
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/* Guest does not negotiate properly? We have to assume nothing. */
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if (val & (1 << VIRTIO_F_BAD_FEATURE)) { |
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if (vdev->bad_features)
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val = vdev->bad_features(vdev); |
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else
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val = 0;
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} |
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if (vdev->set_features)
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vdev->set_features(vdev, val); |
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vdev->features = val; |
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break;
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case VIRTIO_PCI_QUEUE_PFN:
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pa = (target_phys_addr_t)val << VIRTIO_PCI_QUEUE_ADDR_SHIFT; |
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if (pa == 0) |
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virtio_pci_reset(proxy); |
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else
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virtio_queue_set_addr(vdev, vdev->queue_sel, pa); |
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break;
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case VIRTIO_PCI_QUEUE_SEL:
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if (val < VIRTIO_PCI_QUEUE_MAX)
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vdev->queue_sel = val; |
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break;
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case VIRTIO_PCI_QUEUE_NOTIFY:
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virtio_queue_notify(vdev, val); |
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break;
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case VIRTIO_PCI_STATUS:
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vdev->status = val & 0xFF;
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if (vdev->status == 0) |
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virtio_pci_reset(proxy); |
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break;
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case VIRTIO_MSI_CONFIG_VECTOR:
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msix_vector_unuse(&proxy->pci_dev, vdev->config_vector); |
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/* Make it possible for guest to discover an error took place. */
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if (msix_vector_use(&proxy->pci_dev, val) < 0) |
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val = VIRTIO_NO_VECTOR; |
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vdev->config_vector = val; |
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break;
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case VIRTIO_MSI_QUEUE_VECTOR:
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msix_vector_unuse(&proxy->pci_dev, |
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virtio_queue_vector(vdev, vdev->queue_sel)); |
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/* Make it possible for guest to discover an error took place. */
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if (msix_vector_use(&proxy->pci_dev, val) < 0) |
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val = VIRTIO_NO_VECTOR; |
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virtio_queue_set_vector(vdev, vdev->queue_sel, val); |
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break;
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default:
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fprintf(stderr, "%s: unexpected address 0x%x value 0x%x\n",
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__func__, addr, val); |
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break;
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} |
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} |
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static uint32_t virtio_ioport_read(VirtIOPCIProxy *proxy, uint32_t addr)
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{ |
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VirtIODevice *vdev = proxy->vdev; |
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uint32_t ret = 0xFFFFFFFF;
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switch (addr) {
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case VIRTIO_PCI_HOST_FEATURES:
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ret = vdev->get_features(vdev); |
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ret |= (1 << VIRTIO_F_NOTIFY_ON_EMPTY);
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ret |= (1 << VIRTIO_RING_F_INDIRECT_DESC);
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ret |= (1 << VIRTIO_F_BAD_FEATURE);
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break;
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case VIRTIO_PCI_GUEST_FEATURES:
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ret = vdev->features; |
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break;
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case VIRTIO_PCI_QUEUE_PFN:
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ret = virtio_queue_get_addr(vdev, vdev->queue_sel) |
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>> VIRTIO_PCI_QUEUE_ADDR_SHIFT; |
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break;
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case VIRTIO_PCI_QUEUE_NUM:
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ret = virtio_queue_get_num(vdev, vdev->queue_sel); |
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break;
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case VIRTIO_PCI_QUEUE_SEL:
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ret = vdev->queue_sel; |
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break;
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case VIRTIO_PCI_STATUS:
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ret = vdev->status; |
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break;
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case VIRTIO_PCI_ISR:
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/* reading from the ISR also clears it. */
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ret = vdev->isr; |
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vdev->isr = 0;
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qemu_set_irq(proxy->pci_dev.irq[0], 0); |
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break;
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case VIRTIO_MSI_CONFIG_VECTOR:
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ret = vdev->config_vector; |
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break;
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case VIRTIO_MSI_QUEUE_VECTOR:
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ret = virtio_queue_vector(vdev, vdev->queue_sel); |
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break;
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default:
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break;
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} |
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return ret;
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} |
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static uint32_t virtio_pci_config_readb(void *opaque, uint32_t addr) |
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{ |
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VirtIOPCIProxy *proxy = opaque; |
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uint32_t config = VIRTIO_PCI_CONFIG(&proxy->pci_dev); |
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addr -= proxy->addr; |
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if (addr < config)
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return virtio_ioport_read(proxy, addr);
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addr -= config; |
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return virtio_config_readb(proxy->vdev, addr);
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} |
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static uint32_t virtio_pci_config_readw(void *opaque, uint32_t addr) |
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{ |
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VirtIOPCIProxy *proxy = opaque; |
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uint32_t config = VIRTIO_PCI_CONFIG(&proxy->pci_dev); |
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addr -= proxy->addr; |
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if (addr < config)
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return virtio_ioport_read(proxy, addr);
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addr -= config; |
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return virtio_config_readw(proxy->vdev, addr);
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} |
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static uint32_t virtio_pci_config_readl(void *opaque, uint32_t addr) |
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{ |
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VirtIOPCIProxy *proxy = opaque; |
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uint32_t config = VIRTIO_PCI_CONFIG(&proxy->pci_dev); |
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addr -= proxy->addr; |
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if (addr < config)
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return virtio_ioport_read(proxy, addr);
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addr -= config; |
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return virtio_config_readl(proxy->vdev, addr);
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} |
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static void virtio_pci_config_writeb(void *opaque, uint32_t addr, uint32_t val) |
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{ |
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VirtIOPCIProxy *proxy = opaque; |
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uint32_t config = VIRTIO_PCI_CONFIG(&proxy->pci_dev); |
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addr -= proxy->addr; |
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if (addr < config) {
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virtio_ioport_write(proxy, addr, val); |
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return;
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} |
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addr -= config; |
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virtio_config_writeb(proxy->vdev, addr, val); |
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} |
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static void virtio_pci_config_writew(void *opaque, uint32_t addr, uint32_t val) |
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{ |
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VirtIOPCIProxy *proxy = opaque; |
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uint32_t config = VIRTIO_PCI_CONFIG(&proxy->pci_dev); |
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addr -= proxy->addr; |
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if (addr < config) {
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virtio_ioport_write(proxy, addr, val); |
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return;
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} |
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addr -= config; |
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virtio_config_writew(proxy->vdev, addr, val); |
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} |
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static void virtio_pci_config_writel(void *opaque, uint32_t addr, uint32_t val) |
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{ |
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VirtIOPCIProxy *proxy = opaque; |
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uint32_t config = VIRTIO_PCI_CONFIG(&proxy->pci_dev); |
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addr -= proxy->addr; |
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if (addr < config) {
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virtio_ioport_write(proxy, addr, val); |
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return;
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} |
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addr -= config; |
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virtio_config_writel(proxy->vdev, addr, val); |
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} |
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static void virtio_map(PCIDevice *pci_dev, int region_num, |
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uint32_t addr, uint32_t size, int type)
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{ |
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VirtIOPCIProxy *proxy = container_of(pci_dev, VirtIOPCIProxy, pci_dev); |
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VirtIODevice *vdev = proxy->vdev; |
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unsigned config_len = VIRTIO_PCI_REGION_SIZE(pci_dev) + vdev->config_len;
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proxy->addr = addr; |
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register_ioport_write(addr, config_len, 1, virtio_pci_config_writeb, proxy);
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register_ioport_write(addr, config_len, 2, virtio_pci_config_writew, proxy);
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register_ioport_write(addr, config_len, 4, virtio_pci_config_writel, proxy);
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register_ioport_read(addr, config_len, 1, virtio_pci_config_readb, proxy);
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register_ioport_read(addr, config_len, 2, virtio_pci_config_readw, proxy);
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register_ioport_read(addr, config_len, 4, virtio_pci_config_readl, proxy);
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if (vdev->config_len)
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vdev->get_config(vdev, vdev->config); |
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} |
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static void virtio_write_config(PCIDevice *pci_dev, uint32_t address, |
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uint32_t val, int len)
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{ |
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pci_default_write_config(pci_dev, address, val, len); |
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msix_write_config(pci_dev, address, val, len); |
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} |
360 |
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static const VirtIOBindings virtio_pci_bindings = { |
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.notify = virtio_pci_notify, |
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.save_config = virtio_pci_save_config, |
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.load_config = virtio_pci_load_config, |
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.save_queue = virtio_pci_save_queue, |
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.load_queue = virtio_pci_load_queue, |
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}; |
368 |
|
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static void virtio_init_pci(VirtIOPCIProxy *proxy, VirtIODevice *vdev, |
370 |
uint16_t vendor, uint16_t device, |
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uint16_t class_code, uint8_t pif) |
372 |
{ |
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uint8_t *config; |
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uint32_t size; |
375 |
|
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proxy->vdev = vdev; |
377 |
|
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config = proxy->pci_dev.config; |
379 |
pci_config_set_vendor_id(config, vendor); |
380 |
pci_config_set_device_id(config, device); |
381 |
|
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config[0x08] = VIRTIO_PCI_ABI_VERSION;
|
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|
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config[0x09] = pif;
|
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pci_config_set_class(config, class_code); |
386 |
config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; |
387 |
|
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config[0x2c] = vendor & 0xFF; |
389 |
config[0x2d] = (vendor >> 8) & 0xFF; |
390 |
config[0x2e] = vdev->device_id & 0xFF; |
391 |
config[0x2f] = (vdev->device_id >> 8) & 0xFF; |
392 |
|
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config[0x3d] = 1; |
394 |
|
395 |
if (vdev->nvectors && !msix_init(&proxy->pci_dev, vdev->nvectors, 1, 0)) { |
396 |
pci_register_bar(&proxy->pci_dev, 1,
|
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msix_bar_size(&proxy->pci_dev), |
398 |
PCI_ADDRESS_SPACE_MEM, |
399 |
msix_mmio_map); |
400 |
proxy->pci_dev.config_write = virtio_write_config; |
401 |
proxy->pci_dev.unregister = msix_uninit; |
402 |
} else
|
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vdev->nvectors = 0;
|
404 |
|
405 |
size = VIRTIO_PCI_REGION_SIZE(&proxy->pci_dev) + vdev->config_len; |
406 |
if (size & (size-1)) |
407 |
size = 1 << qemu_fls(size);
|
408 |
|
409 |
pci_register_bar(&proxy->pci_dev, 0, size, PCI_ADDRESS_SPACE_IO,
|
410 |
virtio_map); |
411 |
|
412 |
qemu_register_reset(virtio_pci_reset, proxy); |
413 |
|
414 |
virtio_bind_device(vdev, &virtio_pci_bindings, proxy); |
415 |
} |
416 |
|
417 |
static void virtio_blk_init_pci(PCIDevice *pci_dev) |
418 |
{ |
419 |
VirtIOPCIProxy *proxy = DO_UPCAST(VirtIOPCIProxy, pci_dev, pci_dev); |
420 |
VirtIODevice *vdev; |
421 |
|
422 |
vdev = virtio_blk_init(&pci_dev->qdev); |
423 |
virtio_init_pci(proxy, vdev, |
424 |
PCI_VENDOR_ID_REDHAT_QUMRANET, |
425 |
PCI_DEVICE_ID_VIRTIO_BLOCK, |
426 |
PCI_CLASS_STORAGE_OTHER, |
427 |
0x00);
|
428 |
} |
429 |
|
430 |
static void virtio_console_init_pci(PCIDevice *pci_dev) |
431 |
{ |
432 |
VirtIOPCIProxy *proxy = DO_UPCAST(VirtIOPCIProxy, pci_dev, pci_dev); |
433 |
VirtIODevice *vdev; |
434 |
|
435 |
vdev = virtio_console_init(&pci_dev->qdev); |
436 |
virtio_init_pci(proxy, vdev, |
437 |
PCI_VENDOR_ID_REDHAT_QUMRANET, |
438 |
PCI_DEVICE_ID_VIRTIO_CONSOLE, |
439 |
PCI_CLASS_DISPLAY_OTHER, |
440 |
0x00);
|
441 |
} |
442 |
|
443 |
static void virtio_net_init_pci(PCIDevice *pci_dev) |
444 |
{ |
445 |
VirtIOPCIProxy *proxy = DO_UPCAST(VirtIOPCIProxy, pci_dev, pci_dev); |
446 |
VirtIODevice *vdev; |
447 |
|
448 |
vdev = virtio_net_init(&pci_dev->qdev); |
449 |
virtio_init_pci(proxy, vdev, |
450 |
PCI_VENDOR_ID_REDHAT_QUMRANET, |
451 |
PCI_DEVICE_ID_VIRTIO_NET, |
452 |
PCI_CLASS_NETWORK_ETHERNET, |
453 |
0x00);
|
454 |
} |
455 |
|
456 |
static void virtio_balloon_init_pci(PCIDevice *pci_dev) |
457 |
{ |
458 |
VirtIOPCIProxy *proxy = DO_UPCAST(VirtIOPCIProxy, pci_dev, pci_dev); |
459 |
VirtIODevice *vdev; |
460 |
|
461 |
vdev = virtio_balloon_init(&pci_dev->qdev); |
462 |
virtio_init_pci(proxy, vdev, |
463 |
PCI_VENDOR_ID_REDHAT_QUMRANET, |
464 |
PCI_DEVICE_ID_VIRTIO_BALLOON, |
465 |
PCI_CLASS_MEMORY_RAM, |
466 |
0x00);
|
467 |
} |
468 |
|
469 |
static PCIDeviceInfo virtio_info[] = {
|
470 |
{ |
471 |
.qdev.name = "virtio-blk-pci",
|
472 |
.qdev.size = sizeof(VirtIOPCIProxy),
|
473 |
.init = virtio_blk_init_pci, |
474 |
},{ |
475 |
.qdev.name = "virtio-net-pci",
|
476 |
.qdev.size = sizeof(VirtIOPCIProxy),
|
477 |
.init = virtio_net_init_pci, |
478 |
},{ |
479 |
.qdev.name = "virtio-console-pci",
|
480 |
.qdev.size = sizeof(VirtIOPCIProxy),
|
481 |
.init = virtio_console_init_pci, |
482 |
},{ |
483 |
.qdev.name = "virtio-balloon-pci",
|
484 |
.qdev.size = sizeof(VirtIOPCIProxy),
|
485 |
.init = virtio_balloon_init_pci, |
486 |
},{ |
487 |
/* end of list */
|
488 |
} |
489 |
}; |
490 |
|
491 |
static void virtio_pci_register_devices(void) |
492 |
{ |
493 |
pci_qdev_register_many(virtio_info); |
494 |
} |
495 |
|
496 |
device_init(virtio_pci_register_devices) |