Revision 9a62fb24 hw/sun4m.c
| b/hw/sun4m.c | ||
|---|---|---|
| 89 | 89 |
|
| 90 | 90 |
#define MAX_CPUS 16 |
| 91 | 91 |
#define MAX_PILS 16 |
| 92 |
#define MAX_VSIMMS 4 |
|
| 92 | 93 |
|
| 93 | 94 |
#define ESCC_CLOCK 4915200 |
| 94 | 95 |
|
| ... | ... | |
| 98 | 99 |
target_phys_addr_t serial_base, fd_base; |
| 99 | 100 |
target_phys_addr_t afx_base, idreg_base, dma_base, esp_base, le_base; |
| 100 | 101 |
target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base; |
| 102 |
target_phys_addr_t bpp_base, dbri_base, sx_base; |
|
| 103 |
struct {
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|
| 104 |
target_phys_addr_t reg_base, vram_base; |
|
| 105 |
} vsimm[MAX_VSIMMS]; |
|
| 101 | 106 |
target_phys_addr_t ecc_base; |
| 102 | 107 |
uint32_t ecc_version; |
| 103 | 108 |
uint8_t nvram_machine_id; |
| ... | ... | |
| 810 | 815 |
unsigned long kernel_size; |
| 811 | 816 |
DriveInfo *fd[MAX_FD]; |
| 812 | 817 |
void *fw_cfg; |
| 818 |
unsigned int num_vsimms; |
|
| 813 | 819 |
|
| 814 | 820 |
/* init CPUs */ |
| 815 | 821 |
if (!cpu_model) |
| ... | ... | |
| 872 | 878 |
fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth); |
| 873 | 879 |
exit (1); |
| 874 | 880 |
} |
| 875 |
tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height, |
|
| 876 |
graphic_depth); |
|
| 881 |
num_vsimms = 0; |
|
| 882 |
if (num_vsimms == 0) {
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|
| 883 |
tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height, |
|
| 884 |
graphic_depth); |
|
| 885 |
} |
|
| 886 |
|
|
| 887 |
for (i = num_vsimms; i < MAX_VSIMMS; i++) {
|
|
| 888 |
/* vsimm registers probed by OBP */ |
|
| 889 |
if (hwdef->vsimm[i].reg_base) {
|
|
| 890 |
empty_slot_init(hwdef->vsimm[i].reg_base, 0x2000); |
|
| 891 |
} |
|
| 892 |
} |
|
| 893 |
|
|
| 894 |
if (hwdef->sx_base) {
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| 895 |
empty_slot_init(hwdef->sx_base, 0x2000); |
|
| 896 |
} |
|
| 877 | 897 |
|
| 878 | 898 |
lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq); |
| 879 | 899 |
|
| ... | ... | |
| 920 | 940 |
slavio_irq[5]); |
| 921 | 941 |
} |
| 922 | 942 |
|
| 943 |
if (hwdef->dbri_base) {
|
|
| 944 |
/* ISDN chip with attached CS4215 audio codec */ |
|
| 945 |
/* prom space */ |
|
| 946 |
empty_slot_init(hwdef->dbri_base+0x1000, 0x30); |
|
| 947 |
/* reg space */ |
|
| 948 |
empty_slot_init(hwdef->dbri_base+0x10000, 0x100); |
|
| 949 |
} |
|
| 950 |
|
|
| 951 |
if (hwdef->bpp_base) {
|
|
| 952 |
/* parallel port */ |
|
| 953 |
empty_slot_init(hwdef->bpp_base, 0x20); |
|
| 954 |
} |
|
| 955 |
|
|
| 923 | 956 |
kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename, |
| 924 | 957 |
RAM_size); |
| 925 | 958 |
|
| ... | ... | |
| 1063 | 1096 |
.dma_base = 0xef0400000ULL, |
| 1064 | 1097 |
.esp_base = 0xef0800000ULL, |
| 1065 | 1098 |
.le_base = 0xef0c00000ULL, |
| 1099 |
.bpp_base = 0xef4800000ULL, |
|
| 1066 | 1100 |
.apc_base = 0xefa000000ULL, // XXX should not exist |
| 1067 | 1101 |
.aux1_base = 0xff1800000ULL, |
| 1068 | 1102 |
.aux2_base = 0xff1a01000ULL, |
| 1103 |
.dbri_base = 0xee0000000ULL, |
|
| 1104 |
.sx_base = 0xf80000000ULL, |
|
| 1105 |
.vsimm = {
|
|
| 1106 |
{
|
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| 1107 |
.reg_base = 0x9c000000ULL, |
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| 1108 |
.vram_base = 0xfc000000ULL |
|
| 1109 |
}, {
|
|
| 1110 |
.reg_base = 0x90000000ULL, |
|
| 1111 |
.vram_base = 0xf0000000ULL |
|
| 1112 |
}, {
|
|
| 1113 |
.reg_base = 0x94000000ULL |
|
| 1114 |
}, {
|
|
| 1115 |
.reg_base = 0x98000000ULL |
|
| 1116 |
} |
|
| 1117 |
}, |
|
| 1069 | 1118 |
.ecc_base = 0xf00000000ULL, |
| 1070 | 1119 |
.ecc_version = 0x20000000, // version 0, implementation 2 |
| 1071 | 1120 |
.nvram_machine_id = 0x72, |
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