root / hw / pflash_cfi02.c @ 9a87ce9b
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1 | 29133e9a | bellard | /*
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2 | 29133e9a | bellard | * CFI parallel flash with AMD command set emulation
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3 | 5fafdf24 | ths | *
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4 | 29133e9a | bellard | * Copyright (c) 2005 Jocelyn Mayer
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5 | 29133e9a | bellard | *
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6 | 29133e9a | bellard | * This library is free software; you can redistribute it and/or
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7 | 29133e9a | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 29133e9a | bellard | * License as published by the Free Software Foundation; either
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9 | 29133e9a | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 29133e9a | bellard | *
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11 | 29133e9a | bellard | * This library is distributed in the hope that it will be useful,
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12 | 29133e9a | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 29133e9a | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 29133e9a | bellard | * Lesser General Public License for more details.
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15 | 29133e9a | bellard | *
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16 | 29133e9a | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 29133e9a | bellard | * License along with this library; if not, write to the Free Software
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18 | 29133e9a | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | 29133e9a | bellard | */
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20 | 29133e9a | bellard | |
21 | 29133e9a | bellard | /*
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22 | 29133e9a | bellard | * For now, this code can emulate flashes of 1, 2 or 4 bytes width.
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23 | 29133e9a | bellard | * Supported commands/modes are:
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24 | 29133e9a | bellard | * - flash read
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25 | 29133e9a | bellard | * - flash write
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26 | 29133e9a | bellard | * - flash ID read
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27 | 29133e9a | bellard | * - sector erase
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28 | 29133e9a | bellard | * - chip erase
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29 | 29133e9a | bellard | * - unlock bypass command
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30 | 29133e9a | bellard | * - CFI queries
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31 | 29133e9a | bellard | *
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32 | 29133e9a | bellard | * It does not support flash interleaving.
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33 | 29133e9a | bellard | * It does not implement boot blocs with reduced size
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34 | 29133e9a | bellard | * It does not implement software data protection as found in many real chips
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35 | 29133e9a | bellard | * It does not implement erase suspend/resume commands
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36 | 29133e9a | bellard | * It does not implement multiple sectors erase
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37 | 29133e9a | bellard | */
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38 | 29133e9a | bellard | |
39 | 87ecb68b | pbrook | #include "hw.h" |
40 | 87ecb68b | pbrook | #include "flash.h" |
41 | 87ecb68b | pbrook | #include "qemu-timer.h" |
42 | 87ecb68b | pbrook | #include "block.h" |
43 | 29133e9a | bellard | |
44 | 29133e9a | bellard | //#define PFLASH_DEBUG
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45 | 29133e9a | bellard | #ifdef PFLASH_DEBUG
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46 | 29133e9a | bellard | #define DPRINTF(fmt, args...) \
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47 | 29133e9a | bellard | do { \
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48 | 29133e9a | bellard | printf("PFLASH: " fmt , ##args); \ |
49 | 29133e9a | bellard | } while (0) |
50 | 29133e9a | bellard | #else
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51 | 29133e9a | bellard | #define DPRINTF(fmt, args...) do { } while (0) |
52 | 29133e9a | bellard | #endif
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53 | 29133e9a | bellard | |
54 | 29133e9a | bellard | struct pflash_t {
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55 | 29133e9a | bellard | BlockDriverState *bs; |
56 | 71db710f | blueswir1 | target_phys_addr_t base; |
57 | 71db710f | blueswir1 | uint32_t sector_len; |
58 | 71db710f | blueswir1 | uint32_t total_len; |
59 | 29133e9a | bellard | int width;
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60 | 29133e9a | bellard | int wcycle; /* if 0, the flash is read normally */ |
61 | 29133e9a | bellard | int bypass;
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62 | 29133e9a | bellard | int ro;
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63 | 29133e9a | bellard | uint8_t cmd; |
64 | 29133e9a | bellard | uint8_t status; |
65 | 29133e9a | bellard | uint16_t ident[4];
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66 | 29133e9a | bellard | uint8_t cfi_len; |
67 | 29133e9a | bellard | uint8_t cfi_table[0x52];
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68 | 29133e9a | bellard | QEMUTimer *timer; |
69 | 29133e9a | bellard | ram_addr_t off; |
70 | 29133e9a | bellard | int fl_mem;
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71 | 29133e9a | bellard | void *storage;
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72 | 29133e9a | bellard | }; |
73 | 29133e9a | bellard | |
74 | 29133e9a | bellard | static void pflash_timer (void *opaque) |
75 | 29133e9a | bellard | { |
76 | 29133e9a | bellard | pflash_t *pfl = opaque; |
77 | 29133e9a | bellard | |
78 | 29133e9a | bellard | DPRINTF("%s: command %02x done\n", __func__, pfl->cmd);
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79 | 29133e9a | bellard | /* Reset flash */
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80 | 29133e9a | bellard | pfl->status ^= 0x80;
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81 | 29133e9a | bellard | if (pfl->bypass) {
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82 | 29133e9a | bellard | pfl->wcycle = 2;
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83 | 29133e9a | bellard | } else {
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84 | 29133e9a | bellard | cpu_register_physical_memory(pfl->base, pfl->total_len, |
85 | 29133e9a | bellard | pfl->off | IO_MEM_ROMD | pfl->fl_mem); |
86 | 29133e9a | bellard | pfl->wcycle = 0;
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87 | 29133e9a | bellard | } |
88 | 29133e9a | bellard | pfl->cmd = 0;
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89 | 29133e9a | bellard | } |
90 | 29133e9a | bellard | |
91 | 71db710f | blueswir1 | static uint32_t pflash_read (pflash_t *pfl, uint32_t offset, int width) |
92 | 29133e9a | bellard | { |
93 | 71db710f | blueswir1 | uint32_t boff; |
94 | 29133e9a | bellard | uint32_t ret; |
95 | 29133e9a | bellard | uint8_t *p; |
96 | 29133e9a | bellard | |
97 | e96efcfc | j_mayer | DPRINTF("%s: offset " TARGET_FMT_lx "\n", __func__, offset); |
98 | 29133e9a | bellard | ret = -1;
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99 | 29133e9a | bellard | offset -= pfl->base; |
100 | 29133e9a | bellard | boff = offset & 0xFF;
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101 | 29133e9a | bellard | if (pfl->width == 2) |
102 | 29133e9a | bellard | boff = boff >> 1;
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103 | 29133e9a | bellard | else if (pfl->width == 4) |
104 | 29133e9a | bellard | boff = boff >> 2;
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105 | 29133e9a | bellard | switch (pfl->cmd) {
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106 | 29133e9a | bellard | default:
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107 | 29133e9a | bellard | /* This should never happen : reset state & treat it as a read*/
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108 | 29133e9a | bellard | DPRINTF("%s: unknown command state: %x\n", __func__, pfl->cmd);
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109 | 29133e9a | bellard | pfl->wcycle = 0;
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110 | 29133e9a | bellard | pfl->cmd = 0;
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111 | 29133e9a | bellard | case 0x80: |
112 | 29133e9a | bellard | /* We accept reads during second unlock sequence... */
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113 | 29133e9a | bellard | case 0x00: |
114 | 29133e9a | bellard | flash_read:
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115 | 29133e9a | bellard | /* Flash area read */
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116 | 29133e9a | bellard | p = pfl->storage; |
117 | 29133e9a | bellard | switch (width) {
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118 | 29133e9a | bellard | case 1: |
119 | 29133e9a | bellard | ret = p[offset]; |
120 | 29133e9a | bellard | // DPRINTF("%s: data offset %08x %02x\n", __func__, offset, ret);
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121 | 29133e9a | bellard | break;
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122 | 29133e9a | bellard | case 2: |
123 | 29133e9a | bellard | #if defined(TARGET_WORDS_BIGENDIAN)
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124 | 29133e9a | bellard | ret = p[offset] << 8;
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125 | 29133e9a | bellard | ret |= p[offset + 1];
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126 | 29133e9a | bellard | #else
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127 | 29133e9a | bellard | ret = p[offset]; |
128 | 29133e9a | bellard | ret |= p[offset + 1] << 8; |
129 | 29133e9a | bellard | #endif
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130 | 29133e9a | bellard | // DPRINTF("%s: data offset %08x %04x\n", __func__, offset, ret);
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131 | 29133e9a | bellard | break;
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132 | 29133e9a | bellard | case 4: |
133 | 29133e9a | bellard | #if defined(TARGET_WORDS_BIGENDIAN)
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134 | 29133e9a | bellard | ret = p[offset] << 24;
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135 | 29133e9a | bellard | ret |= p[offset + 1] << 16; |
136 | 29133e9a | bellard | ret |= p[offset + 2] << 8; |
137 | 29133e9a | bellard | ret |= p[offset + 3];
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138 | 29133e9a | bellard | #else
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139 | 29133e9a | bellard | ret = p[offset]; |
140 | 29133e9a | bellard | ret |= p[offset + 1] << 8; |
141 | 29133e9a | bellard | ret |= p[offset + 2] << 16; |
142 | 29133e9a | bellard | ret |= p[offset + 3] << 24; |
143 | 29133e9a | bellard | #endif
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144 | 29133e9a | bellard | // DPRINTF("%s: data offset %08x %08x\n", __func__, offset, ret);
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145 | 29133e9a | bellard | break;
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146 | 29133e9a | bellard | } |
147 | 29133e9a | bellard | break;
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148 | 29133e9a | bellard | case 0x90: |
149 | 29133e9a | bellard | /* flash ID read */
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150 | 29133e9a | bellard | switch (boff) {
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151 | 29133e9a | bellard | case 0x00: |
152 | 29133e9a | bellard | case 0x01: |
153 | 29133e9a | bellard | ret = pfl->ident[boff & 0x01];
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154 | 29133e9a | bellard | break;
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155 | 29133e9a | bellard | case 0x02: |
156 | 29133e9a | bellard | ret = 0x00; /* Pretend all sectors are unprotected */ |
157 | 29133e9a | bellard | break;
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158 | 29133e9a | bellard | case 0x0E: |
159 | 29133e9a | bellard | case 0x0F: |
160 | 29133e9a | bellard | if (pfl->ident[2 + (boff & 0x01)] == (uint8_t)-1) |
161 | 29133e9a | bellard | goto flash_read;
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162 | 29133e9a | bellard | ret = pfl->ident[2 + (boff & 0x01)]; |
163 | 29133e9a | bellard | break;
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164 | 29133e9a | bellard | default:
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165 | 29133e9a | bellard | goto flash_read;
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166 | 29133e9a | bellard | } |
167 | e96efcfc | j_mayer | DPRINTF("%s: ID " TARGET_FMT_ld " %x\n", __func__, boff, ret); |
168 | 29133e9a | bellard | break;
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169 | 29133e9a | bellard | case 0xA0: |
170 | 29133e9a | bellard | case 0x10: |
171 | 29133e9a | bellard | case 0x30: |
172 | 29133e9a | bellard | /* Status register read */
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173 | 29133e9a | bellard | ret = pfl->status; |
174 | 29133e9a | bellard | DPRINTF("%s: status %x\n", __func__, ret);
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175 | 29133e9a | bellard | /* Toggle bit 6 */
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176 | 29133e9a | bellard | pfl->status ^= 0x40;
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177 | 29133e9a | bellard | break;
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178 | 29133e9a | bellard | case 0x98: |
179 | 29133e9a | bellard | /* CFI query mode */
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180 | 29133e9a | bellard | if (boff > pfl->cfi_len)
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181 | 29133e9a | bellard | ret = 0;
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182 | 29133e9a | bellard | else
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183 | 29133e9a | bellard | ret = pfl->cfi_table[boff]; |
184 | 29133e9a | bellard | break;
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185 | 29133e9a | bellard | } |
186 | 29133e9a | bellard | |
187 | 29133e9a | bellard | return ret;
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188 | 29133e9a | bellard | } |
189 | 29133e9a | bellard | |
190 | 29133e9a | bellard | /* update flash content on disk */
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191 | 5fafdf24 | ths | static void pflash_update(pflash_t *pfl, int offset, |
192 | 29133e9a | bellard | int size)
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193 | 29133e9a | bellard | { |
194 | 29133e9a | bellard | int offset_end;
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195 | 29133e9a | bellard | if (pfl->bs) {
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196 | 29133e9a | bellard | offset_end = offset + size; |
197 | 29133e9a | bellard | /* round to sectors */
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198 | 29133e9a | bellard | offset = offset >> 9;
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199 | 29133e9a | bellard | offset_end = (offset_end + 511) >> 9; |
200 | 5fafdf24 | ths | bdrv_write(pfl->bs, offset, pfl->storage + (offset << 9),
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201 | 29133e9a | bellard | offset_end - offset); |
202 | 29133e9a | bellard | } |
203 | 29133e9a | bellard | } |
204 | 29133e9a | bellard | |
205 | 71db710f | blueswir1 | static void pflash_write (pflash_t *pfl, uint32_t offset, uint32_t value, |
206 | 29133e9a | bellard | int width)
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207 | 29133e9a | bellard | { |
208 | 71db710f | blueswir1 | uint32_t boff; |
209 | 29133e9a | bellard | uint8_t *p; |
210 | 29133e9a | bellard | uint8_t cmd; |
211 | 29133e9a | bellard | |
212 | 29133e9a | bellard | /* WARNING: when the memory area is in ROMD mode, the offset is a
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213 | 29133e9a | bellard | ram offset, not a physical address */
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214 | 95d1f3ed | j_mayer | cmd = value; |
215 | 95d1f3ed | j_mayer | if (pfl->cmd != 0xA0 && cmd == 0xF0) { |
216 | 95d1f3ed | j_mayer | #if 0
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217 | 95d1f3ed | j_mayer | DPRINTF("%s: flash reset asked (%02x %02x)\n",
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218 | 95d1f3ed | j_mayer | __func__, pfl->cmd, cmd);
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219 | 95d1f3ed | j_mayer | #endif
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220 | 95d1f3ed | j_mayer | goto reset_flash;
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221 | 95d1f3ed | j_mayer | } |
222 | 95d1f3ed | j_mayer | DPRINTF("%s: offset " TARGET_FMT_lx " %08x %d %d\n", __func__, |
223 | 95d1f3ed | j_mayer | offset, value, width, pfl->wcycle); |
224 | 29133e9a | bellard | if (pfl->wcycle == 0) |
225 | 71db710f | blueswir1 | offset -= (uint32_t)(long)pfl->storage;
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226 | 29133e9a | bellard | else
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227 | 29133e9a | bellard | offset -= pfl->base; |
228 | 3b46e624 | ths | |
229 | e96efcfc | j_mayer | DPRINTF("%s: offset " TARGET_FMT_lx " %08x %d\n", __func__, |
230 | e96efcfc | j_mayer | offset, value, width); |
231 | 29133e9a | bellard | /* Set the device in I/O access mode */
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232 | 29133e9a | bellard | cpu_register_physical_memory(pfl->base, pfl->total_len, pfl->fl_mem); |
233 | 29133e9a | bellard | boff = offset & (pfl->sector_len - 1);
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234 | 29133e9a | bellard | if (pfl->width == 2) |
235 | 29133e9a | bellard | boff = boff >> 1;
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236 | 29133e9a | bellard | else if (pfl->width == 4) |
237 | 29133e9a | bellard | boff = boff >> 2;
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238 | 29133e9a | bellard | switch (pfl->wcycle) {
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239 | 29133e9a | bellard | case 0: |
240 | 29133e9a | bellard | /* We're in read mode */
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241 | 29133e9a | bellard | check_unlock0:
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242 | 29133e9a | bellard | if (boff == 0x55 && cmd == 0x98) { |
243 | 29133e9a | bellard | enter_CFI_mode:
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244 | 29133e9a | bellard | /* Enter CFI query mode */
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245 | 29133e9a | bellard | pfl->wcycle = 7;
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246 | 29133e9a | bellard | pfl->cmd = 0x98;
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247 | 29133e9a | bellard | return;
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248 | 29133e9a | bellard | } |
249 | 29133e9a | bellard | if (boff != 0x555 || cmd != 0xAA) { |
250 | e96efcfc | j_mayer | DPRINTF("%s: unlock0 failed " TARGET_FMT_lx " %02x %04x\n", |
251 | 29133e9a | bellard | __func__, boff, cmd, 0x555);
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252 | 29133e9a | bellard | goto reset_flash;
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253 | 29133e9a | bellard | } |
254 | 29133e9a | bellard | DPRINTF("%s: unlock sequence started\n", __func__);
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255 | 29133e9a | bellard | break;
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256 | 29133e9a | bellard | case 1: |
257 | 29133e9a | bellard | /* We started an unlock sequence */
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258 | 29133e9a | bellard | check_unlock1:
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259 | 29133e9a | bellard | if (boff != 0x2AA || cmd != 0x55) { |
260 | e96efcfc | j_mayer | DPRINTF("%s: unlock1 failed " TARGET_FMT_lx " %02x\n", __func__, |
261 | e96efcfc | j_mayer | boff, cmd); |
262 | 29133e9a | bellard | goto reset_flash;
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263 | 29133e9a | bellard | } |
264 | 29133e9a | bellard | DPRINTF("%s: unlock sequence done\n", __func__);
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265 | 29133e9a | bellard | break;
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266 | 29133e9a | bellard | case 2: |
267 | 29133e9a | bellard | /* We finished an unlock sequence */
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268 | 29133e9a | bellard | if (!pfl->bypass && boff != 0x555) { |
269 | e96efcfc | j_mayer | DPRINTF("%s: command failed " TARGET_FMT_lx " %02x\n", __func__, |
270 | e96efcfc | j_mayer | boff, cmd); |
271 | 29133e9a | bellard | goto reset_flash;
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272 | 29133e9a | bellard | } |
273 | 29133e9a | bellard | switch (cmd) {
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274 | 29133e9a | bellard | case 0x20: |
275 | 29133e9a | bellard | pfl->bypass = 1;
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276 | 29133e9a | bellard | goto do_bypass;
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277 | 29133e9a | bellard | case 0x80: |
278 | 29133e9a | bellard | case 0x90: |
279 | 29133e9a | bellard | case 0xA0: |
280 | 29133e9a | bellard | pfl->cmd = cmd; |
281 | 29133e9a | bellard | DPRINTF("%s: starting command %02x\n", __func__, cmd);
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282 | 29133e9a | bellard | break;
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283 | 29133e9a | bellard | default:
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284 | 29133e9a | bellard | DPRINTF("%s: unknown command %02x\n", __func__, cmd);
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285 | 29133e9a | bellard | goto reset_flash;
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286 | 29133e9a | bellard | } |
287 | 29133e9a | bellard | break;
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288 | 29133e9a | bellard | case 3: |
289 | 29133e9a | bellard | switch (pfl->cmd) {
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290 | 29133e9a | bellard | case 0x80: |
291 | 29133e9a | bellard | /* We need another unlock sequence */
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292 | 29133e9a | bellard | goto check_unlock0;
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293 | 29133e9a | bellard | case 0xA0: |
294 | e96efcfc | j_mayer | DPRINTF("%s: write data offset " TARGET_FMT_lx " %08x %d\n", |
295 | 29133e9a | bellard | __func__, offset, value, width); |
296 | 29133e9a | bellard | p = pfl->storage; |
297 | 29133e9a | bellard | switch (width) {
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298 | 29133e9a | bellard | case 1: |
299 | 29133e9a | bellard | p[offset] &= value; |
300 | 29133e9a | bellard | pflash_update(pfl, offset, 1);
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301 | 29133e9a | bellard | break;
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302 | 29133e9a | bellard | case 2: |
303 | 29133e9a | bellard | #if defined(TARGET_WORDS_BIGENDIAN)
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304 | 29133e9a | bellard | p[offset] &= value >> 8;
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305 | 29133e9a | bellard | p[offset + 1] &= value;
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306 | 29133e9a | bellard | #else
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307 | 29133e9a | bellard | p[offset] &= value; |
308 | 29133e9a | bellard | p[offset + 1] &= value >> 8; |
309 | 29133e9a | bellard | #endif
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310 | 29133e9a | bellard | pflash_update(pfl, offset, 2);
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311 | 29133e9a | bellard | break;
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312 | 29133e9a | bellard | case 4: |
313 | 29133e9a | bellard | #if defined(TARGET_WORDS_BIGENDIAN)
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314 | 29133e9a | bellard | p[offset] &= value >> 24;
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315 | 29133e9a | bellard | p[offset + 1] &= value >> 16; |
316 | 29133e9a | bellard | p[offset + 2] &= value >> 8; |
317 | 29133e9a | bellard | p[offset + 3] &= value;
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318 | 29133e9a | bellard | #else
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319 | 29133e9a | bellard | p[offset] &= value; |
320 | 29133e9a | bellard | p[offset + 1] &= value >> 8; |
321 | 29133e9a | bellard | p[offset + 2] &= value >> 16; |
322 | 29133e9a | bellard | p[offset + 3] &= value >> 24; |
323 | 29133e9a | bellard | #endif
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324 | 29133e9a | bellard | pflash_update(pfl, offset, 4);
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325 | 29133e9a | bellard | break;
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326 | 29133e9a | bellard | } |
327 | 29133e9a | bellard | pfl->status = 0x00 | ~(value & 0x80); |
328 | 29133e9a | bellard | /* Let's pretend write is immediate */
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329 | 29133e9a | bellard | if (pfl->bypass)
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330 | 29133e9a | bellard | goto do_bypass;
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331 | 29133e9a | bellard | goto reset_flash;
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332 | 29133e9a | bellard | case 0x90: |
333 | 29133e9a | bellard | if (pfl->bypass && cmd == 0x00) { |
334 | 29133e9a | bellard | /* Unlock bypass reset */
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335 | 29133e9a | bellard | goto reset_flash;
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336 | 29133e9a | bellard | } |
337 | 29133e9a | bellard | /* We can enter CFI query mode from autoselect mode */
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338 | 29133e9a | bellard | if (boff == 0x55 && cmd == 0x98) |
339 | 29133e9a | bellard | goto enter_CFI_mode;
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340 | 29133e9a | bellard | /* No break here */
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341 | 29133e9a | bellard | default:
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342 | 29133e9a | bellard | DPRINTF("%s: invalid write for command %02x\n",
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343 | 29133e9a | bellard | __func__, pfl->cmd); |
344 | 29133e9a | bellard | goto reset_flash;
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345 | 29133e9a | bellard | } |
346 | 29133e9a | bellard | case 4: |
347 | 29133e9a | bellard | switch (pfl->cmd) {
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348 | 29133e9a | bellard | case 0xA0: |
349 | 29133e9a | bellard | /* Ignore writes while flash data write is occuring */
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350 | 29133e9a | bellard | /* As we suppose write is immediate, this should never happen */
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351 | 29133e9a | bellard | return;
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352 | 29133e9a | bellard | case 0x80: |
353 | 29133e9a | bellard | goto check_unlock1;
|
354 | 29133e9a | bellard | default:
|
355 | 29133e9a | bellard | /* Should never happen */
|
356 | 29133e9a | bellard | DPRINTF("%s: invalid command state %02x (wc 4)\n",
|
357 | 29133e9a | bellard | __func__, pfl->cmd); |
358 | 29133e9a | bellard | goto reset_flash;
|
359 | 29133e9a | bellard | } |
360 | 29133e9a | bellard | break;
|
361 | 29133e9a | bellard | case 5: |
362 | 29133e9a | bellard | switch (cmd) {
|
363 | 29133e9a | bellard | case 0x10: |
364 | 29133e9a | bellard | if (boff != 0x555) { |
365 | e96efcfc | j_mayer | DPRINTF("%s: chip erase: invalid address " TARGET_FMT_lx "\n", |
366 | 29133e9a | bellard | __func__, offset); |
367 | 29133e9a | bellard | goto reset_flash;
|
368 | 29133e9a | bellard | } |
369 | 29133e9a | bellard | /* Chip erase */
|
370 | 29133e9a | bellard | DPRINTF("%s: start chip erase\n", __func__);
|
371 | 29133e9a | bellard | memset(pfl->storage, 0xFF, pfl->total_len);
|
372 | 29133e9a | bellard | pfl->status = 0x00;
|
373 | 29133e9a | bellard | pflash_update(pfl, 0, pfl->total_len);
|
374 | 29133e9a | bellard | /* Let's wait 5 seconds before chip erase is done */
|
375 | 5fafdf24 | ths | qemu_mod_timer(pfl->timer, |
376 | 29133e9a | bellard | qemu_get_clock(vm_clock) + (ticks_per_sec * 5));
|
377 | 29133e9a | bellard | break;
|
378 | 29133e9a | bellard | case 0x30: |
379 | 29133e9a | bellard | /* Sector erase */
|
380 | 29133e9a | bellard | p = pfl->storage; |
381 | 29133e9a | bellard | offset &= ~(pfl->sector_len - 1);
|
382 | e96efcfc | j_mayer | DPRINTF("%s: start sector erase at " TARGET_FMT_lx "\n", __func__, |
383 | e96efcfc | j_mayer | offset); |
384 | 29133e9a | bellard | memset(p + offset, 0xFF, pfl->sector_len);
|
385 | 29133e9a | bellard | pflash_update(pfl, offset, pfl->sector_len); |
386 | 29133e9a | bellard | pfl->status = 0x00;
|
387 | 29133e9a | bellard | /* Let's wait 1/2 second before sector erase is done */
|
388 | 5fafdf24 | ths | qemu_mod_timer(pfl->timer, |
389 | 29133e9a | bellard | qemu_get_clock(vm_clock) + (ticks_per_sec / 2));
|
390 | 29133e9a | bellard | break;
|
391 | 29133e9a | bellard | default:
|
392 | 29133e9a | bellard | DPRINTF("%s: invalid command %02x (wc 5)\n", __func__, cmd);
|
393 | 29133e9a | bellard | goto reset_flash;
|
394 | 29133e9a | bellard | } |
395 | 29133e9a | bellard | pfl->cmd = cmd; |
396 | 29133e9a | bellard | break;
|
397 | 29133e9a | bellard | case 6: |
398 | 29133e9a | bellard | switch (pfl->cmd) {
|
399 | 29133e9a | bellard | case 0x10: |
400 | 29133e9a | bellard | /* Ignore writes during chip erase */
|
401 | 29133e9a | bellard | return;
|
402 | 29133e9a | bellard | case 0x30: |
403 | 29133e9a | bellard | /* Ignore writes during sector erase */
|
404 | 29133e9a | bellard | return;
|
405 | 29133e9a | bellard | default:
|
406 | 29133e9a | bellard | /* Should never happen */
|
407 | 29133e9a | bellard | DPRINTF("%s: invalid command state %02x (wc 6)\n",
|
408 | 29133e9a | bellard | __func__, pfl->cmd); |
409 | 29133e9a | bellard | goto reset_flash;
|
410 | 29133e9a | bellard | } |
411 | 29133e9a | bellard | break;
|
412 | 29133e9a | bellard | case 7: /* Special value for CFI queries */ |
413 | 29133e9a | bellard | DPRINTF("%s: invalid write in CFI query mode\n", __func__);
|
414 | 29133e9a | bellard | goto reset_flash;
|
415 | 29133e9a | bellard | default:
|
416 | 29133e9a | bellard | /* Should never happen */
|
417 | 29133e9a | bellard | DPRINTF("%s: invalid write state (wc 7)\n", __func__);
|
418 | 29133e9a | bellard | goto reset_flash;
|
419 | 29133e9a | bellard | } |
420 | 29133e9a | bellard | pfl->wcycle++; |
421 | 29133e9a | bellard | |
422 | 29133e9a | bellard | return;
|
423 | 29133e9a | bellard | |
424 | 29133e9a | bellard | /* Reset flash */
|
425 | 29133e9a | bellard | reset_flash:
|
426 | 95d1f3ed | j_mayer | cpu_register_physical_memory(pfl->base, pfl->total_len, |
427 | 95d1f3ed | j_mayer | pfl->off | IO_MEM_ROMD | pfl->fl_mem); |
428 | 29133e9a | bellard | pfl->bypass = 0;
|
429 | 29133e9a | bellard | pfl->wcycle = 0;
|
430 | 29133e9a | bellard | pfl->cmd = 0;
|
431 | 29133e9a | bellard | return;
|
432 | 29133e9a | bellard | |
433 | 29133e9a | bellard | do_bypass:
|
434 | 29133e9a | bellard | pfl->wcycle = 2;
|
435 | 29133e9a | bellard | pfl->cmd = 0;
|
436 | 29133e9a | bellard | return;
|
437 | 29133e9a | bellard | } |
438 | 29133e9a | bellard | |
439 | 29133e9a | bellard | |
440 | 29133e9a | bellard | static uint32_t pflash_readb (void *opaque, target_phys_addr_t addr) |
441 | 29133e9a | bellard | { |
442 | 29133e9a | bellard | return pflash_read(opaque, addr, 1); |
443 | 29133e9a | bellard | } |
444 | 29133e9a | bellard | |
445 | 29133e9a | bellard | static uint32_t pflash_readw (void *opaque, target_phys_addr_t addr) |
446 | 29133e9a | bellard | { |
447 | 29133e9a | bellard | pflash_t *pfl = opaque; |
448 | 29133e9a | bellard | |
449 | 29133e9a | bellard | return pflash_read(pfl, addr, 2); |
450 | 29133e9a | bellard | } |
451 | 29133e9a | bellard | |
452 | 29133e9a | bellard | static uint32_t pflash_readl (void *opaque, target_phys_addr_t addr) |
453 | 29133e9a | bellard | { |
454 | 29133e9a | bellard | pflash_t *pfl = opaque; |
455 | 29133e9a | bellard | |
456 | 29133e9a | bellard | return pflash_read(pfl, addr, 4); |
457 | 29133e9a | bellard | } |
458 | 29133e9a | bellard | |
459 | 29133e9a | bellard | static void pflash_writeb (void *opaque, target_phys_addr_t addr, |
460 | 29133e9a | bellard | uint32_t value) |
461 | 29133e9a | bellard | { |
462 | 29133e9a | bellard | pflash_write(opaque, addr, value, 1);
|
463 | 29133e9a | bellard | } |
464 | 29133e9a | bellard | |
465 | 29133e9a | bellard | static void pflash_writew (void *opaque, target_phys_addr_t addr, |
466 | 29133e9a | bellard | uint32_t value) |
467 | 29133e9a | bellard | { |
468 | 29133e9a | bellard | pflash_t *pfl = opaque; |
469 | 29133e9a | bellard | |
470 | 29133e9a | bellard | pflash_write(pfl, addr, value, 2);
|
471 | 29133e9a | bellard | } |
472 | 29133e9a | bellard | |
473 | 29133e9a | bellard | static void pflash_writel (void *opaque, target_phys_addr_t addr, |
474 | 29133e9a | bellard | uint32_t value) |
475 | 29133e9a | bellard | { |
476 | 29133e9a | bellard | pflash_t *pfl = opaque; |
477 | 29133e9a | bellard | |
478 | 29133e9a | bellard | pflash_write(pfl, addr, value, 4);
|
479 | 29133e9a | bellard | } |
480 | 29133e9a | bellard | |
481 | 29133e9a | bellard | static CPUWriteMemoryFunc *pflash_write_ops[] = {
|
482 | 29133e9a | bellard | &pflash_writeb, |
483 | 29133e9a | bellard | &pflash_writew, |
484 | 29133e9a | bellard | &pflash_writel, |
485 | 29133e9a | bellard | }; |
486 | 29133e9a | bellard | |
487 | 29133e9a | bellard | static CPUReadMemoryFunc *pflash_read_ops[] = {
|
488 | 29133e9a | bellard | &pflash_readb, |
489 | 29133e9a | bellard | &pflash_readw, |
490 | 29133e9a | bellard | &pflash_readl, |
491 | 29133e9a | bellard | }; |
492 | 29133e9a | bellard | |
493 | 29133e9a | bellard | /* Count trailing zeroes of a 32 bits quantity */
|
494 | 29133e9a | bellard | static int ctz32 (uint32_t n) |
495 | 29133e9a | bellard | { |
496 | 29133e9a | bellard | int ret;
|
497 | 29133e9a | bellard | |
498 | 29133e9a | bellard | ret = 0;
|
499 | 29133e9a | bellard | if (!(n & 0xFFFF)) { |
500 | 29133e9a | bellard | ret += 16;
|
501 | 29133e9a | bellard | n = n >> 16;
|
502 | 29133e9a | bellard | } |
503 | 29133e9a | bellard | if (!(n & 0xFF)) { |
504 | 29133e9a | bellard | ret += 8;
|
505 | 29133e9a | bellard | n = n >> 8;
|
506 | 29133e9a | bellard | } |
507 | 29133e9a | bellard | if (!(n & 0xF)) { |
508 | 29133e9a | bellard | ret += 4;
|
509 | 29133e9a | bellard | n = n >> 4;
|
510 | 29133e9a | bellard | } |
511 | 29133e9a | bellard | if (!(n & 0x3)) { |
512 | 29133e9a | bellard | ret += 2;
|
513 | 29133e9a | bellard | n = n >> 2;
|
514 | 29133e9a | bellard | } |
515 | 29133e9a | bellard | if (!(n & 0x1)) { |
516 | 29133e9a | bellard | ret++; |
517 | 29133e9a | bellard | n = n >> 1;
|
518 | 29133e9a | bellard | } |
519 | 29133e9a | bellard | #if 0 /* This is not necessary as n is never 0 */
|
520 | 29133e9a | bellard | if (!n)
|
521 | 29133e9a | bellard | ret++;
|
522 | 29133e9a | bellard | #endif
|
523 | 29133e9a | bellard | |
524 | 29133e9a | bellard | return ret;
|
525 | 29133e9a | bellard | } |
526 | 29133e9a | bellard | |
527 | 71db710f | blueswir1 | pflash_t *pflash_register (target_phys_addr_t base, ram_addr_t off, |
528 | 29133e9a | bellard | BlockDriverState *bs, |
529 | 71db710f | blueswir1 | uint32_t sector_len, int nb_blocs, int width, |
530 | 5fafdf24 | ths | uint16_t id0, uint16_t id1, |
531 | 29133e9a | bellard | uint16_t id2, uint16_t id3) |
532 | 29133e9a | bellard | { |
533 | 29133e9a | bellard | pflash_t *pfl; |
534 | 71db710f | blueswir1 | int32_t total_len; |
535 | 29133e9a | bellard | |
536 | 29133e9a | bellard | total_len = sector_len * nb_blocs; |
537 | 29133e9a | bellard | /* XXX: to be fixed */
|
538 | 95d1f3ed | j_mayer | #if 0
|
539 | 29133e9a | bellard | if (total_len != (8 * 1024 * 1024) && total_len != (16 * 1024 * 1024) &&
|
540 | 29133e9a | bellard | total_len != (32 * 1024 * 1024) && total_len != (64 * 1024 * 1024))
|
541 | 29133e9a | bellard | return NULL;
|
542 | 95d1f3ed | j_mayer | #endif
|
543 | 29133e9a | bellard | pfl = qemu_mallocz(sizeof(pflash_t));
|
544 | 29133e9a | bellard | if (pfl == NULL) |
545 | 29133e9a | bellard | return NULL; |
546 | 29133e9a | bellard | pfl->storage = phys_ram_base + off; |
547 | 95d1f3ed | j_mayer | pfl->fl_mem = cpu_register_io_memory(0, pflash_read_ops, pflash_write_ops,
|
548 | 95d1f3ed | j_mayer | pfl); |
549 | 29133e9a | bellard | pfl->off = off; |
550 | 29133e9a | bellard | cpu_register_physical_memory(base, total_len, |
551 | 29133e9a | bellard | off | pfl->fl_mem | IO_MEM_ROMD); |
552 | 29133e9a | bellard | pfl->bs = bs; |
553 | 29133e9a | bellard | if (pfl->bs) {
|
554 | 29133e9a | bellard | /* read the initial flash content */
|
555 | 29133e9a | bellard | bdrv_read(pfl->bs, 0, pfl->storage, total_len >> 9); |
556 | 29133e9a | bellard | } |
557 | 29133e9a | bellard | #if 0 /* XXX: there should be a bit to set up read-only,
|
558 | 29133e9a | bellard | * the same way the hardware does (with WP pin).
|
559 | 29133e9a | bellard | */
|
560 | 29133e9a | bellard | pfl->ro = 1;
|
561 | 29133e9a | bellard | #else
|
562 | 29133e9a | bellard | pfl->ro = 0;
|
563 | 29133e9a | bellard | #endif
|
564 | 29133e9a | bellard | pfl->timer = qemu_new_timer(vm_clock, pflash_timer, pfl); |
565 | 29133e9a | bellard | pfl->base = base; |
566 | 29133e9a | bellard | pfl->sector_len = sector_len; |
567 | 29133e9a | bellard | pfl->total_len = total_len; |
568 | 29133e9a | bellard | pfl->width = width; |
569 | 29133e9a | bellard | pfl->wcycle = 0;
|
570 | 29133e9a | bellard | pfl->cmd = 0;
|
571 | 29133e9a | bellard | pfl->status = 0;
|
572 | 29133e9a | bellard | pfl->ident[0] = id0;
|
573 | 29133e9a | bellard | pfl->ident[1] = id1;
|
574 | 29133e9a | bellard | pfl->ident[2] = id2;
|
575 | 29133e9a | bellard | pfl->ident[3] = id3;
|
576 | 29133e9a | bellard | /* Hardcoded CFI table (mostly from SG29 Spansion flash) */
|
577 | 29133e9a | bellard | pfl->cfi_len = 0x52;
|
578 | 29133e9a | bellard | /* Standard "QRY" string */
|
579 | 29133e9a | bellard | pfl->cfi_table[0x10] = 'Q'; |
580 | 29133e9a | bellard | pfl->cfi_table[0x11] = 'R'; |
581 | 29133e9a | bellard | pfl->cfi_table[0x12] = 'Y'; |
582 | 29133e9a | bellard | /* Command set (AMD/Fujitsu) */
|
583 | 29133e9a | bellard | pfl->cfi_table[0x13] = 0x02; |
584 | 29133e9a | bellard | pfl->cfi_table[0x14] = 0x00; |
585 | 29133e9a | bellard | /* Primary extended table address (none) */
|
586 | 29133e9a | bellard | pfl->cfi_table[0x15] = 0x00; |
587 | 29133e9a | bellard | pfl->cfi_table[0x16] = 0x00; |
588 | 29133e9a | bellard | /* Alternate command set (none) */
|
589 | 29133e9a | bellard | pfl->cfi_table[0x17] = 0x00; |
590 | 29133e9a | bellard | pfl->cfi_table[0x18] = 0x00; |
591 | 29133e9a | bellard | /* Alternate extended table (none) */
|
592 | 29133e9a | bellard | pfl->cfi_table[0x19] = 0x00; |
593 | 29133e9a | bellard | pfl->cfi_table[0x1A] = 0x00; |
594 | 29133e9a | bellard | /* Vcc min */
|
595 | 29133e9a | bellard | pfl->cfi_table[0x1B] = 0x27; |
596 | 29133e9a | bellard | /* Vcc max */
|
597 | 29133e9a | bellard | pfl->cfi_table[0x1C] = 0x36; |
598 | 29133e9a | bellard | /* Vpp min (no Vpp pin) */
|
599 | 29133e9a | bellard | pfl->cfi_table[0x1D] = 0x00; |
600 | 29133e9a | bellard | /* Vpp max (no Vpp pin) */
|
601 | 29133e9a | bellard | pfl->cfi_table[0x1E] = 0x00; |
602 | 29133e9a | bellard | /* Reserved */
|
603 | 29133e9a | bellard | pfl->cfi_table[0x1F] = 0x07; |
604 | 29133e9a | bellard | /* Timeout for min size buffer write (16 ?s) */
|
605 | 29133e9a | bellard | pfl->cfi_table[0x20] = 0x04; |
606 | 29133e9a | bellard | /* Typical timeout for block erase (512 ms) */
|
607 | 29133e9a | bellard | pfl->cfi_table[0x21] = 0x09; |
608 | 29133e9a | bellard | /* Typical timeout for full chip erase (4096 ms) */
|
609 | 29133e9a | bellard | pfl->cfi_table[0x22] = 0x0C; |
610 | 29133e9a | bellard | /* Reserved */
|
611 | 29133e9a | bellard | pfl->cfi_table[0x23] = 0x01; |
612 | 29133e9a | bellard | /* Max timeout for buffer write */
|
613 | 29133e9a | bellard | pfl->cfi_table[0x24] = 0x04; |
614 | 29133e9a | bellard | /* Max timeout for block erase */
|
615 | 29133e9a | bellard | pfl->cfi_table[0x25] = 0x0A; |
616 | 29133e9a | bellard | /* Max timeout for chip erase */
|
617 | 29133e9a | bellard | pfl->cfi_table[0x26] = 0x0D; |
618 | 29133e9a | bellard | /* Device size */
|
619 | 29133e9a | bellard | pfl->cfi_table[0x27] = ctz32(total_len) + 1; |
620 | 29133e9a | bellard | /* Flash device interface (8 & 16 bits) */
|
621 | 29133e9a | bellard | pfl->cfi_table[0x28] = 0x02; |
622 | 29133e9a | bellard | pfl->cfi_table[0x29] = 0x00; |
623 | 29133e9a | bellard | /* Max number of bytes in multi-bytes write */
|
624 | 95d1f3ed | j_mayer | /* XXX: disable buffered write as it's not supported */
|
625 | 95d1f3ed | j_mayer | // pfl->cfi_table[0x2A] = 0x05;
|
626 | 95d1f3ed | j_mayer | pfl->cfi_table[0x2A] = 0x00; |
627 | 29133e9a | bellard | pfl->cfi_table[0x2B] = 0x00; |
628 | 29133e9a | bellard | /* Number of erase block regions (uniform) */
|
629 | 29133e9a | bellard | pfl->cfi_table[0x2C] = 0x01; |
630 | 29133e9a | bellard | /* Erase block region 1 */
|
631 | 29133e9a | bellard | pfl->cfi_table[0x2D] = nb_blocs - 1; |
632 | 29133e9a | bellard | pfl->cfi_table[0x2E] = (nb_blocs - 1) >> 8; |
633 | 29133e9a | bellard | pfl->cfi_table[0x2F] = sector_len >> 8; |
634 | 29133e9a | bellard | pfl->cfi_table[0x30] = sector_len >> 16; |
635 | 29133e9a | bellard | |
636 | 29133e9a | bellard | return pfl;
|
637 | 29133e9a | bellard | } |