root / hw / slavio_timer.c @ 9a87ce9b
History | View | Annotate | Download (10.5 kB)
1 | e80cfcfc | bellard | /*
|
---|---|---|---|
2 | e80cfcfc | bellard | * QEMU Sparc SLAVIO timer controller emulation
|
3 | e80cfcfc | bellard | *
|
4 | 66321a11 | bellard | * Copyright (c) 2003-2005 Fabrice Bellard
|
5 | 5fafdf24 | ths | *
|
6 | e80cfcfc | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
|
7 | e80cfcfc | bellard | * of this software and associated documentation files (the "Software"), to deal
|
8 | e80cfcfc | bellard | * in the Software without restriction, including without limitation the rights
|
9 | e80cfcfc | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
10 | e80cfcfc | bellard | * copies of the Software, and to permit persons to whom the Software is
|
11 | e80cfcfc | bellard | * furnished to do so, subject to the following conditions:
|
12 | e80cfcfc | bellard | *
|
13 | e80cfcfc | bellard | * The above copyright notice and this permission notice shall be included in
|
14 | e80cfcfc | bellard | * all copies or substantial portions of the Software.
|
15 | e80cfcfc | bellard | *
|
16 | e80cfcfc | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
17 | e80cfcfc | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
18 | e80cfcfc | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
19 | e80cfcfc | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
20 | e80cfcfc | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
21 | e80cfcfc | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
22 | e80cfcfc | bellard | * THE SOFTWARE.
|
23 | e80cfcfc | bellard | */
|
24 | 87ecb68b | pbrook | #include "hw.h" |
25 | 87ecb68b | pbrook | #include "sun4m.h" |
26 | 87ecb68b | pbrook | #include "qemu-timer.h" |
27 | e80cfcfc | bellard | |
28 | e80cfcfc | bellard | //#define DEBUG_TIMER
|
29 | e80cfcfc | bellard | |
30 | 66321a11 | bellard | #ifdef DEBUG_TIMER
|
31 | 66321a11 | bellard | #define DPRINTF(fmt, args...) \
|
32 | 66321a11 | bellard | do { printf("TIMER: " fmt , ##args); } while (0) |
33 | 66321a11 | bellard | #else
|
34 | 66321a11 | bellard | #define DPRINTF(fmt, args...)
|
35 | 66321a11 | bellard | #endif
|
36 | 66321a11 | bellard | |
37 | e80cfcfc | bellard | /*
|
38 | e80cfcfc | bellard | * Registers of hardware timer in sun4m.
|
39 | e80cfcfc | bellard | *
|
40 | e80cfcfc | bellard | * This is the timer/counter part of chip STP2001 (Slave I/O), also
|
41 | e80cfcfc | bellard | * produced as NCR89C105. See
|
42 | e80cfcfc | bellard | * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
|
43 | 5fafdf24 | ths | *
|
44 | e80cfcfc | bellard | * The 31-bit counter is incremented every 500ns by bit 9. Bits 8..0
|
45 | e80cfcfc | bellard | * are zero. Bit 31 is 1 when count has been reached.
|
46 | e80cfcfc | bellard | *
|
47 | ba3c64fb | bellard | * Per-CPU timers interrupt local CPU, system timer uses normal
|
48 | ba3c64fb | bellard | * interrupt routing.
|
49 | ba3c64fb | bellard | *
|
50 | e80cfcfc | bellard | */
|
51 | e80cfcfc | bellard | |
52 | 81732d19 | blueswir1 | #define MAX_CPUS 16 |
53 | 81732d19 | blueswir1 | |
54 | e80cfcfc | bellard | typedef struct SLAVIO_TIMERState { |
55 | d7edfd27 | blueswir1 | qemu_irq irq; |
56 | 8d05ea8a | blueswir1 | ptimer_state *timer; |
57 | 8d05ea8a | blueswir1 | uint32_t count, counthigh, reached; |
58 | 8d05ea8a | blueswir1 | uint64_t limit; |
59 | 115646b6 | blueswir1 | // processor only
|
60 | 115646b6 | blueswir1 | int running;
|
61 | 115646b6 | blueswir1 | struct SLAVIO_TIMERState *master;
|
62 | 115646b6 | blueswir1 | int slave_index;
|
63 | 115646b6 | blueswir1 | // system only
|
64 | 81732d19 | blueswir1 | struct SLAVIO_TIMERState *slave[MAX_CPUS];
|
65 | 81732d19 | blueswir1 | uint32_t slave_mode; |
66 | e80cfcfc | bellard | } SLAVIO_TIMERState; |
67 | e80cfcfc | bellard | |
68 | e80cfcfc | bellard | #define TIMER_MAXADDR 0x1f |
69 | 115646b6 | blueswir1 | #define SYS_TIMER_SIZE 0x14 |
70 | 81732d19 | blueswir1 | #define CPU_TIMER_SIZE 0x10 |
71 | e80cfcfc | bellard | |
72 | 115646b6 | blueswir1 | static int slavio_timer_is_user(SLAVIO_TIMERState *s) |
73 | 115646b6 | blueswir1 | { |
74 | 115646b6 | blueswir1 | return s->master && (s->master->slave_mode & (1 << s->slave_index)); |
75 | 115646b6 | blueswir1 | } |
76 | 115646b6 | blueswir1 | |
77 | e80cfcfc | bellard | // Update count, set irq, update expire_time
|
78 | 8d05ea8a | blueswir1 | // Convert from ptimer countdown units
|
79 | e80cfcfc | bellard | static void slavio_timer_get_out(SLAVIO_TIMERState *s) |
80 | e80cfcfc | bellard | { |
81 | 8d05ea8a | blueswir1 | uint64_t count; |
82 | e80cfcfc | bellard | |
83 | 8d05ea8a | blueswir1 | count = s->limit - (ptimer_get_count(s->timer) << 9);
|
84 | 8d05ea8a | blueswir1 | DPRINTF("get_out: limit %" PRIx64 " count %x%08x\n", s->limit, s->counthigh, |
85 | 8d05ea8a | blueswir1 | s->count); |
86 | 8d05ea8a | blueswir1 | s->count = count & 0xfffffe00;
|
87 | 8d05ea8a | blueswir1 | s->counthigh = count >> 32;
|
88 | e80cfcfc | bellard | } |
89 | e80cfcfc | bellard | |
90 | e80cfcfc | bellard | // timer callback
|
91 | e80cfcfc | bellard | static void slavio_timer_irq(void *opaque) |
92 | e80cfcfc | bellard | { |
93 | e80cfcfc | bellard | SLAVIO_TIMERState *s = opaque; |
94 | e80cfcfc | bellard | |
95 | e80cfcfc | bellard | slavio_timer_get_out(s); |
96 | 8d05ea8a | blueswir1 | DPRINTF("callback: count %x%08x\n", s->counthigh, s->count);
|
97 | 115646b6 | blueswir1 | if (!slavio_timer_is_user(s)) {
|
98 | 115646b6 | blueswir1 | s->reached = 0x80000000;
|
99 | f930d07e | blueswir1 | qemu_irq_raise(s->irq); |
100 | 115646b6 | blueswir1 | } |
101 | e80cfcfc | bellard | } |
102 | e80cfcfc | bellard | |
103 | e80cfcfc | bellard | static uint32_t slavio_timer_mem_readl(void *opaque, target_phys_addr_t addr) |
104 | e80cfcfc | bellard | { |
105 | e80cfcfc | bellard | SLAVIO_TIMERState *s = opaque; |
106 | 8d05ea8a | blueswir1 | uint32_t saddr, ret; |
107 | e80cfcfc | bellard | |
108 | e80cfcfc | bellard | saddr = (addr & TIMER_MAXADDR) >> 2;
|
109 | e80cfcfc | bellard | switch (saddr) {
|
110 | e80cfcfc | bellard | case 0: |
111 | f930d07e | blueswir1 | // read limit (system counter mode) or read most signifying
|
112 | f930d07e | blueswir1 | // part of counter (user mode)
|
113 | 115646b6 | blueswir1 | if (slavio_timer_is_user(s)) {
|
114 | 115646b6 | blueswir1 | // read user timer MSW
|
115 | 115646b6 | blueswir1 | slavio_timer_get_out(s); |
116 | 115646b6 | blueswir1 | ret = s->counthigh; |
117 | 115646b6 | blueswir1 | } else {
|
118 | 115646b6 | blueswir1 | // read limit
|
119 | f930d07e | blueswir1 | // clear irq
|
120 | d7edfd27 | blueswir1 | qemu_irq_lower(s->irq); |
121 | f930d07e | blueswir1 | s->reached = 0;
|
122 | 8d05ea8a | blueswir1 | ret = s->limit & 0x7fffffff;
|
123 | f930d07e | blueswir1 | } |
124 | 8d05ea8a | blueswir1 | break;
|
125 | e80cfcfc | bellard | case 1: |
126 | f930d07e | blueswir1 | // read counter and reached bit (system mode) or read lsbits
|
127 | f930d07e | blueswir1 | // of counter (user mode)
|
128 | f930d07e | blueswir1 | slavio_timer_get_out(s); |
129 | 115646b6 | blueswir1 | if (slavio_timer_is_user(s)) // read user timer LSW |
130 | a702b353 | bellard | ret = s->count & 0xfffffe00;
|
131 | 115646b6 | blueswir1 | else // read limit |
132 | 115646b6 | blueswir1 | ret = (s->count & 0x7ffffe00) | s->reached;
|
133 | 8d05ea8a | blueswir1 | break;
|
134 | e80cfcfc | bellard | case 3: |
135 | 115646b6 | blueswir1 | // only available in processor counter/timer
|
136 | f930d07e | blueswir1 | // read start/stop status
|
137 | 115646b6 | blueswir1 | ret = s->running; |
138 | 8d05ea8a | blueswir1 | break;
|
139 | e80cfcfc | bellard | case 4: |
140 | 115646b6 | blueswir1 | // only available in system counter
|
141 | f930d07e | blueswir1 | // read user/system mode
|
142 | 81732d19 | blueswir1 | ret = s->slave_mode; |
143 | 8d05ea8a | blueswir1 | break;
|
144 | e80cfcfc | bellard | default:
|
145 | 115646b6 | blueswir1 | DPRINTF("invalid read address " TARGET_FMT_plx "\n", addr); |
146 | 8d05ea8a | blueswir1 | ret = 0;
|
147 | 8d05ea8a | blueswir1 | break;
|
148 | e80cfcfc | bellard | } |
149 | 8d05ea8a | blueswir1 | DPRINTF("read " TARGET_FMT_plx " = %08x\n", addr, ret); |
150 | 8d05ea8a | blueswir1 | |
151 | 8d05ea8a | blueswir1 | return ret;
|
152 | e80cfcfc | bellard | } |
153 | e80cfcfc | bellard | |
154 | e80cfcfc | bellard | static void slavio_timer_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
155 | e80cfcfc | bellard | { |
156 | e80cfcfc | bellard | SLAVIO_TIMERState *s = opaque; |
157 | e80cfcfc | bellard | uint32_t saddr; |
158 | 8d05ea8a | blueswir1 | int reload = 0; |
159 | e80cfcfc | bellard | |
160 | 8d05ea8a | blueswir1 | DPRINTF("write " TARGET_FMT_plx " %08x\n", addr, val); |
161 | e80cfcfc | bellard | saddr = (addr & TIMER_MAXADDR) >> 2;
|
162 | e80cfcfc | bellard | switch (saddr) {
|
163 | e80cfcfc | bellard | case 0: |
164 | 115646b6 | blueswir1 | if (slavio_timer_is_user(s)) {
|
165 | 115646b6 | blueswir1 | // set user counter MSW, reset counter
|
166 | 81732d19 | blueswir1 | qemu_irq_lower(s->irq); |
167 | 115646b6 | blueswir1 | s->limit = 0x7ffffffffffffe00ULL;
|
168 | 115646b6 | blueswir1 | DPRINTF("processor %d user timer reset\n", s->slave_index);
|
169 | 115646b6 | blueswir1 | ptimer_set_limit(s->timer, s->limit >> 9, 1); |
170 | 115646b6 | blueswir1 | } else {
|
171 | 115646b6 | blueswir1 | // set limit, reset counter
|
172 | 115646b6 | blueswir1 | qemu_irq_lower(s->irq); |
173 | 115646b6 | blueswir1 | s->limit = val & 0x7ffffe00ULL;
|
174 | 81732d19 | blueswir1 | if (!s->limit)
|
175 | 115646b6 | blueswir1 | s->limit = 0x7ffffe00ULL;
|
176 | 81732d19 | blueswir1 | ptimer_set_limit(s->timer, s->limit >> 9, 1); |
177 | 81732d19 | blueswir1 | } |
178 | 115646b6 | blueswir1 | break;
|
179 | 115646b6 | blueswir1 | case 1: |
180 | 115646b6 | blueswir1 | if (slavio_timer_is_user(s)) {
|
181 | 115646b6 | blueswir1 | // set user counter LSW, reset counter
|
182 | 115646b6 | blueswir1 | qemu_irq_lower(s->irq); |
183 | 115646b6 | blueswir1 | s->limit = 0x7ffffffffffffe00ULL;
|
184 | 115646b6 | blueswir1 | DPRINTF("processor %d user timer reset\n", s->slave_index);
|
185 | 115646b6 | blueswir1 | ptimer_set_limit(s->timer, s->limit >> 9, 1); |
186 | 115646b6 | blueswir1 | } else
|
187 | 115646b6 | blueswir1 | DPRINTF("not user timer\n");
|
188 | 115646b6 | blueswir1 | break;
|
189 | e80cfcfc | bellard | case 2: |
190 | f930d07e | blueswir1 | // set limit without resetting counter
|
191 | 8d05ea8a | blueswir1 | s->limit = val & 0x7ffffe00ULL;
|
192 | 8d05ea8a | blueswir1 | if (!s->limit)
|
193 | 8d05ea8a | blueswir1 | s->limit = 0x7ffffe00ULL;
|
194 | 8d05ea8a | blueswir1 | ptimer_set_limit(s->timer, s->limit >> 9, reload);
|
195 | f930d07e | blueswir1 | break;
|
196 | e80cfcfc | bellard | case 3: |
197 | 115646b6 | blueswir1 | if (slavio_timer_is_user(s)) {
|
198 | 115646b6 | blueswir1 | // start/stop user counter
|
199 | 115646b6 | blueswir1 | if ((val & 1) && !s->running) { |
200 | 115646b6 | blueswir1 | DPRINTF("processor %d user timer started\n", s->slave_index);
|
201 | 8d05ea8a | blueswir1 | ptimer_run(s->timer, 0);
|
202 | 115646b6 | blueswir1 | s->running = 1;
|
203 | 115646b6 | blueswir1 | } else if (!(val & 1) && s->running) { |
204 | 115646b6 | blueswir1 | DPRINTF("processor %d user timer stopped\n", s->slave_index);
|
205 | 115646b6 | blueswir1 | ptimer_stop(s->timer); |
206 | 115646b6 | blueswir1 | s->running = 0;
|
207 | f930d07e | blueswir1 | } |
208 | f930d07e | blueswir1 | } |
209 | f930d07e | blueswir1 | break;
|
210 | e80cfcfc | bellard | case 4: |
211 | 115646b6 | blueswir1 | if (s->master == NULL) { |
212 | 81732d19 | blueswir1 | unsigned int i; |
213 | 81732d19 | blueswir1 | |
214 | 81732d19 | blueswir1 | for (i = 0; i < MAX_CPUS; i++) { |
215 | 81732d19 | blueswir1 | if (val & (1 << i)) { |
216 | 81732d19 | blueswir1 | qemu_irq_lower(s->slave[i]->irq); |
217 | 81732d19 | blueswir1 | s->slave[i]->limit = -1ULL;
|
218 | 81732d19 | blueswir1 | } |
219 | 115646b6 | blueswir1 | if ((val & (1 << i)) != (s->slave_mode & (1 << i))) { |
220 | 115646b6 | blueswir1 | ptimer_stop(s->slave[i]->timer); |
221 | 115646b6 | blueswir1 | ptimer_set_limit(s->slave[i]->timer, s->slave[i]->limit >> 9, 1); |
222 | 115646b6 | blueswir1 | DPRINTF("processor %d timer changed\n", s->slave[i]->slave_index);
|
223 | 115646b6 | blueswir1 | ptimer_run(s->slave[i]->timer, 0);
|
224 | 115646b6 | blueswir1 | } |
225 | 81732d19 | blueswir1 | } |
226 | 81732d19 | blueswir1 | s->slave_mode = val & ((1 << MAX_CPUS) - 1); |
227 | 115646b6 | blueswir1 | } else
|
228 | 115646b6 | blueswir1 | DPRINTF("not system timer\n");
|
229 | f930d07e | blueswir1 | break;
|
230 | e80cfcfc | bellard | default:
|
231 | 115646b6 | blueswir1 | DPRINTF("invalid write address " TARGET_FMT_plx "\n", addr); |
232 | f930d07e | blueswir1 | break;
|
233 | e80cfcfc | bellard | } |
234 | e80cfcfc | bellard | } |
235 | e80cfcfc | bellard | |
236 | e80cfcfc | bellard | static CPUReadMemoryFunc *slavio_timer_mem_read[3] = { |
237 | e80cfcfc | bellard | slavio_timer_mem_readl, |
238 | e80cfcfc | bellard | slavio_timer_mem_readl, |
239 | e80cfcfc | bellard | slavio_timer_mem_readl, |
240 | e80cfcfc | bellard | }; |
241 | e80cfcfc | bellard | |
242 | e80cfcfc | bellard | static CPUWriteMemoryFunc *slavio_timer_mem_write[3] = { |
243 | e80cfcfc | bellard | slavio_timer_mem_writel, |
244 | e80cfcfc | bellard | slavio_timer_mem_writel, |
245 | e80cfcfc | bellard | slavio_timer_mem_writel, |
246 | e80cfcfc | bellard | }; |
247 | e80cfcfc | bellard | |
248 | e80cfcfc | bellard | static void slavio_timer_save(QEMUFile *f, void *opaque) |
249 | e80cfcfc | bellard | { |
250 | e80cfcfc | bellard | SLAVIO_TIMERState *s = opaque; |
251 | e80cfcfc | bellard | |
252 | 8d05ea8a | blueswir1 | qemu_put_be64s(f, &s->limit); |
253 | e80cfcfc | bellard | qemu_put_be32s(f, &s->count); |
254 | e80cfcfc | bellard | qemu_put_be32s(f, &s->counthigh); |
255 | d7edfd27 | blueswir1 | qemu_put_be32(f, 0); // Was irq |
256 | e80cfcfc | bellard | qemu_put_be32s(f, &s->reached); |
257 | 115646b6 | blueswir1 | qemu_put_be32s(f, &s->running); |
258 | 115646b6 | blueswir1 | qemu_put_be32s(f, 0); // Was mode |
259 | 8d05ea8a | blueswir1 | qemu_put_ptimer(f, s->timer); |
260 | e80cfcfc | bellard | } |
261 | e80cfcfc | bellard | |
262 | e80cfcfc | bellard | static int slavio_timer_load(QEMUFile *f, void *opaque, int version_id) |
263 | e80cfcfc | bellard | { |
264 | e80cfcfc | bellard | SLAVIO_TIMERState *s = opaque; |
265 | d7edfd27 | blueswir1 | uint32_t tmp; |
266 | 3b46e624 | ths | |
267 | 8d05ea8a | blueswir1 | if (version_id != 2) |
268 | e80cfcfc | bellard | return -EINVAL;
|
269 | e80cfcfc | bellard | |
270 | 8d05ea8a | blueswir1 | qemu_get_be64s(f, &s->limit); |
271 | e80cfcfc | bellard | qemu_get_be32s(f, &s->count); |
272 | e80cfcfc | bellard | qemu_get_be32s(f, &s->counthigh); |
273 | d7edfd27 | blueswir1 | qemu_get_be32s(f, &tmp); // Was irq
|
274 | e80cfcfc | bellard | qemu_get_be32s(f, &s->reached); |
275 | 115646b6 | blueswir1 | qemu_get_be32s(f, &s->running); |
276 | 115646b6 | blueswir1 | qemu_get_be32s(f, &tmp); // Was mode
|
277 | 8d05ea8a | blueswir1 | qemu_get_ptimer(f, s->timer); |
278 | 8d05ea8a | blueswir1 | |
279 | e80cfcfc | bellard | return 0; |
280 | e80cfcfc | bellard | } |
281 | e80cfcfc | bellard | |
282 | e80cfcfc | bellard | static void slavio_timer_reset(void *opaque) |
283 | e80cfcfc | bellard | { |
284 | e80cfcfc | bellard | SLAVIO_TIMERState *s = opaque; |
285 | e80cfcfc | bellard | |
286 | 115646b6 | blueswir1 | if (slavio_timer_is_user(s))
|
287 | 115646b6 | blueswir1 | s->limit = 0x7ffffffffffffe00ULL;
|
288 | 115646b6 | blueswir1 | else
|
289 | 115646b6 | blueswir1 | s->limit = 0x7ffffe00ULL;
|
290 | e80cfcfc | bellard | s->count = 0;
|
291 | e80cfcfc | bellard | s->reached = 0;
|
292 | 8d05ea8a | blueswir1 | ptimer_set_limit(s->timer, s->limit >> 9, 1); |
293 | 8d05ea8a | blueswir1 | ptimer_run(s->timer, 0);
|
294 | 115646b6 | blueswir1 | s->running = 1;
|
295 | d7edfd27 | blueswir1 | qemu_irq_lower(s->irq); |
296 | e80cfcfc | bellard | } |
297 | e80cfcfc | bellard | |
298 | 81732d19 | blueswir1 | static SLAVIO_TIMERState *slavio_timer_init(target_phys_addr_t addr,
|
299 | 115646b6 | blueswir1 | qemu_irq irq, |
300 | 115646b6 | blueswir1 | SLAVIO_TIMERState *master, |
301 | 115646b6 | blueswir1 | int slave_index)
|
302 | e80cfcfc | bellard | { |
303 | e80cfcfc | bellard | int slavio_timer_io_memory;
|
304 | e80cfcfc | bellard | SLAVIO_TIMERState *s; |
305 | 8d05ea8a | blueswir1 | QEMUBH *bh; |
306 | e80cfcfc | bellard | |
307 | e80cfcfc | bellard | s = qemu_mallocz(sizeof(SLAVIO_TIMERState));
|
308 | e80cfcfc | bellard | if (!s)
|
309 | 81732d19 | blueswir1 | return s;
|
310 | e80cfcfc | bellard | s->irq = irq; |
311 | 115646b6 | blueswir1 | s->master = master; |
312 | 115646b6 | blueswir1 | s->slave_index = slave_index; |
313 | 8d05ea8a | blueswir1 | bh = qemu_bh_new(slavio_timer_irq, s); |
314 | 8d05ea8a | blueswir1 | s->timer = ptimer_init(bh); |
315 | 8d05ea8a | blueswir1 | ptimer_set_period(s->timer, 500ULL);
|
316 | e80cfcfc | bellard | |
317 | e80cfcfc | bellard | slavio_timer_io_memory = cpu_register_io_memory(0, slavio_timer_mem_read,
|
318 | f930d07e | blueswir1 | slavio_timer_mem_write, s); |
319 | 115646b6 | blueswir1 | if (master)
|
320 | 81732d19 | blueswir1 | cpu_register_physical_memory(addr, CPU_TIMER_SIZE, slavio_timer_io_memory); |
321 | 81732d19 | blueswir1 | else
|
322 | 115646b6 | blueswir1 | cpu_register_physical_memory(addr, SYS_TIMER_SIZE, slavio_timer_io_memory); |
323 | 8d05ea8a | blueswir1 | register_savevm("slavio_timer", addr, 2, slavio_timer_save, slavio_timer_load, s); |
324 | e80cfcfc | bellard | qemu_register_reset(slavio_timer_reset, s); |
325 | e80cfcfc | bellard | slavio_timer_reset(s); |
326 | 81732d19 | blueswir1 | |
327 | 81732d19 | blueswir1 | return s;
|
328 | 81732d19 | blueswir1 | } |
329 | 81732d19 | blueswir1 | |
330 | 81732d19 | blueswir1 | void slavio_timer_init_all(target_phys_addr_t base, qemu_irq master_irq,
|
331 | 81732d19 | blueswir1 | qemu_irq *cpu_irqs) |
332 | 81732d19 | blueswir1 | { |
333 | 81732d19 | blueswir1 | SLAVIO_TIMERState *master; |
334 | 81732d19 | blueswir1 | unsigned int i; |
335 | 81732d19 | blueswir1 | |
336 | 115646b6 | blueswir1 | master = slavio_timer_init(base + 0x10000ULL, master_irq, NULL, 0); |
337 | 81732d19 | blueswir1 | |
338 | 81732d19 | blueswir1 | for (i = 0; i < MAX_CPUS; i++) { |
339 | 81732d19 | blueswir1 | master->slave[i] = slavio_timer_init(base + (target_phys_addr_t) |
340 | 81732d19 | blueswir1 | (i * TARGET_PAGE_SIZE), |
341 | 115646b6 | blueswir1 | cpu_irqs[i], master, i); |
342 | 81732d19 | blueswir1 | } |
343 | e80cfcfc | bellard | } |