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1 | 69b91039 | bellard | /*
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2 | 69b91039 | bellard | * QEMU PCI bus manager
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3 | 69b91039 | bellard | *
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4 | 69b91039 | bellard | * Copyright (c) 2004 Fabrice Bellard
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5 | 69b91039 | bellard | *
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6 | 69b91039 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 69b91039 | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 69b91039 | bellard | * in the Software without restriction, including without limitation the rights
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9 | 69b91039 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 69b91039 | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 69b91039 | bellard | * furnished to do so, subject to the following conditions:
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12 | 69b91039 | bellard | *
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13 | 69b91039 | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 69b91039 | bellard | * all copies or substantial portions of the Software.
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15 | 69b91039 | bellard | *
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16 | 69b91039 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 69b91039 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 69b91039 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 69b91039 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 69b91039 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 69b91039 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 69b91039 | bellard | * THE SOFTWARE.
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23 | 69b91039 | bellard | */
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24 | 69b91039 | bellard | #include "vl.h" |
25 | 69b91039 | bellard | |
26 | 69b91039 | bellard | //#define DEBUG_PCI
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27 | 69b91039 | bellard | |
28 | 30468f78 | bellard | struct PCIBus {
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29 | 30468f78 | bellard | int bus_num;
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30 | 30468f78 | bellard | int devfn_min;
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31 | 502a5395 | pbrook | pci_set_irq_fn set_irq; |
32 | 30468f78 | bellard | uint32_t config_reg; /* XXX: suppress */
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33 | 384d8876 | bellard | /* low level pic */
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34 | 384d8876 | bellard | SetIRQFunc *low_set_irq; |
35 | 384d8876 | bellard | void *irq_opaque;
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36 | 30468f78 | bellard | PCIDevice *devices[256];
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37 | 30468f78 | bellard | }; |
38 | 69b91039 | bellard | |
39 | 1941d19c | bellard | static void pci_update_mappings(PCIDevice *d); |
40 | 1941d19c | bellard | |
41 | 69b91039 | bellard | target_phys_addr_t pci_mem_base; |
42 | 0ac32c83 | bellard | static int pci_irq_index; |
43 | 30468f78 | bellard | static PCIBus *first_bus;
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44 | 30468f78 | bellard | |
45 | 502a5395 | pbrook | PCIBus *pci_register_bus(pci_set_irq_fn set_irq, void *pic, int devfn_min) |
46 | 30468f78 | bellard | { |
47 | 30468f78 | bellard | PCIBus *bus; |
48 | 30468f78 | bellard | bus = qemu_mallocz(sizeof(PCIBus));
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49 | 502a5395 | pbrook | bus->set_irq = set_irq; |
50 | 502a5395 | pbrook | bus->irq_opaque = pic; |
51 | 502a5395 | pbrook | bus->devfn_min = devfn_min; |
52 | 30468f78 | bellard | first_bus = bus; |
53 | 30468f78 | bellard | return bus;
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54 | 30468f78 | bellard | } |
55 | 69b91039 | bellard | |
56 | 502a5395 | pbrook | int pci_bus_num(PCIBus *s)
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57 | 502a5395 | pbrook | { |
58 | 502a5395 | pbrook | return s->bus_num;
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59 | 502a5395 | pbrook | } |
60 | 502a5395 | pbrook | |
61 | 1941d19c | bellard | void pci_device_save(PCIDevice *s, QEMUFile *f)
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62 | 30ca2aab | bellard | { |
63 | 1941d19c | bellard | qemu_put_be32(f, 1); /* PCI device version */ |
64 | 30ca2aab | bellard | qemu_put_buffer(f, s->config, 256);
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65 | 30ca2aab | bellard | } |
66 | 30ca2aab | bellard | |
67 | 1941d19c | bellard | int pci_device_load(PCIDevice *s, QEMUFile *f)
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68 | 30ca2aab | bellard | { |
69 | 1941d19c | bellard | uint32_t version_id; |
70 | 1941d19c | bellard | version_id = qemu_get_be32(f); |
71 | 30ca2aab | bellard | if (version_id != 1) |
72 | 30ca2aab | bellard | return -EINVAL;
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73 | 30ca2aab | bellard | qemu_get_buffer(f, s->config, 256);
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74 | 1941d19c | bellard | pci_update_mappings(s); |
75 | 30ca2aab | bellard | return 0; |
76 | 30ca2aab | bellard | } |
77 | 30ca2aab | bellard | |
78 | 69b91039 | bellard | /* -1 for devfn means auto assign */
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79 | 30468f78 | bellard | PCIDevice *pci_register_device(PCIBus *bus, const char *name, |
80 | 30468f78 | bellard | int instance_size, int devfn, |
81 | 69b91039 | bellard | PCIConfigReadFunc *config_read, |
82 | 69b91039 | bellard | PCIConfigWriteFunc *config_write) |
83 | 69b91039 | bellard | { |
84 | 30468f78 | bellard | PCIDevice *pci_dev; |
85 | 69b91039 | bellard | |
86 | 0ac32c83 | bellard | if (pci_irq_index >= PCI_DEVICES_MAX)
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87 | 0ac32c83 | bellard | return NULL; |
88 | 0ac32c83 | bellard | |
89 | 69b91039 | bellard | if (devfn < 0) { |
90 | 30468f78 | bellard | for(devfn = bus->devfn_min ; devfn < 256; devfn += 8) { |
91 | 30468f78 | bellard | if (!bus->devices[devfn])
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92 | 69b91039 | bellard | goto found;
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93 | 69b91039 | bellard | } |
94 | 69b91039 | bellard | return NULL; |
95 | 69b91039 | bellard | found: ;
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96 | 69b91039 | bellard | } |
97 | 69b91039 | bellard | pci_dev = qemu_mallocz(instance_size); |
98 | 69b91039 | bellard | if (!pci_dev)
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99 | 69b91039 | bellard | return NULL; |
100 | 30468f78 | bellard | pci_dev->bus = bus; |
101 | 69b91039 | bellard | pci_dev->devfn = devfn; |
102 | 69b91039 | bellard | pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
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103 | 0ac32c83 | bellard | |
104 | 0ac32c83 | bellard | if (!config_read)
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105 | 0ac32c83 | bellard | config_read = pci_default_read_config; |
106 | 0ac32c83 | bellard | if (!config_write)
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107 | 0ac32c83 | bellard | config_write = pci_default_write_config; |
108 | 69b91039 | bellard | pci_dev->config_read = config_read; |
109 | 69b91039 | bellard | pci_dev->config_write = config_write; |
110 | 0ac32c83 | bellard | pci_dev->irq_index = pci_irq_index++; |
111 | 30468f78 | bellard | bus->devices[devfn] = pci_dev; |
112 | 69b91039 | bellard | return pci_dev;
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113 | 69b91039 | bellard | } |
114 | 69b91039 | bellard | |
115 | 69b91039 | bellard | void pci_register_io_region(PCIDevice *pci_dev, int region_num, |
116 | 69b91039 | bellard | uint32_t size, int type,
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117 | 69b91039 | bellard | PCIMapIORegionFunc *map_func) |
118 | 69b91039 | bellard | { |
119 | 69b91039 | bellard | PCIIORegion *r; |
120 | d7ce493a | pbrook | uint32_t addr; |
121 | 69b91039 | bellard | |
122 | 8a8696a3 | bellard | if ((unsigned int)region_num >= PCI_NUM_REGIONS) |
123 | 69b91039 | bellard | return;
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124 | 69b91039 | bellard | r = &pci_dev->io_regions[region_num]; |
125 | 69b91039 | bellard | r->addr = -1;
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126 | 69b91039 | bellard | r->size = size; |
127 | 69b91039 | bellard | r->type = type; |
128 | 69b91039 | bellard | r->map_func = map_func; |
129 | d7ce493a | pbrook | if (region_num == PCI_ROM_SLOT) {
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130 | d7ce493a | pbrook | addr = 0x30;
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131 | d7ce493a | pbrook | } else {
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132 | d7ce493a | pbrook | addr = 0x10 + region_num * 4; |
133 | d7ce493a | pbrook | } |
134 | d7ce493a | pbrook | *(uint32_t *)(pci_dev->config + addr) = cpu_to_le32(type); |
135 | 69b91039 | bellard | } |
136 | 69b91039 | bellard | |
137 | 502a5395 | pbrook | target_phys_addr_t pci_to_cpu_addr(target_phys_addr_t addr) |
138 | 69b91039 | bellard | { |
139 | 502a5395 | pbrook | return addr + pci_mem_base;
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140 | 69b91039 | bellard | } |
141 | 69b91039 | bellard | |
142 | 0ac32c83 | bellard | static void pci_update_mappings(PCIDevice *d) |
143 | 0ac32c83 | bellard | { |
144 | 0ac32c83 | bellard | PCIIORegion *r; |
145 | 0ac32c83 | bellard | int cmd, i;
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146 | 8a8696a3 | bellard | uint32_t last_addr, new_addr, config_ofs; |
147 | 0ac32c83 | bellard | |
148 | 0ac32c83 | bellard | cmd = le16_to_cpu(*(uint16_t *)(d->config + PCI_COMMAND)); |
149 | 8a8696a3 | bellard | for(i = 0; i < PCI_NUM_REGIONS; i++) { |
150 | 0ac32c83 | bellard | r = &d->io_regions[i]; |
151 | 8a8696a3 | bellard | if (i == PCI_ROM_SLOT) {
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152 | 8a8696a3 | bellard | config_ofs = 0x30;
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153 | 8a8696a3 | bellard | } else {
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154 | 8a8696a3 | bellard | config_ofs = 0x10 + i * 4; |
155 | 8a8696a3 | bellard | } |
156 | 0ac32c83 | bellard | if (r->size != 0) { |
157 | 0ac32c83 | bellard | if (r->type & PCI_ADDRESS_SPACE_IO) {
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158 | 0ac32c83 | bellard | if (cmd & PCI_COMMAND_IO) {
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159 | 0ac32c83 | bellard | new_addr = le32_to_cpu(*(uint32_t *)(d->config + |
160 | 8a8696a3 | bellard | config_ofs)); |
161 | 0ac32c83 | bellard | new_addr = new_addr & ~(r->size - 1);
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162 | 0ac32c83 | bellard | last_addr = new_addr + r->size - 1;
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163 | 0ac32c83 | bellard | /* NOTE: we have only 64K ioports on PC */
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164 | 0ac32c83 | bellard | if (last_addr <= new_addr || new_addr == 0 || |
165 | 0ac32c83 | bellard | last_addr >= 0x10000) {
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166 | 0ac32c83 | bellard | new_addr = -1;
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167 | 0ac32c83 | bellard | } |
168 | 0ac32c83 | bellard | } else {
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169 | 0ac32c83 | bellard | new_addr = -1;
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170 | 0ac32c83 | bellard | } |
171 | 0ac32c83 | bellard | } else {
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172 | 0ac32c83 | bellard | if (cmd & PCI_COMMAND_MEMORY) {
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173 | 0ac32c83 | bellard | new_addr = le32_to_cpu(*(uint32_t *)(d->config + |
174 | 8a8696a3 | bellard | config_ofs)); |
175 | 8a8696a3 | bellard | /* the ROM slot has a specific enable bit */
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176 | 8a8696a3 | bellard | if (i == PCI_ROM_SLOT && !(new_addr & 1)) |
177 | 8a8696a3 | bellard | goto no_mem_map;
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178 | 0ac32c83 | bellard | new_addr = new_addr & ~(r->size - 1);
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179 | 0ac32c83 | bellard | last_addr = new_addr + r->size - 1;
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180 | 0ac32c83 | bellard | /* NOTE: we do not support wrapping */
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181 | 0ac32c83 | bellard | /* XXX: as we cannot support really dynamic
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182 | 0ac32c83 | bellard | mappings, we handle specific values as invalid
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183 | 0ac32c83 | bellard | mappings. */
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184 | 0ac32c83 | bellard | if (last_addr <= new_addr || new_addr == 0 || |
185 | 0ac32c83 | bellard | last_addr == -1) {
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186 | 0ac32c83 | bellard | new_addr = -1;
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187 | 0ac32c83 | bellard | } |
188 | 0ac32c83 | bellard | } else {
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189 | 8a8696a3 | bellard | no_mem_map:
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190 | 0ac32c83 | bellard | new_addr = -1;
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191 | 0ac32c83 | bellard | } |
192 | 0ac32c83 | bellard | } |
193 | 0ac32c83 | bellard | /* now do the real mapping */
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194 | 0ac32c83 | bellard | if (new_addr != r->addr) {
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195 | 0ac32c83 | bellard | if (r->addr != -1) { |
196 | 0ac32c83 | bellard | if (r->type & PCI_ADDRESS_SPACE_IO) {
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197 | 0ac32c83 | bellard | int class;
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198 | 0ac32c83 | bellard | /* NOTE: specific hack for IDE in PC case:
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199 | 0ac32c83 | bellard | only one byte must be mapped. */
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200 | 0ac32c83 | bellard | class = d->config[0x0a] | (d->config[0x0b] << 8); |
201 | 0ac32c83 | bellard | if (class == 0x0101 && r->size == 4) { |
202 | 0ac32c83 | bellard | isa_unassign_ioport(r->addr + 2, 1); |
203 | 0ac32c83 | bellard | } else {
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204 | 0ac32c83 | bellard | isa_unassign_ioport(r->addr, r->size); |
205 | 0ac32c83 | bellard | } |
206 | 0ac32c83 | bellard | } else {
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207 | 502a5395 | pbrook | cpu_register_physical_memory(pci_to_cpu_addr(r->addr), |
208 | 0ac32c83 | bellard | r->size, |
209 | 0ac32c83 | bellard | IO_MEM_UNASSIGNED); |
210 | 0ac32c83 | bellard | } |
211 | 0ac32c83 | bellard | } |
212 | 0ac32c83 | bellard | r->addr = new_addr; |
213 | 0ac32c83 | bellard | if (r->addr != -1) { |
214 | 0ac32c83 | bellard | r->map_func(d, i, r->addr, r->size, r->type); |
215 | 0ac32c83 | bellard | } |
216 | 0ac32c83 | bellard | } |
217 | 0ac32c83 | bellard | } |
218 | 0ac32c83 | bellard | } |
219 | 0ac32c83 | bellard | } |
220 | 0ac32c83 | bellard | |
221 | 0ac32c83 | bellard | uint32_t pci_default_read_config(PCIDevice *d, |
222 | 0ac32c83 | bellard | uint32_t address, int len)
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223 | 69b91039 | bellard | { |
224 | 0ac32c83 | bellard | uint32_t val; |
225 | 0ac32c83 | bellard | switch(len) {
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226 | 0ac32c83 | bellard | case 1: |
227 | 0ac32c83 | bellard | val = d->config[address]; |
228 | 0ac32c83 | bellard | break;
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229 | 0ac32c83 | bellard | case 2: |
230 | 0ac32c83 | bellard | val = le16_to_cpu(*(uint16_t *)(d->config + address)); |
231 | 0ac32c83 | bellard | break;
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232 | 0ac32c83 | bellard | default:
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233 | 0ac32c83 | bellard | case 4: |
234 | 0ac32c83 | bellard | val = le32_to_cpu(*(uint32_t *)(d->config + address)); |
235 | 0ac32c83 | bellard | break;
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236 | 0ac32c83 | bellard | } |
237 | 0ac32c83 | bellard | return val;
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238 | 0ac32c83 | bellard | } |
239 | 0ac32c83 | bellard | |
240 | 0ac32c83 | bellard | void pci_default_write_config(PCIDevice *d,
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241 | 0ac32c83 | bellard | uint32_t address, uint32_t val, int len)
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242 | 0ac32c83 | bellard | { |
243 | 0ac32c83 | bellard | int can_write, i;
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244 | 7bf5be70 | bellard | uint32_t end, addr; |
245 | 0ac32c83 | bellard | |
246 | 8a8696a3 | bellard | if (len == 4 && ((address >= 0x10 && address < 0x10 + 4 * 6) || |
247 | 8a8696a3 | bellard | (address >= 0x30 && address < 0x34))) { |
248 | 0ac32c83 | bellard | PCIIORegion *r; |
249 | 0ac32c83 | bellard | int reg;
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250 | 0ac32c83 | bellard | |
251 | 8a8696a3 | bellard | if ( address >= 0x30 ) { |
252 | 8a8696a3 | bellard | reg = PCI_ROM_SLOT; |
253 | 8a8696a3 | bellard | }else{
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254 | 8a8696a3 | bellard | reg = (address - 0x10) >> 2; |
255 | 8a8696a3 | bellard | } |
256 | 0ac32c83 | bellard | r = &d->io_regions[reg]; |
257 | 0ac32c83 | bellard | if (r->size == 0) |
258 | 0ac32c83 | bellard | goto default_config;
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259 | 0ac32c83 | bellard | /* compute the stored value */
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260 | 8a8696a3 | bellard | if (reg == PCI_ROM_SLOT) {
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261 | 8a8696a3 | bellard | /* keep ROM enable bit */
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262 | 8a8696a3 | bellard | val &= (~(r->size - 1)) | 1; |
263 | 8a8696a3 | bellard | } else {
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264 | 8a8696a3 | bellard | val &= ~(r->size - 1);
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265 | 8a8696a3 | bellard | val |= r->type; |
266 | 8a8696a3 | bellard | } |
267 | 8a8696a3 | bellard | *(uint32_t *)(d->config + address) = cpu_to_le32(val); |
268 | 0ac32c83 | bellard | pci_update_mappings(d); |
269 | 69b91039 | bellard | return;
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270 | 0ac32c83 | bellard | } |
271 | 0ac32c83 | bellard | default_config:
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272 | 0ac32c83 | bellard | /* not efficient, but simple */
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273 | 7bf5be70 | bellard | addr = address; |
274 | 0ac32c83 | bellard | for(i = 0; i < len; i++) { |
275 | 0ac32c83 | bellard | /* default read/write accesses */
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276 | 1f62d938 | bellard | switch(d->config[0x0e]) { |
277 | 0ac32c83 | bellard | case 0x00: |
278 | 1f62d938 | bellard | case 0x80: |
279 | 1f62d938 | bellard | switch(addr) {
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280 | 1f62d938 | bellard | case 0x00: |
281 | 1f62d938 | bellard | case 0x01: |
282 | 1f62d938 | bellard | case 0x02: |
283 | 1f62d938 | bellard | case 0x03: |
284 | 1f62d938 | bellard | case 0x08: |
285 | 1f62d938 | bellard | case 0x09: |
286 | 1f62d938 | bellard | case 0x0a: |
287 | 1f62d938 | bellard | case 0x0b: |
288 | 1f62d938 | bellard | case 0x0e: |
289 | 1f62d938 | bellard | case 0x10 ... 0x27: /* base */ |
290 | 1f62d938 | bellard | case 0x30 ... 0x33: /* rom */ |
291 | 1f62d938 | bellard | case 0x3d: |
292 | 1f62d938 | bellard | can_write = 0;
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293 | 1f62d938 | bellard | break;
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294 | 1f62d938 | bellard | default:
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295 | 1f62d938 | bellard | can_write = 1;
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296 | 1f62d938 | bellard | break;
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297 | 1f62d938 | bellard | } |
298 | 0ac32c83 | bellard | break;
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299 | 0ac32c83 | bellard | default:
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300 | 1f62d938 | bellard | case 0x01: |
301 | 1f62d938 | bellard | switch(addr) {
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302 | 1f62d938 | bellard | case 0x00: |
303 | 1f62d938 | bellard | case 0x01: |
304 | 1f62d938 | bellard | case 0x02: |
305 | 1f62d938 | bellard | case 0x03: |
306 | 1f62d938 | bellard | case 0x08: |
307 | 1f62d938 | bellard | case 0x09: |
308 | 1f62d938 | bellard | case 0x0a: |
309 | 1f62d938 | bellard | case 0x0b: |
310 | 1f62d938 | bellard | case 0x0e: |
311 | 1f62d938 | bellard | case 0x38 ... 0x3b: /* rom */ |
312 | 1f62d938 | bellard | case 0x3d: |
313 | 1f62d938 | bellard | can_write = 0;
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314 | 1f62d938 | bellard | break;
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315 | 1f62d938 | bellard | default:
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316 | 1f62d938 | bellard | can_write = 1;
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317 | 1f62d938 | bellard | break;
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318 | 1f62d938 | bellard | } |
319 | 0ac32c83 | bellard | break;
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320 | 0ac32c83 | bellard | } |
321 | 0ac32c83 | bellard | if (can_write) {
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322 | 7bf5be70 | bellard | d->config[addr] = val; |
323 | 0ac32c83 | bellard | } |
324 | 7bf5be70 | bellard | addr++; |
325 | 0ac32c83 | bellard | val >>= 8;
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326 | 0ac32c83 | bellard | } |
327 | 0ac32c83 | bellard | |
328 | 0ac32c83 | bellard | end = address + len; |
329 | 0ac32c83 | bellard | if (end > PCI_COMMAND && address < (PCI_COMMAND + 2)) { |
330 | 0ac32c83 | bellard | /* if the command register is modified, we must modify the mappings */
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331 | 0ac32c83 | bellard | pci_update_mappings(d); |
332 | 69b91039 | bellard | } |
333 | 69b91039 | bellard | } |
334 | 69b91039 | bellard | |
335 | 502a5395 | pbrook | void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len) |
336 | 69b91039 | bellard | { |
337 | 30468f78 | bellard | PCIBus *s = opaque; |
338 | 30468f78 | bellard | PCIDevice *pci_dev; |
339 | 30468f78 | bellard | int config_addr, bus_num;
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340 | 69b91039 | bellard | |
341 | 69b91039 | bellard | #if defined(DEBUG_PCI) && 0 |
342 | 69b91039 | bellard | printf("pci_data_write: addr=%08x val=%08x len=%d\n",
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343 | 502a5395 | pbrook | addr, val, len); |
344 | 69b91039 | bellard | #endif
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345 | 502a5395 | pbrook | bus_num = (addr >> 16) & 0xff; |
346 | 30468f78 | bellard | if (bus_num != 0) |
347 | 69b91039 | bellard | return;
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348 | 502a5395 | pbrook | pci_dev = s->devices[(addr >> 8) & 0xff]; |
349 | 69b91039 | bellard | if (!pci_dev)
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350 | 69b91039 | bellard | return;
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351 | 502a5395 | pbrook | config_addr = addr & 0xff;
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352 | 69b91039 | bellard | #if defined(DEBUG_PCI)
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353 | 69b91039 | bellard | printf("pci_config_write: %s: addr=%02x val=%08x len=%d\n",
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354 | 69b91039 | bellard | pci_dev->name, config_addr, val, len); |
355 | 69b91039 | bellard | #endif
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356 | 0ac32c83 | bellard | pci_dev->config_write(pci_dev, config_addr, val, len); |
357 | 69b91039 | bellard | } |
358 | 69b91039 | bellard | |
359 | 502a5395 | pbrook | uint32_t pci_data_read(void *opaque, uint32_t addr, int len) |
360 | 69b91039 | bellard | { |
361 | 30468f78 | bellard | PCIBus *s = opaque; |
362 | 30468f78 | bellard | PCIDevice *pci_dev; |
363 | 30468f78 | bellard | int config_addr, bus_num;
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364 | 69b91039 | bellard | uint32_t val; |
365 | 69b91039 | bellard | |
366 | 502a5395 | pbrook | bus_num = (addr >> 16) & 0xff; |
367 | 30468f78 | bellard | if (bus_num != 0) |
368 | 69b91039 | bellard | goto fail;
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369 | 502a5395 | pbrook | pci_dev = s->devices[(addr >> 8) & 0xff]; |
370 | 69b91039 | bellard | if (!pci_dev) {
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371 | 69b91039 | bellard | fail:
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372 | 63ce9e0a | bellard | switch(len) {
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373 | 63ce9e0a | bellard | case 1: |
374 | 63ce9e0a | bellard | val = 0xff;
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375 | 63ce9e0a | bellard | break;
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376 | 63ce9e0a | bellard | case 2: |
377 | 63ce9e0a | bellard | val = 0xffff;
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378 | 63ce9e0a | bellard | break;
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379 | 63ce9e0a | bellard | default:
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380 | 63ce9e0a | bellard | case 4: |
381 | 63ce9e0a | bellard | val = 0xffffffff;
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382 | 63ce9e0a | bellard | break;
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383 | 63ce9e0a | bellard | } |
384 | 69b91039 | bellard | goto the_end;
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385 | 69b91039 | bellard | } |
386 | 502a5395 | pbrook | config_addr = addr & 0xff;
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387 | 69b91039 | bellard | val = pci_dev->config_read(pci_dev, config_addr, len); |
388 | 69b91039 | bellard | #if defined(DEBUG_PCI)
|
389 | 69b91039 | bellard | printf("pci_config_read: %s: addr=%02x val=%08x len=%d\n",
|
390 | 69b91039 | bellard | pci_dev->name, config_addr, val, len); |
391 | 69b91039 | bellard | #endif
|
392 | 69b91039 | bellard | the_end:
|
393 | 69b91039 | bellard | #if defined(DEBUG_PCI) && 0 |
394 | 69b91039 | bellard | printf("pci_data_read: addr=%08x val=%08x len=%d\n",
|
395 | 502a5395 | pbrook | addr, val, len); |
396 | 69b91039 | bellard | #endif
|
397 | 69b91039 | bellard | return val;
|
398 | 69b91039 | bellard | } |
399 | 69b91039 | bellard | |
400 | 502a5395 | pbrook | /***********************************************************/
|
401 | 502a5395 | pbrook | /* generic PCI irq support */
|
402 | 30468f78 | bellard | |
403 | 502a5395 | pbrook | /* 0 <= irq_num <= 3. level must be 0 or 1 */
|
404 | 502a5395 | pbrook | void pci_set_irq(PCIDevice *pci_dev, int irq_num, int level) |
405 | 69b91039 | bellard | { |
406 | 502a5395 | pbrook | PCIBus *bus = pci_dev->bus; |
407 | 502a5395 | pbrook | bus->set_irq(pci_dev, bus->irq_opaque, irq_num, level); |
408 | 69b91039 | bellard | } |
409 | 69b91039 | bellard | |
410 | 502a5395 | pbrook | /***********************************************************/
|
411 | 502a5395 | pbrook | /* monitor info on PCI */
|
412 | 0ac32c83 | bellard | |
413 | 6650ee6d | pbrook | typedef struct { |
414 | 6650ee6d | pbrook | uint16_t class; |
415 | 6650ee6d | pbrook | const char *desc; |
416 | 6650ee6d | pbrook | } pci_class_desc; |
417 | 6650ee6d | pbrook | |
418 | 6650ee6d | pbrook | static pci_class_desc pci_class_descriptions[] =
|
419 | 6650ee6d | pbrook | { |
420 | 4ca9c76f | pbrook | { 0x0100, "SCSI controller"}, |
421 | 6650ee6d | pbrook | { 0x0101, "IDE controller"}, |
422 | 6650ee6d | pbrook | { 0x0200, "Ethernet controller"}, |
423 | 6650ee6d | pbrook | { 0x0300, "VGA controller"}, |
424 | 6650ee6d | pbrook | { 0x0600, "Host bridge"}, |
425 | 6650ee6d | pbrook | { 0x0601, "ISA bridge"}, |
426 | 6650ee6d | pbrook | { 0x0604, "PCI bridge"}, |
427 | 6650ee6d | pbrook | { 0x0c03, "USB controller"}, |
428 | 6650ee6d | pbrook | { 0, NULL} |
429 | 6650ee6d | pbrook | }; |
430 | 6650ee6d | pbrook | |
431 | 502a5395 | pbrook | static void pci_info_device(PCIDevice *d) |
432 | 30468f78 | bellard | { |
433 | 502a5395 | pbrook | int i, class;
|
434 | 502a5395 | pbrook | PCIIORegion *r; |
435 | 6650ee6d | pbrook | pci_class_desc *desc; |
436 | 30468f78 | bellard | |
437 | 502a5395 | pbrook | term_printf(" Bus %2d, device %3d, function %d:\n",
|
438 | 502a5395 | pbrook | d->bus->bus_num, d->devfn >> 3, d->devfn & 7); |
439 | 502a5395 | pbrook | class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE))); |
440 | 502a5395 | pbrook | term_printf(" ");
|
441 | 6650ee6d | pbrook | desc = pci_class_descriptions; |
442 | 6650ee6d | pbrook | while (desc->desc && class != desc->class)
|
443 | 6650ee6d | pbrook | desc++; |
444 | 6650ee6d | pbrook | if (desc->desc) {
|
445 | 6650ee6d | pbrook | term_printf("%s", desc->desc);
|
446 | 6650ee6d | pbrook | } else {
|
447 | 502a5395 | pbrook | term_printf("Class %04x", class);
|
448 | 72cc6cfe | bellard | } |
449 | 502a5395 | pbrook | term_printf(": PCI device %04x:%04x\n",
|
450 | 502a5395 | pbrook | le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))), |
451 | 502a5395 | pbrook | le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID)))); |
452 | 30468f78 | bellard | |
453 | 502a5395 | pbrook | if (d->config[PCI_INTERRUPT_PIN] != 0) { |
454 | 502a5395 | pbrook | term_printf(" IRQ %d.\n", d->config[PCI_INTERRUPT_LINE]);
|
455 | 30468f78 | bellard | } |
456 | 502a5395 | pbrook | for(i = 0;i < PCI_NUM_REGIONS; i++) { |
457 | 502a5395 | pbrook | r = &d->io_regions[i]; |
458 | 502a5395 | pbrook | if (r->size != 0) { |
459 | 502a5395 | pbrook | term_printf(" BAR%d: ", i);
|
460 | 502a5395 | pbrook | if (r->type & PCI_ADDRESS_SPACE_IO) {
|
461 | 502a5395 | pbrook | term_printf("I/O at 0x%04x [0x%04x].\n",
|
462 | 502a5395 | pbrook | r->addr, r->addr + r->size - 1);
|
463 | 502a5395 | pbrook | } else {
|
464 | 502a5395 | pbrook | term_printf("32 bit memory at 0x%08x [0x%08x].\n",
|
465 | 502a5395 | pbrook | r->addr, r->addr + r->size - 1);
|
466 | 502a5395 | pbrook | } |
467 | 502a5395 | pbrook | } |
468 | 77d4bc34 | bellard | } |
469 | 384d8876 | bellard | } |
470 | 384d8876 | bellard | |
471 | 502a5395 | pbrook | void pci_for_each_device(void (*fn)(PCIDevice *d)) |
472 | 384d8876 | bellard | { |
473 | 502a5395 | pbrook | PCIBus *bus = first_bus; |
474 | 384d8876 | bellard | PCIDevice *d; |
475 | 502a5395 | pbrook | int devfn;
|
476 | 384d8876 | bellard | |
477 | 502a5395 | pbrook | if (bus) {
|
478 | 502a5395 | pbrook | for(devfn = 0; devfn < 256; devfn++) { |
479 | 502a5395 | pbrook | d = bus->devices[devfn]; |
480 | 502a5395 | pbrook | if (d)
|
481 | 502a5395 | pbrook | fn(d); |
482 | 502a5395 | pbrook | } |
483 | f2aa58c6 | bellard | } |
484 | f2aa58c6 | bellard | } |
485 | f2aa58c6 | bellard | |
486 | 502a5395 | pbrook | void pci_info(void) |
487 | f2aa58c6 | bellard | { |
488 | 502a5395 | pbrook | pci_for_each_device(pci_info_device); |
489 | 77d4bc34 | bellard | } |
490 | a41b2ff2 | pbrook | |
491 | a41b2ff2 | pbrook | /* Initialize a PCI NIC. */
|
492 | a41b2ff2 | pbrook | void pci_nic_init(PCIBus *bus, NICInfo *nd)
|
493 | a41b2ff2 | pbrook | { |
494 | a41b2ff2 | pbrook | if (strcmp(nd->model, "ne2k_pci") == 0) { |
495 | a41b2ff2 | pbrook | pci_ne2000_init(bus, nd); |
496 | a41b2ff2 | pbrook | } else if (strcmp(nd->model, "rtl8139") == 0) { |
497 | a41b2ff2 | pbrook | pci_rtl8139_init(bus, nd); |
498 | e3c2613f | bellard | } else if (strcmp(nd->model, "pcnet") == 0) { |
499 | e3c2613f | bellard | pci_pcnet_init(bus, nd); |
500 | a41b2ff2 | pbrook | } else {
|
501 | a41b2ff2 | pbrook | fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd->model);
|
502 | a41b2ff2 | pbrook | exit (1);
|
503 | a41b2ff2 | pbrook | } |
504 | a41b2ff2 | pbrook | } |