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1 | 420557e8 | bellard | /*
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2 | 420557e8 | bellard | * QEMU SPARC iommu emulation
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3 | 420557e8 | bellard | *
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4 | 66321a11 | bellard | * Copyright (c) 2003-2005 Fabrice Bellard
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5 | 5fafdf24 | ths | *
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6 | 420557e8 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 420557e8 | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 420557e8 | bellard | * in the Software without restriction, including without limitation the rights
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9 | 420557e8 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 420557e8 | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 420557e8 | bellard | * furnished to do so, subject to the following conditions:
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12 | 420557e8 | bellard | *
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13 | 420557e8 | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 420557e8 | bellard | * all copies or substantial portions of the Software.
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15 | 420557e8 | bellard | *
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16 | 420557e8 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 420557e8 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 420557e8 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 420557e8 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 420557e8 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 420557e8 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 420557e8 | bellard | * THE SOFTWARE.
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23 | 420557e8 | bellard | */
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24 | 5f750b2e | Blue Swirl | |
25 | 87ecb68b | pbrook | #include "sun4m.h" |
26 | 5f750b2e | Blue Swirl | #include "sysbus.h" |
27 | 420557e8 | bellard | |
28 | 420557e8 | bellard | /* debug iommu */
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29 | 420557e8 | bellard | //#define DEBUG_IOMMU
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30 | 420557e8 | bellard | |
31 | 66321a11 | bellard | #ifdef DEBUG_IOMMU
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32 | 001faf32 | Blue Swirl | #define DPRINTF(fmt, ...) \
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33 | 001faf32 | Blue Swirl | do { printf("IOMMU: " fmt , ## __VA_ARGS__); } while (0) |
34 | 66321a11 | bellard | #else
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35 | 001faf32 | Blue Swirl | #define DPRINTF(fmt, ...)
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36 | 66321a11 | bellard | #endif
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37 | 420557e8 | bellard | |
38 | e5e38121 | blueswir1 | #define IOMMU_NREGS (4*4096/4) |
39 | 4e3b1ea1 | bellard | #define IOMMU_CTRL (0x0000 >> 2) |
40 | 420557e8 | bellard | #define IOMMU_CTRL_IMPL 0xf0000000 /* Implementation */ |
41 | 420557e8 | bellard | #define IOMMU_CTRL_VERS 0x0f000000 /* Version */ |
42 | 420557e8 | bellard | #define IOMMU_CTRL_RNGE 0x0000001c /* Mapping RANGE */ |
43 | 420557e8 | bellard | #define IOMMU_RNGE_16MB 0x00000000 /* 0xff000000 -> 0xffffffff */ |
44 | 420557e8 | bellard | #define IOMMU_RNGE_32MB 0x00000004 /* 0xfe000000 -> 0xffffffff */ |
45 | 420557e8 | bellard | #define IOMMU_RNGE_64MB 0x00000008 /* 0xfc000000 -> 0xffffffff */ |
46 | 420557e8 | bellard | #define IOMMU_RNGE_128MB 0x0000000c /* 0xf8000000 -> 0xffffffff */ |
47 | 420557e8 | bellard | #define IOMMU_RNGE_256MB 0x00000010 /* 0xf0000000 -> 0xffffffff */ |
48 | 420557e8 | bellard | #define IOMMU_RNGE_512MB 0x00000014 /* 0xe0000000 -> 0xffffffff */ |
49 | 420557e8 | bellard | #define IOMMU_RNGE_1GB 0x00000018 /* 0xc0000000 -> 0xffffffff */ |
50 | 420557e8 | bellard | #define IOMMU_RNGE_2GB 0x0000001c /* 0x80000000 -> 0xffffffff */ |
51 | 420557e8 | bellard | #define IOMMU_CTRL_ENAB 0x00000001 /* IOMMU Enable */ |
52 | 4e3b1ea1 | bellard | #define IOMMU_CTRL_MASK 0x0000001d |
53 | 4e3b1ea1 | bellard | |
54 | 4e3b1ea1 | bellard | #define IOMMU_BASE (0x0004 >> 2) |
55 | 4e3b1ea1 | bellard | #define IOMMU_BASE_MASK 0x07fffc00 |
56 | 4e3b1ea1 | bellard | |
57 | 4e3b1ea1 | bellard | #define IOMMU_TLBFLUSH (0x0014 >> 2) |
58 | 4e3b1ea1 | bellard | #define IOMMU_TLBFLUSH_MASK 0xffffffff |
59 | 4e3b1ea1 | bellard | |
60 | 4e3b1ea1 | bellard | #define IOMMU_PGFLUSH (0x0018 >> 2) |
61 | 4e3b1ea1 | bellard | #define IOMMU_PGFLUSH_MASK 0xffffffff |
62 | 4e3b1ea1 | bellard | |
63 | 225d4be7 | blueswir1 | #define IOMMU_AFSR (0x1000 >> 2) |
64 | 225d4be7 | blueswir1 | #define IOMMU_AFSR_ERR 0x80000000 /* LE, TO, or BE asserted */ |
65 | 5ad6bb97 | blueswir1 | #define IOMMU_AFSR_LE 0x40000000 /* SBUS reports error after |
66 | 5ad6bb97 | blueswir1 | transaction */
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67 | 5ad6bb97 | blueswir1 | #define IOMMU_AFSR_TO 0x20000000 /* Write access took more than |
68 | 5ad6bb97 | blueswir1 | 12.8 us. */
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69 | 5ad6bb97 | blueswir1 | #define IOMMU_AFSR_BE 0x10000000 /* Write access received error |
70 | 5ad6bb97 | blueswir1 | acknowledge */
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71 | 225d4be7 | blueswir1 | #define IOMMU_AFSR_SIZE 0x0e000000 /* Size of transaction causing error */ |
72 | 225d4be7 | blueswir1 | #define IOMMU_AFSR_S 0x01000000 /* Sparc was in supervisor mode */ |
73 | 5ad6bb97 | blueswir1 | #define IOMMU_AFSR_RESV 0x00800000 /* Reserved, forced to 0x8 by |
74 | 5ad6bb97 | blueswir1 | hardware */
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75 | 225d4be7 | blueswir1 | #define IOMMU_AFSR_ME 0x00080000 /* Multiple errors occurred */ |
76 | 225d4be7 | blueswir1 | #define IOMMU_AFSR_RD 0x00040000 /* A read operation was in progress */ |
77 | 225d4be7 | blueswir1 | #define IOMMU_AFSR_FAV 0x00020000 /* IOMMU afar has valid contents */ |
78 | c52428fc | blueswir1 | #define IOMMU_AFSR_MASK 0xff0fffff |
79 | 225d4be7 | blueswir1 | |
80 | 225d4be7 | blueswir1 | #define IOMMU_AFAR (0x1004 >> 2) |
81 | 225d4be7 | blueswir1 | |
82 | 7b169687 | blueswir1 | #define IOMMU_AER (0x1008 >> 2) /* Arbiter Enable Register */ |
83 | 7b169687 | blueswir1 | #define IOMMU_AER_EN_P0_ARB 0x00000001 /* MBus master 0x8 (Always 1) */ |
84 | 7b169687 | blueswir1 | #define IOMMU_AER_EN_P1_ARB 0x00000002 /* MBus master 0x9 */ |
85 | 7b169687 | blueswir1 | #define IOMMU_AER_EN_P2_ARB 0x00000004 /* MBus master 0xa */ |
86 | 7b169687 | blueswir1 | #define IOMMU_AER_EN_P3_ARB 0x00000008 /* MBus master 0xb */ |
87 | 7b169687 | blueswir1 | #define IOMMU_AER_EN_0 0x00010000 /* SBus slot 0 */ |
88 | 7b169687 | blueswir1 | #define IOMMU_AER_EN_1 0x00020000 /* SBus slot 1 */ |
89 | 7b169687 | blueswir1 | #define IOMMU_AER_EN_2 0x00040000 /* SBus slot 2 */ |
90 | 7b169687 | blueswir1 | #define IOMMU_AER_EN_3 0x00080000 /* SBus slot 3 */ |
91 | 7b169687 | blueswir1 | #define IOMMU_AER_EN_F 0x00100000 /* SBus on-board */ |
92 | 7b169687 | blueswir1 | #define IOMMU_AER_SBW 0x80000000 /* S-to-M asynchronous writes */ |
93 | 7b169687 | blueswir1 | #define IOMMU_AER_MASK 0x801f000f |
94 | 7b169687 | blueswir1 | |
95 | 4e3b1ea1 | bellard | #define IOMMU_SBCFG0 (0x1010 >> 2) /* SBUS configration per-slot */ |
96 | 4e3b1ea1 | bellard | #define IOMMU_SBCFG1 (0x1014 >> 2) /* SBUS configration per-slot */ |
97 | 4e3b1ea1 | bellard | #define IOMMU_SBCFG2 (0x1018 >> 2) /* SBUS configration per-slot */ |
98 | 4e3b1ea1 | bellard | #define IOMMU_SBCFG3 (0x101c >> 2) /* SBUS configration per-slot */ |
99 | 5ad6bb97 | blueswir1 | #define IOMMU_SBCFG_SAB30 0x00010000 /* Phys-address bit 30 when |
100 | 5ad6bb97 | blueswir1 | bypass enabled */
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101 | 4e3b1ea1 | bellard | #define IOMMU_SBCFG_BA16 0x00000004 /* Slave supports 16 byte bursts */ |
102 | 4e3b1ea1 | bellard | #define IOMMU_SBCFG_BA8 0x00000002 /* Slave supports 8 byte bursts */ |
103 | 4e3b1ea1 | bellard | #define IOMMU_SBCFG_BYPASS 0x00000001 /* Bypass IOMMU, treat all addresses |
104 | f930d07e | blueswir1 | produced by this device as pure
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105 | 4e3b1ea1 | bellard | physical. */
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106 | 4e3b1ea1 | bellard | #define IOMMU_SBCFG_MASK 0x00010003 |
107 | 4e3b1ea1 | bellard | |
108 | 4e3b1ea1 | bellard | #define IOMMU_ARBEN (0x2000 >> 2) /* SBUS arbitration enable */ |
109 | 4e3b1ea1 | bellard | #define IOMMU_ARBEN_MASK 0x001f0000 |
110 | 4e3b1ea1 | bellard | #define IOMMU_MID 0x00000008 |
111 | 420557e8 | bellard | |
112 | e5e38121 | blueswir1 | #define IOMMU_MASK_ID (0x3018 >> 2) /* Mask ID */ |
113 | e5e38121 | blueswir1 | #define IOMMU_MASK_ID_MASK 0x00ffffff |
114 | e5e38121 | blueswir1 | |
115 | e5e38121 | blueswir1 | #define IOMMU_MSII_MASK 0x26000000 /* microSPARC II mask number */ |
116 | e5e38121 | blueswir1 | #define IOMMU_TS_MASK 0x23000000 /* turboSPARC mask number */ |
117 | e5e38121 | blueswir1 | |
118 | 420557e8 | bellard | /* The format of an iopte in the page tables */
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119 | 498fbd8a | blueswir1 | #define IOPTE_PAGE 0xffffff00 /* Physical page number (PA[35:12]) */ |
120 | 5ad6bb97 | blueswir1 | #define IOPTE_CACHE 0x00000080 /* Cached (in vme IOCACHE or |
121 | 5ad6bb97 | blueswir1 | Viking/MXCC) */
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122 | 420557e8 | bellard | #define IOPTE_WRITE 0x00000004 /* Writeable */ |
123 | 420557e8 | bellard | #define IOPTE_VALID 0x00000002 /* IOPTE is valid */ |
124 | 420557e8 | bellard | #define IOPTE_WAZ 0x00000001 /* Write as zeros */ |
125 | 420557e8 | bellard | |
126 | 8b0de438 | blueswir1 | #define IOMMU_PAGE_SHIFT 12 |
127 | 8b0de438 | blueswir1 | #define IOMMU_PAGE_SIZE (1 << IOMMU_PAGE_SHIFT) |
128 | 8b0de438 | blueswir1 | #define IOMMU_PAGE_MASK ~(IOMMU_PAGE_SIZE - 1) |
129 | 420557e8 | bellard | |
130 | 420557e8 | bellard | typedef struct IOMMUState { |
131 | 5f750b2e | Blue Swirl | SysBusDevice busdev; |
132 | 66321a11 | bellard | uint32_t regs[IOMMU_NREGS]; |
133 | c227f099 | Anthony Liguori | target_phys_addr_t iostart; |
134 | 7fbfb139 | blueswir1 | uint32_t version; |
135 | ff403da6 | blueswir1 | qemu_irq irq; |
136 | 420557e8 | bellard | } IOMMUState; |
137 | 420557e8 | bellard | |
138 | c227f099 | Anthony Liguori | static uint32_t iommu_mem_readl(void *opaque, target_phys_addr_t addr) |
139 | 420557e8 | bellard | { |
140 | 420557e8 | bellard | IOMMUState *s = opaque; |
141 | c227f099 | Anthony Liguori | target_phys_addr_t saddr; |
142 | ff403da6 | blueswir1 | uint32_t ret; |
143 | 420557e8 | bellard | |
144 | 8da3ff18 | pbrook | saddr = addr >> 2;
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145 | 420557e8 | bellard | switch (saddr) {
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146 | 420557e8 | bellard | default:
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147 | ff403da6 | blueswir1 | ret = s->regs[saddr]; |
148 | ff403da6 | blueswir1 | break;
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149 | ff403da6 | blueswir1 | case IOMMU_AFAR:
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150 | ff403da6 | blueswir1 | case IOMMU_AFSR:
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151 | ff403da6 | blueswir1 | ret = s->regs[saddr]; |
152 | ff403da6 | blueswir1 | qemu_irq_lower(s->irq); |
153 | f930d07e | blueswir1 | break;
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154 | 420557e8 | bellard | } |
155 | ff403da6 | blueswir1 | DPRINTF("read reg[%d] = %x\n", (int)saddr, ret); |
156 | ff403da6 | blueswir1 | return ret;
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157 | 420557e8 | bellard | } |
158 | 420557e8 | bellard | |
159 | c227f099 | Anthony Liguori | static void iommu_mem_writel(void *opaque, target_phys_addr_t addr, |
160 | 5ad6bb97 | blueswir1 | uint32_t val) |
161 | 420557e8 | bellard | { |
162 | 420557e8 | bellard | IOMMUState *s = opaque; |
163 | c227f099 | Anthony Liguori | target_phys_addr_t saddr; |
164 | 420557e8 | bellard | |
165 | 8da3ff18 | pbrook | saddr = addr >> 2;
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166 | 981a2e99 | blueswir1 | DPRINTF("write reg[%d] = %x\n", (int)saddr, val); |
167 | 420557e8 | bellard | switch (saddr) {
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168 | 4e3b1ea1 | bellard | case IOMMU_CTRL:
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169 | f930d07e | blueswir1 | switch (val & IOMMU_CTRL_RNGE) {
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170 | f930d07e | blueswir1 | case IOMMU_RNGE_16MB:
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171 | f930d07e | blueswir1 | s->iostart = 0xffffffffff000000ULL;
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172 | f930d07e | blueswir1 | break;
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173 | f930d07e | blueswir1 | case IOMMU_RNGE_32MB:
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174 | f930d07e | blueswir1 | s->iostart = 0xfffffffffe000000ULL;
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175 | f930d07e | blueswir1 | break;
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176 | f930d07e | blueswir1 | case IOMMU_RNGE_64MB:
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177 | f930d07e | blueswir1 | s->iostart = 0xfffffffffc000000ULL;
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178 | f930d07e | blueswir1 | break;
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179 | f930d07e | blueswir1 | case IOMMU_RNGE_128MB:
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180 | f930d07e | blueswir1 | s->iostart = 0xfffffffff8000000ULL;
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181 | f930d07e | blueswir1 | break;
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182 | f930d07e | blueswir1 | case IOMMU_RNGE_256MB:
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183 | f930d07e | blueswir1 | s->iostart = 0xfffffffff0000000ULL;
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184 | f930d07e | blueswir1 | break;
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185 | f930d07e | blueswir1 | case IOMMU_RNGE_512MB:
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186 | f930d07e | blueswir1 | s->iostart = 0xffffffffe0000000ULL;
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187 | f930d07e | blueswir1 | break;
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188 | f930d07e | blueswir1 | case IOMMU_RNGE_1GB:
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189 | f930d07e | blueswir1 | s->iostart = 0xffffffffc0000000ULL;
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190 | f930d07e | blueswir1 | break;
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191 | f930d07e | blueswir1 | default:
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192 | f930d07e | blueswir1 | case IOMMU_RNGE_2GB:
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193 | f930d07e | blueswir1 | s->iostart = 0xffffffff80000000ULL;
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194 | f930d07e | blueswir1 | break;
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195 | f930d07e | blueswir1 | } |
196 | f930d07e | blueswir1 | DPRINTF("iostart = " TARGET_FMT_plx "\n", s->iostart); |
197 | 7fbfb139 | blueswir1 | s->regs[saddr] = ((val & IOMMU_CTRL_MASK) | s->version); |
198 | f930d07e | blueswir1 | break;
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199 | 4e3b1ea1 | bellard | case IOMMU_BASE:
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200 | f930d07e | blueswir1 | s->regs[saddr] = val & IOMMU_BASE_MASK; |
201 | f930d07e | blueswir1 | break;
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202 | 4e3b1ea1 | bellard | case IOMMU_TLBFLUSH:
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203 | f930d07e | blueswir1 | DPRINTF("tlb flush %x\n", val);
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204 | f930d07e | blueswir1 | s->regs[saddr] = val & IOMMU_TLBFLUSH_MASK; |
205 | f930d07e | blueswir1 | break;
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206 | 4e3b1ea1 | bellard | case IOMMU_PGFLUSH:
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207 | f930d07e | blueswir1 | DPRINTF("page flush %x\n", val);
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208 | f930d07e | blueswir1 | s->regs[saddr] = val & IOMMU_PGFLUSH_MASK; |
209 | f930d07e | blueswir1 | break;
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210 | ff403da6 | blueswir1 | case IOMMU_AFAR:
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211 | ff403da6 | blueswir1 | s->regs[saddr] = val; |
212 | ff403da6 | blueswir1 | qemu_irq_lower(s->irq); |
213 | ff403da6 | blueswir1 | break;
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214 | 7b169687 | blueswir1 | case IOMMU_AER:
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215 | 7b169687 | blueswir1 | s->regs[saddr] = (val & IOMMU_AER_MASK) | IOMMU_AER_EN_P0_ARB; |
216 | 7b169687 | blueswir1 | break;
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217 | c52428fc | blueswir1 | case IOMMU_AFSR:
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218 | c52428fc | blueswir1 | s->regs[saddr] = (val & IOMMU_AFSR_MASK) | IOMMU_AFSR_RESV; |
219 | ff403da6 | blueswir1 | qemu_irq_lower(s->irq); |
220 | c52428fc | blueswir1 | break;
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221 | 4e3b1ea1 | bellard | case IOMMU_SBCFG0:
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222 | 4e3b1ea1 | bellard | case IOMMU_SBCFG1:
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223 | 4e3b1ea1 | bellard | case IOMMU_SBCFG2:
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224 | 4e3b1ea1 | bellard | case IOMMU_SBCFG3:
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225 | f930d07e | blueswir1 | s->regs[saddr] = val & IOMMU_SBCFG_MASK; |
226 | f930d07e | blueswir1 | break;
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227 | 4e3b1ea1 | bellard | case IOMMU_ARBEN:
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228 | 4e3b1ea1 | bellard | // XXX implement SBus probing: fault when reading unmapped
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229 | 4e3b1ea1 | bellard | // addresses, fault cause and address stored to MMU/IOMMU
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230 | f930d07e | blueswir1 | s->regs[saddr] = (val & IOMMU_ARBEN_MASK) | IOMMU_MID; |
231 | f930d07e | blueswir1 | break;
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232 | e5e38121 | blueswir1 | case IOMMU_MASK_ID:
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233 | e5e38121 | blueswir1 | s->regs[saddr] |= val & IOMMU_MASK_ID_MASK; |
234 | e5e38121 | blueswir1 | break;
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235 | 420557e8 | bellard | default:
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236 | f930d07e | blueswir1 | s->regs[saddr] = val; |
237 | f930d07e | blueswir1 | break;
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238 | 420557e8 | bellard | } |
239 | 420557e8 | bellard | } |
240 | 420557e8 | bellard | |
241 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const iommu_mem_read[3] = { |
242 | 7c560456 | blueswir1 | NULL,
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243 | 7c560456 | blueswir1 | NULL,
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244 | 7c560456 | blueswir1 | iommu_mem_readl, |
245 | 420557e8 | bellard | }; |
246 | 420557e8 | bellard | |
247 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const iommu_mem_write[3] = { |
248 | 7c560456 | blueswir1 | NULL,
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249 | 7c560456 | blueswir1 | NULL,
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250 | 7c560456 | blueswir1 | iommu_mem_writel, |
251 | 420557e8 | bellard | }; |
252 | 420557e8 | bellard | |
253 | c227f099 | Anthony Liguori | static uint32_t iommu_page_get_flags(IOMMUState *s, target_phys_addr_t addr)
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254 | 420557e8 | bellard | { |
255 | 5e3b100b | blueswir1 | uint32_t ret; |
256 | c227f099 | Anthony Liguori | target_phys_addr_t iopte; |
257 | 981a2e99 | blueswir1 | #ifdef DEBUG_IOMMU
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258 | c227f099 | Anthony Liguori | target_phys_addr_t pa = addr; |
259 | 981a2e99 | blueswir1 | #endif
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260 | 420557e8 | bellard | |
261 | 981a2e99 | blueswir1 | iopte = s->regs[IOMMU_BASE] << 4;
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262 | 66321a11 | bellard | addr &= ~s->iostart; |
263 | 8b0de438 | blueswir1 | iopte += (addr >> (IOMMU_PAGE_SHIFT - 2)) & ~3; |
264 | 5e3b100b | blueswir1 | cpu_physical_memory_read(iopte, (uint8_t *)&ret, 4);
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265 | 748e4993 | blueswir1 | tswap32s(&ret); |
266 | 5e3b100b | blueswir1 | DPRINTF("get flags addr " TARGET_FMT_plx " => pte " TARGET_FMT_plx |
267 | 5e3b100b | blueswir1 | ", *pte = %x\n", pa, iopte, ret);
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268 | 981a2e99 | blueswir1 | |
269 | 981a2e99 | blueswir1 | return ret;
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270 | a917d384 | pbrook | } |
271 | a917d384 | pbrook | |
272 | c227f099 | Anthony Liguori | static target_phys_addr_t iommu_translate_pa(target_phys_addr_t addr,
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273 | 5dcb6b91 | blueswir1 | uint32_t pte) |
274 | a917d384 | pbrook | { |
275 | a917d384 | pbrook | uint32_t tmppte; |
276 | c227f099 | Anthony Liguori | target_phys_addr_t pa; |
277 | 5dcb6b91 | blueswir1 | |
278 | 5dcb6b91 | blueswir1 | tmppte = pte; |
279 | 8b0de438 | blueswir1 | pa = ((pte & IOPTE_PAGE) << 4) + (addr & ~IOMMU_PAGE_MASK);
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280 | 5dcb6b91 | blueswir1 | DPRINTF("xlate dva " TARGET_FMT_plx " => pa " TARGET_FMT_plx |
281 | 5dcb6b91 | blueswir1 | " (iopte = %x)\n", addr, pa, tmppte);
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282 | a917d384 | pbrook | |
283 | 66321a11 | bellard | return pa;
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284 | 420557e8 | bellard | } |
285 | 420557e8 | bellard | |
286 | c227f099 | Anthony Liguori | static void iommu_bad_addr(IOMMUState *s, target_phys_addr_t addr, |
287 | 5ad6bb97 | blueswir1 | int is_write)
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288 | 225d4be7 | blueswir1 | { |
289 | 225d4be7 | blueswir1 | DPRINTF("bad addr " TARGET_FMT_plx "\n", addr); |
290 | 5ad6bb97 | blueswir1 | s->regs[IOMMU_AFSR] = IOMMU_AFSR_ERR | IOMMU_AFSR_LE | IOMMU_AFSR_RESV | |
291 | 225d4be7 | blueswir1 | IOMMU_AFSR_FAV; |
292 | 225d4be7 | blueswir1 | if (!is_write)
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293 | 225d4be7 | blueswir1 | s->regs[IOMMU_AFSR] |= IOMMU_AFSR_RD; |
294 | 225d4be7 | blueswir1 | s->regs[IOMMU_AFAR] = addr; |
295 | ff403da6 | blueswir1 | qemu_irq_raise(s->irq); |
296 | 225d4be7 | blueswir1 | } |
297 | 225d4be7 | blueswir1 | |
298 | c227f099 | Anthony Liguori | void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr, |
299 | 67e999be | bellard | uint8_t *buf, int len, int is_write) |
300 | a917d384 | pbrook | { |
301 | 5dcb6b91 | blueswir1 | int l;
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302 | 5dcb6b91 | blueswir1 | uint32_t flags; |
303 | c227f099 | Anthony Liguori | target_phys_addr_t page, phys_addr; |
304 | a917d384 | pbrook | |
305 | a917d384 | pbrook | while (len > 0) { |
306 | 8b0de438 | blueswir1 | page = addr & IOMMU_PAGE_MASK; |
307 | 8b0de438 | blueswir1 | l = (page + IOMMU_PAGE_SIZE) - addr; |
308 | a917d384 | pbrook | if (l > len)
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309 | a917d384 | pbrook | l = len; |
310 | a917d384 | pbrook | flags = iommu_page_get_flags(opaque, page); |
311 | 225d4be7 | blueswir1 | if (!(flags & IOPTE_VALID)) {
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312 | 225d4be7 | blueswir1 | iommu_bad_addr(opaque, page, is_write); |
313 | a917d384 | pbrook | return;
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314 | 225d4be7 | blueswir1 | } |
315 | 22548760 | blueswir1 | phys_addr = iommu_translate_pa(addr, flags); |
316 | a917d384 | pbrook | if (is_write) {
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317 | 225d4be7 | blueswir1 | if (!(flags & IOPTE_WRITE)) {
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318 | 225d4be7 | blueswir1 | iommu_bad_addr(opaque, page, is_write); |
319 | a917d384 | pbrook | return;
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320 | 225d4be7 | blueswir1 | } |
321 | a5cdf952 | blueswir1 | cpu_physical_memory_write(phys_addr, buf, l); |
322 | a917d384 | pbrook | } else {
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323 | a5cdf952 | blueswir1 | cpu_physical_memory_read(phys_addr, buf, l); |
324 | a917d384 | pbrook | } |
325 | a917d384 | pbrook | len -= l; |
326 | a917d384 | pbrook | buf += l; |
327 | a917d384 | pbrook | addr += l; |
328 | a917d384 | pbrook | } |
329 | a917d384 | pbrook | } |
330 | a917d384 | pbrook | |
331 | db3c9e08 | Blue Swirl | static const VMStateDescription vmstate_iommu = { |
332 | db3c9e08 | Blue Swirl | .name ="iommu",
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333 | db3c9e08 | Blue Swirl | .version_id = 2,
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334 | db3c9e08 | Blue Swirl | .minimum_version_id = 2,
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335 | db3c9e08 | Blue Swirl | .minimum_version_id_old = 2,
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336 | db3c9e08 | Blue Swirl | .fields = (VMStateField []) { |
337 | db3c9e08 | Blue Swirl | VMSTATE_UINT32_ARRAY(regs, IOMMUState, IOMMU_NREGS), |
338 | db3c9e08 | Blue Swirl | VMSTATE_UINT64(iostart, IOMMUState), |
339 | db3c9e08 | Blue Swirl | VMSTATE_END_OF_LIST() |
340 | db3c9e08 | Blue Swirl | } |
341 | db3c9e08 | Blue Swirl | }; |
342 | e80cfcfc | bellard | |
343 | 1a522e8a | Blue Swirl | static void iommu_reset(DeviceState *d) |
344 | e80cfcfc | bellard | { |
345 | 1a522e8a | Blue Swirl | IOMMUState *s = container_of(d, IOMMUState, busdev.qdev); |
346 | e80cfcfc | bellard | |
347 | 66321a11 | bellard | memset(s->regs, 0, IOMMU_NREGS * 4); |
348 | e80cfcfc | bellard | s->iostart = 0;
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349 | 7fbfb139 | blueswir1 | s->regs[IOMMU_CTRL] = s->version; |
350 | 7fbfb139 | blueswir1 | s->regs[IOMMU_ARBEN] = IOMMU_MID; |
351 | 5ad6bb97 | blueswir1 | s->regs[IOMMU_AFSR] = IOMMU_AFSR_RESV; |
352 | 7b169687 | blueswir1 | s->regs[IOMMU_AER] = IOMMU_AER_EN_P0_ARB | IOMMU_AER_EN_P1_ARB; |
353 | e5e38121 | blueswir1 | s->regs[IOMMU_MASK_ID] = IOMMU_TS_MASK; |
354 | e80cfcfc | bellard | } |
355 | e80cfcfc | bellard | |
356 | 81a322d4 | Gerd Hoffmann | static int iommu_init1(SysBusDevice *dev) |
357 | 5f750b2e | Blue Swirl | { |
358 | 5f750b2e | Blue Swirl | IOMMUState *s = FROM_SYSBUS(IOMMUState, dev); |
359 | 5f750b2e | Blue Swirl | int io;
|
360 | 420557e8 | bellard | |
361 | 5f750b2e | Blue Swirl | sysbus_init_irq(dev, &s->irq); |
362 | 420557e8 | bellard | |
363 | 5f750b2e | Blue Swirl | io = cpu_register_io_memory(iommu_mem_read, iommu_mem_write, s); |
364 | 5f750b2e | Blue Swirl | sysbus_init_mmio(dev, IOMMU_NREGS * sizeof(uint32_t), io);
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365 | 3b46e624 | ths | |
366 | 1a522e8a | Blue Swirl | iommu_reset(&s->busdev.qdev); |
367 | 1a522e8a | Blue Swirl | |
368 | 81a322d4 | Gerd Hoffmann | return 0; |
369 | 420557e8 | bellard | } |
370 | 5f750b2e | Blue Swirl | |
371 | 5f750b2e | Blue Swirl | static SysBusDeviceInfo iommu_info = {
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372 | 5f750b2e | Blue Swirl | .init = iommu_init1, |
373 | 5f750b2e | Blue Swirl | .qdev.name = "iommu",
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374 | 5f750b2e | Blue Swirl | .qdev.size = sizeof(IOMMUState),
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375 | 1a522e8a | Blue Swirl | .qdev.vmsd = &vmstate_iommu, |
376 | 1a522e8a | Blue Swirl | .qdev.reset = iommu_reset, |
377 | ee6847d1 | Gerd Hoffmann | .qdev.props = (Property[]) { |
378 | 668724a7 | Gerd Hoffmann | DEFINE_PROP_HEX32("version", IOMMUState, version, 0), |
379 | 668724a7 | Gerd Hoffmann | DEFINE_PROP_END_OF_LIST(), |
380 | 5f750b2e | Blue Swirl | } |
381 | 5f750b2e | Blue Swirl | }; |
382 | 5f750b2e | Blue Swirl | |
383 | 5f750b2e | Blue Swirl | static void iommu_register_devices(void) |
384 | 5f750b2e | Blue Swirl | { |
385 | 5f750b2e | Blue Swirl | sysbus_register_withprop(&iommu_info); |
386 | 5f750b2e | Blue Swirl | } |
387 | 5f750b2e | Blue Swirl | |
388 | 5f750b2e | Blue Swirl | device_init(iommu_register_devices) |