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1 | 27c7ca7e | bellard | /*
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2 | 27c7ca7e | bellard | * SH7750 device
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3 | 5fafdf24 | ths | *
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4 | 80f515e6 | balrog | * Copyright (c) 2007 Magnus Damm
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5 | 27c7ca7e | bellard | * Copyright (c) 2005 Samuel Tardieu
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6 | 5fafdf24 | ths | *
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7 | 27c7ca7e | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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8 | 27c7ca7e | bellard | * of this software and associated documentation files (the "Software"), to deal
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9 | 27c7ca7e | bellard | * in the Software without restriction, including without limitation the rights
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10 | 27c7ca7e | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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11 | 27c7ca7e | bellard | * copies of the Software, and to permit persons to whom the Software is
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12 | 27c7ca7e | bellard | * furnished to do so, subject to the following conditions:
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13 | 27c7ca7e | bellard | *
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14 | 27c7ca7e | bellard | * The above copyright notice and this permission notice shall be included in
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15 | 27c7ca7e | bellard | * all copies or substantial portions of the Software.
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16 | 27c7ca7e | bellard | *
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17 | 27c7ca7e | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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18 | 27c7ca7e | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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19 | 27c7ca7e | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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20 | 27c7ca7e | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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21 | 27c7ca7e | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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22 | 27c7ca7e | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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23 | 27c7ca7e | bellard | * THE SOFTWARE.
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24 | 27c7ca7e | bellard | */
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25 | 27c7ca7e | bellard | #include <stdio.h> |
26 | 87ecb68b | pbrook | #include "hw.h" |
27 | 87ecb68b | pbrook | #include "sh.h" |
28 | 87ecb68b | pbrook | #include "sysemu.h" |
29 | 27c7ca7e | bellard | #include "sh7750_regs.h" |
30 | 27c7ca7e | bellard | #include "sh7750_regnames.h" |
31 | 80f515e6 | balrog | #include "sh_intc.h" |
32 | 06afe2c8 | aurel32 | #include "exec-all.h" |
33 | 29e179bc | aurel32 | #include "cpu.h" |
34 | 27c7ca7e | bellard | |
35 | 27c7ca7e | bellard | #define NB_DEVICES 4 |
36 | 27c7ca7e | bellard | |
37 | 27c7ca7e | bellard | typedef struct SH7750State { |
38 | 27c7ca7e | bellard | /* CPU */
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39 | 27c7ca7e | bellard | CPUSH4State *cpu; |
40 | 27c7ca7e | bellard | /* Peripheral frequency in Hz */
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41 | 27c7ca7e | bellard | uint32_t periph_freq; |
42 | 27c7ca7e | bellard | /* SDRAM controller */
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43 | c2f01775 | balrog | uint32_t bcr1; |
44 | c2432a42 | aurel32 | uint16_t bcr2; |
45 | c2432a42 | aurel32 | uint16_t bcr3; |
46 | c2432a42 | aurel32 | uint32_t bcr4; |
47 | 27c7ca7e | bellard | uint16_t rfcr; |
48 | c2432a42 | aurel32 | /* PCMCIA controller */
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49 | c2432a42 | aurel32 | uint16_t pcr; |
50 | 27c7ca7e | bellard | /* IO ports */
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51 | 27c7ca7e | bellard | uint16_t gpioic; |
52 | 27c7ca7e | bellard | uint32_t pctra; |
53 | 27c7ca7e | bellard | uint32_t pctrb; |
54 | 27c7ca7e | bellard | uint16_t portdira; /* Cached */
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55 | 27c7ca7e | bellard | uint16_t portpullupa; /* Cached */
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56 | 27c7ca7e | bellard | uint16_t portdirb; /* Cached */
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57 | 27c7ca7e | bellard | uint16_t portpullupb; /* Cached */
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58 | 27c7ca7e | bellard | uint16_t pdtra; |
59 | 27c7ca7e | bellard | uint16_t pdtrb; |
60 | 27c7ca7e | bellard | uint16_t periph_pdtra; /* Imposed by the peripherals */
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61 | 27c7ca7e | bellard | uint16_t periph_portdira; /* Direction seen from the peripherals */
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62 | 27c7ca7e | bellard | uint16_t periph_pdtrb; /* Imposed by the peripherals */
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63 | 27c7ca7e | bellard | uint16_t periph_portdirb; /* Direction seen from the peripherals */
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64 | 27c7ca7e | bellard | sh7750_io_device *devices[NB_DEVICES]; /* External peripherals */
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65 | 3464c589 | ths | |
66 | 27c7ca7e | bellard | /* Cache */
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67 | 27c7ca7e | bellard | uint32_t ccr; |
68 | 27c7ca7e | bellard | |
69 | 80f515e6 | balrog | struct intc_desc intc;
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70 | cd1a3f68 | ths | } SH7750State; |
71 | 27c7ca7e | bellard | |
72 | 86178a57 | Juan Quintela | static inline int has_bcr3_and_bcr4(SH7750State * s) |
73 | c2432a42 | aurel32 | { |
74 | c2432a42 | aurel32 | return (s->cpu->features & SH_FEATURE_BCR3_AND_BCR4);
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75 | c2432a42 | aurel32 | } |
76 | 27c7ca7e | bellard | /**********************************************************************
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77 | 27c7ca7e | bellard | I/O ports
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78 | 27c7ca7e | bellard | **********************************************************************/
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79 | 27c7ca7e | bellard | |
80 | 27c7ca7e | bellard | int sh7750_register_io_device(SH7750State * s, sh7750_io_device * device)
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81 | 27c7ca7e | bellard | { |
82 | 27c7ca7e | bellard | int i;
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83 | 27c7ca7e | bellard | |
84 | 27c7ca7e | bellard | for (i = 0; i < NB_DEVICES; i++) { |
85 | 27c7ca7e | bellard | if (s->devices[i] == NULL) { |
86 | 27c7ca7e | bellard | s->devices[i] = device; |
87 | 27c7ca7e | bellard | return 0; |
88 | 27c7ca7e | bellard | } |
89 | 27c7ca7e | bellard | } |
90 | 27c7ca7e | bellard | return -1; |
91 | 27c7ca7e | bellard | } |
92 | 27c7ca7e | bellard | |
93 | 27c7ca7e | bellard | static uint16_t portdir(uint32_t v)
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94 | 27c7ca7e | bellard | { |
95 | 27c7ca7e | bellard | #define EVENPORTMASK(n) ((v & (1<<((n)<<1))) >> (n)) |
96 | 27c7ca7e | bellard | return
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97 | 27c7ca7e | bellard | EVENPORTMASK(15) | EVENPORTMASK(14) | EVENPORTMASK(13) | |
98 | 27c7ca7e | bellard | EVENPORTMASK(12) | EVENPORTMASK(11) | EVENPORTMASK(10) | |
99 | 27c7ca7e | bellard | EVENPORTMASK(9) | EVENPORTMASK(8) | EVENPORTMASK(7) | |
100 | 27c7ca7e | bellard | EVENPORTMASK(6) | EVENPORTMASK(5) | EVENPORTMASK(4) | |
101 | 27c7ca7e | bellard | EVENPORTMASK(3) | EVENPORTMASK(2) | EVENPORTMASK(1) | |
102 | 27c7ca7e | bellard | EVENPORTMASK(0);
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103 | 27c7ca7e | bellard | } |
104 | 27c7ca7e | bellard | |
105 | 27c7ca7e | bellard | static uint16_t portpullup(uint32_t v)
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106 | 27c7ca7e | bellard | { |
107 | 27c7ca7e | bellard | #define ODDPORTMASK(n) ((v & (1<<(((n)<<1)+1))) >> (n)) |
108 | 27c7ca7e | bellard | return
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109 | 27c7ca7e | bellard | ODDPORTMASK(15) | ODDPORTMASK(14) | ODDPORTMASK(13) | |
110 | 27c7ca7e | bellard | ODDPORTMASK(12) | ODDPORTMASK(11) | ODDPORTMASK(10) | |
111 | 27c7ca7e | bellard | ODDPORTMASK(9) | ODDPORTMASK(8) | ODDPORTMASK(7) | ODDPORTMASK(6) | |
112 | 27c7ca7e | bellard | ODDPORTMASK(5) | ODDPORTMASK(4) | ODDPORTMASK(3) | ODDPORTMASK(2) | |
113 | 27c7ca7e | bellard | ODDPORTMASK(1) | ODDPORTMASK(0); |
114 | 27c7ca7e | bellard | } |
115 | 27c7ca7e | bellard | |
116 | 27c7ca7e | bellard | static uint16_t porta_lines(SH7750State * s)
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117 | 27c7ca7e | bellard | { |
118 | 27c7ca7e | bellard | return (s->portdira & s->pdtra) | /* CPU */ |
119 | 27c7ca7e | bellard | (s->periph_portdira & s->periph_pdtra) | /* Peripherals */
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120 | 27c7ca7e | bellard | (~(s->portdira | s->periph_portdira) & s->portpullupa); /* Pullups */
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121 | 27c7ca7e | bellard | } |
122 | 27c7ca7e | bellard | |
123 | 27c7ca7e | bellard | static uint16_t portb_lines(SH7750State * s)
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124 | 27c7ca7e | bellard | { |
125 | 27c7ca7e | bellard | return (s->portdirb & s->pdtrb) | /* CPU */ |
126 | 27c7ca7e | bellard | (s->periph_portdirb & s->periph_pdtrb) | /* Peripherals */
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127 | 27c7ca7e | bellard | (~(s->portdirb | s->periph_portdirb) & s->portpullupb); /* Pullups */
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128 | 27c7ca7e | bellard | } |
129 | 27c7ca7e | bellard | |
130 | 27c7ca7e | bellard | static void gen_port_interrupts(SH7750State * s) |
131 | 27c7ca7e | bellard | { |
132 | 27c7ca7e | bellard | /* XXXXX interrupts not generated */
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133 | 27c7ca7e | bellard | } |
134 | 27c7ca7e | bellard | |
135 | 27c7ca7e | bellard | static void porta_changed(SH7750State * s, uint16_t prev) |
136 | 27c7ca7e | bellard | { |
137 | 27c7ca7e | bellard | uint16_t currenta, changes; |
138 | 27c7ca7e | bellard | int i, r = 0; |
139 | 27c7ca7e | bellard | |
140 | 27c7ca7e | bellard | #if 0
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141 | 27c7ca7e | bellard | fprintf(stderr, "porta changed from 0x%04x to 0x%04x\n",
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142 | 27c7ca7e | bellard | prev, porta_lines(s));
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143 | 27c7ca7e | bellard | fprintf(stderr, "pdtra=0x%04x, pctra=0x%08x\n", s->pdtra, s->pctra);
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144 | 27c7ca7e | bellard | #endif
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145 | 27c7ca7e | bellard | currenta = porta_lines(s); |
146 | 27c7ca7e | bellard | if (currenta == prev)
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147 | 27c7ca7e | bellard | return;
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148 | 27c7ca7e | bellard | changes = currenta ^ prev; |
149 | 27c7ca7e | bellard | |
150 | 27c7ca7e | bellard | for (i = 0; i < NB_DEVICES; i++) { |
151 | 27c7ca7e | bellard | if (s->devices[i] && (s->devices[i]->portamask_trigger & changes)) {
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152 | 27c7ca7e | bellard | r |= s->devices[i]->port_change_cb(currenta, portb_lines(s), |
153 | 27c7ca7e | bellard | &s->periph_pdtra, |
154 | 27c7ca7e | bellard | &s->periph_portdira, |
155 | 27c7ca7e | bellard | &s->periph_pdtrb, |
156 | 27c7ca7e | bellard | &s->periph_portdirb); |
157 | 27c7ca7e | bellard | } |
158 | 27c7ca7e | bellard | } |
159 | 27c7ca7e | bellard | |
160 | 27c7ca7e | bellard | if (r)
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161 | 27c7ca7e | bellard | gen_port_interrupts(s); |
162 | 27c7ca7e | bellard | } |
163 | 27c7ca7e | bellard | |
164 | 27c7ca7e | bellard | static void portb_changed(SH7750State * s, uint16_t prev) |
165 | 27c7ca7e | bellard | { |
166 | 27c7ca7e | bellard | uint16_t currentb, changes; |
167 | 27c7ca7e | bellard | int i, r = 0; |
168 | 27c7ca7e | bellard | |
169 | 27c7ca7e | bellard | currentb = portb_lines(s); |
170 | 27c7ca7e | bellard | if (currentb == prev)
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171 | 27c7ca7e | bellard | return;
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172 | 27c7ca7e | bellard | changes = currentb ^ prev; |
173 | 27c7ca7e | bellard | |
174 | 27c7ca7e | bellard | for (i = 0; i < NB_DEVICES; i++) { |
175 | 27c7ca7e | bellard | if (s->devices[i] && (s->devices[i]->portbmask_trigger & changes)) {
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176 | 27c7ca7e | bellard | r |= s->devices[i]->port_change_cb(portb_lines(s), currentb, |
177 | 27c7ca7e | bellard | &s->periph_pdtra, |
178 | 27c7ca7e | bellard | &s->periph_portdira, |
179 | 27c7ca7e | bellard | &s->periph_pdtrb, |
180 | 27c7ca7e | bellard | &s->periph_portdirb); |
181 | 27c7ca7e | bellard | } |
182 | 27c7ca7e | bellard | } |
183 | 27c7ca7e | bellard | |
184 | 27c7ca7e | bellard | if (r)
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185 | 27c7ca7e | bellard | gen_port_interrupts(s); |
186 | 27c7ca7e | bellard | } |
187 | 27c7ca7e | bellard | |
188 | 27c7ca7e | bellard | /**********************************************************************
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189 | 27c7ca7e | bellard | Memory
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190 | 27c7ca7e | bellard | **********************************************************************/
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191 | 27c7ca7e | bellard | |
192 | c227f099 | Anthony Liguori | static void error_access(const char *kind, target_phys_addr_t addr) |
193 | 27c7ca7e | bellard | { |
194 | 526ccb7a | balrog | fprintf(stderr, "%s to %s (0x" TARGET_FMT_plx ") not supported\n", |
195 | 27c7ca7e | bellard | kind, regname(addr), addr); |
196 | 27c7ca7e | bellard | } |
197 | 27c7ca7e | bellard | |
198 | c227f099 | Anthony Liguori | static void ignore_access(const char *kind, target_phys_addr_t addr) |
199 | 27c7ca7e | bellard | { |
200 | 526ccb7a | balrog | fprintf(stderr, "%s to %s (0x" TARGET_FMT_plx ") ignored\n", |
201 | 27c7ca7e | bellard | kind, regname(addr), addr); |
202 | 27c7ca7e | bellard | } |
203 | 27c7ca7e | bellard | |
204 | c227f099 | Anthony Liguori | static uint32_t sh7750_mem_readb(void *opaque, target_phys_addr_t addr) |
205 | 27c7ca7e | bellard | { |
206 | 27c7ca7e | bellard | switch (addr) {
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207 | 27c7ca7e | bellard | default:
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208 | 27c7ca7e | bellard | error_access("byte read", addr);
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209 | 27c7ca7e | bellard | assert(0);
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210 | 27c7ca7e | bellard | } |
211 | 27c7ca7e | bellard | } |
212 | 27c7ca7e | bellard | |
213 | c227f099 | Anthony Liguori | static uint32_t sh7750_mem_readw(void *opaque, target_phys_addr_t addr) |
214 | 27c7ca7e | bellard | { |
215 | 27c7ca7e | bellard | SH7750State *s = opaque; |
216 | 27c7ca7e | bellard | |
217 | 27c7ca7e | bellard | switch (addr) {
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218 | c2f01775 | balrog | case SH7750_BCR2_A7:
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219 | c2f01775 | balrog | return s->bcr2;
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220 | c2432a42 | aurel32 | case SH7750_BCR3_A7:
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221 | c2432a42 | aurel32 | if(!has_bcr3_and_bcr4(s))
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222 | c2432a42 | aurel32 | error_access("word read", addr);
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223 | c2432a42 | aurel32 | return s->bcr3;
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224 | ed8e0a4d | ths | case SH7750_FRQCR_A7:
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225 | ed8e0a4d | ths | return 0; |
226 | c2432a42 | aurel32 | case SH7750_PCR_A7:
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227 | c2432a42 | aurel32 | return s->pcr;
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228 | 27c7ca7e | bellard | case SH7750_RFCR_A7:
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229 | 27c7ca7e | bellard | fprintf(stderr, |
230 | 27c7ca7e | bellard | "Read access to refresh count register, incrementing\n");
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231 | 27c7ca7e | bellard | return s->rfcr++;
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232 | 27c7ca7e | bellard | case SH7750_PDTRA_A7:
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233 | 27c7ca7e | bellard | return porta_lines(s);
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234 | 27c7ca7e | bellard | case SH7750_PDTRB_A7:
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235 | 27c7ca7e | bellard | return portb_lines(s);
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236 | c2432a42 | aurel32 | case SH7750_RTCOR_A7:
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237 | c2432a42 | aurel32 | case SH7750_RTCNT_A7:
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238 | c2432a42 | aurel32 | case SH7750_RTCSR_A7:
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239 | c2432a42 | aurel32 | ignore_access("word read", addr);
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240 | c2432a42 | aurel32 | return 0; |
241 | 27c7ca7e | bellard | default:
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242 | 27c7ca7e | bellard | error_access("word read", addr);
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243 | 27c7ca7e | bellard | assert(0);
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244 | 27c7ca7e | bellard | } |
245 | 27c7ca7e | bellard | } |
246 | 27c7ca7e | bellard | |
247 | c227f099 | Anthony Liguori | static uint32_t sh7750_mem_readl(void *opaque, target_phys_addr_t addr) |
248 | 27c7ca7e | bellard | { |
249 | 27c7ca7e | bellard | SH7750State *s = opaque; |
250 | 27c7ca7e | bellard | |
251 | 27c7ca7e | bellard | switch (addr) {
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252 | c2f01775 | balrog | case SH7750_BCR1_A7:
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253 | c2f01775 | balrog | return s->bcr1;
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254 | c2f01775 | balrog | case SH7750_BCR4_A7:
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255 | c2432a42 | aurel32 | if(!has_bcr3_and_bcr4(s))
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256 | c2432a42 | aurel32 | error_access("long read", addr);
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257 | c2432a42 | aurel32 | return s->bcr4;
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258 | c2f01775 | balrog | case SH7750_WCR1_A7:
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259 | c2f01775 | balrog | case SH7750_WCR2_A7:
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260 | c2f01775 | balrog | case SH7750_WCR3_A7:
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261 | c2f01775 | balrog | case SH7750_MCR_A7:
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262 | c2f01775 | balrog | ignore_access("long read", addr);
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263 | c2f01775 | balrog | return 0; |
264 | 27c7ca7e | bellard | case SH7750_MMUCR_A7:
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265 | 27c7ca7e | bellard | return s->cpu->mmucr;
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266 | 27c7ca7e | bellard | case SH7750_PTEH_A7:
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267 | 27c7ca7e | bellard | return s->cpu->pteh;
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268 | 27c7ca7e | bellard | case SH7750_PTEL_A7:
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269 | 27c7ca7e | bellard | return s->cpu->ptel;
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270 | 27c7ca7e | bellard | case SH7750_TTB_A7:
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271 | 27c7ca7e | bellard | return s->cpu->ttb;
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272 | 27c7ca7e | bellard | case SH7750_TEA_A7:
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273 | 27c7ca7e | bellard | return s->cpu->tea;
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274 | 27c7ca7e | bellard | case SH7750_TRA_A7:
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275 | 27c7ca7e | bellard | return s->cpu->tra;
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276 | 27c7ca7e | bellard | case SH7750_EXPEVT_A7:
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277 | 27c7ca7e | bellard | return s->cpu->expevt;
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278 | 27c7ca7e | bellard | case SH7750_INTEVT_A7:
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279 | 27c7ca7e | bellard | return s->cpu->intevt;
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280 | 27c7ca7e | bellard | case SH7750_CCR_A7:
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281 | 27c7ca7e | bellard | return s->ccr;
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282 | 0fd3ca30 | aurel32 | case 0x1f000030: /* Processor version */ |
283 | 0fd3ca30 | aurel32 | return s->cpu->pvr;
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284 | 0fd3ca30 | aurel32 | case 0x1f000040: /* Cache version */ |
285 | 0fd3ca30 | aurel32 | return s->cpu->cvr;
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286 | 0fd3ca30 | aurel32 | case 0x1f000044: /* Processor revision */ |
287 | 0fd3ca30 | aurel32 | return s->cpu->prr;
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288 | 27c7ca7e | bellard | default:
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289 | 27c7ca7e | bellard | error_access("long read", addr);
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290 | 27c7ca7e | bellard | assert(0);
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291 | 27c7ca7e | bellard | } |
292 | 27c7ca7e | bellard | } |
293 | 27c7ca7e | bellard | |
294 | c2432a42 | aurel32 | #define is_in_sdrmx(a, x) (a >= SH7750_SDMR ## x ## _A7 \ |
295 | c2432a42 | aurel32 | && a <= (SH7750_SDMR ## x ## _A7 + SH7750_SDMR ## x ## _REGNB)) |
296 | c227f099 | Anthony Liguori | static void sh7750_mem_writeb(void *opaque, target_phys_addr_t addr, |
297 | 27c7ca7e | bellard | uint32_t mem_value) |
298 | 27c7ca7e | bellard | { |
299 | c2432a42 | aurel32 | |
300 | c2432a42 | aurel32 | if (is_in_sdrmx(addr, 2) || is_in_sdrmx(addr, 3)) { |
301 | 27c7ca7e | bellard | ignore_access("byte write", addr);
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302 | 27c7ca7e | bellard | return;
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303 | 27c7ca7e | bellard | } |
304 | c2432a42 | aurel32 | |
305 | c2432a42 | aurel32 | error_access("byte write", addr);
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306 | c2432a42 | aurel32 | assert(0);
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307 | 27c7ca7e | bellard | } |
308 | 27c7ca7e | bellard | |
309 | c227f099 | Anthony Liguori | static void sh7750_mem_writew(void *opaque, target_phys_addr_t addr, |
310 | 27c7ca7e | bellard | uint32_t mem_value) |
311 | 27c7ca7e | bellard | { |
312 | 27c7ca7e | bellard | SH7750State *s = opaque; |
313 | 27c7ca7e | bellard | uint16_t temp; |
314 | 27c7ca7e | bellard | |
315 | 27c7ca7e | bellard | switch (addr) {
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316 | 27c7ca7e | bellard | /* SDRAM controller */
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317 | 27c7ca7e | bellard | case SH7750_BCR2_A7:
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318 | c2f01775 | balrog | s->bcr2 = mem_value; |
319 | c2f01775 | balrog | return;
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320 | 27c7ca7e | bellard | case SH7750_BCR3_A7:
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321 | c2432a42 | aurel32 | if(!has_bcr3_and_bcr4(s))
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322 | c2432a42 | aurel32 | error_access("word write", addr);
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323 | c2432a42 | aurel32 | s->bcr3 = mem_value; |
324 | c2432a42 | aurel32 | return;
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325 | c2432a42 | aurel32 | case SH7750_PCR_A7:
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326 | c2432a42 | aurel32 | s->pcr = mem_value; |
327 | c2432a42 | aurel32 | return;
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328 | 27c7ca7e | bellard | case SH7750_RTCNT_A7:
|
329 | c2432a42 | aurel32 | case SH7750_RTCOR_A7:
|
330 | 27c7ca7e | bellard | case SH7750_RTCSR_A7:
|
331 | 27c7ca7e | bellard | ignore_access("word write", addr);
|
332 | 27c7ca7e | bellard | return;
|
333 | 27c7ca7e | bellard | /* IO ports */
|
334 | 27c7ca7e | bellard | case SH7750_PDTRA_A7:
|
335 | 27c7ca7e | bellard | temp = porta_lines(s); |
336 | 27c7ca7e | bellard | s->pdtra = mem_value; |
337 | 27c7ca7e | bellard | porta_changed(s, temp); |
338 | 27c7ca7e | bellard | return;
|
339 | 27c7ca7e | bellard | case SH7750_PDTRB_A7:
|
340 | 27c7ca7e | bellard | temp = portb_lines(s); |
341 | 27c7ca7e | bellard | s->pdtrb = mem_value; |
342 | 27c7ca7e | bellard | portb_changed(s, temp); |
343 | 27c7ca7e | bellard | return;
|
344 | 27c7ca7e | bellard | case SH7750_RFCR_A7:
|
345 | 27c7ca7e | bellard | fprintf(stderr, "Write access to refresh count register\n");
|
346 | 27c7ca7e | bellard | s->rfcr = mem_value; |
347 | 27c7ca7e | bellard | return;
|
348 | 27c7ca7e | bellard | case SH7750_GPIOIC_A7:
|
349 | 27c7ca7e | bellard | s->gpioic = mem_value; |
350 | 27c7ca7e | bellard | if (mem_value != 0) { |
351 | 27c7ca7e | bellard | fprintf(stderr, "I/O interrupts not implemented\n");
|
352 | 27c7ca7e | bellard | assert(0);
|
353 | 27c7ca7e | bellard | } |
354 | 27c7ca7e | bellard | return;
|
355 | 27c7ca7e | bellard | default:
|
356 | 27c7ca7e | bellard | error_access("word write", addr);
|
357 | 27c7ca7e | bellard | assert(0);
|
358 | 27c7ca7e | bellard | } |
359 | 27c7ca7e | bellard | } |
360 | 27c7ca7e | bellard | |
361 | c227f099 | Anthony Liguori | static void sh7750_mem_writel(void *opaque, target_phys_addr_t addr, |
362 | 27c7ca7e | bellard | uint32_t mem_value) |
363 | 27c7ca7e | bellard | { |
364 | 27c7ca7e | bellard | SH7750State *s = opaque; |
365 | 27c7ca7e | bellard | uint16_t temp; |
366 | 27c7ca7e | bellard | |
367 | 27c7ca7e | bellard | switch (addr) {
|
368 | 27c7ca7e | bellard | /* SDRAM controller */
|
369 | 27c7ca7e | bellard | case SH7750_BCR1_A7:
|
370 | c2f01775 | balrog | s->bcr1 = mem_value; |
371 | c2f01775 | balrog | return;
|
372 | 27c7ca7e | bellard | case SH7750_BCR4_A7:
|
373 | c2432a42 | aurel32 | if(!has_bcr3_and_bcr4(s))
|
374 | c2432a42 | aurel32 | error_access("long write", addr);
|
375 | c2432a42 | aurel32 | s->bcr4 = mem_value; |
376 | c2432a42 | aurel32 | return;
|
377 | 27c7ca7e | bellard | case SH7750_WCR1_A7:
|
378 | 27c7ca7e | bellard | case SH7750_WCR2_A7:
|
379 | 27c7ca7e | bellard | case SH7750_WCR3_A7:
|
380 | 27c7ca7e | bellard | case SH7750_MCR_A7:
|
381 | 27c7ca7e | bellard | ignore_access("long write", addr);
|
382 | 27c7ca7e | bellard | return;
|
383 | 27c7ca7e | bellard | /* IO ports */
|
384 | 27c7ca7e | bellard | case SH7750_PCTRA_A7:
|
385 | 27c7ca7e | bellard | temp = porta_lines(s); |
386 | 27c7ca7e | bellard | s->pctra = mem_value; |
387 | 27c7ca7e | bellard | s->portdira = portdir(mem_value); |
388 | 27c7ca7e | bellard | s->portpullupa = portpullup(mem_value); |
389 | 27c7ca7e | bellard | porta_changed(s, temp); |
390 | 27c7ca7e | bellard | return;
|
391 | 27c7ca7e | bellard | case SH7750_PCTRB_A7:
|
392 | 27c7ca7e | bellard | temp = portb_lines(s); |
393 | 27c7ca7e | bellard | s->pctrb = mem_value; |
394 | 27c7ca7e | bellard | s->portdirb = portdir(mem_value); |
395 | 27c7ca7e | bellard | s->portpullupb = portpullup(mem_value); |
396 | 27c7ca7e | bellard | portb_changed(s, temp); |
397 | 27c7ca7e | bellard | return;
|
398 | 27c7ca7e | bellard | case SH7750_MMUCR_A7:
|
399 | 27c7ca7e | bellard | s->cpu->mmucr = mem_value; |
400 | 27c7ca7e | bellard | return;
|
401 | 27c7ca7e | bellard | case SH7750_PTEH_A7:
|
402 | 06afe2c8 | aurel32 | /* If asid changes, clear all registered tlb entries. */
|
403 | 06afe2c8 | aurel32 | if ((s->cpu->pteh & 0xff) != (mem_value & 0xff)) |
404 | 06afe2c8 | aurel32 | tlb_flush(s->cpu, 1);
|
405 | 27c7ca7e | bellard | s->cpu->pteh = mem_value; |
406 | 27c7ca7e | bellard | return;
|
407 | 27c7ca7e | bellard | case SH7750_PTEL_A7:
|
408 | 27c7ca7e | bellard | s->cpu->ptel = mem_value; |
409 | 27c7ca7e | bellard | return;
|
410 | ea2b542a | aurel32 | case SH7750_PTEA_A7:
|
411 | ea2b542a | aurel32 | s->cpu->ptea = mem_value & 0x0000000f;
|
412 | ea2b542a | aurel32 | return;
|
413 | 27c7ca7e | bellard | case SH7750_TTB_A7:
|
414 | 27c7ca7e | bellard | s->cpu->ttb = mem_value; |
415 | 27c7ca7e | bellard | return;
|
416 | 27c7ca7e | bellard | case SH7750_TEA_A7:
|
417 | 27c7ca7e | bellard | s->cpu->tea = mem_value; |
418 | 27c7ca7e | bellard | return;
|
419 | 27c7ca7e | bellard | case SH7750_TRA_A7:
|
420 | 27c7ca7e | bellard | s->cpu->tra = mem_value & 0x000007ff;
|
421 | 27c7ca7e | bellard | return;
|
422 | 27c7ca7e | bellard | case SH7750_EXPEVT_A7:
|
423 | 27c7ca7e | bellard | s->cpu->expevt = mem_value & 0x000007ff;
|
424 | 27c7ca7e | bellard | return;
|
425 | 27c7ca7e | bellard | case SH7750_INTEVT_A7:
|
426 | 27c7ca7e | bellard | s->cpu->intevt = mem_value & 0x000007ff;
|
427 | 27c7ca7e | bellard | return;
|
428 | 27c7ca7e | bellard | case SH7750_CCR_A7:
|
429 | 27c7ca7e | bellard | s->ccr = mem_value; |
430 | 27c7ca7e | bellard | return;
|
431 | 27c7ca7e | bellard | default:
|
432 | 27c7ca7e | bellard | error_access("long write", addr);
|
433 | 27c7ca7e | bellard | assert(0);
|
434 | 27c7ca7e | bellard | } |
435 | 27c7ca7e | bellard | } |
436 | 27c7ca7e | bellard | |
437 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const sh7750_mem_read[] = { |
438 | 27c7ca7e | bellard | sh7750_mem_readb, |
439 | 27c7ca7e | bellard | sh7750_mem_readw, |
440 | 27c7ca7e | bellard | sh7750_mem_readl |
441 | 27c7ca7e | bellard | }; |
442 | 27c7ca7e | bellard | |
443 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const sh7750_mem_write[] = { |
444 | 27c7ca7e | bellard | sh7750_mem_writeb, |
445 | 27c7ca7e | bellard | sh7750_mem_writew, |
446 | 27c7ca7e | bellard | sh7750_mem_writel |
447 | 27c7ca7e | bellard | }; |
448 | 27c7ca7e | bellard | |
449 | 80f515e6 | balrog | /* sh775x interrupt controller tables for sh_intc.c
|
450 | 80f515e6 | balrog | * stolen from linux/arch/sh/kernel/cpu/sh4/setup-sh7750.c
|
451 | 80f515e6 | balrog | */
|
452 | 80f515e6 | balrog | |
453 | 80f515e6 | balrog | enum {
|
454 | 80f515e6 | balrog | UNUSED = 0,
|
455 | 80f515e6 | balrog | |
456 | 80f515e6 | balrog | /* interrupt sources */
|
457 | c6d86a33 | balrog | IRL_0, IRL_1, IRL_2, IRL_3, IRL_4, IRL_5, IRL_6, IRL_7, |
458 | c6d86a33 | balrog | IRL_8, IRL_9, IRL_A, IRL_B, IRL_C, IRL_D, IRL_E, |
459 | c6d86a33 | balrog | IRL0, IRL1, IRL2, IRL3, |
460 | 80f515e6 | balrog | HUDI, GPIOI, |
461 | 80f515e6 | balrog | DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, DMAC_DMTE3, |
462 | 80f515e6 | balrog | DMAC_DMTE4, DMAC_DMTE5, DMAC_DMTE6, DMAC_DMTE7, |
463 | 80f515e6 | balrog | DMAC_DMAE, |
464 | 80f515e6 | balrog | PCIC0_PCISERR, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON, |
465 | 80f515e6 | balrog | PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3, |
466 | 80f515e6 | balrog | TMU3, TMU4, TMU0, TMU1, TMU2_TUNI, TMU2_TICPI, |
467 | 80f515e6 | balrog | RTC_ATI, RTC_PRI, RTC_CUI, |
468 | 80f515e6 | balrog | SCI1_ERI, SCI1_RXI, SCI1_TXI, SCI1_TEI, |
469 | 80f515e6 | balrog | SCIF_ERI, SCIF_RXI, SCIF_BRI, SCIF_TXI, |
470 | 80f515e6 | balrog | WDT, |
471 | 80f515e6 | balrog | REF_RCMI, REF_ROVI, |
472 | 80f515e6 | balrog | |
473 | 80f515e6 | balrog | /* interrupt groups */
|
474 | 80f515e6 | balrog | DMAC, PCIC1, TMU2, RTC, SCI1, SCIF, REF, |
475 | c6d86a33 | balrog | /* irl bundle */
|
476 | c6d86a33 | balrog | IRL, |
477 | 80f515e6 | balrog | |
478 | 80f515e6 | balrog | NR_SOURCES, |
479 | 80f515e6 | balrog | }; |
480 | 80f515e6 | balrog | |
481 | 80f515e6 | balrog | static struct intc_vect vectors[] = { |
482 | 80f515e6 | balrog | INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620), |
483 | 80f515e6 | balrog | INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), |
484 | 80f515e6 | balrog | INTC_VECT(TMU2_TUNI, 0x440), INTC_VECT(TMU2_TICPI, 0x460), |
485 | 80f515e6 | balrog | INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0), |
486 | 80f515e6 | balrog | INTC_VECT(RTC_CUI, 0x4c0),
|
487 | 80f515e6 | balrog | INTC_VECT(SCI1_ERI, 0x4e0), INTC_VECT(SCI1_RXI, 0x500), |
488 | 80f515e6 | balrog | INTC_VECT(SCI1_TXI, 0x520), INTC_VECT(SCI1_TEI, 0x540), |
489 | 80f515e6 | balrog | INTC_VECT(SCIF_ERI, 0x700), INTC_VECT(SCIF_RXI, 0x720), |
490 | 80f515e6 | balrog | INTC_VECT(SCIF_BRI, 0x740), INTC_VECT(SCIF_TXI, 0x760), |
491 | 80f515e6 | balrog | INTC_VECT(WDT, 0x560),
|
492 | 80f515e6 | balrog | INTC_VECT(REF_RCMI, 0x580), INTC_VECT(REF_ROVI, 0x5a0), |
493 | 80f515e6 | balrog | }; |
494 | 80f515e6 | balrog | |
495 | 80f515e6 | balrog | static struct intc_group groups[] = { |
496 | 80f515e6 | balrog | INTC_GROUP(TMU2, TMU2_TUNI, TMU2_TICPI), |
497 | 80f515e6 | balrog | INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI), |
498 | 80f515e6 | balrog | INTC_GROUP(SCI1, SCI1_ERI, SCI1_RXI, SCI1_TXI, SCI1_TEI), |
499 | 80f515e6 | balrog | INTC_GROUP(SCIF, SCIF_ERI, SCIF_RXI, SCIF_BRI, SCIF_TXI), |
500 | 80f515e6 | balrog | INTC_GROUP(REF, REF_RCMI, REF_ROVI), |
501 | 80f515e6 | balrog | }; |
502 | 80f515e6 | balrog | |
503 | 80f515e6 | balrog | static struct intc_prio_reg prio_registers[] = { |
504 | 80f515e6 | balrog | { 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } }, |
505 | 80f515e6 | balrog | { 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, SCI1, 0 } }, |
506 | 80f515e6 | balrog | { 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, SCIF, HUDI } }, |
507 | 80f515e6 | balrog | { 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } }, |
508 | 80f515e6 | balrog | { 0xfe080000, 0, 32, 4, /* INTPRI00 */ { 0, 0, 0, 0, |
509 | 80f515e6 | balrog | TMU4, TMU3, |
510 | 80f515e6 | balrog | PCIC1, PCIC0_PCISERR } }, |
511 | 80f515e6 | balrog | }; |
512 | 80f515e6 | balrog | |
513 | 80f515e6 | balrog | /* SH7750, SH7750S, SH7751 and SH7091 all have 4-channel DMA controllers */
|
514 | 80f515e6 | balrog | |
515 | 80f515e6 | balrog | static struct intc_vect vectors_dma4[] = { |
516 | 80f515e6 | balrog | INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660), |
517 | 80f515e6 | balrog | INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0), |
518 | 80f515e6 | balrog | INTC_VECT(DMAC_DMAE, 0x6c0),
|
519 | 80f515e6 | balrog | }; |
520 | 80f515e6 | balrog | |
521 | 80f515e6 | balrog | static struct intc_group groups_dma4[] = { |
522 | 80f515e6 | balrog | INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, |
523 | 80f515e6 | balrog | DMAC_DMTE3, DMAC_DMAE), |
524 | 80f515e6 | balrog | }; |
525 | 80f515e6 | balrog | |
526 | 80f515e6 | balrog | /* SH7750R and SH7751R both have 8-channel DMA controllers */
|
527 | 80f515e6 | balrog | |
528 | 80f515e6 | balrog | static struct intc_vect vectors_dma8[] = { |
529 | 80f515e6 | balrog | INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660), |
530 | 80f515e6 | balrog | INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0), |
531 | 80f515e6 | balrog | INTC_VECT(DMAC_DMTE4, 0x780), INTC_VECT(DMAC_DMTE5, 0x7a0), |
532 | 80f515e6 | balrog | INTC_VECT(DMAC_DMTE6, 0x7c0), INTC_VECT(DMAC_DMTE7, 0x7e0), |
533 | 80f515e6 | balrog | INTC_VECT(DMAC_DMAE, 0x6c0),
|
534 | 80f515e6 | balrog | }; |
535 | 80f515e6 | balrog | |
536 | 80f515e6 | balrog | static struct intc_group groups_dma8[] = { |
537 | 80f515e6 | balrog | INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, |
538 | 80f515e6 | balrog | DMAC_DMTE3, DMAC_DMTE4, DMAC_DMTE5, |
539 | 80f515e6 | balrog | DMAC_DMTE6, DMAC_DMTE7, DMAC_DMAE), |
540 | 80f515e6 | balrog | }; |
541 | 80f515e6 | balrog | |
542 | 80f515e6 | balrog | /* SH7750R, SH7751 and SH7751R all have two extra timer channels */
|
543 | 80f515e6 | balrog | |
544 | 80f515e6 | balrog | static struct intc_vect vectors_tmu34[] = { |
545 | 80f515e6 | balrog | INTC_VECT(TMU3, 0xb00), INTC_VECT(TMU4, 0xb80), |
546 | 80f515e6 | balrog | }; |
547 | 80f515e6 | balrog | |
548 | 80f515e6 | balrog | static struct intc_mask_reg mask_registers[] = { |
549 | 80f515e6 | balrog | { 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */ |
550 | 80f515e6 | balrog | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
551 | 80f515e6 | balrog | 0, 0, 0, 0, 0, 0, TMU4, TMU3, |
552 | 80f515e6 | balrog | PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON, |
553 | 80f515e6 | balrog | PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, |
554 | 80f515e6 | balrog | PCIC1_PCIDMA3, PCIC0_PCISERR } }, |
555 | 80f515e6 | balrog | }; |
556 | 80f515e6 | balrog | |
557 | 80f515e6 | balrog | /* SH7750S, SH7750R, SH7751 and SH7751R all have IRLM priority registers */
|
558 | 80f515e6 | balrog | |
559 | 80f515e6 | balrog | static struct intc_vect vectors_irlm[] = { |
560 | 80f515e6 | balrog | INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0), |
561 | 80f515e6 | balrog | INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360), |
562 | 80f515e6 | balrog | }; |
563 | 80f515e6 | balrog | |
564 | 80f515e6 | balrog | /* SH7751 and SH7751R both have PCI */
|
565 | 80f515e6 | balrog | |
566 | 80f515e6 | balrog | static struct intc_vect vectors_pci[] = { |
567 | 80f515e6 | balrog | INTC_VECT(PCIC0_PCISERR, 0xa00), INTC_VECT(PCIC1_PCIERR, 0xae0), |
568 | 80f515e6 | balrog | INTC_VECT(PCIC1_PCIPWDWN, 0xac0), INTC_VECT(PCIC1_PCIPWON, 0xaa0), |
569 | 80f515e6 | balrog | INTC_VECT(PCIC1_PCIDMA0, 0xa80), INTC_VECT(PCIC1_PCIDMA1, 0xa60), |
570 | 80f515e6 | balrog | INTC_VECT(PCIC1_PCIDMA2, 0xa40), INTC_VECT(PCIC1_PCIDMA3, 0xa20), |
571 | 80f515e6 | balrog | }; |
572 | 80f515e6 | balrog | |
573 | 80f515e6 | balrog | static struct intc_group groups_pci[] = { |
574 | 80f515e6 | balrog | INTC_GROUP(PCIC1, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON, |
575 | 80f515e6 | balrog | PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3), |
576 | 80f515e6 | balrog | }; |
577 | 80f515e6 | balrog | |
578 | c6d86a33 | balrog | static struct intc_vect vectors_irl[] = { |
579 | c6d86a33 | balrog | INTC_VECT(IRL_0, 0x200),
|
580 | c6d86a33 | balrog | INTC_VECT(IRL_1, 0x220),
|
581 | c6d86a33 | balrog | INTC_VECT(IRL_2, 0x240),
|
582 | c6d86a33 | balrog | INTC_VECT(IRL_3, 0x260),
|
583 | c6d86a33 | balrog | INTC_VECT(IRL_4, 0x280),
|
584 | c6d86a33 | balrog | INTC_VECT(IRL_5, 0x2a0),
|
585 | c6d86a33 | balrog | INTC_VECT(IRL_6, 0x2c0),
|
586 | c6d86a33 | balrog | INTC_VECT(IRL_7, 0x2e0),
|
587 | c6d86a33 | balrog | INTC_VECT(IRL_8, 0x300),
|
588 | c6d86a33 | balrog | INTC_VECT(IRL_9, 0x320),
|
589 | c6d86a33 | balrog | INTC_VECT(IRL_A, 0x340),
|
590 | c6d86a33 | balrog | INTC_VECT(IRL_B, 0x360),
|
591 | c6d86a33 | balrog | INTC_VECT(IRL_C, 0x380),
|
592 | c6d86a33 | balrog | INTC_VECT(IRL_D, 0x3a0),
|
593 | c6d86a33 | balrog | INTC_VECT(IRL_E, 0x3c0),
|
594 | c6d86a33 | balrog | }; |
595 | c6d86a33 | balrog | |
596 | c6d86a33 | balrog | static struct intc_group groups_irl[] = { |
597 | c6d86a33 | balrog | INTC_GROUP(IRL, IRL_0, IRL_1, IRL_2, IRL_3, IRL_4, IRL_5, IRL_6, |
598 | c6d86a33 | balrog | IRL_7, IRL_8, IRL_9, IRL_A, IRL_B, IRL_C, IRL_D, IRL_E), |
599 | c6d86a33 | balrog | }; |
600 | c6d86a33 | balrog | |
601 | 29e179bc | aurel32 | /**********************************************************************
|
602 | 29e179bc | aurel32 | Memory mapped cache and TLB
|
603 | 29e179bc | aurel32 | **********************************************************************/
|
604 | 29e179bc | aurel32 | |
605 | 29e179bc | aurel32 | #define MM_REGION_MASK 0x07000000 |
606 | 29e179bc | aurel32 | #define MM_ICACHE_ADDR (0) |
607 | 29e179bc | aurel32 | #define MM_ICACHE_DATA (1) |
608 | 29e179bc | aurel32 | #define MM_ITLB_ADDR (2) |
609 | 29e179bc | aurel32 | #define MM_ITLB_DATA (3) |
610 | 29e179bc | aurel32 | #define MM_OCACHE_ADDR (4) |
611 | 29e179bc | aurel32 | #define MM_OCACHE_DATA (5) |
612 | 29e179bc | aurel32 | #define MM_UTLB_ADDR (6) |
613 | 29e179bc | aurel32 | #define MM_UTLB_DATA (7) |
614 | 29e179bc | aurel32 | #define MM_REGION_TYPE(addr) ((addr & MM_REGION_MASK) >> 24) |
615 | 29e179bc | aurel32 | |
616 | c227f099 | Anthony Liguori | static uint32_t invalid_read(void *opaque, target_phys_addr_t addr) |
617 | 29e179bc | aurel32 | { |
618 | 29e179bc | aurel32 | assert(0);
|
619 | 29e179bc | aurel32 | |
620 | 29e179bc | aurel32 | return 0; |
621 | 29e179bc | aurel32 | } |
622 | 29e179bc | aurel32 | |
623 | c227f099 | Anthony Liguori | static uint32_t sh7750_mmct_readl(void *opaque, target_phys_addr_t addr) |
624 | 29e179bc | aurel32 | { |
625 | 29e179bc | aurel32 | uint32_t ret = 0;
|
626 | 29e179bc | aurel32 | |
627 | 29e179bc | aurel32 | switch (MM_REGION_TYPE(addr)) {
|
628 | 29e179bc | aurel32 | case MM_ICACHE_ADDR:
|
629 | 29e179bc | aurel32 | case MM_ICACHE_DATA:
|
630 | 29e179bc | aurel32 | /* do nothing */
|
631 | 29e179bc | aurel32 | break;
|
632 | 29e179bc | aurel32 | case MM_ITLB_ADDR:
|
633 | 29e179bc | aurel32 | case MM_ITLB_DATA:
|
634 | 29e179bc | aurel32 | /* XXXXX */
|
635 | 29e179bc | aurel32 | assert(0);
|
636 | 29e179bc | aurel32 | break;
|
637 | 29e179bc | aurel32 | case MM_OCACHE_ADDR:
|
638 | 29e179bc | aurel32 | case MM_OCACHE_DATA:
|
639 | 29e179bc | aurel32 | /* do nothing */
|
640 | 29e179bc | aurel32 | break;
|
641 | 29e179bc | aurel32 | case MM_UTLB_ADDR:
|
642 | 29e179bc | aurel32 | case MM_UTLB_DATA:
|
643 | 29e179bc | aurel32 | /* XXXXX */
|
644 | 29e179bc | aurel32 | assert(0);
|
645 | 29e179bc | aurel32 | break;
|
646 | 29e179bc | aurel32 | default:
|
647 | 29e179bc | aurel32 | assert(0);
|
648 | 29e179bc | aurel32 | } |
649 | 29e179bc | aurel32 | |
650 | 29e179bc | aurel32 | return ret;
|
651 | 29e179bc | aurel32 | } |
652 | 29e179bc | aurel32 | |
653 | c227f099 | Anthony Liguori | static void invalid_write(void *opaque, target_phys_addr_t addr, |
654 | 29e179bc | aurel32 | uint32_t mem_value) |
655 | 29e179bc | aurel32 | { |
656 | 29e179bc | aurel32 | assert(0);
|
657 | 29e179bc | aurel32 | } |
658 | 29e179bc | aurel32 | |
659 | c227f099 | Anthony Liguori | static void sh7750_mmct_writel(void *opaque, target_phys_addr_t addr, |
660 | 29e179bc | aurel32 | uint32_t mem_value) |
661 | 29e179bc | aurel32 | { |
662 | 29e179bc | aurel32 | SH7750State *s = opaque; |
663 | 29e179bc | aurel32 | |
664 | 29e179bc | aurel32 | switch (MM_REGION_TYPE(addr)) {
|
665 | 29e179bc | aurel32 | case MM_ICACHE_ADDR:
|
666 | 29e179bc | aurel32 | case MM_ICACHE_DATA:
|
667 | 29e179bc | aurel32 | /* do nothing */
|
668 | 29e179bc | aurel32 | break;
|
669 | 29e179bc | aurel32 | case MM_ITLB_ADDR:
|
670 | 29e179bc | aurel32 | case MM_ITLB_DATA:
|
671 | 29e179bc | aurel32 | /* XXXXX */
|
672 | 29e179bc | aurel32 | assert(0);
|
673 | 29e179bc | aurel32 | break;
|
674 | 29e179bc | aurel32 | case MM_OCACHE_ADDR:
|
675 | 29e179bc | aurel32 | case MM_OCACHE_DATA:
|
676 | 29e179bc | aurel32 | /* do nothing */
|
677 | 29e179bc | aurel32 | break;
|
678 | 29e179bc | aurel32 | case MM_UTLB_ADDR:
|
679 | 29e179bc | aurel32 | cpu_sh4_write_mmaped_utlb_addr(s->cpu, addr, mem_value); |
680 | 29e179bc | aurel32 | break;
|
681 | 29e179bc | aurel32 | case MM_UTLB_DATA:
|
682 | 29e179bc | aurel32 | /* XXXXX */
|
683 | 29e179bc | aurel32 | assert(0);
|
684 | 29e179bc | aurel32 | break;
|
685 | 29e179bc | aurel32 | default:
|
686 | 29e179bc | aurel32 | assert(0);
|
687 | 29e179bc | aurel32 | break;
|
688 | 29e179bc | aurel32 | } |
689 | 29e179bc | aurel32 | } |
690 | 29e179bc | aurel32 | |
691 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const sh7750_mmct_read[] = { |
692 | 29e179bc | aurel32 | invalid_read, |
693 | 29e179bc | aurel32 | invalid_read, |
694 | 29e179bc | aurel32 | sh7750_mmct_readl |
695 | 29e179bc | aurel32 | }; |
696 | 29e179bc | aurel32 | |
697 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const sh7750_mmct_write[] = { |
698 | 29e179bc | aurel32 | invalid_write, |
699 | 29e179bc | aurel32 | invalid_write, |
700 | 29e179bc | aurel32 | sh7750_mmct_writel |
701 | 29e179bc | aurel32 | }; |
702 | 29e179bc | aurel32 | |
703 | 27c7ca7e | bellard | SH7750State *sh7750_init(CPUSH4State * cpu) |
704 | 27c7ca7e | bellard | { |
705 | 27c7ca7e | bellard | SH7750State *s; |
706 | 27c7ca7e | bellard | int sh7750_io_memory;
|
707 | 29e179bc | aurel32 | int sh7750_mm_cache_and_tlb; /* memory mapped cache and tlb */ |
708 | 27c7ca7e | bellard | |
709 | 27c7ca7e | bellard | s = qemu_mallocz(sizeof(SH7750State));
|
710 | 27c7ca7e | bellard | s->cpu = cpu; |
711 | 27c7ca7e | bellard | s->periph_freq = 60000000; /* 60MHz */ |
712 | 1eed09cb | Avi Kivity | sh7750_io_memory = cpu_register_io_memory(sh7750_mem_read, |
713 | 27c7ca7e | bellard | sh7750_mem_write, s); |
714 | 486579de | balrog | cpu_register_physical_memory_offset(0x1f000000, 0x1000, |
715 | 486579de | balrog | sh7750_io_memory, 0x1f000000);
|
716 | 5c16736a | balrog | cpu_register_physical_memory_offset(0xff000000, 0x1000, |
717 | 5c16736a | balrog | sh7750_io_memory, 0x1f000000);
|
718 | 486579de | balrog | cpu_register_physical_memory_offset(0x1f800000, 0x1000, |
719 | 486579de | balrog | sh7750_io_memory, 0x1f800000);
|
720 | 5c16736a | balrog | cpu_register_physical_memory_offset(0xff800000, 0x1000, |
721 | 5c16736a | balrog | sh7750_io_memory, 0x1f800000);
|
722 | 486579de | balrog | cpu_register_physical_memory_offset(0x1fc00000, 0x1000, |
723 | 486579de | balrog | sh7750_io_memory, 0x1fc00000);
|
724 | 5c16736a | balrog | cpu_register_physical_memory_offset(0xffc00000, 0x1000, |
725 | 5c16736a | balrog | sh7750_io_memory, 0x1fc00000);
|
726 | 2f062c72 | ths | |
727 | 1eed09cb | Avi Kivity | sh7750_mm_cache_and_tlb = cpu_register_io_memory(sh7750_mmct_read, |
728 | 29e179bc | aurel32 | sh7750_mmct_write, s); |
729 | 29e179bc | aurel32 | cpu_register_physical_memory(0xf0000000, 0x08000000, |
730 | 29e179bc | aurel32 | sh7750_mm_cache_and_tlb); |
731 | 29e179bc | aurel32 | |
732 | 80f515e6 | balrog | sh_intc_init(&s->intc, NR_SOURCES, |
733 | 80f515e6 | balrog | _INTC_ARRAY(mask_registers), |
734 | 80f515e6 | balrog | _INTC_ARRAY(prio_registers)); |
735 | 80f515e6 | balrog | |
736 | 0fd3ca30 | aurel32 | sh_intc_register_sources(&s->intc, |
737 | 80f515e6 | balrog | _INTC_ARRAY(vectors), |
738 | 80f515e6 | balrog | _INTC_ARRAY(groups)); |
739 | 80f515e6 | balrog | |
740 | e96e2044 | ths | cpu->intc_handle = &s->intc; |
741 | e96e2044 | ths | |
742 | bf5b7423 | aurel32 | sh_serial_init(0x1fe00000, 0, s->periph_freq, serial_hds[0], |
743 | 4e7ed2d1 | aurel32 | s->intc.irqs[SCI1_ERI], |
744 | 4e7ed2d1 | aurel32 | s->intc.irqs[SCI1_RXI], |
745 | 4e7ed2d1 | aurel32 | s->intc.irqs[SCI1_TXI], |
746 | 4e7ed2d1 | aurel32 | s->intc.irqs[SCI1_TEI], |
747 | bf5b7423 | aurel32 | NULL);
|
748 | 2f062c72 | ths | sh_serial_init(0x1fe80000, SH_SERIAL_FEAT_SCIF,
|
749 | bf5b7423 | aurel32 | s->periph_freq, serial_hds[1],
|
750 | 4e7ed2d1 | aurel32 | s->intc.irqs[SCIF_ERI], |
751 | 4e7ed2d1 | aurel32 | s->intc.irqs[SCIF_RXI], |
752 | 4e7ed2d1 | aurel32 | s->intc.irqs[SCIF_TXI], |
753 | bf5b7423 | aurel32 | NULL,
|
754 | 4e7ed2d1 | aurel32 | s->intc.irqs[SCIF_BRI]); |
755 | cd1a3f68 | ths | |
756 | cd1a3f68 | ths | tmu012_init(0x1fd80000,
|
757 | cd1a3f68 | ths | TMU012_FEAT_TOCR | TMU012_FEAT_3CHAN | TMU012_FEAT_EXTCLK, |
758 | 703243a0 | balrog | s->periph_freq, |
759 | 96e2fc41 | aurel32 | s->intc.irqs[TMU0], |
760 | 96e2fc41 | aurel32 | s->intc.irqs[TMU1], |
761 | 96e2fc41 | aurel32 | s->intc.irqs[TMU2_TUNI], |
762 | 96e2fc41 | aurel32 | s->intc.irqs[TMU2_TICPI]); |
763 | 80f515e6 | balrog | |
764 | 0fd3ca30 | aurel32 | if (cpu->id & (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7751)) {
|
765 | 0fd3ca30 | aurel32 | sh_intc_register_sources(&s->intc, |
766 | 80f515e6 | balrog | _INTC_ARRAY(vectors_dma4), |
767 | 80f515e6 | balrog | _INTC_ARRAY(groups_dma4)); |
768 | 80f515e6 | balrog | } |
769 | 80f515e6 | balrog | |
770 | 0fd3ca30 | aurel32 | if (cpu->id & (SH_CPU_SH7750R | SH_CPU_SH7751R)) {
|
771 | 0fd3ca30 | aurel32 | sh_intc_register_sources(&s->intc, |
772 | 80f515e6 | balrog | _INTC_ARRAY(vectors_dma8), |
773 | 80f515e6 | balrog | _INTC_ARRAY(groups_dma8)); |
774 | 80f515e6 | balrog | } |
775 | 80f515e6 | balrog | |
776 | 0fd3ca30 | aurel32 | if (cpu->id & (SH_CPU_SH7750R | SH_CPU_SH7751 | SH_CPU_SH7751R)) {
|
777 | 0fd3ca30 | aurel32 | sh_intc_register_sources(&s->intc, |
778 | 80f515e6 | balrog | _INTC_ARRAY(vectors_tmu34), |
779 | f26ae302 | bellard | NULL, 0); |
780 | 703243a0 | balrog | tmu012_init(0x1e100000, 0, s->periph_freq, |
781 | 96e2fc41 | aurel32 | s->intc.irqs[TMU3], |
782 | 96e2fc41 | aurel32 | s->intc.irqs[TMU4], |
783 | 703243a0 | balrog | NULL, NULL); |
784 | 80f515e6 | balrog | } |
785 | 80f515e6 | balrog | |
786 | 0fd3ca30 | aurel32 | if (cpu->id & (SH_CPU_SH7751_ALL)) {
|
787 | 0fd3ca30 | aurel32 | sh_intc_register_sources(&s->intc, |
788 | 80f515e6 | balrog | _INTC_ARRAY(vectors_pci), |
789 | 80f515e6 | balrog | _INTC_ARRAY(groups_pci)); |
790 | 80f515e6 | balrog | } |
791 | 80f515e6 | balrog | |
792 | 0fd3ca30 | aurel32 | if (cpu->id & (SH_CPU_SH7750S | SH_CPU_SH7750R | SH_CPU_SH7751_ALL)) {
|
793 | 0fd3ca30 | aurel32 | sh_intc_register_sources(&s->intc, |
794 | 80f515e6 | balrog | _INTC_ARRAY(vectors_irlm), |
795 | f26ae302 | bellard | NULL, 0); |
796 | 80f515e6 | balrog | } |
797 | 80f515e6 | balrog | |
798 | c6d86a33 | balrog | sh_intc_register_sources(&s->intc, |
799 | c6d86a33 | balrog | _INTC_ARRAY(vectors_irl), |
800 | c6d86a33 | balrog | _INTC_ARRAY(groups_irl)); |
801 | 27c7ca7e | bellard | return s;
|
802 | 27c7ca7e | bellard | } |
803 | c6d86a33 | balrog | |
804 | c6d86a33 | balrog | qemu_irq sh7750_irl(SH7750State *s) |
805 | c6d86a33 | balrog | { |
806 | c6d86a33 | balrog | sh_intc_toggle_source(sh_intc_source(&s->intc, IRL), 1, 0); /* enable */ |
807 | c6d86a33 | balrog | return qemu_allocate_irqs(sh_intc_set_irl, sh_intc_source(&s->intc, IRL),
|
808 | c6d86a33 | balrog | 1)[0]; |
809 | c6d86a33 | balrog | } |