root / hw / piix_pci.c @ 9bba1eb1
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1 | 502a5395 | pbrook | /*
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2 | 502a5395 | pbrook | * QEMU i440FX/PIIX3 PCI Bridge Emulation
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3 | 502a5395 | pbrook | *
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4 | 502a5395 | pbrook | * Copyright (c) 2006 Fabrice Bellard
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5 | 5fafdf24 | ths | *
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6 | 502a5395 | pbrook | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 502a5395 | pbrook | * of this software and associated documentation files (the "Software"), to deal
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8 | 502a5395 | pbrook | * in the Software without restriction, including without limitation the rights
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9 | 502a5395 | pbrook | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 502a5395 | pbrook | * copies of the Software, and to permit persons to whom the Software is
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11 | 502a5395 | pbrook | * furnished to do so, subject to the following conditions:
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12 | 502a5395 | pbrook | *
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13 | 502a5395 | pbrook | * The above copyright notice and this permission notice shall be included in
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14 | 502a5395 | pbrook | * all copies or substantial portions of the Software.
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15 | 502a5395 | pbrook | *
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16 | 502a5395 | pbrook | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 502a5395 | pbrook | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 502a5395 | pbrook | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 502a5395 | pbrook | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 502a5395 | pbrook | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 502a5395 | pbrook | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 502a5395 | pbrook | * THE SOFTWARE.
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23 | 502a5395 | pbrook | */
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24 | 502a5395 | pbrook | |
25 | 87ecb68b | pbrook | #include "hw.h" |
26 | 87ecb68b | pbrook | #include "pc.h" |
27 | 87ecb68b | pbrook | #include "pci.h" |
28 | 4f5e19e6 | Isaku Yamahata | #include "pci_host.h" |
29 | f75247f1 | Gerd Hoffmann | #include "isa.h" |
30 | 8a14daa5 | Gerd Hoffmann | #include "sysbus.h" |
31 | bf1b0071 | Blue Swirl | #include "range.h" |
32 | 41445300 | Anthony PERARD | #include "xen.h" |
33 | 87ecb68b | pbrook | |
34 | 56594fe3 | Isaku Yamahata | /*
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35 | 56594fe3 | Isaku Yamahata | * I440FX chipset data sheet.
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36 | 56594fe3 | Isaku Yamahata | * http://download.intel.com/design/chipsets/datashts/29054901.pdf
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37 | 56594fe3 | Isaku Yamahata | */
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38 | 56594fe3 | Isaku Yamahata | |
39 | 502a5395 | pbrook | typedef PCIHostState I440FXState;
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40 | 502a5395 | pbrook | |
41 | ab431c28 | Isaku Yamahata | #define PIIX_NUM_PIC_IRQS 16 /* i8259 * 2 */ |
42 | e735b55a | Isaku Yamahata | #define PIIX_NUM_PIRQS 4ULL /* PIRQ[A-D] */ |
43 | ab431c28 | Isaku Yamahata | #define PIIX_PIRQC 0x60 |
44 | e735b55a | Isaku Yamahata | |
45 | fd37d881 | Juan Quintela | typedef struct PIIX3State { |
46 | fd37d881 | Juan Quintela | PCIDevice dev; |
47 | ab431c28 | Isaku Yamahata | |
48 | ab431c28 | Isaku Yamahata | /*
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49 | ab431c28 | Isaku Yamahata | * bitmap to track pic levels.
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50 | ab431c28 | Isaku Yamahata | * The pic level is the logical OR of all the PCI irqs mapped to it
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51 | ab431c28 | Isaku Yamahata | * So one PIC level is tracked by PIIX_NUM_PIRQS bits.
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52 | ab431c28 | Isaku Yamahata | *
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53 | ab431c28 | Isaku Yamahata | * PIRQ is mapped to PIC pins, we track it by
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54 | ab431c28 | Isaku Yamahata | * PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with
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55 | ab431c28 | Isaku Yamahata | * pic_irq * PIIX_NUM_PIRQS + pirq
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56 | ab431c28 | Isaku Yamahata | */
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57 | ab431c28 | Isaku Yamahata | #if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64 |
58 | ab431c28 | Isaku Yamahata | #error "unable to encode pic state in 64bit in pic_levels." |
59 | ab431c28 | Isaku Yamahata | #endif
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60 | ab431c28 | Isaku Yamahata | uint64_t pic_levels; |
61 | ab431c28 | Isaku Yamahata | |
62 | bd7dce87 | Juan Quintela | qemu_irq *pic; |
63 | e735b55a | Isaku Yamahata | |
64 | e735b55a | Isaku Yamahata | /* This member isn't used. Just for save/load compatibility */
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65 | e735b55a | Isaku Yamahata | int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS]; |
66 | 7cd9eee0 | Gerd Hoffmann | } PIIX3State; |
67 | bd7dce87 | Juan Quintela | |
68 | 0a3bacf3 | Juan Quintela | struct PCII440FXState {
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69 | 0a3bacf3 | Juan Quintela | PCIDevice dev; |
70 | c227f099 | Anthony Liguori | target_phys_addr_t isa_page_descs[384 / 4]; |
71 | 6c009fa4 | Juan Quintela | uint8_t smm_enabled; |
72 | 7cd9eee0 | Gerd Hoffmann | PIIX3State *piix3; |
73 | 0a3bacf3 | Juan Quintela | }; |
74 | 0a3bacf3 | Juan Quintela | |
75 | f2c688bb | Isaku Yamahata | |
76 | f2c688bb | Isaku Yamahata | #define I440FX_PAM 0x59 |
77 | f2c688bb | Isaku Yamahata | #define I440FX_PAM_SIZE 7 |
78 | f2c688bb | Isaku Yamahata | #define I440FX_SMRAM 0x72 |
79 | f2c688bb | Isaku Yamahata | |
80 | ab431c28 | Isaku Yamahata | static void piix3_set_irq(void *opaque, int pirq, int level); |
81 | d2b59317 | pbrook | |
82 | d2b59317 | pbrook | /* return the global irq number corresponding to a given device irq
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83 | d2b59317 | pbrook | pin. We could also use the bus number to have a more precise
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84 | d2b59317 | pbrook | mapping. */
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85 | ab431c28 | Isaku Yamahata | static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx) |
86 | d2b59317 | pbrook | { |
87 | d2b59317 | pbrook | int slot_addend;
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88 | d2b59317 | pbrook | slot_addend = (pci_dev->devfn >> 3) - 1; |
89 | ab431c28 | Isaku Yamahata | return (pci_intx + slot_addend) & 3; |
90 | d2b59317 | pbrook | } |
91 | 502a5395 | pbrook | |
92 | 0a3bacf3 | Juan Quintela | static void update_pam(PCII440FXState *d, uint32_t start, uint32_t end, int r) |
93 | 84631fd7 | bellard | { |
94 | 84631fd7 | bellard | uint32_t addr; |
95 | 84631fd7 | bellard | |
96 | 84631fd7 | bellard | // printf("ISA mapping %08x-0x%08x: %d\n", start, end, r);
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97 | 84631fd7 | bellard | switch(r) {
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98 | 84631fd7 | bellard | case 3: |
99 | 84631fd7 | bellard | /* RAM */
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100 | 5fafdf24 | ths | cpu_register_physical_memory(start, end - start, |
101 | 84631fd7 | bellard | start); |
102 | 84631fd7 | bellard | break;
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103 | 84631fd7 | bellard | case 1: |
104 | 84631fd7 | bellard | /* ROM (XXX: not quite correct) */
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105 | 5fafdf24 | ths | cpu_register_physical_memory(start, end - start, |
106 | 84631fd7 | bellard | start | IO_MEM_ROM); |
107 | 84631fd7 | bellard | break;
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108 | 84631fd7 | bellard | case 2: |
109 | 84631fd7 | bellard | case 0: |
110 | 84631fd7 | bellard | /* XXX: should distinguish read/write cases */
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111 | 84631fd7 | bellard | for(addr = start; addr < end; addr += 4096) { |
112 | 5fafdf24 | ths | cpu_register_physical_memory(addr, 4096,
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113 | 6c009fa4 | Juan Quintela | d->isa_page_descs[(addr - 0xa0000) >> 12]); |
114 | 84631fd7 | bellard | } |
115 | 84631fd7 | bellard | break;
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116 | 84631fd7 | bellard | } |
117 | 84631fd7 | bellard | } |
118 | ee0ea1d0 | bellard | |
119 | 0a3bacf3 | Juan Quintela | static void i440fx_update_memory_mappings(PCII440FXState *d) |
120 | ee0ea1d0 | bellard | { |
121 | ee0ea1d0 | bellard | int i, r;
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122 | 84631fd7 | bellard | uint32_t smram, addr; |
123 | 84631fd7 | bellard | |
124 | f2c688bb | Isaku Yamahata | update_pam(d, 0xf0000, 0x100000, (d->dev.config[I440FX_PAM] >> 4) & 3); |
125 | 84631fd7 | bellard | for(i = 0; i < 12; i++) { |
126 | f2c688bb | Isaku Yamahata | r = (d->dev.config[(i >> 1) + (I440FX_PAM + 1)] >> ((i & 1) * 4)) & 3; |
127 | 84631fd7 | bellard | update_pam(d, 0xc0000 + 0x4000 * i, 0xc0000 + 0x4000 * (i + 1), r); |
128 | ee0ea1d0 | bellard | } |
129 | f2c688bb | Isaku Yamahata | smram = d->dev.config[I440FX_SMRAM]; |
130 | 6c009fa4 | Juan Quintela | if ((d->smm_enabled && (smram & 0x08)) || (smram & 0x40)) { |
131 | 84631fd7 | bellard | cpu_register_physical_memory(0xa0000, 0x20000, 0xa0000); |
132 | 84631fd7 | bellard | } else {
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133 | 84631fd7 | bellard | for(addr = 0xa0000; addr < 0xc0000; addr += 4096) { |
134 | 5fafdf24 | ths | cpu_register_physical_memory(addr, 4096,
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135 | 6c009fa4 | Juan Quintela | d->isa_page_descs[(addr - 0xa0000) >> 12]); |
136 | ee0ea1d0 | bellard | } |
137 | ee0ea1d0 | bellard | } |
138 | ee0ea1d0 | bellard | } |
139 | ee0ea1d0 | bellard | |
140 | f885f1ea | Isaku Yamahata | static void i440fx_set_smm(int val, void *arg) |
141 | ee0ea1d0 | bellard | { |
142 | f885f1ea | Isaku Yamahata | PCII440FXState *d = arg; |
143 | f885f1ea | Isaku Yamahata | |
144 | ee0ea1d0 | bellard | val = (val != 0);
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145 | 6c009fa4 | Juan Quintela | if (d->smm_enabled != val) {
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146 | 6c009fa4 | Juan Quintela | d->smm_enabled = val; |
147 | ee0ea1d0 | bellard | i440fx_update_memory_mappings(d); |
148 | ee0ea1d0 | bellard | } |
149 | ee0ea1d0 | bellard | } |
150 | ee0ea1d0 | bellard | |
151 | ee0ea1d0 | bellard | |
152 | ee0ea1d0 | bellard | /* XXX: suppress when better memory API. We make the assumption that
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153 | ee0ea1d0 | bellard | no device (in particular the VGA) changes the memory mappings in
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154 | ee0ea1d0 | bellard | the 0xa0000-0x100000 range */
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155 | 0a3bacf3 | Juan Quintela | void i440fx_init_memory_mappings(PCII440FXState *d)
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156 | ee0ea1d0 | bellard | { |
157 | ee0ea1d0 | bellard | int i;
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158 | ee0ea1d0 | bellard | for(i = 0; i < 96; i++) { |
159 | 6c009fa4 | Juan Quintela | d->isa_page_descs[i] = cpu_get_physical_page_desc(0xa0000 + i * 0x1000); |
160 | ee0ea1d0 | bellard | } |
161 | ee0ea1d0 | bellard | } |
162 | ee0ea1d0 | bellard | |
163 | 0a3bacf3 | Juan Quintela | static void i440fx_write_config(PCIDevice *dev, |
164 | ee0ea1d0 | bellard | uint32_t address, uint32_t val, int len)
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165 | ee0ea1d0 | bellard | { |
166 | 0a3bacf3 | Juan Quintela | PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev); |
167 | 0a3bacf3 | Juan Quintela | |
168 | ee0ea1d0 | bellard | /* XXX: implement SMRAM.D_LOCK */
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169 | 0a3bacf3 | Juan Quintela | pci_default_write_config(dev, address, val, len); |
170 | 4da5fcd3 | Isaku Yamahata | if (ranges_overlap(address, len, I440FX_PAM, I440FX_PAM_SIZE) ||
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171 | 4da5fcd3 | Isaku Yamahata | range_covers_byte(address, len, I440FX_SMRAM)) { |
172 | ee0ea1d0 | bellard | i440fx_update_memory_mappings(d); |
173 | 4da5fcd3 | Isaku Yamahata | } |
174 | ee0ea1d0 | bellard | } |
175 | ee0ea1d0 | bellard | |
176 | 41445300 | Anthony PERARD | static void i440fx_write_config_xen(PCIDevice *dev, |
177 | 41445300 | Anthony PERARD | uint32_t address, uint32_t val, int len)
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178 | 41445300 | Anthony PERARD | { |
179 | 41445300 | Anthony PERARD | xen_piix_pci_write_config_client(address, val, len); |
180 | 41445300 | Anthony PERARD | i440fx_write_config(dev, address, val, len); |
181 | 41445300 | Anthony PERARD | } |
182 | 41445300 | Anthony PERARD | |
183 | 0c7d19e5 | Juan Quintela | static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id) |
184 | ee0ea1d0 | bellard | { |
185 | 0a3bacf3 | Juan Quintela | PCII440FXState *d = opaque; |
186 | 52fc1d83 | balrog | int ret, i;
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187 | ee0ea1d0 | bellard | |
188 | 0a3bacf3 | Juan Quintela | ret = pci_device_load(&d->dev, f); |
189 | ee0ea1d0 | bellard | if (ret < 0) |
190 | ee0ea1d0 | bellard | return ret;
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191 | ee0ea1d0 | bellard | i440fx_update_memory_mappings(d); |
192 | 6c009fa4 | Juan Quintela | qemu_get_8s(f, &d->smm_enabled); |
193 | 52fc1d83 | balrog | |
194 | e735b55a | Isaku Yamahata | if (version_id == 2) { |
195 | e735b55a | Isaku Yamahata | for (i = 0; i < PIIX_NUM_PIRQS; i++) { |
196 | e735b55a | Isaku Yamahata | qemu_get_be32(f); /* dummy load for compatibility */
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197 | e735b55a | Isaku Yamahata | } |
198 | e735b55a | Isaku Yamahata | } |
199 | 52fc1d83 | balrog | |
200 | ee0ea1d0 | bellard | return 0; |
201 | ee0ea1d0 | bellard | } |
202 | ee0ea1d0 | bellard | |
203 | e59fb374 | Juan Quintela | static int i440fx_post_load(void *opaque, int version_id) |
204 | 0c7d19e5 | Juan Quintela | { |
205 | 0c7d19e5 | Juan Quintela | PCII440FXState *d = opaque; |
206 | 0c7d19e5 | Juan Quintela | |
207 | 0c7d19e5 | Juan Quintela | i440fx_update_memory_mappings(d); |
208 | 0c7d19e5 | Juan Quintela | return 0; |
209 | 0c7d19e5 | Juan Quintela | } |
210 | 0c7d19e5 | Juan Quintela | |
211 | 0c7d19e5 | Juan Quintela | static const VMStateDescription vmstate_i440fx = { |
212 | 0c7d19e5 | Juan Quintela | .name = "I440FX",
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213 | 0c7d19e5 | Juan Quintela | .version_id = 3,
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214 | 0c7d19e5 | Juan Quintela | .minimum_version_id = 3,
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215 | 0c7d19e5 | Juan Quintela | .minimum_version_id_old = 1,
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216 | 0c7d19e5 | Juan Quintela | .load_state_old = i440fx_load_old, |
217 | 752ff2fa | Juan Quintela | .post_load = i440fx_post_load, |
218 | 0c7d19e5 | Juan Quintela | .fields = (VMStateField []) { |
219 | 0c7d19e5 | Juan Quintela | VMSTATE_PCI_DEVICE(dev, PCII440FXState), |
220 | 0c7d19e5 | Juan Quintela | VMSTATE_UINT8(smm_enabled, PCII440FXState), |
221 | 0c7d19e5 | Juan Quintela | VMSTATE_END_OF_LIST() |
222 | 0c7d19e5 | Juan Quintela | } |
223 | 0c7d19e5 | Juan Quintela | }; |
224 | 0c7d19e5 | Juan Quintela | |
225 | 81a322d4 | Gerd Hoffmann | static int i440fx_pcihost_initfn(SysBusDevice *dev) |
226 | 502a5395 | pbrook | { |
227 | 8a14daa5 | Gerd Hoffmann | I440FXState *s = FROM_SYSBUS(I440FXState, dev); |
228 | 502a5395 | pbrook | |
229 | f08b32fe | Isaku Yamahata | pci_host_conf_register_ioport(0xcf8, s);
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230 | 502a5395 | pbrook | |
231 | 4f5e19e6 | Isaku Yamahata | pci_host_data_register_ioport(0xcfc, s);
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232 | 81a322d4 | Gerd Hoffmann | return 0; |
233 | 8a14daa5 | Gerd Hoffmann | } |
234 | 502a5395 | pbrook | |
235 | 0a3bacf3 | Juan Quintela | static int i440fx_initfn(PCIDevice *dev) |
236 | 8a14daa5 | Gerd Hoffmann | { |
237 | 0a3bacf3 | Juan Quintela | PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev); |
238 | ee0ea1d0 | bellard | |
239 | 0a3bacf3 | Juan Quintela | pci_config_set_vendor_id(d->dev.config, PCI_VENDOR_ID_INTEL); |
240 | 0a3bacf3 | Juan Quintela | pci_config_set_device_id(d->dev.config, PCI_DEVICE_ID_INTEL_82441); |
241 | 0a3bacf3 | Juan Quintela | d->dev.config[0x08] = 0x02; // revision |
242 | 0a3bacf3 | Juan Quintela | pci_config_set_class(d->dev.config, PCI_CLASS_BRIDGE_HOST); |
243 | 0a3bacf3 | Juan Quintela | |
244 | f2c688bb | Isaku Yamahata | d->dev.config[I440FX_SMRAM] = 0x02;
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245 | ee0ea1d0 | bellard | |
246 | f885f1ea | Isaku Yamahata | cpu_smm_register(&i440fx_set_smm, d); |
247 | 81a322d4 | Gerd Hoffmann | return 0; |
248 | 8a14daa5 | Gerd Hoffmann | } |
249 | 8a14daa5 | Gerd Hoffmann | |
250 | 41445300 | Anthony PERARD | static PCIBus *i440fx_common_init(const char *device_name, |
251 | 41445300 | Anthony PERARD | PCII440FXState **pi440fx_state, |
252 | 41445300 | Anthony PERARD | int *piix3_devfn,
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253 | 41445300 | Anthony PERARD | qemu_irq *pic, ram_addr_t ram_size) |
254 | 8a14daa5 | Gerd Hoffmann | { |
255 | 8a14daa5 | Gerd Hoffmann | DeviceState *dev; |
256 | 8a14daa5 | Gerd Hoffmann | PCIBus *b; |
257 | 8a14daa5 | Gerd Hoffmann | PCIDevice *d; |
258 | 8a14daa5 | Gerd Hoffmann | I440FXState *s; |
259 | 7cd9eee0 | Gerd Hoffmann | PIIX3State *piix3; |
260 | 8a14daa5 | Gerd Hoffmann | |
261 | 8a14daa5 | Gerd Hoffmann | dev = qdev_create(NULL, "i440FX-pcihost"); |
262 | 8a14daa5 | Gerd Hoffmann | s = FROM_SYSBUS(I440FXState, sysbus_from_qdev(dev)); |
263 | 7cd9eee0 | Gerd Hoffmann | b = pci_bus_new(&s->busdev.qdev, NULL, 0); |
264 | 8a14daa5 | Gerd Hoffmann | s->bus = b; |
265 | e23a1b33 | Markus Armbruster | qdev_init_nofail(dev); |
266 | 8a14daa5 | Gerd Hoffmann | |
267 | 41445300 | Anthony PERARD | d = pci_create_simple(b, 0, device_name);
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268 | 0a3bacf3 | Juan Quintela | *pi440fx_state = DO_UPCAST(PCII440FXState, dev, d); |
269 | 8a14daa5 | Gerd Hoffmann | |
270 | 7cd9eee0 | Gerd Hoffmann | piix3 = DO_UPCAST(PIIX3State, dev, |
271 | fecb93c4 | Isaku Yamahata | pci_create_simple_multifunction(b, -1, true, "PIIX3")); |
272 | 7cd9eee0 | Gerd Hoffmann | piix3->pic = pic; |
273 | 41445300 | Anthony PERARD | |
274 | 7cd9eee0 | Gerd Hoffmann | (*pi440fx_state)->piix3 = piix3; |
275 | 7cd9eee0 | Gerd Hoffmann | |
276 | 7cd9eee0 | Gerd Hoffmann | *piix3_devfn = piix3->dev.devfn; |
277 | 85a750ca | Juan Quintela | |
278 | ec5f92ce | Bernhard M. Wiedemann | ram_size = ram_size / 8 / 1024 / 1024; |
279 | ec5f92ce | Bernhard M. Wiedemann | if (ram_size > 255) |
280 | ec5f92ce | Bernhard M. Wiedemann | ram_size = 255;
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281 | ec5f92ce | Bernhard M. Wiedemann | (*pi440fx_state)->dev.config[0x57]=ram_size;
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282 | ec5f92ce | Bernhard M. Wiedemann | |
283 | 502a5395 | pbrook | return b;
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284 | 502a5395 | pbrook | } |
285 | 502a5395 | pbrook | |
286 | 41445300 | Anthony PERARD | PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix3_devfn,
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287 | 41445300 | Anthony PERARD | qemu_irq *pic, ram_addr_t ram_size) |
288 | 41445300 | Anthony PERARD | { |
289 | 41445300 | Anthony PERARD | PCIBus *b; |
290 | 41445300 | Anthony PERARD | |
291 | 41445300 | Anthony PERARD | b = i440fx_common_init("i440FX", pi440fx_state, piix3_devfn, pic, ram_size);
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292 | 41445300 | Anthony PERARD | pci_bus_irqs(b, piix3_set_irq, pci_slot_get_pirq, (*pi440fx_state)->piix3, |
293 | 41445300 | Anthony PERARD | PIIX_NUM_PIRQS); |
294 | 41445300 | Anthony PERARD | |
295 | 41445300 | Anthony PERARD | return b;
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296 | 41445300 | Anthony PERARD | } |
297 | 41445300 | Anthony PERARD | |
298 | 41445300 | Anthony PERARD | PCIBus *i440fx_xen_init(PCII440FXState **pi440fx_state, int *piix3_devfn,
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299 | 41445300 | Anthony PERARD | qemu_irq *pic, ram_addr_t ram_size) |
300 | 41445300 | Anthony PERARD | { |
301 | 41445300 | Anthony PERARD | PCIBus *b; |
302 | 41445300 | Anthony PERARD | |
303 | 41445300 | Anthony PERARD | b = i440fx_common_init("i440FX-xen", pi440fx_state, piix3_devfn, pic, ram_size);
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304 | 41445300 | Anthony PERARD | pci_bus_irqs(b, xen_piix3_set_irq, xen_pci_slot_get_pirq, |
305 | 41445300 | Anthony PERARD | (*pi440fx_state)->piix3, PIIX_NUM_PIRQS); |
306 | 41445300 | Anthony PERARD | |
307 | 41445300 | Anthony PERARD | return b;
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308 | 41445300 | Anthony PERARD | } |
309 | 41445300 | Anthony PERARD | |
310 | 502a5395 | pbrook | /* PIIX3 PCI to ISA bridge */
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311 | ab431c28 | Isaku Yamahata | static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq) |
312 | ab431c28 | Isaku Yamahata | { |
313 | ab431c28 | Isaku Yamahata | qemu_set_irq(piix3->pic[pic_irq], |
314 | ab431c28 | Isaku Yamahata | !!(piix3->pic_levels & |
315 | 09de0f46 | TeLeMan | (((1ULL << PIIX_NUM_PIRQS) - 1) << |
316 | ab431c28 | Isaku Yamahata | (pic_irq * PIIX_NUM_PIRQS)))); |
317 | ab431c28 | Isaku Yamahata | } |
318 | 502a5395 | pbrook | |
319 | afe3ef1d | Isaku Yamahata | static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level) |
320 | ab431c28 | Isaku Yamahata | { |
321 | ab431c28 | Isaku Yamahata | int pic_irq;
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322 | ab431c28 | Isaku Yamahata | uint64_t mask; |
323 | ab431c28 | Isaku Yamahata | |
324 | ab431c28 | Isaku Yamahata | pic_irq = piix3->dev.config[PIIX_PIRQC + pirq]; |
325 | ab431c28 | Isaku Yamahata | if (pic_irq >= PIIX_NUM_PIC_IRQS) {
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326 | ab431c28 | Isaku Yamahata | return;
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327 | ab431c28 | Isaku Yamahata | } |
328 | ab431c28 | Isaku Yamahata | |
329 | ab431c28 | Isaku Yamahata | mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq);
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330 | ab431c28 | Isaku Yamahata | piix3->pic_levels &= ~mask; |
331 | ab431c28 | Isaku Yamahata | piix3->pic_levels |= mask * !!level; |
332 | ab431c28 | Isaku Yamahata | |
333 | afe3ef1d | Isaku Yamahata | piix3_set_irq_pic(piix3, pic_irq); |
334 | ab431c28 | Isaku Yamahata | } |
335 | ab431c28 | Isaku Yamahata | |
336 | ab431c28 | Isaku Yamahata | static void piix3_set_irq(void *opaque, int pirq, int level) |
337 | 502a5395 | pbrook | { |
338 | 7cd9eee0 | Gerd Hoffmann | PIIX3State *piix3 = opaque; |
339 | afe3ef1d | Isaku Yamahata | piix3_set_irq_level(piix3, pirq, level); |
340 | ab431c28 | Isaku Yamahata | } |
341 | 502a5395 | pbrook | |
342 | ab431c28 | Isaku Yamahata | /* irq routing is changed. so rebuild bitmap */
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343 | ab431c28 | Isaku Yamahata | static void piix3_update_irq_levels(PIIX3State *piix3) |
344 | ab431c28 | Isaku Yamahata | { |
345 | ab431c28 | Isaku Yamahata | int pirq;
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346 | ab431c28 | Isaku Yamahata | |
347 | ab431c28 | Isaku Yamahata | piix3->pic_levels = 0;
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348 | ab431c28 | Isaku Yamahata | for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) { |
349 | ab431c28 | Isaku Yamahata | piix3_set_irq_level(piix3, pirq, |
350 | afe3ef1d | Isaku Yamahata | pci_bus_get_irq_level(piix3->dev.bus, pirq)); |
351 | ab431c28 | Isaku Yamahata | } |
352 | ab431c28 | Isaku Yamahata | } |
353 | ab431c28 | Isaku Yamahata | |
354 | ab431c28 | Isaku Yamahata | static void piix3_write_config(PCIDevice *dev, |
355 | ab431c28 | Isaku Yamahata | uint32_t address, uint32_t val, int len)
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356 | ab431c28 | Isaku Yamahata | { |
357 | ab431c28 | Isaku Yamahata | pci_default_write_config(dev, address, val, len); |
358 | ab431c28 | Isaku Yamahata | if (ranges_overlap(address, len, PIIX_PIRQC, 4)) { |
359 | ab431c28 | Isaku Yamahata | PIIX3State *piix3 = DO_UPCAST(PIIX3State, dev, dev); |
360 | ab431c28 | Isaku Yamahata | int pic_irq;
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361 | ab431c28 | Isaku Yamahata | piix3_update_irq_levels(piix3); |
362 | ab431c28 | Isaku Yamahata | for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) { |
363 | ab431c28 | Isaku Yamahata | piix3_set_irq_pic(piix3, pic_irq); |
364 | d2b59317 | pbrook | } |
365 | 502a5395 | pbrook | } |
366 | 502a5395 | pbrook | } |
367 | 502a5395 | pbrook | |
368 | 15a1956a | Gleb Natapov | static void piix3_reset(void *opaque) |
369 | 502a5395 | pbrook | { |
370 | fd37d881 | Juan Quintela | PIIX3State *d = opaque; |
371 | fd37d881 | Juan Quintela | uint8_t *pci_conf = d->dev.config; |
372 | 502a5395 | pbrook | |
373 | 502a5395 | pbrook | pci_conf[0x04] = 0x07; // master, memory and I/O |
374 | 502a5395 | pbrook | pci_conf[0x05] = 0x00; |
375 | 502a5395 | pbrook | pci_conf[0x06] = 0x00; |
376 | 502a5395 | pbrook | pci_conf[0x07] = 0x02; // PCI_status_devsel_medium |
377 | 502a5395 | pbrook | pci_conf[0x4c] = 0x4d; |
378 | 502a5395 | pbrook | pci_conf[0x4e] = 0x03; |
379 | 502a5395 | pbrook | pci_conf[0x4f] = 0x00; |
380 | 502a5395 | pbrook | pci_conf[0x60] = 0x80; |
381 | 477afee3 | aurel32 | pci_conf[0x61] = 0x80; |
382 | 477afee3 | aurel32 | pci_conf[0x62] = 0x80; |
383 | 477afee3 | aurel32 | pci_conf[0x63] = 0x80; |
384 | 502a5395 | pbrook | pci_conf[0x69] = 0x02; |
385 | 502a5395 | pbrook | pci_conf[0x70] = 0x80; |
386 | 502a5395 | pbrook | pci_conf[0x76] = 0x0c; |
387 | 502a5395 | pbrook | pci_conf[0x77] = 0x0c; |
388 | 502a5395 | pbrook | pci_conf[0x78] = 0x02; |
389 | 502a5395 | pbrook | pci_conf[0x79] = 0x00; |
390 | 502a5395 | pbrook | pci_conf[0x80] = 0x00; |
391 | 502a5395 | pbrook | pci_conf[0x82] = 0x00; |
392 | 502a5395 | pbrook | pci_conf[0xa0] = 0x08; |
393 | 502a5395 | pbrook | pci_conf[0xa2] = 0x00; |
394 | 502a5395 | pbrook | pci_conf[0xa3] = 0x00; |
395 | 502a5395 | pbrook | pci_conf[0xa4] = 0x00; |
396 | 502a5395 | pbrook | pci_conf[0xa5] = 0x00; |
397 | 502a5395 | pbrook | pci_conf[0xa6] = 0x00; |
398 | 502a5395 | pbrook | pci_conf[0xa7] = 0x00; |
399 | 502a5395 | pbrook | pci_conf[0xa8] = 0x0f; |
400 | 502a5395 | pbrook | pci_conf[0xaa] = 0x00; |
401 | 502a5395 | pbrook | pci_conf[0xab] = 0x00; |
402 | 502a5395 | pbrook | pci_conf[0xac] = 0x00; |
403 | 502a5395 | pbrook | pci_conf[0xae] = 0x00; |
404 | ab431c28 | Isaku Yamahata | |
405 | ab431c28 | Isaku Yamahata | d->pic_levels = 0;
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406 | ab431c28 | Isaku Yamahata | } |
407 | ab431c28 | Isaku Yamahata | |
408 | ab431c28 | Isaku Yamahata | static int piix3_post_load(void *opaque, int version_id) |
409 | ab431c28 | Isaku Yamahata | { |
410 | ab431c28 | Isaku Yamahata | PIIX3State *piix3 = opaque; |
411 | ab431c28 | Isaku Yamahata | piix3_update_irq_levels(piix3); |
412 | ab431c28 | Isaku Yamahata | return 0; |
413 | e735b55a | Isaku Yamahata | } |
414 | 15a1956a | Gleb Natapov | |
415 | e735b55a | Isaku Yamahata | static void piix3_pre_save(void *opaque) |
416 | e735b55a | Isaku Yamahata | { |
417 | e735b55a | Isaku Yamahata | int i;
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418 | e735b55a | Isaku Yamahata | PIIX3State *piix3 = opaque; |
419 | e735b55a | Isaku Yamahata | |
420 | e735b55a | Isaku Yamahata | for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) { |
421 | e735b55a | Isaku Yamahata | piix3->pci_irq_levels_vmstate[i] = |
422 | e735b55a | Isaku Yamahata | pci_bus_get_irq_level(piix3->dev.bus, i); |
423 | e735b55a | Isaku Yamahata | } |
424 | 502a5395 | pbrook | } |
425 | 502a5395 | pbrook | |
426 | d1f171bd | Juan Quintela | static const VMStateDescription vmstate_piix3 = { |
427 | d1f171bd | Juan Quintela | .name = "PIIX3",
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428 | d1f171bd | Juan Quintela | .version_id = 3,
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429 | d1f171bd | Juan Quintela | .minimum_version_id = 2,
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430 | d1f171bd | Juan Quintela | .minimum_version_id_old = 2,
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431 | ab431c28 | Isaku Yamahata | .post_load = piix3_post_load, |
432 | e735b55a | Isaku Yamahata | .pre_save = piix3_pre_save, |
433 | d1f171bd | Juan Quintela | .fields = (VMStateField []) { |
434 | d1f171bd | Juan Quintela | VMSTATE_PCI_DEVICE(dev, PIIX3State), |
435 | e735b55a | Isaku Yamahata | VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State, |
436 | e735b55a | Isaku Yamahata | PIIX_NUM_PIRQS, 3),
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437 | d1f171bd | Juan Quintela | VMSTATE_END_OF_LIST() |
438 | da64182c | Juan Quintela | } |
439 | d1f171bd | Juan Quintela | }; |
440 | 1941d19c | bellard | |
441 | fd37d881 | Juan Quintela | static int piix3_initfn(PCIDevice *dev) |
442 | 502a5395 | pbrook | { |
443 | fd37d881 | Juan Quintela | PIIX3State *d = DO_UPCAST(PIIX3State, dev, dev); |
444 | 502a5395 | pbrook | uint8_t *pci_conf; |
445 | 502a5395 | pbrook | |
446 | fd37d881 | Juan Quintela | isa_bus_new(&d->dev.qdev); |
447 | 502a5395 | pbrook | |
448 | fd37d881 | Juan Quintela | pci_conf = d->dev.config; |
449 | deb54399 | aliguori | pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL); |
450 | deb54399 | aliguori | pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371SB_0); // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
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451 | 173a543b | blueswir1 | pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_ISA); |
452 | 502a5395 | pbrook | |
453 | a08d4367 | Jan Kiszka | qemu_register_reset(piix3_reset, d); |
454 | 81a322d4 | Gerd Hoffmann | return 0; |
455 | 502a5395 | pbrook | } |
456 | 5c2b87e3 | ths | |
457 | 8a14daa5 | Gerd Hoffmann | static PCIDeviceInfo i440fx_info[] = {
|
458 | 8a14daa5 | Gerd Hoffmann | { |
459 | 8a14daa5 | Gerd Hoffmann | .qdev.name = "i440FX",
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460 | 8a14daa5 | Gerd Hoffmann | .qdev.desc = "Host bridge",
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461 | 0a3bacf3 | Juan Quintela | .qdev.size = sizeof(PCII440FXState),
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462 | be73cfe2 | Juan Quintela | .qdev.vmsd = &vmstate_i440fx, |
463 | 8a14daa5 | Gerd Hoffmann | .qdev.no_user = 1,
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464 | 0965f12d | Gerd Hoffmann | .no_hotplug = 1,
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465 | 8a14daa5 | Gerd Hoffmann | .init = i440fx_initfn, |
466 | 8a14daa5 | Gerd Hoffmann | .config_write = i440fx_write_config, |
467 | 8a14daa5 | Gerd Hoffmann | },{ |
468 | 41445300 | Anthony PERARD | .qdev.name = "i440FX-xen",
|
469 | 41445300 | Anthony PERARD | .qdev.desc = "Host bridge",
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470 | 41445300 | Anthony PERARD | .qdev.size = sizeof(PCII440FXState),
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471 | 41445300 | Anthony PERARD | .qdev.vmsd = &vmstate_i440fx, |
472 | 41445300 | Anthony PERARD | .qdev.no_user = 1,
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473 | 41445300 | Anthony PERARD | .init = i440fx_initfn, |
474 | 41445300 | Anthony PERARD | .config_write = i440fx_write_config_xen, |
475 | 41445300 | Anthony PERARD | },{ |
476 | 8a14daa5 | Gerd Hoffmann | .qdev.name = "PIIX3",
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477 | 8a14daa5 | Gerd Hoffmann | .qdev.desc = "ISA bridge",
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478 | fd37d881 | Juan Quintela | .qdev.size = sizeof(PIIX3State),
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479 | be73cfe2 | Juan Quintela | .qdev.vmsd = &vmstate_piix3, |
480 | 8a14daa5 | Gerd Hoffmann | .qdev.no_user = 1,
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481 | 0965f12d | Gerd Hoffmann | .no_hotplug = 1,
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482 | 8a14daa5 | Gerd Hoffmann | .init = piix3_initfn, |
483 | ab431c28 | Isaku Yamahata | .config_write = piix3_write_config, |
484 | 8a14daa5 | Gerd Hoffmann | },{ |
485 | 8a14daa5 | Gerd Hoffmann | /* end of list */
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486 | 8a14daa5 | Gerd Hoffmann | } |
487 | 8a14daa5 | Gerd Hoffmann | }; |
488 | 8a14daa5 | Gerd Hoffmann | |
489 | 8a14daa5 | Gerd Hoffmann | static SysBusDeviceInfo i440fx_pcihost_info = {
|
490 | 8a14daa5 | Gerd Hoffmann | .init = i440fx_pcihost_initfn, |
491 | 8a14daa5 | Gerd Hoffmann | .qdev.name = "i440FX-pcihost",
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492 | 779206de | Gleb Natapov | .qdev.fw_name = "pci",
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493 | 8a14daa5 | Gerd Hoffmann | .qdev.size = sizeof(I440FXState),
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494 | 8a14daa5 | Gerd Hoffmann | .qdev.no_user = 1,
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495 | 8a14daa5 | Gerd Hoffmann | }; |
496 | 8a14daa5 | Gerd Hoffmann | |
497 | 8a14daa5 | Gerd Hoffmann | static void i440fx_register(void) |
498 | 8a14daa5 | Gerd Hoffmann | { |
499 | 8a14daa5 | Gerd Hoffmann | sysbus_register_withprop(&i440fx_pcihost_info); |
500 | 8a14daa5 | Gerd Hoffmann | pci_qdev_register_many(i440fx_info); |
501 | 8a14daa5 | Gerd Hoffmann | } |
502 | 8a14daa5 | Gerd Hoffmann | device_init(i440fx_register); |