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1 | 94a420b1 | Stefan Hajnoczi | # Trace events for debugging and performance instrumentation |
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2 | 94a420b1 | Stefan Hajnoczi | # |
3 | 94a420b1 | Stefan Hajnoczi | # This file is processed by the tracetool script during the build. |
4 | 94a420b1 | Stefan Hajnoczi | # |
5 | 94a420b1 | Stefan Hajnoczi | # To add a new trace event: |
6 | 94a420b1 | Stefan Hajnoczi | # |
7 | 94a420b1 | Stefan Hajnoczi | # 1. Choose a name for the trace event. Declare its arguments and format |
8 | 94a420b1 | Stefan Hajnoczi | # string. |
9 | 94a420b1 | Stefan Hajnoczi | # |
10 | 94a420b1 | Stefan Hajnoczi | # 2. Call the trace event from code using trace_##name, e.g. multiwrite_cb() -> |
11 | 94a420b1 | Stefan Hajnoczi | # trace_multiwrite_cb(). The source file must #include "trace.h". |
12 | 94a420b1 | Stefan Hajnoczi | # |
13 | 94a420b1 | Stefan Hajnoczi | # Format of a trace event: |
14 | 94a420b1 | Stefan Hajnoczi | # |
15 | 1e2cf2bc | Stefan Hajnoczi | # [disable] <name>(<type1> <arg1>[, <type2> <arg2>] ...) "<format-string>" |
16 | 94a420b1 | Stefan Hajnoczi | # |
17 | 94a420b1 | Stefan Hajnoczi | # Example: qemu_malloc(size_t size) "size %zu" |
18 | 94a420b1 | Stefan Hajnoczi | # |
19 | 1e2cf2bc | Stefan Hajnoczi | # The "disable" keyword will build without the trace event. |
20 | 1e2cf2bc | Stefan Hajnoczi | # In case of 'simple' trace backend, it will allow the trace event to be |
21 | 1e2cf2bc | Stefan Hajnoczi | # compiled, but this would be turned off by default. It can be toggled on via |
22 | 1e2cf2bc | Stefan Hajnoczi | # the monitor. |
23 | 1e2cf2bc | Stefan Hajnoczi | # |
24 | 94a420b1 | Stefan Hajnoczi | # The <name> must be a valid as a C function name. |
25 | 94a420b1 | Stefan Hajnoczi | # |
26 | 94a420b1 | Stefan Hajnoczi | # Types should be standard C types. Use void * for pointers because the trace |
27 | 94a420b1 | Stefan Hajnoczi | # system may not have the necessary headers included. |
28 | 94a420b1 | Stefan Hajnoczi | # |
29 | 94a420b1 | Stefan Hajnoczi | # The <format-string> should be a sprintf()-compatible format string. |
30 | cd245a19 | Stefan Hajnoczi | |
31 | cd245a19 | Stefan Hajnoczi | # qemu-malloc.c |
32 | cd245a19 | Stefan Hajnoczi | disable qemu_malloc(size_t size, void *ptr) "size %zu ptr %p" |
33 | cd245a19 | Stefan Hajnoczi | disable qemu_realloc(void *ptr, size_t size, void *newptr) "ptr %p size %zu newptr %p" |
34 | cd245a19 | Stefan Hajnoczi | disable qemu_free(void *ptr) "ptr %p" |
35 | cd245a19 | Stefan Hajnoczi | |
36 | cd245a19 | Stefan Hajnoczi | # osdep.c |
37 | cd245a19 | Stefan Hajnoczi | disable qemu_memalign(size_t alignment, size_t size, void *ptr) "alignment %zu size %zu ptr %p" |
38 | dda85211 | Blue Swirl | disable qemu_vmalloc(size_t size, void *ptr) "size %zu ptr %p" |
39 | cd245a19 | Stefan Hajnoczi | disable qemu_vfree(void *ptr) "ptr %p" |
40 | 6d519a5f | Stefan Hajnoczi | |
41 | 64979a4d | Stefan Hajnoczi | # hw/virtio.c |
42 | 64979a4d | Stefan Hajnoczi | disable virtqueue_fill(void *vq, const void *elem, unsigned int len, unsigned int idx) "vq %p elem %p len %u idx %u" |
43 | 64979a4d | Stefan Hajnoczi | disable virtqueue_flush(void *vq, unsigned int count) "vq %p count %u" |
44 | 64979a4d | Stefan Hajnoczi | disable virtqueue_pop(void *vq, void *elem, unsigned int in_num, unsigned int out_num) "vq %p elem %p in_num %u out_num %u" |
45 | 64979a4d | Stefan Hajnoczi | disable virtio_queue_notify(void *vdev, int n, void *vq) "vdev %p n %d vq %p" |
46 | 64979a4d | Stefan Hajnoczi | disable virtio_irq(void *vq) "vq %p" |
47 | 64979a4d | Stefan Hajnoczi | disable virtio_notify(void *vdev, void *vq) "vdev %p vq %p" |
48 | 64979a4d | Stefan Hajnoczi | |
49 | 6d519a5f | Stefan Hajnoczi | # block.c |
50 | 6d519a5f | Stefan Hajnoczi | disable multiwrite_cb(void *mcb, int ret) "mcb %p ret %d" |
51 | 6d519a5f | Stefan Hajnoczi | disable bdrv_aio_multiwrite(void *mcb, int num_callbacks, int num_reqs) "mcb %p num_callbacks %d num_reqs %d" |
52 | 6d519a5f | Stefan Hajnoczi | disable bdrv_aio_multiwrite_earlyfail(void *mcb) "mcb %p" |
53 | 6d519a5f | Stefan Hajnoczi | disable bdrv_aio_multiwrite_latefail(void *mcb, int i) "mcb %p i %d" |
54 | bbf0a440 | Stefan Hajnoczi | disable bdrv_aio_readv(void *bs, int64_t sector_num, int nb_sectors, void *opaque) "bs %p sector_num %"PRId64" nb_sectors %d opaque %p" |
55 | bbf0a440 | Stefan Hajnoczi | disable bdrv_aio_writev(void *bs, int64_t sector_num, int nb_sectors, void *opaque) "bs %p sector_num %"PRId64" nb_sectors %d opaque %p" |
56 | 6d519a5f | Stefan Hajnoczi | |
57 | 6d519a5f | Stefan Hajnoczi | # hw/virtio-blk.c |
58 | 6d519a5f | Stefan Hajnoczi | disable virtio_blk_req_complete(void *req, int status) "req %p status %d" |
59 | 6d519a5f | Stefan Hajnoczi | disable virtio_blk_rw_complete(void *req, int ret) "req %p ret %d" |
60 | 9a85d394 | Stefan Hajnoczi | disable virtio_blk_handle_write(void *req, uint64_t sector, size_t nsectors) "req %p sector %"PRIu64" nsectors %zu" |
61 | 6d519a5f | Stefan Hajnoczi | |
62 | 6d519a5f | Stefan Hajnoczi | # posix-aio-compat.c |
63 | 9a85d394 | Stefan Hajnoczi | disable paio_submit(void *acb, void *opaque, int64_t sector_num, int nb_sectors, int type) "acb %p opaque %p sector_num %"PRId64" nb_sectors %d type %d" |
64 | bd3c9aa5 | Prerna Saxena | |
65 | bd3c9aa5 | Prerna Saxena | # ioport.c |
66 | bd3c9aa5 | Prerna Saxena | disable cpu_in(unsigned int addr, unsigned int val) "addr %#x value %u" |
67 | bd3c9aa5 | Prerna Saxena | disable cpu_out(unsigned int addr, unsigned int val) "addr %#x value %u" |
68 | 62dd89de | Prerna Saxena | |
69 | 62dd89de | Prerna Saxena | # balloon.c |
70 | 62dd89de | Prerna Saxena | # Since requests are raised via monitor, not many tracepoints are needed. |
71 | 62dd89de | Prerna Saxena | disable balloon_event(void *opaque, unsigned long addr) "opaque %p addr %lu" |
72 | d8023f31 | Blue Swirl | |
73 | d8023f31 | Blue Swirl | # hw/apic.c |
74 | d8023f31 | Blue Swirl | disable apic_local_deliver(int vector, uint32_t lvt) "vector %d delivery mode %d" |
75 | d8023f31 | Blue Swirl | disable apic_deliver_irq(uint8_t dest, uint8_t dest_mode, uint8_t delivery_mode, uint8_t vector_num, uint8_t polarity, uint8_t trigger_mode) "dest %d dest_mode %d delivery_mode %d vector %d polarity %d trigger_mode %d" |
76 | d8023f31 | Blue Swirl | disable cpu_set_apic_base(uint64_t val) "%016"PRIx64"" |
77 | d8023f31 | Blue Swirl | disable cpu_get_apic_base(uint64_t val) "%016"PRIx64"" |
78 | d8023f31 | Blue Swirl | disable apic_mem_readl(uint64_t addr, uint32_t val) "%"PRIx64" = %08x" |
79 | d8023f31 | Blue Swirl | disable apic_mem_writel(uint64_t addr, uint32_t val) "%"PRIx64" = %08x" |
80 | d8023f31 | Blue Swirl | # coalescing |
81 | d8023f31 | Blue Swirl | disable apic_reset_irq_delivered(int apic_irq_delivered) "old coalescing %d" |
82 | d8023f31 | Blue Swirl | disable apic_get_irq_delivered(int apic_irq_delivered) "returning coalescing %d" |
83 | d8023f31 | Blue Swirl | disable apic_set_irq(int apic_irq_delivered) "coalescing %d" |
84 | 97bf4851 | Blue Swirl | |
85 | 97bf4851 | Blue Swirl | # hw/cs4231.c |
86 | 97bf4851 | Blue Swirl | disable cs4231_mem_readl_dreg(uint32_t reg, uint32_t ret) "read dreg %d: 0x%02x" |
87 | 97bf4851 | Blue Swirl | disable cs4231_mem_readl_reg(uint32_t reg, uint32_t ret) "read reg %d: 0x%08x" |
88 | 97bf4851 | Blue Swirl | disable cs4231_mem_writel_reg(uint32_t reg, uint32_t old, uint32_t val) "write reg %d: 0x%08x -> 0x%08x" |
89 | 97bf4851 | Blue Swirl | disable cs4231_mem_writel_dreg(uint32_t reg, uint32_t old, uint32_t val) "write dreg %d: 0x%02x -> 0x%02x" |
90 | 97bf4851 | Blue Swirl | |
91 | 97bf4851 | Blue Swirl | # hw/eccmemctl.c |
92 | 97bf4851 | Blue Swirl | disable ecc_mem_writel_mer(uint32_t val) "Write memory enable %08x" |
93 | 97bf4851 | Blue Swirl | disable ecc_mem_writel_mdr(uint32_t val) "Write memory delay %08x" |
94 | 97bf4851 | Blue Swirl | disable ecc_mem_writel_mfsr(uint32_t val) "Write memory fault status %08x" |
95 | 97bf4851 | Blue Swirl | disable ecc_mem_writel_vcr(uint32_t val) "Write slot configuration %08x" |
96 | 97bf4851 | Blue Swirl | disable ecc_mem_writel_dr(uint32_t val) "Write diagnostic %08x" |
97 | 97bf4851 | Blue Swirl | disable ecc_mem_writel_ecr0(uint32_t val) "Write event count 1 %08x" |
98 | 97bf4851 | Blue Swirl | disable ecc_mem_writel_ecr1(uint32_t val) "Write event count 2 %08x" |
99 | 97bf4851 | Blue Swirl | disable ecc_mem_readl_mer(uint32_t ret) "Read memory enable %08x" |
100 | 97bf4851 | Blue Swirl | disable ecc_mem_readl_mdr(uint32_t ret) "Read memory delay %08x" |
101 | 97bf4851 | Blue Swirl | disable ecc_mem_readl_mfsr(uint32_t ret) "Read memory fault status %08x" |
102 | 97bf4851 | Blue Swirl | disable ecc_mem_readl_vcr(uint32_t ret) "Read slot configuration %08x" |
103 | 97bf4851 | Blue Swirl | disable ecc_mem_readl_mfar0(uint32_t ret) "Read memory fault address 0 %08x" |
104 | 97bf4851 | Blue Swirl | disable ecc_mem_readl_mfar1(uint32_t ret) "Read memory fault address 1 %08x" |
105 | 97bf4851 | Blue Swirl | disable ecc_mem_readl_dr(uint32_t ret) "Read diagnostic %08x" |
106 | 97bf4851 | Blue Swirl | disable ecc_mem_readl_ecr0(uint32_t ret) "Read event count 1 %08x" |
107 | 97bf4851 | Blue Swirl | disable ecc_mem_readl_ecr1(uint32_t ret) "Read event count 2 %08x" |
108 | 97bf4851 | Blue Swirl | disable ecc_diag_mem_writeb(uint64_t addr, uint32_t val) "Write diagnostic %"PRId64" = %02x" |
109 | 97bf4851 | Blue Swirl | disable ecc_diag_mem_readb(uint64_t addr, uint32_t ret) "Read diagnostic %"PRId64"= %02x" |
110 | 97bf4851 | Blue Swirl | |
111 | 97bf4851 | Blue Swirl | # hw/lance.c |
112 | 97bf4851 | Blue Swirl | disable lance_mem_readw(uint64_t addr, uint32_t ret) "addr=%"PRIx64"val=0x%04x" |
113 | 97bf4851 | Blue Swirl | disable lance_mem_writew(uint64_t addr, uint32_t val) "addr=%"PRIx64"val=0x%04x" |
114 | 97bf4851 | Blue Swirl | |
115 | 97bf4851 | Blue Swirl | # hw/slavio_intctl.c |
116 | 97bf4851 | Blue Swirl | disable slavio_intctl_mem_readl(uint32_t cpu, uint64_t addr, uint32_t ret) "read cpu %d reg 0x%"PRIx64" = %x" |
117 | 97bf4851 | Blue Swirl | disable slavio_intctl_mem_writel(uint32_t cpu, uint64_t addr, uint32_t val) "write cpu %d reg 0x%"PRIx64" = %x" |
118 | 97bf4851 | Blue Swirl | disable slavio_intctl_mem_writel_clear(uint32_t cpu, uint32_t val, uint32_t intreg_pending) "Cleared cpu %d irq mask %x, curmask %x" |
119 | 97bf4851 | Blue Swirl | disable slavio_intctl_mem_writel_set(uint32_t cpu, uint32_t val, uint32_t intreg_pending) "Set cpu %d irq mask %x, curmask %x" |
120 | 97bf4851 | Blue Swirl | disable slavio_intctlm_mem_readl(uint64_t addr, uint32_t ret) "read system reg 0x%"PRIx64" = %x" |
121 | 97bf4851 | Blue Swirl | disable slavio_intctlm_mem_writel(uint64_t addr, uint32_t val) "write system reg 0x%"PRIx64" = %x" |
122 | 97bf4851 | Blue Swirl | disable slavio_intctlm_mem_writel_enable(uint32_t val, uint32_t intregm_disabled) "Enabled master irq mask %x, curmask %x" |
123 | 97bf4851 | Blue Swirl | disable slavio_intctlm_mem_writel_disable(uint32_t val, uint32_t intregm_disabled) "Disabled master irq mask %x, curmask %x" |
124 | 97bf4851 | Blue Swirl | disable slavio_intctlm_mem_writel_target(uint32_t cpu) "Set master irq cpu %d" |
125 | 97bf4851 | Blue Swirl | disable slavio_check_interrupts(uint32_t pending, uint32_t intregm_disabled) "pending %x disabled %x" |
126 | 97bf4851 | Blue Swirl | disable slavio_set_irq(uint32_t target_cpu, int irq, uint32_t pil, int level) "Set cpu %d irq %d -> pil %d level %d" |
127 | 97bf4851 | Blue Swirl | disable slavio_set_timer_irq_cpu(int cpu, int level) "Set cpu %d local timer level %d" |
128 | 97bf4851 | Blue Swirl | |
129 | 97bf4851 | Blue Swirl | # hw/slavio_misc.c |
130 | 97bf4851 | Blue Swirl | disable slavio_misc_update_irq_raise(void) "Raise IRQ" |
131 | 97bf4851 | Blue Swirl | disable slavio_misc_update_irq_lower(void) "Lower IRQ" |
132 | 97bf4851 | Blue Swirl | disable slavio_set_power_fail(int power_failing, uint8_t config) "Power fail: %d, config: %d" |
133 | 97bf4851 | Blue Swirl | disable slavio_cfg_mem_writeb(uint32_t val) "Write config %02x" |
134 | 97bf4851 | Blue Swirl | disable slavio_cfg_mem_readb(uint32_t ret) "Read config %02x" |
135 | 97bf4851 | Blue Swirl | disable slavio_diag_mem_writeb(uint32_t val) "Write diag %02x" |
136 | 97bf4851 | Blue Swirl | disable slavio_diag_mem_readb(uint32_t ret) "Read diag %02x" |
137 | 97bf4851 | Blue Swirl | disable slavio_mdm_mem_writeb(uint32_t val) "Write modem control %02x" |
138 | 97bf4851 | Blue Swirl | disable slavio_mdm_mem_readb(uint32_t ret) "Read modem control %02x" |
139 | 97bf4851 | Blue Swirl | disable slavio_aux1_mem_writeb(uint32_t val) "Write aux1 %02x" |
140 | 97bf4851 | Blue Swirl | disable slavio_aux1_mem_readb(uint32_t ret) "Read aux1 %02x" |
141 | 97bf4851 | Blue Swirl | disable slavio_aux2_mem_writeb(uint32_t val) "Write aux2 %02x" |
142 | 97bf4851 | Blue Swirl | disable slavio_aux2_mem_readb(uint32_t ret) "Read aux2 %02x" |
143 | 97bf4851 | Blue Swirl | disable apc_mem_writeb(uint32_t val) "Write power management %02x" |
144 | 97bf4851 | Blue Swirl | disable apc_mem_readb(uint32_t ret) "Read power management %02x" |
145 | 97bf4851 | Blue Swirl | disable slavio_sysctrl_mem_writel(uint32_t val) "Write system control %08x" |
146 | 97bf4851 | Blue Swirl | disable slavio_sysctrl_mem_readl(uint32_t ret) "Read system control %08x" |
147 | 97bf4851 | Blue Swirl | disable slavio_led_mem_writew(uint32_t val) "Write diagnostic LED %04x" |
148 | 97bf4851 | Blue Swirl | disable slavio_led_mem_readw(uint32_t ret) "Read diagnostic LED %04x" |
149 | 97bf4851 | Blue Swirl | |
150 | 97bf4851 | Blue Swirl | # hw/slavio_timer.c |
151 | 97bf4851 | Blue Swirl | disable slavio_timer_get_out(uint64_t limit, uint32_t counthigh, uint32_t count) "limit %"PRIx64" count %x%08x" |
152 | 97bf4851 | Blue Swirl | disable slavio_timer_irq(uint32_t counthigh, uint32_t count) "callback: count %x%08x" |
153 | 97bf4851 | Blue Swirl | disable slavio_timer_mem_readl_invalid(uint64_t addr) "invalid read address %"PRIx64"" |
154 | 97bf4851 | Blue Swirl | disable slavio_timer_mem_readl(uint64_t addr, uint32_t ret) "read %"PRIx64" = %08x" |
155 | 97bf4851 | Blue Swirl | disable slavio_timer_mem_writel(uint64_t addr, uint32_t val) "write %"PRIx64" = %08x" |
156 | 97bf4851 | Blue Swirl | disable slavio_timer_mem_writel_limit(unsigned int timer_index, uint64_t count) "processor %d user timer set to %016"PRIx64"" |
157 | 97bf4851 | Blue Swirl | disable slavio_timer_mem_writel_counter_invalid(void) "not user timer" |
158 | 97bf4851 | Blue Swirl | disable slavio_timer_mem_writel_status_start(unsigned int timer_index) "processor %d user timer started" |
159 | 97bf4851 | Blue Swirl | disable slavio_timer_mem_writel_status_stop(unsigned int timer_index) "processor %d user timer stopped" |
160 | 97bf4851 | Blue Swirl | disable slavio_timer_mem_writel_mode_user(unsigned int timer_index) "processor %d changed from counter to user timer" |
161 | 97bf4851 | Blue Swirl | disable slavio_timer_mem_writel_mode_counter(unsigned int timer_index) "processor %d changed from user timer to counter" |
162 | 97bf4851 | Blue Swirl | disable slavio_timer_mem_writel_mode_invalid(void) "not system timer" |
163 | 97bf4851 | Blue Swirl | disable slavio_timer_mem_writel_invalid(uint64_t addr) "invalid write address %"PRIx64"" |
164 | 97bf4851 | Blue Swirl | |
165 | 97bf4851 | Blue Swirl | # hw/sparc32_dma.c |
166 | 97bf4851 | Blue Swirl | disable ledma_memory_read(uint64_t addr) "DMA read addr 0x%"PRIx64"" |
167 | 97bf4851 | Blue Swirl | disable ledma_memory_write(uint64_t addr) "DMA write addr 0x%"PRIx64"" |
168 | 97bf4851 | Blue Swirl | disable sparc32_dma_set_irq_raise(void) "Raise IRQ" |
169 | 97bf4851 | Blue Swirl | disable sparc32_dma_set_irq_lower(void) "Lower IRQ" |
170 | 97bf4851 | Blue Swirl | disable espdma_memory_read(uint32_t addr) "DMA read addr 0x%08x" |
171 | 97bf4851 | Blue Swirl | disable espdma_memory_write(uint32_t addr) "DMA write addr 0x%08x" |
172 | 97bf4851 | Blue Swirl | disable sparc32_dma_mem_readl(uint64_t addr, uint32_t ret) "read dmareg %"PRIx64": 0x%08x" |
173 | 97bf4851 | Blue Swirl | disable sparc32_dma_mem_writel(uint64_t addr, uint32_t old, uint32_t val) "write dmareg %"PRIx64": 0x%08x -> 0x%08x" |
174 | 97bf4851 | Blue Swirl | disable sparc32_dma_enable_raise(void) "Raise DMA enable" |
175 | 97bf4851 | Blue Swirl | disable sparc32_dma_enable_lower(void) "Lower DMA enable" |
176 | 97bf4851 | Blue Swirl | |
177 | 97bf4851 | Blue Swirl | # hw/sun4m.c |
178 | 97bf4851 | Blue Swirl | disable sun4m_cpu_interrupt(unsigned int level) "Set CPU IRQ %d" |
179 | 97bf4851 | Blue Swirl | disable sun4m_cpu_reset_interrupt(unsigned int level) "Reset CPU IRQ %d" |
180 | 97bf4851 | Blue Swirl | disable sun4m_cpu_set_irq_raise(int level) "Raise CPU IRQ %d" |
181 | 97bf4851 | Blue Swirl | disable sun4m_cpu_set_irq_lower(int level) "Lower CPU IRQ %d" |
182 | 97bf4851 | Blue Swirl | |
183 | 97bf4851 | Blue Swirl | # hw/sun4m_iommu.c |
184 | 97bf4851 | Blue Swirl | disable sun4m_iommu_mem_readl(uint64_t addr, uint32_t ret) "read reg[%"PRIx64"] = %x" |
185 | 97bf4851 | Blue Swirl | disable sun4m_iommu_mem_writel(uint64_t addr, uint32_t val) "write reg[%"PRIx64"] = %x" |
186 | 97bf4851 | Blue Swirl | disable sun4m_iommu_mem_writel_ctrl(uint64_t iostart) "iostart = %"PRIx64"" |
187 | 97bf4851 | Blue Swirl | disable sun4m_iommu_mem_writel_tlbflush(uint32_t val) "tlb flush %x" |
188 | 97bf4851 | Blue Swirl | disable sun4m_iommu_mem_writel_pgflush(uint32_t val) "page flush %x" |
189 | 97bf4851 | Blue Swirl | disable sun4m_iommu_page_get_flags(uint64_t pa, uint64_t iopte, uint32_t ret) "get flags addr %"PRIx64" => pte %"PRIx64", *pte = %x" |
190 | 97bf4851 | Blue Swirl | disable sun4m_iommu_translate_pa(uint64_t addr, uint64_t pa, uint32_t iopte) "xlate dva %"PRIx64" => pa %"PRIx64" iopte = %x" |
191 | 97bf4851 | Blue Swirl | disable sun4m_iommu_bad_addr(uint64_t addr) "bad addr %"PRIx64"" |