Revision 9bfa659e
| b/hw/arm_boot.c | ||
|---|---|---|
| 216 | 216 |
static int load_dtb(target_phys_addr_t addr, const struct arm_boot_info *binfo) |
| 217 | 217 |
{
|
| 218 | 218 |
#ifdef CONFIG_FDT |
| 219 |
uint32_t mem_reg_property[] = { cpu_to_be32(binfo->loader_start),
|
|
| 220 |
cpu_to_be32(binfo->ram_size) };
|
|
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uint32_t *mem_reg_property;
|
|
| 220 |
uint32_t mem_reg_propsize;
|
|
| 221 | 221 |
void *fdt = NULL; |
| 222 | 222 |
char *filename; |
| 223 | 223 |
int size, rc; |
| 224 |
uint32_t acells, scells, hival; |
|
| 224 | 225 |
|
| 225 | 226 |
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, binfo->dtb_filename); |
| 226 | 227 |
if (!filename) {
|
| ... | ... | |
| 236 | 237 |
} |
| 237 | 238 |
g_free(filename); |
| 238 | 239 |
|
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acells = qemu_devtree_getprop_cell(fdt, "/", "#address-cells"); |
|
| 241 |
scells = qemu_devtree_getprop_cell(fdt, "/", "#size-cells"); |
|
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if (acells == 0 || scells == 0) {
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fprintf(stderr, "dtb file invalid (#address-cells or #size-cells 0)\n"); |
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return -1; |
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} |
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|
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mem_reg_propsize = acells + scells; |
|
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mem_reg_property = g_new0(uint32_t, mem_reg_propsize); |
|
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mem_reg_property[acells - 1] = cpu_to_be32(binfo->loader_start); |
|
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hival = cpu_to_be32(binfo->loader_start >> 32); |
|
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if (acells > 1) {
|
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mem_reg_property[acells - 2] = hival; |
|
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} else if (hival != 0) {
|
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fprintf(stderr, "qemu: dtb file not compatible with " |
|
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"RAM start address > 4GB\n"); |
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exit(1); |
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} |
|
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mem_reg_property[acells + scells - 1] = cpu_to_be32(binfo->ram_size); |
|
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hival = cpu_to_be32(binfo->ram_size >> 32); |
|
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if (scells > 1) {
|
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mem_reg_property[acells + scells - 2] = hival; |
|
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} else if (hival != 0) {
|
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fprintf(stderr, "qemu: dtb file not compatible with " |
|
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"RAM size > 4GB\n"); |
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exit(1); |
|
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} |
|
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|
|
| 239 | 268 |
rc = qemu_devtree_setprop(fdt, "/memory", "reg", mem_reg_property, |
| 240 |
sizeof(mem_reg_property));
|
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mem_reg_propsize * sizeof(uint32_t));
|
|
| 241 | 270 |
if (rc < 0) {
|
| 242 | 271 |
fprintf(stderr, "couldn't set /memory/reg\n"); |
| 243 | 272 |
} |
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